Semiconductor composite synergistic planarization device and method

Abstract

The invention is suitable for the technical field of semiconductor ultra-precision machining, and provides a semiconductor composite synergistic planarization device and method.The device comprises a polishing system and an electrical system; the polishing system comprises at least one ECMP polishing module, at least one CMP polishing module and a head rotating mechanism. Each ECMP polishing module and each CMP polishing module are correspondingly provided with a polishing disc; the head rotating mechanism comprises a plurality of polishing heads; the electrical system comprises a plurality of independent power supplies; positive electrodes of the independent power supplies are connected with the polishing heads in a one-to-one correspondence manner; each polishing disk is provided with a cathode end, and the cathode of each independent power supply is connected with the cathode end of each polishing disk. The problems of low polishing efficiency, high polishing pressure and poor surface type quality of SiC wafers and the like can be solved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor ultra-precision processing technology, and in particular, relates to a semiconductor composite synergistic planarization device and method. Background Art

[0002] With the rapid development of the semiconductor industry, compound semiconductors have gradually formed a scale. For example, silicon carbide (SiC), as a representative of the third-generation semiconductor materials, is a semiconductor with excellent comprehensive performance. Compared with traditional semiconductor materials, it has the characteristics of high thermal conductivity, high critical breakdown electric field, high saturated electron drift rate, high bonding energy and wide bandgap. It is the preferred material for high-frequency, high-temperature, high-power, radiation-resistant electronic devices and sensors. It is also an ideal substrate material for manufacturing large-size, ultra-high brightness white light, blue light diodes and laser diodes. It has important applications in aviation, aerospace exploration, automotive new energy, nuclear energy development, radar and communications.

[0003] With the rapid development of optoelectronics, micro-electromechanical systems and information technology, the surface processing accuracy and surface quality of single-crystal SiC substrates used in related devices have been proposed to meet the requirements of sub-nanometer manufacturing accuracy and ultra-smooth surface manufacturing without sub-surface defects. However, due to the high hardness, high brittleness and high stability of crystals such as SiC, it is difficult to ensure the wafer polishing efficiency. At present, for the wafer polishing process, the traditional chemical mechanical polishing (CMP) device has a large polishing pressure, and the wafer is easily deformed under the action of cutting force, resulting in wafer surface damage, and the wafer polishing efficiency is low. Electrochemical mechanical polishing (ECMP) has a wide range of material applicability (such as SiC, GaN and other wafers), and can quickly achieve global planarization of materials under low load conditions. Although ECMP has played the advantages of both electrochemical and mechanical polishing, it is not restricted by the size and shape of the wafer and can polish large-sized wafers, but the ECMP process has the disadvantages of poor polishing surface quality and no CMP repair function.

[0004] Therefore, new polishing devices and methods are urgently needed to solve problems such as low polishing efficiency, high polishing pressure and poor polishing surface quality of SiC wafers. Summary of the invention

[0005] In order to overcome the problems existing in the related art, the embodiments of the present application provide a semiconductor composite synergistic planarization device and method, which can solve the problems of low polishing efficiency, high polishing pressure and poor surface quality of SiC wafers.

[0006] This application is implemented through the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a semiconductor composite synergistic planarization device, including: a polishing system and an electrical system;

[0008] The polishing system includes at least one ECMP polishing module, at least one CMP polishing module and a head rotating mechanism; each ECMP polishing module and each CMP polishing module is provided with a corresponding polishing disk; the head rotating mechanism includes a plurality of polishing heads;

[0009] The electrical system includes multiple independent power supplies; the positive poles of the independent power supplies are connected to the polishing heads one by one; each polishing disc is provided with a cathode terminal, and the negative pole of each independent power supply is connected to the cathode terminal of each polishing disc.

[0010] In one embodiment, the number of ECMP polishing modules is 2, and each ECMP polishing module is correspondingly provided with a first polishing disc and a second polishing disc; the first polishing disc includes a first cathode end, a second cathode end, a third cathode end, and a fourth cathode end; the second polishing disc includes a fifth cathode end, a sixth cathode end, a seventh cathode end, and an eighth cathode end;

[0011] The number of CMP polishing modules is 1, and the CMP polishing module is correspondingly provided with a third polishing disk; the third polishing disk includes a ninth cathode end, a tenth cathode end, an eleventh cathode end, and a twelfth cathode end; the plurality of polishing heads includes a first polishing head, a second polishing head, a third polishing head, and a fourth polishing head; the plurality of independent power supplies includes a first power supply, a second power supply, a third power supply, and a fourth power supply;

[0012] The first polishing head is connected to the positive electrode of the first power supply; the second polishing head is connected to the positive electrode of the second power supply; the third polishing head is connected to the positive electrode of the third power supply; the fourth polishing head is connected to the positive electrode of the fourth power supply;

[0013] The negative electrode of the first power supply is connected to the first cathode terminal, the fifth cathode terminal and the ninth cathode terminal respectively;

[0014] The negative electrode of the second power supply is connected to the second cathode terminal, the sixth cathode terminal and the tenth cathode terminal respectively;

[0015] The negative electrode of the third power supply is connected to the third cathode terminal, the seventh cathode terminal and the eleventh cathode terminal respectively;

[0016] The negative electrode of the fourth power supply is connected to the fourth cathode terminal, the eighth cathode terminal and the twelfth cathode terminal respectively.

[0017] In one embodiment, the CMP polishing module is selectively electrically connected to a plurality of independent power supplies;

[0018] If the CMP polishing module is electrically connected to a plurality of independent power supplies, the CMP polishing module has an ECMP polishing function.

[0019] In one embodiment, the polishing system further comprises at least one first wafer stage, at least one second wafer stage, at least one polishing stage and at least one transfer mechanism;

[0020] The polishing stage includes a loading platform and a nozzle; the nozzle is used to detect whether the wafer is placed on the loading platform;

[0021] The first wafer stage and the second wafer stage are arranged in parallel and used for carrying the wafer;

[0022] The transfer mechanism is arranged between the first wafer stage, the second wafer stage and the loading platform, and is used for clamping the polished wafer from the loading platform to the first wafer stage, and clamping the unpolished wafer from the second wafer stage to the loading platform.

[0023] In one embodiment, the ECMP polishing module and the CMP polishing module each include a corresponding polishing disc, a polishing pad, a polishing pad dresser and a polishing liquid guide arm;

[0024] The polishing disc is used as an electrochemical cathode; the polishing pad is attached to the corresponding polishing disc;

[0025] The polishing pad dresser is used to dynamically sweep the corresponding polishing pad;

[0026] The polishing liquid guide arm is used to provide the polishing liquid and deionized water required by the wafer.

[0027] In one embodiment, the polishing pressure of the ECMP polishing module is lower than the polishing pressure of the CMP polishing module.

[0028] In one embodiment, the semiconductor composite synergistic planarization device further includes a transfer system, a transmission system, and a cleaning and drying system;

[0029] The transfer system and the cleaning and drying system are arranged in parallel between the polishing system and the transmission system;

[0030] The transfer system includes a moving guide rail, a turning mechanism and a transfer tray;

[0031] The transfer tray is used to carry the wafers transferred by the transfer system;

[0032] The flipping mechanism is connected to the movable guide rail. The combination of the flipping mechanism and the movable guide rail is used to clamp the wafer on the transfer plate to the second wafer carrier, turn over the wafer polished by the polishing system, and send the polished wafer to the cleaning and drying system.

[0033] In one embodiment, the cleaning and drying system includes a cleaning module and a drying module;

[0034] The cleaning module comprises at least one acid cleaning unit and at least one alkaline cleaning unit; wherein the acid cleaning unit is used to clean the wafer using an acidic solution, and the alkaline cleaning unit is used to clean the wafer using an alkaline solution;

[0035] The combination of the flip mechanism and the moving guide rail is also used to clamp the cleaned wafer to the drying module.

[0036] In a second aspect, an embodiment of the present application provides a semiconductor composite synergistic planarization method, which is implemented based on the semiconductor composite synergistic planarization device of the first aspect, and includes:

[0037] A plurality of polishing heads controlling the head rotation mechanism polish the wafers on at least one ECMP polishing module and at least one CMP polishing module in turn; wherein, when the polishing head contacts the polishing disk, the polishing head, the polishing disk and the independent power supply form a closed loop; each ECMP polishing module and each CMP polishing module are provided with a corresponding polishing disk; the positive pole of the independent power supply is connected to the polishing head in a one-to-one correspondence; each polishing disk is provided with a cathode terminal, and the negative pole of each independent power supply is connected to the cathode terminal of each polishing disk.

[0038] In one embodiment, controlling a plurality of polishing heads of a head rotating mechanism to sequentially polish a wafer on at least one ECMP polishing module and at least one CMP polishing module comprises:

[0039] The head rotating mechanism is started, and the first wafer is clamped from the load table by the first polishing head; the plurality of polishing heads include a first polishing head, a second polishing head, a third polishing head and a fourth polishing head; the first polishing head, the second polishing head, the third polishing head and the fourth polishing head are arranged in a cross shape;

[0040] After the first polishing head clamps the first wafer for a preset time, the first polishing head is rotated to the first ECMP polishing module, the first polishing head is connected to the cathode end of the polishing disk of the first ECMP polishing module, and polishing is performed in the first ECMP polishing module for a preset time; at the same time, the second wafer is clamped from the load table by the second polishing head; the ECMP polishing module includes a first ECMP polishing module and a second ECMP polishing module;

[0041] After the first polishing head is used to polish in the first ECMP polishing module for a preset time, the first polishing head is rotated to the second ECMP polishing module, the first polishing head is connected to the cathode end of the polishing disk of the second ECMP polishing module, and polishing is performed in the second ECMP polishing module for a preset time; at the same time, the second polishing head is rotated to the first ECMP polishing module, the second polishing head is connected to the cathode end of the polishing disk of the first ECMP polishing module, and polishing is performed for a preset time; and the second wafer is clamped from the load table by the third polishing head;

[0042] After the first polishing head is used to polish in the second ECMP polishing module for a preset time, the first polishing head is rotated to the CMP polishing module and polished in the CMP polishing module for a preset time; at the same time, the second polishing head is rotated to the second ECMP polishing module, the second polishing head is connected to the cathode end of the polishing disk of the second ECMP polishing module, and polishing is performed for a preset time; and the third polishing head is rotated to the first ECMP polishing module, the third polishing head is connected to the cathode end of the polishing disk of the first ECMP polishing module, and polishing is performed for a preset time; and the third wafer is clamped from the load table by the fourth polishing head; wherein the electrical connection between each polishing head and the cathode end of the polishing disk of the CMP polishing module remains closed;

[0043] After the first polishing head is used to polish the CMP polishing module for a preset time, the first polishing head is rotated back to the load platform to complete the polishing step of the first wafer, and the remaining wafers are cyclically polished according to the polishing step of the first wafer.

[0044] Compared with the related art, the embodiments of the present application have the following beneficial effects:

[0045] The embodiment of the present application is equipped with at least one ECMP polishing module, which improves the material removal rate of SiC wafers and reduces the wafer polishing pressure. It is equipped with a CMP polishing module, which improves the wafer surface quality, has a high degree of process integration, and increases the wafer output yield as a whole. Among them, ECMP adopts a connection method of multiple independent power supplies, polishing heads and polishing discs, forming a multi-contact electrical connection method, so that any power supply can be independently applied to each polishing head and each polishing disc, and the power supplies are not affected by other power supplies, realizing autonomous controllable functions. Overall, it solves the problems of low polishing efficiency, high polishing pressure and poor surface quality of semiconductor wafers such as SiC.

[0046] The beneficial effects of the second aspect mentioned above refer to the beneficial effects of the semiconductor composite synergistic planarization device of the first aspect, which will not be repeated here.

[0047] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0049] Figure 1 It is a schematic structural diagram of a semiconductor composite synergistic planarization device provided in one embodiment of the present application;

[0050] Figure 2 is a schematic diagram of electrical connection between an electrical system and a polishing system provided in one embodiment of the present application;

[0051] Figure 3 It is a schematic diagram of electrical connection between an electrical system provided with a controllable switch and a polishing system provided in one embodiment of the present application.

[0052] Figure numerals: A, polishing system; B, transfer system; C, transmission system; D, cleaning and drying system; E, electrical system; 1, first ECMP component; 1-1, first polishing disc; 1-2, first polishing pad; 1-3, first polishing pad dresser; 1-4, first polishing liquid guide arm; 2, second ECMP component; 2-1, second polishing disc; 2-2, second polishing pad; 2-3, second polishing pad dresser; 2-4, second polishing liquid guide arm 2-4; 3, third ECMP component; 3-1, third polishing disc; 3-2, third polishing pad; 3-3, third polishing pad dresser; 3-4, third polishing liquid guide arm; 4, polishing carrier; 4-1, carrier; 4-2, nozzle; 5. Head rotation mechanism; H1. First polishing head; H2. Second polishing head; H3. Third polishing head; H4. Fourth polishing head; E1. First power supply; E2. Second power supply; E3. Third power supply; E4. Fourth power supply; 6. Inter-disc cleaning tank; 7. Transfer mechanism; 8. First wafer carrier; 9. Second wafer carrier; 10-1. Moving guide rail; 10-2. Flipping mechanism; 11. Transfer tray; 12. Wafer; 13-1. Sliding guide rail; 13-2. Transmission mechanism; 14. First wafer box; 15. Second wafer box; 16. Third wafer box; 17. Fourth wafer box; 18. Cleaning module; 18-1. Acid cleaning unit; 18-2. Alkaline cleaning unit; 19. Drying module. DETAILED DESCRIPTION

[0053] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0054] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0055] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0056] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0057] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0058] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0059] In order to more clearly describe the solution of the present application, some knowledge about CMP and ECMP related to the embodiments of the present application is first introduced below.

[0060] SiC wafers are known for being difficult to grow and process. Their Mohs hardness is slightly lower than that of diamond, and they are chemically inert to all but the most oxidizing polishing fluids. These characteristics make SiC a difficult-to-polish material. To solve the problem of SiC wafer polishing, the current SiC polishing process mainly uses chemical mechanical polishing (CMP) and electrochemical mechanical polishing (ECMP).

[0061] Chemical Mechanical Polishing (CMP): CMP is an important means of semiconductor processing at present. It is also the most effective process method for processing the wafer surface to atomic level smoothness. It is a practical technology that can achieve local and global flattening during the processing. CMP combines two external forces, chemical and mechanical. During the polishing process, the rotating wafer is pressed on the polishing pad that rotates with the worktable with a certain pressure, and the polishing liquid composed of submicron or nano abrasives and chemical solutions flows between the workpiece and the polishing pad, and produces a softening film on the wafer surface. The softening film formed on the wafer surface is removed by the mechanical friction of the abrasives. The processing efficiency of CMP is mainly determined by the chemical reaction rate on the wafer surface. The current polishing device is a multi-disk multi-head CMP, without superimposing other polishing processes. Therefore, it is still a pain point in the industry in terms of polishing efficiency, wafer yield and output.

[0062] Electrochemical mechanical polishing (ECMP): ECMP adds positive electricity to the wafer in the polishing liquid, uses the anodic dissolution to remove the surface material of the wafer, and thus oxidizes the surface of the wafer. The processing effect of electrochemical polishing mainly depends on the composition of the polishing liquid, the current intensity and the length of the processing time. On the basis of electrochemical polishing, electrochemical polishing is organically combined with mechanical grinding and polishing. This method is called electrochemical mechanical polishing. As described in the background technology, ECMP can polish large-sized wafers, but the disadvantages of the ECMP process are poor polishing surface quality and no CMP repair function. Moreover, common ECMP polishing devices are not equipped with CMP polishing devices.

[0063] Therefore, the polishing pressure required by traditional CMP is relatively high, and wafers are prone to deformation, fragmentation and other defects under high polishing pressure. Due to the high hardness, difficulty in oxidation and removal of SiC wafers, the CMP polishing effect is slightly slow. The polishing devices on the market are multi-disc multi-head CMP, which makes the overall polishing rate of traditional CMP low.

[0064] The electrochemical mechanical polishing process is to organically couple electrochemical polishing with mechanical grinding polishing, and ECMP is also single-sided oxidation polishing. At present, due to the material characteristics of SiC wafers that are difficult to oxidize and remove, the shape control of SiC wafers cannot be guaranteed under dynamic electrochemical action. Common ECMP polishing devices do not have CMP polishing and repair functions, so the development of new polishing devices for SiC wafers to adjust the wafer surface quality has great potential and practical value.

[0065] In response to the need to take into account the three indicators of SiC wafer polishing efficiency, polishing pressure and surface quality, this application is equipped with ECMP polishing module and CMP polishing module at the same time, which improves the SiC wafer material removal rate, reduces the wafer polishing pressure, and improves the wafer surface quality. The process integration is high, and the overall wafer output yield is increased. The multi-contact electrical connection method is adopted, so that any power supply can be independently applied to each polishing head and each polishing disk, and the power supply is not affected by other power supplies, realizing autonomous controllable functions.

[0066] Figure 1 is a schematic diagram of the structure of a semiconductor composite synergistic planarization device provided in an embodiment of the present application, referring to Figure 1 The semiconductor composite synergistic planarization device is described in detail as follows:

[0067] The semiconductor composite synergistic planarization device consists of five parts: polishing system A, polishing system B, transmission system C, cleaning and drying system D and electrical system E.

[0068] In this embodiment, in order to meet the requirement of taking into account the three indicators of polishing efficiency, polishing pressure and surface quality of SiC wafers at the same time, the semiconductor composite efficiency-enhancing flattening device includes at least a polishing system A and an electrical system E to achieve this. Therefore, the polishing system A and the electrical system E are first introduced.

[0069] The polishing system A includes at least one ECMP polishing module, at least one CMP polishing module and a head rotating mechanism 5; each ECMP polishing module and each CMP polishing module is provided with a corresponding polishing disk; the head rotating mechanism 5 includes a plurality of polishing heads.

[0070] For example, according to the location of the inter-disk rinsing tank 6, the polishing system A is divided into 4 parts, one of which is selected as a load table without a polishing disk for clamping the wafer, and the other 3 parts are set as ECMP polishing modules or CMP polishing modules. When the head rotating mechanism 5 enters the rotating working state, the polishing head (H1, H2, H3, H4) rotates the wafer clamped by the load table to the ECMP polishing module or CMP polishing module for sequential polishing. It should be noted that the polishing system A is divided into 4 parts here only for the convenience of understanding this scheme, but it is not limited to Figure 1 form.

[0071] The electrical system E includes multiple independent power supplies; the positive poles of the independent power supplies are connected to the polishing heads one by one; each polishing disc is provided with a cathode terminal, and the negative pole of each independent power supply is connected to the cathode terminal of each polishing disc.

[0072] Exemplarily, the CMP polishing module includes an ECMP assembly and a polishing head, and performs chemical mechanical polishing during the polishing process. The ECMP assembly consists of a polishing disc, a polishing pad, a polishing pad dresser, and a polishing liquid guide arm. The polishing pad is a hollow polyurethane polishing pad. The ECMP polishing module also includes an ECMP assembly and a polishing head. The difference from the CMP polishing module is that during the polishing process, the polishing head acts as an anode and the polishing disc acts as a cathode to perform electrochemical mechanical polishing.

[0073] This embodiment is equipped with at least one ECMP polishing module, which improves the SiC wafer material removal rate and reduces the wafer polishing pressure. It is equipped with at least one CMP polishing module, which improves the wafer surface quality, has a high degree of process integration, and increases the wafer output yield as a whole. Among them, ECMP adopts a connection method of multiple independent power supplies, polishing heads and polishing discs, forming a multi-contact electrical connection method, so that any power supply can be independently applied to each polishing head and each polishing disc, and the power supplies are not affected by other power supplies, realizing autonomous controllable functions. Overall, it solves the problems of low polishing efficiency, high polishing pressure and poor surface quality of semiconductor wafers such as SiC.

[0074] In one embodiment, the CMP polishing module is selectively electrically connected to a plurality of independent power supplies; if the CMP polishing module is electrically connected to a plurality of independent power supplies, the CMP polishing module has an ECMP polishing function.

[0075] For example, when the wafer size and shape are relatively special and the requirements for the wafer surface quality are relatively low, the CMP polishing module can be electrically connected to an independent power supply to form an ECMP polishing module. In this case, three ECMP polishing modules are used for polishing.

[0076] Similarly, when the wafer size and shape are regular, and the wafer surface quality requirements are high, a part of the ECMP polishing module can be disconnected from the independent power supply, and the ECMP polishing module is converted into a CMP polishing module. For example, one ECMP polishing module and two CMP polishing modules are combined, or three CMP polishing modules are combined. The electrochemical mechanical polishing component can selectively open or close the electrical connection, so that it can freely choose to become a traditional CMP polishing device or an ECMP polishing device.

[0077] In one embodiment, see Figure 1 and Figure 2 In order to enable any power source to be independently applied to each polishing head and each polishing plate, the present invention provides a schematic diagram of electrical connection between the electrical system E and the polishing system A, as shown in FIG. Figure 2 As shown, the polishing process using two ECMP polishing modules and one CMP polishing module in sequence is used as an example to illustrate. Figure 2P1, P2 and P3 represent the first polishing disc 1-1, the second polishing disc 2-1 and the third polishing disc 3-1 respectively. The head rotating mechanism 5 carries four independently moving polishing heads, and the head rotating mechanism 5 is used to drive different polishing heads to work on polishing discs on different electrochemical mechanical polishing assemblies.

[0078] The number of ECMP polishing modules is 2, and each ECMP polishing module is correspondingly provided with a first polishing disc 1-1 and a second polishing disc 2-1; the first polishing disc 1-1 includes a first cathode end CE1, a second cathode end CE2, a third cathode end CE3 and a fourth cathode end CE4; the second polishing disc 2-1 includes a fifth cathode end CE5, a sixth cathode end CE6, a seventh cathode end CE7 and an eighth cathode end CE8.

[0079] The number of CMP polishing modules is 1, and the CMP polishing module is correspondingly provided with a third polishing disk 3-1; the third polishing disk 3-1 includes a ninth cathode end CE9, a tenth cathode end CE10, an eleventh cathode end CE11 and a twelfth cathode end CE12; the multiple polishing heads include a first polishing head H1, a second polishing head H2, a third polishing head H3 and a fourth polishing head H4; the multiple independent power supplies include a first power supply E1, a second power supply E2, a third power supply E3 and a fourth power supply E4.

[0080] Wherein, each cathode terminal can be arranged on an edge contact point of a corresponding polishing disk.

[0081] The first polishing head H1 is connected to the positive pole of the first power source E1; the second polishing head H2 is connected to the positive pole of the second power source E2; the third polishing head H3 is connected to the positive pole of the third power source E3; and the fourth polishing head H4 is connected to the positive pole of the fourth power source E4.

[0082] The negative electrode of the first power supply E1 is connected to the first cathode terminal CE1, the fifth cathode terminal CE5 and the ninth cathode terminal CE9 respectively. The negative electrode of the second power supply E2 is connected to the second cathode terminal CE2, the sixth cathode terminal CE6 and the tenth cathode terminal CE10 respectively. The negative electrode of the third power supply E3 is connected to the third cathode terminal CE3, the seventh cathode terminal CE7 and the eleventh cathode terminal CE11 respectively. The negative electrode of the fourth power supply E4 is connected to the fourth cathode terminal CE4, the eighth cathode terminal CE8 and the twelfth cathode terminal CE12 respectively.

[0083] Exemplarily, when polishing SiC wafers, mechanical polishing parameters and electrochemical parameters need to be set. For mechanical polishing parameters: the rotation speed range of the first polishing disc 1-1 (P1), the second polishing disc 2-1 (P2) and the third polishing disc 3-1 (P3) is 30 to 120 rpm (revolutions per minute), the rotation speed range of the first polishing head H1, the second polishing head H2, the third polishing head H3 and the fourth polishing head H4 is 40 to 110 rpm, the main polishing pressure of the first polishing disc 1-1 and the second polishing disc 2-1 is 0.5 to 5 psi (pounds per square inch), and the main polishing pressure of the third polishing disc 3-1 is 0.5 to 6 psi. Here, the main polishing pressure is directly The main pressure acting on the contact surface between the polishing pad and the wafer. Since ECMP can achieve effective polishing effect under low mechanical pressure, the main polishing pressure of the first polishing disc 1-1 and the second polishing disc 2-1 as the ECMP polishing module is lower than the main polishing pressure of the third polishing disc 3-1 as the CMP polishing module. The temperature will not be too high, which can reduce the wear of the polishing equipment and polishing liquid. Compared with the traditional CMP polishing pressure of 7psi to 9psi, the wear of the required polishing equipment and consumables will also be reduced accordingly due to the reduced polishing pressure, which helps to reduce production costs. The polishing time of the three polishing discs is 5 to 20 minutes, and the polishing liquid flow rate is 50 to 200mL / min (milliliters per minute). The above process parameters can be defined in the process menu.

[0084] For electrochemical parameters, the applied voltage parameter is 15V to 40V, the current parameter is 1A to 4A, and both the steady voltage and steady current modes are available. The electrolysis time is 5 to 20 minutes, and the electrolyte can be a commonly used polishing liquid, such as cerium dioxide polishing liquid, silicon dioxide polishing liquid, and aluminum oxide polishing liquid.

[0085] exist Figure 2 When wafer 12 is Figure 1When transmitting along P1~P2~P3 (counterclockwise), P1 and P2 are ECMP polishing discs, and P3 is a CMP polishing disc (ECMP function is retained, but the power is not turned on during polishing). The cathodes of independent power supplies E1~E4 are respectively connected to the edge contacts of each polishing disc, so the P1, P2 and P3 polishing discs all have 4 cathode points corresponding to the power supply. In this way, no matter which polishing head is on any polishing disc, it can only form a closed loop with the cathode on the polishing disc where it is located. For example, when the first polishing head H1 performs ECMP on the first polishing disc P1, the first polishing head H1 only forms a closed loop with the first cathode end CE1 of the first polishing disc 1-1P1. When the first polishing head H1 performs ECMP on the second polishing disc 2-1P2, the first polishing head H1 only forms a closed loop with the fifth cathode end CE5 of the second polishing disc 2-1P2. When the first polishing head H1 performs ECMP on the third polishing disc 3-1P3, the first polishing head H1 only forms a closed loop with the ninth cathode end CE9 of the third polishing disc 3-1P3. Similarly, the second polishing head H2, the third polishing head H3 and the fourth polishing head H4 are also the same, and no interference will be generated to other power supplies or other polishing discs.

[0086] In addition, for the third polishing plate 3-1, controllable switches S9, S10, S11 and S12 are correspondingly arranged on the circuits near the ninth cathode terminal CE9, the tenth cathode terminal CE10, the eleventh cathode terminal CE11 and the twelfth cathode terminal CE12 of the third polishing plate 3-1. Figure 3 As shown, when the third polishing disc 3-1 is used as a CMP polishing module, the controllable switches S9, S10, S11 and S12 are disconnected by program control, and each polishing head performs chemical mechanical polishing whenever it reaches the third polishing disc 3-1, and the electrical connection between each polishing head and the first polishing disc 1-1 and the second polishing disc 2-1 is not affected. Similarly, the first cathode terminal CE1, the second cathode terminal CE2, the third cathode terminal CE3 and the fourth cathode terminal CE4 of the first polishing disc 1-1 are also correspondingly provided with controllable switches S1, S2, S3 and S4, and the nearby circuits of the fifth cathode terminal CE5, the sixth cathode terminal CE6, the seventh cathode terminal CE7 and the eighth cathode terminal CE8 of the second polishing disc 2-1 are also correspondingly provided with controllable switches S5, S6, S7 and S8. The principle is consistent with the above process, and the electrical connection between each polishing head and other discs cannot be affected. It will not be described here, and it will not be repeatedly marked in the figure.

[0087] This embodiment adopts a multi-contact electrical connection method. The advantage of this method is that any power source can be independently applied to each polishing head and each polishing disk, and each independent power source is not affected by other power sources, thereby realizing the autonomous and controllable function of ECMP.

[0088] In one embodiment, see Figure 1The polishing system A also includes at least one first wafer stage 8, at least one second wafer stage 9, at least one polishing stage 4 and at least one transfer mechanism 7.

[0089] The polishing platform 4 includes a loading platform 4-1 and a nozzle 4-2; the nozzle 4-2 is used to detect whether the wafer 12 is placed on the loading platform 4-1. The nozzle 4-2 is set in the middle of the loading platform 4-1. When the wafer 12 is placed on the loading platform 4-1, the water sprayed by the nozzle 4-2 will be blocked. At the same time, the water sprayed by the nozzle 4-2 will have the effect of cleaning and wetting the wafer 12. When there is no wafer 12 on the loading platform 4-1, water will be sprayed out. It can be judged by detecting water pressure or other methods whether the wafer 12 is placed on the loading platform 4-1.

[0090] The first wafer stage 8 and the second wafer stage 9 are arranged in parallel to carry the wafer 12 .

[0091] The transfer mechanism 7 is disposed between the first wafer stage 8, the second wafer stage 9 and the loading platform 4-1, and is used to clamp the polished wafer 12 from the loading platform 4-1 to the first wafer stage 8, and to clamp the unpolished wafer 12 from the second wafer stage 9 to the loading platform 4-1.

[0092] In this embodiment, two wafer carriers are provided to avoid wafer transmission conflicts. One wafer carrier serves as a receiving device for the direction entering the polishing system A, and the other wafer carrier serves as a receiving device for the direction exiting the polishing system A. Polishing is carried out in an orderly manner without confusion.

[0093] In one embodiment, see Figure 1 The ECMP polishing module and the CMP polishing module each include a corresponding polishing disc, a polishing pad, a polishing pad dresser and a polishing liquid guide arm.

[0094] The polishing disc serves as an electrochemical cathode; the polishing pad is attached to the corresponding polishing disc.

[0095] The polishing pad dresser is used to dynamically sweep the corresponding polishing pad.

[0096] The polishing liquid guide arm is used to provide the polishing liquid and deionized water required by the wafer 12 .

[0097] Exemplarily, the first ECMP polishing module includes a first ECMP component 1; the first ECMP component 1 is composed of a first polishing disc 1-1, a first polishing pad 1-2, a first polishing pad dresser 1-3, and a first polishing liquid guide arm 1-4. The first polishing disc 1-1 is used as an electrochemical cathode, on which a first polishing pad 1-2 made of hollow polyurethane is attached, the first polishing pad dresser 1-3 dynamically scans and adjusts the first polishing pad 1-2 so that the grooves on the first polishing pad 1-2 are not filled with materials, and the polishing performance is better, and the first polishing liquid guide arm 1-4 provides the polishing liquid and deionized water required by the wafer 12.

[0098] Similarly, the second ECMP polishing module includes a second ECMP assembly 2; the second ECMP assembly 2 is composed of a second polishing disc 2-1, a second polishing pad 2-2, a second polishing pad dresser 2-3, and a second polishing liquid guide arm 2-4. The CMP polishing module includes a third ECMP assembly 3; the third ECMP assembly 3 is composed of a third polishing disc 3-1, a third polishing pad 3-2, a third polishing pad dresser 3-3, and a third polishing liquid guide arm 3-4.

[0099] The polishing pressure of the ECMP polishing module is less than that of the CMP polishing module, and there is a certain difference between the polishing pressure of the CMP polishing module and the polishing pressure of the ECMP polishing module, wherein the difference ranges from about 0 to 5.5 psi, and the preferred difference ranges from 2 psi to 4 psi.

[0100] Exemplarily, the polishing system A further comprises an inter-disk cleaning tank 6 . The inter-disk cleaning tank 6 is disposed between various ECMP assemblies and is used to wet the polishing head in an idle state, or wet the wafer 12 loaded by the head rotating mechanism 5 .

[0101] In this embodiment, the dynamic sweeping function of the polishing pad dresser helps to maintain the uniformity and consistency of the polishing pad surface, and reduce the degradation of polishing quality caused by local wear or accumulated impurities. The design of the polishing liquid guide arm enables the polishing liquid and deionized water to be evenly distributed to the wafer surface, ensuring that the chemical reaction and mechanical grinding action of the polishing process can be carried out evenly. This not only improves the polishing efficiency, but also avoids the problem of inconsistent wafer surface quality caused by uneven distribution of the polishing liquid. The inter-disk cleaning tank 6 wets the polishing head airbag when the machine is not loaded with a wafer, or when the wafer is in a dry state, wets the wafer loaded on the head to improve the polishing efficiency.

[0102] In one embodiment, the semiconductor composite synergistic planarization device further includes a polishing system B, a transmission system C and a cleaning and drying system D.

[0103] The polishing system B and the cleaning and drying system D are arranged in parallel between the polishing system A and the transmission system C. The polishing system B includes a moving guide rail 10 - 1 , a turning mechanism 10 - 2 and a transfer plate 11 .

[0104] The transfer tray 11 is used to carry the wafers 12 transferred by the transfer system C.

[0105] The flip mechanism 10-2 is connected to the moving guide rail 10-1. The combination of the flip mechanism 10-2 and the moving guide rail 10-1 is used to clamp the wafer 12 on the transfer plate 11 to the second wafer stage 9, turn over the wafer 12 polished by the polishing system A, and send the polished wafer 12 to the cleaning and drying system D. Among them, the moving guide rail 10-1 is used to guide the flip mechanism 10-2 to move when clamping and flipping the wafer 12.

[0106] Exemplarily, when the SiC wafer 12 in the wafer box is in a state where the Si surface is facing up and the C surface is facing down, it is generally stipulated that the C surface of the SiC wafer 12 is polished first. At this time, the Si surface of the wafer 12 is facing up and the C surface is facing down (the robot arm of the flip mechanism 10-2 does not flip). After the polishing is completed, the robot arm of the flip mechanism 10-2 flips the wafer 12 and sends it to the cleaning and drying system D. At this time, the state of the wafer 12 is C surface facing up and the Si surface is facing down. After the polishing of the C surface of all SiC wafers 12 is completed, the Si surface is polished. At this time, the C surface of the wafer 12 is facing up and the Si surface is facing down (the robot arm of the flip mechanism 10-2 does not flip). After the polishing is completed, the robot arm flips the wafer 12 and sends it to the cleaning and drying system D. At this time, the state of the wafer 12 is Si surface facing up and the C surface is facing down, so that the wafer 12 enters the machine with the Si surface facing up and exits the machine with the Si surface facing up.

[0107] Exemplarily, the cleaning and drying system D includes a cleaning module 18 and a drying module 19 .

[0108] The cleaning module 18 includes at least one acid cleaning unit 18-1 and at least one alkaline cleaning unit 18-2; wherein the acid cleaning unit 18-1 is used to clean the wafer 12 using an acid solution, and the alkaline cleaning unit 18-2 is used to clean the wafer 12 using an alkaline solution. The process of cleaning the wafer 12 by the acid cleaning unit 18-1 and the alkaline cleaning unit 18-2 can be achieved by setting a cleaning brush.

[0109] The combination of the flip mechanism 10 - 2 and the movable guide rail 10 - 1 is also used to clamp the cleaned wafer to the drying module 19 .

[0110] In this embodiment, the combination of the flipping mechanism 10-2 and the movable guide rail 10-1 has multiple functions, realizing the transmission of wafers 12 between the transmission system C and the polishing system B, the cleaning and drying system D and the transmission system C, and the cleaning and drying system D and the polishing system A, and combining the cleaning and drying module 19 to improve the surface quality of the wafers.

[0111] In one embodiment, the transport system C further includes a sliding rail 13 - 1 , a transport mechanism 13 - 2 and a wafer box.

[0112] The sliding guide rail 13 - 1 and the transmission mechanism 13 - 2 are used to cooperate in taking out the unpolished wafers from the wafer box and placing them into the transfer plate 11 , and to clamp the dried wafers 12 into the wafer box in the transmission system C.

[0113] Exemplarily, the transport mechanism 13 - 2 is used to transport the dried unpolished wafers 12 to the polishing line, and is also used to clamp the dried wafers 12 out of the polishing line, thereby realizing the process of drying the wafers 12 in and out.

[0114] And, the wafer box is provided with multiple, such as Figure 1 As shown, a first wafer box 14, a second wafer box 15, a third wafer box 16 and a fourth wafer box 17 are provided here, a total of four wafer boxes, which meet the number of wafers 12 to be polished within a certain period of time during the automatic polishing process.

[0115] Compared with the traditional CMP polishing device, the semiconductor composite synergistic planarization device of the present application has the key innovation of being equipped with two ECMP polishing modules, which improves the SiC wafer material removal rate, and being equipped with one CMP polishing module, which improves the wafer surface quality, has a high degree of process integration, and increases the wafer output yield as a whole. A double-disc ECMP polishing process is also proposed. The advantage of this process is that the polishing disks do not interfere with each other and are independent of each other. This solution has at least two ECMP polishing processes, and the device is highly flexible. In particular, an ECMP multi-contact electrical connection method is creatively proposed. The advantage of this method is that any power supply can be independently applied to each polishing head and each polishing disk, and the power supplies are not affected by other power supplies, thus realizing autonomous controllable functions.

[0116] The present application provides a semiconductor composite synergistic planarization method, which is implemented based on the semiconductor composite synergistic planarization device of the above embodiment, and includes:

[0117] A plurality of polishing heads controlling the head rotating mechanism sequentially polish the wafer on at least one ECMP polishing module and at least one CMP polishing module.

[0118] Among them, when the polishing head contacts the polishing disk, the polishing head, the polishing disk and the independent power supply form a closed loop; each ECMP polishing module and each CMP polishing module are correspondingly provided with a polishing disk; the positive pole of the independent power supply is connected to the polishing head one by one; each polishing disk is provided with a cathode end, and the negative pole of each independent power supply is connected to the cathode end of each polishing disk.

[0119] In one embodiment, controlling a plurality of polishing heads of a head rotating mechanism to sequentially polish a wafer on at least one ECMP polishing module and at least one CMP polishing module comprises:

[0120] Start the head rotating mechanism 5 and use the first polishing head H1 to clamp the first wafer from the load platform 4-1; the head rotating mechanism 5 includes the first polishing head H1, the second polishing head H2, the third polishing head H3 and the fourth polishing head H4; the first polishing head H1, the second polishing head H2, the third polishing head H3 and the fourth polishing head H4 are arranged in a cross shape.

[0121] After the first polishing head H1 clamps the first wafer for a preset time, the first polishing head H1 is rotated to the first ECMP polishing module, the first polishing head H1 is connected to the cathode end of the polishing disk of the first ECMP polishing module, and polishing is performed in the first ECMP polishing module for a preset time; at the same time, the second polishing head H2 is used to clamp the second wafer from the load platform 4-1.

[0122] After the first polishing head H1 is used to polish in the first ECMP polishing module for a preset time, the first polishing head H1 is rotated to the second ECMP polishing module, the first polishing head H1 is connected to the cathode end of the polishing disk of the second ECMP polishing module, and polishing is performed in the second ECMP polishing module for a preset time; at the same time, the second polishing head H2 is rotated to the first ECMP polishing module, the second polishing head H2 is connected to the cathode end of the polishing disk of the first ECMP polishing module, and polishing is performed for a preset time; and the third polishing head H3 is used to clamp the second wafer from the load table 4-1.

[0123] After the first polishing head H1 is used to polish in the second ECMP polishing module for a preset time, the first polishing head H1 is rotated to the CMP polishing module and polished in the CMP polishing module for a preset time; at the same time, the second polishing head H2 is rotated to the second ECMP polishing module, the second polishing head H2 is connected to the cathode end of the polishing disk of the second ECMP polishing module, and polished for a preset time; and, the third polishing head H3 is rotated to the first ECMP polishing module, the third polishing head H3 is connected to the cathode end of the polishing disk of the first ECMP polishing module, and polished for a preset time; and, the fourth polishing head H4 is used to clamp the third wafer from the load platform 4-1; wherein, the electrical connection between each polishing head and the cathode end of the polishing disk of the CMP polishing module remains closed.

[0124] After the first polishing head H1 is used to polish the CMP polishing module for a preset time, the first polishing head H1 is rotated back to the loading platform 4-1 to complete the polishing step of the first wafer, and the remaining wafers are cyclically polished according to the polishing step of the first wafer.

[0125] The semiconductor composite efficiency-enhancing planarization method of the embodiment of the present application is polished sequentially through two ECMP polishing modules and one CMP polishing module, which improves the SiC wafer material removal rate, reduces the wafer polishing pressure, and improves the wafer surface quality at the same time. The process integration is high, and the overall wafer output yield is increased. ECMP also adopts a multi-contact electric connection method. The advantage of this method is that any power supply can be independently applied to each polishing head and each polishing disk, and the power supply is not affected by other power supplies, realizing an autonomous controllable function. It can solve the problems of low polishing efficiency, high polishing pressure and poor surface quality of SiC wafers.

[0126] In addition, it can continuously polish multiple wafers at the same time, reducing the waiting time and switching time of single wafer processing, significantly improving production efficiency, and batch polishing reduces the steps and waiting links in the production process, thereby shortening the overall production cycle. At the same time, it can reduce the consumption of polishing liquid, further reduce production costs, and can uniformly control various parameters in the polishing process, such as polishing time, pressure, rotation speed, etc., to ensure that each wafer receives the same processing conditions, improving the consistency and stability of the process.

[0127] It should be understood that the execution order of the above processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. In order to reduce the complexity of the patent description, the present invention provides a compound semiconductor composite synergistic planarization device and process, and the obvious changes or similar layouts derived therefrom are still within the protection scope of the present invention. For example, the present invention adopts ECMP assisted polishing process, and can also adopt photoelectrochemical mechanical polishing process (PECMP), as well as values ​​other than the process parameters related to the present invention.

[0128] Of course, the number of ECMP components in this application is given as 4 examples. If the number of ECMP components is expanded to 5, 6 or other numbers with reference to the aforementioned embodiments, it is still within the protection scope of this application.

[0129] It should be noted that the information interaction, execution process and other contents between the above-mentioned devices are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0130] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0131] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A semiconductor composite synergistic planarization device, characterized in that: include: Polishing system and electrical system; The polishing system comprises at least one ECMP polishing module, at least one CMP polishing module and a head rotating mechanism; each ECMP polishing module and each CMP polishing module is provided with a corresponding polishing disk; the head rotating mechanism comprises a plurality of polishing heads; The electrical system includes multiple independent power supplies; the positive poles of the independent power supplies are connected to the polishing heads one by one; each polishing disc is provided with a cathode end, and the negative pole of each independent power supply is connected to the cathode end of each polishing disc.

2. The semiconductor composite synergistic planarization device according to claim 1, characterized in that: The number of the ECMP polishing modules is 2, and each ECMP polishing module is correspondingly provided with a first polishing disc and a second polishing disc; the first polishing disc includes a first cathode end, a second cathode end, a third cathode end, and a fourth cathode end; the second polishing disc includes a fifth cathode end, a sixth cathode end, a seventh cathode end, and an eighth cathode end; The number of the CMP polishing modules is 1, and the CMP polishing module is correspondingly provided with a third polishing disk; the third polishing disk includes a ninth cathode end, a tenth cathode end, an eleventh cathode end, and a twelfth cathode end; the plurality of polishing heads include a first polishing head, a second polishing head, a third polishing head, and a fourth polishing head; the plurality of independent power supplies include a first power supply, a second power supply, a third power supply, and a fourth power supply; The first polishing head is connected to the positive electrode of the first power supply; the second polishing head is connected to the positive electrode of the second power supply; the third polishing head is connected to the positive electrode of the third power supply; the fourth polishing head is connected to the positive electrode of the fourth power supply; The negative electrode of the first power supply is connected to the first cathode terminal, the fifth cathode terminal and the ninth cathode terminal respectively; The negative electrode of the second power supply is connected to the second cathode terminal, the sixth cathode terminal and the tenth cathode terminal respectively; The negative electrode of the third power supply is respectively connected to the third cathode terminal, the seventh cathode terminal and the eleventh cathode terminal; The negative electrode of the fourth power supply is connected to the fourth cathode terminal, the eighth cathode terminal and the twelfth cathode terminal respectively.

3. The semiconductor composite synergistic planarization device according to claim 1, characterized in that: The CMP polishing module is selectively electrically connected to the plurality of independent power supplies; If the CMP polishing module is electrically connected to the multiple independent power supplies, the CMP polishing module has an ECMP polishing function.

4. The semiconductor composite synergistic planarization device according to claim 1, characterized in that: The polishing system further comprises at least one first wafer stage, at least one second wafer stage, at least one polishing stage and at least one transfer mechanism; The polishing stage comprises a loading platform and a nozzle; the nozzle is used to detect whether the wafer is placed on the loading platform; The first wafer stage and the second wafer stage are arranged in parallel and are used to carry wafers; The transfer mechanism is disposed between the first wafer stage, the second wafer stage and the loading platform, and is used to clamp the polished wafer from the loading platform to the first wafer stage, and to clamp the unpolished wafer from the second wafer stage to the loading platform.

5. The semiconductor composite synergistic planarization device according to claim 1, characterized in that: The ECMP polishing module and the CMP polishing module each include the polishing disc, polishing pad, polishing pad dresser and polishing liquid guide arm corresponding to each other; The polishing disc is used as an electrochemical cathode; the polishing pad is attached to the corresponding polishing disc; The polishing pad dresser is used to dynamically scan the corresponding polishing pad; The polishing liquid guide arm is used to provide the polishing liquid and deionized water required by the wafer.

6. The semiconductor composite synergistic planarization device according to claim 1, characterized in that: The polishing pressure of the ECMP polishing module is lower than the polishing pressure of the CMP polishing module.

7. The semiconductor composite synergistic planarization device according to claim 4, characterized in that: The semiconductor composite synergistic planarization device also includes a transfer system, a transmission system and a cleaning and drying system; The transfer system and the cleaning and drying system are arranged in parallel between the polishing system and the transmission system; The transfer system includes a moving guide rail, a turning mechanism and a transfer tray; The transfer tray is used to carry the wafers transferred by the transfer system; The flipping mechanism is connected to the movable guide rail, and the combination of the flipping mechanism and the movable guide rail is used to clamp the wafer on the transfer plate to the second wafer carrier, flip the wafer polished by the polishing system, and send the polished wafer to the cleaning and drying system.

8. The semiconductor composite synergistic planarization device according to claim 7, characterized in that: The cleaning and drying system comprises a cleaning module and a drying module; The cleaning module comprises at least one acid cleaning unit and at least one alkaline cleaning unit; wherein the acid cleaning unit is used to clean the wafer using an acidic solution, and the alkaline cleaning unit is used to clean the wafer using an alkaline solution; The combination of the flipping mechanism and the moving guide rail is also used to clamp the cleaned wafer to the drying module.

9. A semiconductor composite synergistic planarization method, characterized in that: The semiconductor composite synergistic planarization device according to any one of claims 1 to 8 is implemented, comprising: A plurality of polishing heads controlling the head rotation mechanism polish the wafers on at least one ECMP polishing module and at least one CMP polishing module in turn; wherein, when the polishing head contacts the polishing disk, the polishing head, the polishing disk and the independent power supply form a closed loop; each ECMP polishing module and each CMP polishing module is provided with a corresponding polishing disk; the positive pole of the independent power supply is connected to the polishing head in a one-to-one correspondence; each polishing disk is provided with a cathode end, and the negative pole of each independent power supply is connected to the cathode end of each polishing disk.

10. The semiconductor composite synergistic planarization method according to claim 9, characterized in that: The multiple polishing heads of the control head rotation mechanism sequentially polish the wafer on at least one ECMP polishing module and at least one CMP polishing module, including: The head rotating mechanism is started, and the first wafer is clamped from the load platform by the first polishing head; the plurality of polishing heads include the first polishing head, the second polishing head, the third polishing head and the fourth polishing head; the first polishing head, the second polishing head, the third polishing head and the fourth polishing head are arranged in a cross shape; After the first polishing head clamps the first wafer for a preset time, the first polishing head is rotated to the first ECMP polishing module, the first polishing head is connected to the cathode end of the polishing disk of the first ECMP polishing module, and polishing is performed in the first ECMP polishing module for a preset time; at the same time, the second polishing head is used to clamp the second wafer from the load table; the ECMP polishing module includes the first ECMP polishing module and the second ECMP polishing module; After the first ECMP polishing module is polished for a preset time by using the first polishing head, the first polishing head is rotated to the second ECMP polishing module, the first polishing head is connected to the cathode end of the polishing disk of the second ECMP polishing module, and polishing is performed for a preset time in the second ECMP polishing module; at the same time, the second polishing head is rotated to the first ECMP polishing module, the second polishing head is connected to the cathode end of the polishing disk of the first ECMP polishing module, and polishing is performed for a preset time; and the second wafer is clamped from the load table by using the third polishing head; After the first polishing head is used to polish the second ECMP polishing module for a preset time, the first polishing head is rotated to the CMP polishing module and polished for a preset time in the CMP polishing module; at the same time, the second polishing head is rotated to the second ECMP polishing module, the second polishing head is connected to the cathode end of the polishing disk of the second ECMP polishing module, and polished for a preset time; and the third polishing head is rotated to the first ECMP polishing module, the third polishing head is connected to the cathode end of the polishing disk of the first ECMP polishing module, and polished for a preset time; and the fourth polishing head is used to clamp the third wafer from the load table; wherein the electrical connection between each polishing head and the cathode end of the polishing disk of the CMP polishing module remains closed; After the first polishing head is used to polish the CMP polishing module for a preset time, the first polishing head is rotated back to the load platform to complete the polishing step of the first wafer, and the remaining wafers are cyclically polished according to the polishing step of the first wafer.

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