Chip detection circuit and chip detection method

Abstract

The embodiment of the invention discloses a chip detection circuit and a chip detection method. The chip detection circuit comprises an ATE, a single bus protocol conversion processor and a chip to be detected. Wherein the ATE is connected with the unibus protocol conversion processor, and the unibus protocol conversion processor is connected with a chip to be detected; when the chip to be detected is subjected to first detection, the unibus protocol conversion processor carries out unibus protocol conversion on transmission data between the ATE and the chip to be detected, protocol conversion is carried out through the unibus protocol conversion processor, reliable clock communication between the ATE and the chip to be detected can be guaranteed, and therefore the chip detection accuracy can be improved; through the introduction of the single bus protocol conversion processor, the ATE can perform parallel detection on a plurality of chips to be detected through each IO channel, and the chip detection efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a chip detection circuit and a chip detection method. Background Art

[0002] In chip testing, chip probing (CP) and final test (FT) are usually used. CP testing is between wafer manufacturing and packaging in the chip manufacturing process. FT testing is performed after the chip is packaged to select unqualified chips.

[0003] CP testing uses general chip detection equipment (Auto Test Equipment, ATE). In the AC testing (AC) of CP testing, general ATE accurately applies bit-level stimulation to each input and output (IO) of the chip under test by running test vectors, and obtains bit-level responses and compares them with expected values.

[0004] In the AC test of FT test, the test vector is not applied directly to the IO. Instead, a dedicated ATE is used to indirectly apply high-level (character level or frame level) stimulus to each IO of the chip under test using the communication interface circuit to obtain the high-level response of the chip and compare it with the expected value.

[0005] In AC testing, both output drive and input sampling use timing circuits, either using internal clock timing or external synchronous clock. In the FT testing phase, most single-bus chips do not have clock input signal pins due to the limitation of small packages, and cannot communicate with ATE synchronously. Single-bus chips use internal clocks to communicate with ATE, resulting in clock deviation between the chip to be tested and ATE. When the clock deviation accumulates to a certain extent, it causes communication failure with ATE or power failure of the chip to be tested, resulting in FT test failure, affecting the actual yield of FT testing and failing to increase chip production costs.

[0006] In the prior art, a dedicated ATE with a matching function is used to realize the communication between the chip to be tested and the ATE. However, the dedicated ATE equipment with a matching function is expensive and has requirements and restrictions on the ATE used in production. In addition, the dedicated ATE does not support the matching function for each digital IO channel, which affects the parallel number of chips to be tested in the FT test, thereby reducing the FT test efficiency.

[0007] Therefore, it is necessary to provide a chip detection circuit and a chip detection method thereof to solve the communication problem between the single-bus chip to be detected and the general ATE, so as to improve the accuracy and efficiency of the chip FT test. Summary of the invention

[0008] The present invention provides a chip detection circuit and a chip detection method to improve the accuracy and efficiency of chip FT testing.

[0009] According to one aspect of the present invention, a chip detection circuit is provided, the chip detection circuit comprising: a chip detection device ATE, a single bus protocol conversion processor, and a chip to be detected; wherein:

[0010] The ATE is connected to the single bus protocol conversion processor, and the single bus protocol conversion processor is connected to the chip to be detected;

[0011] When performing a first detection on the chip to be detected, the single bus protocol conversion processor performs single bus protocol conversion on the transmission data between the ATE and the chip to be detected.

[0012] Optionally, the chip detection circuit further includes: a plurality of circuit switching switches;

[0013] The ATE is connected to the single bus protocol conversion processor via a first circuit switching switch, and the chip to be detected is connected to the single bus protocol conversion processor via a second circuit switching switch;

[0014] When performing the first detection on the chip to be detected, the first circuit switching switch is turned on to connect the ATE with the single bus protocol conversion processor, and the second circuit switching switch is turned on to connect the single bus protocol conversion processor with the chip to be detected.

[0015] Optionally, the chip detection circuit further includes: when performing a second detection on the chip to be detected, the first circuit switching switch and the second circuit switching switch are both disconnected, so that the ATE is directly connected to the chip to be detected.

[0016] Optionally, in the chip detection circuit, ATE is directly connected to the chip to be tested to perform short circuit, open circuit, leakage current and power tests in DC tests.

[0017] Optionally, in the chip detection circuit, a power supply DPS in the ATE is connected to the chip to be detected through a third circuit switching switch.

[0018] Optionally, the chip detection circuit also includes: when the power consumption test in the first detection is performed on the chip to be detected, the third circuit switching switch is turned on to connect the power supply in the ATE to the chip to be detected, so as to power the chip to be detected through the power supply in the ATE.

[0019] Optionally, the chip detection circuit further includes: a capacitor; the capacitor is connected to the chip to be detected through a third circuit switching switch;

[0020] When the chip to be detected is subjected to a functional test in the first test, the third circuit switching switch is disconnected, so that the capacitor is connected to the chip to be detected, so as to supply power to the chip to be detected through the capacitor.

[0021] Optionally, the interface communication mode between the ATE and the single bus protocol conversion processor is synchronous communication.

[0022] According to another aspect of the present invention, a chip detection method is provided. The chip detection method is applied to a chip detection circuit provided in any embodiment of the present invention. The chip detection method includes:

[0023] When the first detection is performed on the chip to be detected, the transmission data between the ATE and the chip to be detected is converted into a single bus protocol by the single bus protocol conversion processor.

[0024] Optional chip detection method, including:

[0025] The ATE is connected to the single bus protocol conversion processor via a first circuit switching switch, and the chip to be detected is connected to the single bus protocol conversion processor via a second circuit switching switch;

[0026] When the first detection is performed on the chip to be detected, the first circuit switch and the second circuit switch are controlled to be turned on, so that the ATE, the single bus protocol conversion processor and the chip to be detected are connected in sequence.

[0027] Optional chip detection method, including:

[0028] When the chip to be detected is subjected to the second detection, the first circuit switch and the second circuit switch are controlled to be disconnected, so that the ATE is directly connected to the chip to be detected.

[0029] The technical solution of the embodiment of the present invention is to set up a chip detection circuit including chip detection equipment ATE, a single-bus protocol conversion processor, and a chip to be detected, wherein: ATE is connected to the single-bus protocol conversion processor, and the single-bus protocol conversion processor is connected to the chip to be detected; when the first detection is performed on the chip to be detected, the single-bus protocol conversion processor performs single-bus protocol conversion on the transmission data between ATE and the chip to be detected, thereby solving the communication problem between the single-bus chip to be detected and the general ATE. By performing protocol conversion through the single-bus protocol conversion processor, reliable clock communication between ATE and the chip to be detected can be guaranteed, thereby improving the chip detection accuracy; by introducing the single-bus protocol conversion processor, ATE can perform parallel detection on multiple chips to be detected through each IO channel, thereby improving the chip detection efficiency.

[0030] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 is a schematic diagram of the structure of a chip detection circuit provided according to an embodiment of the present invention;

[0033] Figure 2 is a schematic diagram of the structure of a chip detection circuit provided according to an embodiment of the present invention;

[0034] Figure 3 is a schematic diagram of the structure of a chip detection circuit provided according to an embodiment of the present invention;

[0035] Figure 4 It is a flowchart of a chip detection method provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] Figure 1 1 is a schematic diagram of a chip detection circuit according to an embodiment of the present invention. This embodiment is applicable to the case of performing FT detection on a chip. Figure 1 As shown, the chip detection circuit includes: a chip detection device ATE 110, a single bus protocol conversion processor 120, and a chip to be detected 130.

[0039] Among them, ATE is connected to the single bus protocol conversion processor, and the single bus protocol conversion processor is connected to the chip to be detected; when performing the first detection on the chip to be detected, the single bus protocol conversion processor performs single bus protocol conversion on the transmission data between ATE and the chip to be detected.

[0040] When the first detection is performed on the chip to be detected, the connection channels among the ATE, the single bus protocol conversion processor and the chip to be detected are turned on to form a first detection channel for the chip to be detected.

[0041] In an embodiment of the present invention, the chip to be detected may be a single bus chip, that is, an integrated circuit chip (IC) with a single bus communication interface. The single signal line of the single bus chip provides both power and data transmission, and has strict timing requirements for communication. If the timing requirements are not met in the single bus chip, it may cause communication failure or chip power failure, resulting in chip detection failure.

[0042] The first test can be an FT test. Specifically, the first test can be an AC test in an FT test. The main function of the AC test is to use the test vector (PATTERN) stored in the ATE to generate the input signal required for the unit under test (UUT) through the ATE timing generator module (TimingGenerator), the waveform format module (Waveform Formatter) and the signal level driver module (Driver); at the same time, the output signal of the UUT is also compared with the expected value stored in the ATE through the ATE signal comparison module (Comparator), the timing generator module and the processor (Sequencer) to test whether the output signal of the UUT is normal. The AC test can use the test vector stored in the ATE. The test vector is a language that the integrated circuit tester can understand, and is stored in the memory of the ATE after compilation. The test vector can be generated using the chip's behavioral level simulation software (Design For Test, DFT).

[0043] The single bus protocol conversion unit (SPCU) can realize single bus communication, control timing, and protocol conversion. Specifically, the SPCU may have a microcontroller (MCU). Through the high-flexibility programming of the MCU, single bus communication, control timing, and protocol conversion can be realized. That is, the MATCH function of the original dedicated ATE is instantiated as SPCU through MCU programming to solve the problems of single bus communication, control timing, and protocol conversion. Even if the general ATE does not have the MATCH function, the SPCU can be used to ensure the timing requirements of the ATE and the chip to be tested, thereby improving the FT test yield.

[0044] The single-bus communication bus not only provides power to the UUT, but also requires communication and interaction between ATE and UUT, and has strictly controlled timing. If the UUT timing is faster than ATE, ATE will delay receiving the UUT response data error; if the UUT timing is slower than ATE, ATE will receive the UUT response data in advance, which may cause the UUT chip to lose power. Since ATE is precisely timed, and UUT uses the internal clock as the system clock, the actual production process deviation of the UUT will cause a certain deviation in the internal clock of each UUT chip to be tested, which will affect the UUT to execute a certain function for a longer time or the UUT returns more response data bytes. When the timing accumulates to a certain extent, it causes the single-bus communication with ATE to fail or the UUT chip to lose power, resulting in FT test failure, which ultimately affects the yield of the FT test. In the embodiment of the present invention, the SPCU performs single-bus protocol conversion on the ATE transmission data and performs single-bus decoding on the UUT output data, which can avoid the above-mentioned internal clock deviation problem of the UUT, thereby improving the accuracy of the FT test.

[0045] The first detection channel may be a detection circuit for performing an AC test in a FT test of a UUT. Figure 1 As shown, the connection channels among ATE, the single bus protocol conversion processor and the chip to be detected are turned on.

[0046] In an embodiment of the present invention, ATE is used to send a first detection command and transmit the first detection command to a single bus protocol conversion processor. Specifically, ATE can convert the pattern into a timing signal and an electrical signal and output it to the single bus protocol conversion processor to implement input driving of the IO port of the UUT.

[0047] In an optional implementation of an embodiment of the present invention, in order to simplify the communication between ATE and the single bus protocol conversion processor, the interface communication mode between ATE and the single bus protocol conversion processor is synchronous communication. That is, ATE transmits the first detection command to the single bus protocol conversion processor through synchronous communication. The use of synchronous communication is simpler than the use of asynchronous communication, and can simplify the PATTERN program and speed up the FT import time. Among them, synchronous communication can be communication protocols such as SPI, I2C and 7816, which is convenient for ATE to use PATTERN timing control.

[0048] The single bus protocol conversion processor is used to perform single bus communication encoding on the first detection command, generate first detection coding information, and transmit the first detection coding information to the chip to be detected. SPCU converts simple synchronous communication into single bus communication with strict timing requirements. In the FT test phase, since ATE uses synchronous communication and SPCU, there are no special requirements for general ATE machines, and no complex MATCH programming is required, which greatly reduces the difficulty of PATTERN programs, reduces the debugging time of FT programs, and reduces the production cost of products in the FT stage. Since SPCU uses MCU as the main control, and MCU programming is highly flexible, it can complete the function of converting synchronous communication to single bus communication. MCU has rich software and hardware resources, and it is easy to solve the problem of communication failure or chip power failure caused by system clock errors in the chip under test.

[0049] like Figure 1 As shown, the SPCU can be set on an external printed circuit board (Load Board, LB) of the ATE. The LB board is a test tool for testing semiconductor chips. There are a series of interfaces and pins on the LB board for connecting the chip under test to the ATE. The LB board also includes some circuits and components for providing test signals and power to ensure that the chip under test can work properly. The LB board is usually used to test and screen chips on the production line to ensure the quality and reliability of the chips.

[0050] In actual applications, a socket for the chip to be tested can be placed on the LB board, and the chip to be tested can be installed on the LB board through the socket. In order to improve the efficiency of FT testing, multiple sockets can be placed on the LB board for testing multiple chips to be tested. Correspondingly, multiple SPCUs can be set on the LB board, which are used to convert the communication protocol when testing each chip to be tested. By testing multiple UUTs through multiple SPCUs, there is no need for ATE to have a MATCH function, which can reduce the number of ATEs in FT testing, improve detection efficiency, and save debugging time.

[0051] The chip to be detected is used to perform single bus communication decoding on the first detection coding information, execute the command to obtain the first response data; encode the first response data using the single bus communication to obtain the first response coding information, and transmit the first response coding information to the single bus protocol conversion processor. The single bus protocol conversion processor is used to perform single bus communication decoding on the first response coding information to obtain the first target response data, and transmit the first target response data to the ATE. The ATE is used to compare the first target response data with the first preset expected data to determine the first detection result of the chip to be detected.

[0052] ATE can determine whether the UUT is working properly by sampling the UUT's output and comparing the results.

[0053] In the technical solution of the embodiment of the present invention, a chip detection circuit including ATE, a single bus protocol conversion processor, and a chip to be detected is set, wherein: when the first detection is performed on the chip to be detected, the connection channels among the ATE, the single bus protocol conversion processor and the chip to be detected are turned on to form a first detection channel for the chip to be detected; the ATE is used to send a first detection command and transmit the first detection command to the single bus protocol conversion processor; the single bus protocol conversion processor is used to perform single bus communication encoding on the first detection command, generate first detection coding information, and transmit the first detection coding information to the chip to be detected; the chip to be detected is used to perform single bus communication decoding on the first detection coding information, execute the command to obtain first response data; the first response data is encoded using the single bus communication to obtain first response coding information, and the first response coding information is transmitted to the single bus protocol conversion processor; The bus protocol conversion processor is used to perform single bus communication decoding on the first response coding information to obtain the first target response data, and transmit the first target response data to the ATE; the ATE is used to compare the first target response data with the first preset expected data to determine the first detection result of the chip to be detected, thereby solving the clock communication problem between the chip to be detected and the general ATE. By performing single bus communication conversion through the SPCU, communication failure due to system clock error or chip power failure between the general ATE and the UUT can be avoided, thereby improving the accuracy of the chip FT test; multiple UUTs can be tested through the SPCU, thereby avoiding the problem that ATE cannot perform protocol conversion on each IO channel, thereby improving the FT test efficiency; in addition, through the technical solution of the embodiment of the present invention, the FT test of the UUT can be realized without using a dedicated ATE with MATCH, thereby reducing the chip test cost.

[0054] Figure 21 is a schematic diagram of a chip detection circuit according to an embodiment of the present invention. This embodiment is a further addition to the above technical solution. The technical solution in this embodiment can be combined with each optional solution in one or more of the above embodiments. Figure 2 As shown, the chip detection circuit includes: a chip detection device ATE 110 , a single bus protocol conversion processor 120 , a chip to be detected 130 and a plurality of circuit switching switches 140 .

[0055] The ATE is connected to the single bus protocol conversion processor via a first circuit switching switch, and the chip to be detected is connected to the single bus protocol conversion processor via a second circuit switching switch.

[0056] When performing the first detection on the chip to be detected, the first circuit switching switch is turned on to connect the ATE to the single bus protocol conversion processor, and the second circuit switching switch is turned on to connect the single bus protocol conversion processor to the chip to be detected.

[0057] ATE, used for sending a first detection command and transmitting the first detection command to a single bus protocol conversion processor; the single bus protocol conversion processor, used for performing single bus communication encoding on the first detection command, generating first detection coding information, and transmitting the first detection coding information to the chip to be detected; the chip to be detected, used for performing single bus communication decoding on the first detection coding information, executing the command to obtain first response data; encoding the first response data using a single bus communication, obtaining first response coding information, and transmitting the first response coding information to the single bus protocol conversion processor; the single bus protocol conversion processor, used for performing single bus communication decoding on the first response coding information, obtaining first target response data, and transmitting the first target response data to ATE; ATE, used for comparing the first target response data with the first preset expected data, and determining a first detection result of the chip to be detected.

[0058] In the technical solution of the embodiment of the present invention, the circuit can be turned on and off by using a plurality of circuit switching switches, wherein the circuit switching switch can be an analog switch or a relay switching switch.

[0059] Take the circuit switching switch as a relay as an example. Figure 3 1 is a schematic diagram of a chip detection circuit according to an embodiment of the present invention. Figure 3 As shown, when performing AC testing in FT detection on UUT, the first circuit switching switch (RLYn) and the second circuit switching switch (RLY1) can be controlled, using the normally open unit of the relay, that is, ATE uses the relay switching circuit to connect SPCU between ATE and UUT.

[0060] When performing AC testing on the chip to be tested, the SPCU can use the ATE's Device Power Supply (DPS) for power supply. DPS is a power supply that provides a voltage source and is also a set of measuring equipment with measurable current values. DPS has a current limiting function to protect the UUT from being burned by the applied current. DPS supplies the power required for the UUT to work and measures whether the static or dynamic current of the IC is normal.

[0061] In an optional implementation of the embodiment of the present invention, Figure 3 As shown, the DPS in the ATE is connected to the chip to be tested through a third circuit switching switch (RLY0).

[0062] By connecting the DPS and the UUT through the third circuit switching switch, multiple types of tests can be implemented when the UUT is subjected to AC testing. In an optional implementation of the embodiment of the present invention, when the power consumption test in the first test is performed on the chip to be tested, the third circuit switching switch is turned on to connect the power supply in the ATE to the chip to be tested, so that the chip to be tested is powered by the power supply in the ATE.

[0063] like Figure 3 As shown, when the power consumption test of the UUT is performed in AC detection, the third circuit switching switch (RLY0) is not controlled and the relay is not energized. The normally closed channel of the relay is used to power the chip to be tested and the SPCU through the DPS in the ATE to perform basic electrical tests on the chip.

[0064] Specifically, Figure 3 As shown, when the power consumption test of the UUT is performed in the AC test, the relay RLY0 is not controlled and is not energized; the relays RLY1 and RLYn are controlled and energized; a channel is formed to connect the ATE and the UUT through the SPCU. At the same time, the DPS in the ATE is used to power the SPCU and the UUT to perform basic electrical tests on the chip.

[0065] In another optional implementation of the embodiment of the present invention, Figure 3 As shown, the chip detection circuit also includes: a capacitor; the capacitor is connected to the chip to be detected through a third circuit switching switch; when the chip to be detected is subjected to a functional test in the first detection, the third circuit switching switch is disconnected, so that the capacitor is connected to the chip to be detected, so as to power the chip to be detected through the capacitor.

[0066] Among them, the functional test can correspond to the actual application scenario of the chip, so using a capacitor to power the UUT is more in line with the actual application scenario. When performing a functional test in the AC test on the UUT, the capacitor can be connected to the UUT through a third circuit switch, that is, the capacitor is used to power the UUT.

[0067] Specifically, Figure 3 As shown, when the UUT is subjected to a functional test in an AC test, relays RLY0, RLY1, and RLYn are all controlled and attracted, forming a channel for connecting ATE with the UUT through the SPCU. At the same time, the DPS in the ATE is used to power the SPCU, and the capacitor is used to power the UUT, so as to perform a functional test on the chip in accordance with the actual application scenario.

[0068] In the technical solution of the embodiment of the present invention, multiple circuit switching switches can be used to implement not only AC testing in FT testing of the chip, but also direct current (DC) testing in FT testing. DC testing uses the parameter measurement unit (PMU) in ATE to measure the leakage current, input and output working current and voltage of the UUT related to the IC. PMU is a set of measuring equipment that can measure current and voltage values.

[0069] In an optional implementation of the embodiment of the present invention, when the second detection is performed on the chip to be detected, the first circuit switch and the second circuit switch are both disconnected, so that the ATE is directly connected to the chip to be detected.

[0070] When performing DC testing on the chip, the test environment requires that the ATE and UUT establish a direct electrical connection, and there is no other circuit outside the UUT, which retains the advantages of ATE's DC testing. Figure 3 As shown, relay switches RLY0, RLY1, and RLYn are not controlled, and the normally closed units of the respective relays are used. When performing DC testing, there is no need to use the SPCU.

[0071] In an optional implementation of the embodiment of the present invention, the ATE is directly connected to the chip to be tested to perform short circuit, open circuit, leakage current and power tests in the DC test.

[0072] In practical applications, the open circuit and short circuit test (OpenShort, O / S) in the DC test can be placed at the first step of chip detection as the basis for subsequent detection. After the O / S test, only the leakage current test is left. After that, the AC test of the UUT can be achieved by controlling multiple circuit switching switches.

[0073] It should be noted that when testing the chip to be detected, multiple chips can be tested in parallel, and the number of first circuit switching switches (RLYn), the number of second circuit switching switches (RLY1), and the number of SPCUs can be increased. Figure 3The chip detection circuit shown can be adjusted accordingly. For example, each SPCU can use channel 0 and channel 1 to receive the PATTERN of ATE; each SPCU can be connected to ATE through the channel n of the corresponding first circuit switching switch (RLYn); each SPCU can be connected to the corresponding UUT through the corresponding second circuit switching switch (RLY1). Each circuit switching switch can receive a switch control signal, for example, RLYn receives a Kn signal, RLY1 receives a K1 signal, and RLY0 receives a K0 signal. DPS can provide power signals DPS_F0, DPS_F1 and DPS_Fn to power the SPCU and UUT. The specific connection circuit can be as follows Figure 3 shown.

[0074] In the technical solution of the embodiment of the present invention, a chip detection circuit is set up including a chip detection device ATE, a single bus protocol conversion processor, a chip to be detected and a plurality of circuit switching switches, wherein the ATE is connected to the single bus protocol conversion processor through a first circuit switching switch, and the chip to be detected is connected to the single bus protocol conversion processor through a second circuit switching switch; when performing a first detection on the chip to be detected, the first circuit switching switch and the second circuit switching switch are controlled to connect the connection channels between the ATE, the single bus protocol conversion processor and the chip to be detected, thereby forming a first detection channel for the chip to be detected; when performing a second detection on the chip to be detected, the first circuit switching switch and the second circuit switching switch are controlled to connect the connection channels between the ATE and the chip to be detected, thereby forming a second detection channel for the chip to be detected. Two detection channels; the power supply DPS in the ATE is connected to the chip to be detected through the third circuit switching switch; when the power consumption test in the first detection is performed on the chip to be detected, the third circuit switching switch is controlled to connect the connection channel between the power supply in the ATE and the chip to be detected, so as to power the chip to be detected through the power supply in the ATE; the capacitor is connected to the chip to be detected through the third circuit switching switch; when the functional test in the first detection is performed on the chip to be detected, the third circuit switching switch is controlled to connect the connection channel between the capacitor and the chip to be detected, so as to power the chip to be detected through the capacitor, which solves the FT test problem of the chip to be detected, can take into account both DC test and AC test, improve the accuracy and efficiency of chip FT test, reduce ATE cost in FT test, and make chip test closer to user scenarios.

[0075] Figure 4 The figure is a flow chart of a chip detection method provided according to an embodiment of the present invention. The chip detection method provided by the embodiment of the present invention can be applied to the chip detection circuit provided by any embodiment of the present invention.

[0076] like Figure 4As shown, the chip detection method includes: when performing a first detection on the chip to be detected, performing a single bus protocol conversion on the transmission data between the ATE and the chip to be detected by the single bus protocol conversion processor.

[0077] Specifically, when the first detection is performed on the chip to be detected, the connection channels of ATE, single bus protocol conversion processor and chip to be detected are turned on to form the first detection channel of the chip to be detected. The first detection command is sent by ATE, and the first detection command is transmitted to the single bus protocol conversion processor. The first detection command is encoded by the single bus communication by the single bus protocol conversion processor to generate first detection coding information, and the first detection coding information is transmitted to the chip to be detected. The first detection coding information is decoded by the chip to be detected by single bus communication, and the command is executed to obtain the first response data; the first response data is encoded by single bus communication to obtain the first response coding information, and the first response coding information is transmitted to the single bus protocol conversion processor. The first response coding information is decoded by the single bus communication by the single bus protocol conversion processor to obtain the first target response data, and the first target response data is transmitted to the ATE. The first target response data is compared with the first preset expected data by ATE to determine the first detection result of the chip to be detected.

[0078] On the basis of the above implementation mode, optionally, the chip detection method also includes: ATE is connected to the single bus protocol conversion processor through a first circuit switching switch, and the chip to be detected is connected to the single bus protocol conversion processor through a second circuit switching switch; when performing a first detection on the chip to be detected, the first circuit switching switch and the second circuit switching switch are controlled to be turned on, so that the ATE, the single bus protocol conversion processor and the chip to be detected are connected in sequence.

[0079] On the basis of the above implementation, optionally, the chip detection method further includes: when performing a second detection on the chip to be detected, controlling the first circuit switching switch and the second circuit switching switch to be disconnected so that the ATE is directly connected to the chip to be detected.

[0080] On the basis of the above implementation manner, optionally, the chip detection method further includes: directly connecting to the chip to be tested through ATE to perform short circuit, open circuit, leakage current and power tests in DC tests.

[0081] On the basis of the above implementation, optionally, the power supply DPS in the ATE is connected to the chip to be detected through a third circuit switching switch.

[0082] On the basis of the above implementation manner, optionally, the chip detection method further includes: when performing a power consumption test in a first detection on the chip to be detected, controlling the third circuit switching switch to be turned on, so that the power supply in the ATE is connected to the chip to be detected, so as to power the chip to be detected through the power supply in the ATE.

[0083] Based on the above implementation mode, optionally, the capacitor is connected to the chip to be detected through a third circuit switching switch; the chip detection method also includes: when performing a functional test on the chip to be detected in the first detection, controlling the third circuit switching switch to be turned on, so that the capacitor is connected to the chip to be detected, so as to power the chip to be detected through the capacitor.

[0084] Based on the above implementation, optionally, the interface communication mode between the ATE and the single bus protocol conversion processor is synchronous communication.

[0085] The technical solution of the embodiment of the present invention is as follows: when performing the first detection on the chip to be detected, the connection channels of ATE, a single-bus protocol conversion processor and the chip to be detected are turned on to form the first detection channel of the chip to be detected; the first detection command is sent by the ATE, and the first detection command is transmitted to the single-bus protocol conversion processor; the first detection command is encoded by the single-bus communication by the single-bus protocol conversion processor to generate first detection coding information, and the first detection coding information is transmitted to the chip to be detected; the first detection coding information is decoded by the chip to be detected by the single-bus communication, and the command is executed to obtain the first response data; the first response data is encoded by the single-bus communication to obtain the first response coding information, and the first response coding information is transmitted to the single-bus protocol conversion processor; the first response coding information is decoded by the single-bus communication by the single-bus protocol conversion processor to obtain the first target response data, and the first target response data is transmitted to the ATE; the first target response data is compared with the first preset expected data by the ATE to determine the first detection result of the chip to be detected, thereby solving the clock communication problem between the chip to be detected and the general ATE, and improving the accuracy and efficiency of the chip FT test.

[0086] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0087] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip detection circuit, characterized in that: The chip detection circuit comprises: a chip detection device ATE, a single bus protocol conversion processor, and a chip to be detected; wherein: The ATE is connected to the single bus protocol conversion processor, and the single bus protocol conversion processor is connected to the chip to be detected; When performing a first detection on the chip to be detected, the single bus protocol conversion processor performs single bus protocol conversion on the transmission data between the ATE and the chip to be detected.

2. The chip detection circuit according to claim 1, characterized in that: Also includes: Multiple circuit switching switches; The ATE is connected to the single bus protocol conversion processor via a first circuit switching switch, and the chip to be detected is connected to the single bus protocol conversion processor via a second circuit switching switch; When performing the first detection on the chip to be detected, the first circuit switching switch is turned on to connect the ATE with the single bus protocol conversion processor, and the second circuit switching switch is turned on to connect the single bus protocol conversion processor with the chip to be detected.

3. The chip detection circuit according to claim 2, characterized in that: When the chip to be detected is subjected to a second detection, both the first circuit switch and the second circuit switch are disconnected, so that the ATE is directly connected to the chip to be detected.

4. The chip detection circuit according to claim 3, characterized in that: ATE is directly connected to the chip under test to perform short circuit, open circuit, leakage current and power tests in DC tests.

5. The chip detection circuit according to claim 2, characterized in that: The power supply DPS in the ATE is connected to the chip to be tested through a third circuit switching switch.

6. The chip detection circuit according to claim 5, characterized in that: When the power consumption test in the first test is performed on the chip to be tested, the third circuit switching switch is turned on to connect the power supply in the ATE to the chip to be tested, so as to supply power to the chip to be tested through the power supply in the ATE.

7. The chip detection circuit according to claim 5, characterized in that: Also includes: capacitance; The capacitor is connected to the chip to be detected through a third circuit switching switch; When the chip to be detected is subjected to a functional test in the first test, the third circuit switching switch is disconnected, so that the capacitor is connected to the chip to be detected, so as to supply power to the chip to be detected through the capacitor.

8. The chip detection circuit according to claim 1, characterized in that: The interface communication mode between ATE and the single bus protocol conversion processor is synchronous communication.

9. A chip detection method, characterized in that: The chip detection method is applied to the chip detection circuit according to any one of claims 1 to 8, and the chip detection method includes: When the first detection is performed on the chip to be detected, the transmission data between the ATE and the chip to be detected is converted into a single bus protocol by the single bus protocol conversion processor.

10. The method according to claim 9, characterized in that The ATE is connected to the single bus protocol conversion processor via a first circuit switching switch, and the chip to be detected is connected to the single bus protocol conversion processor via a second circuit switching switch; When the first detection is performed on the chip to be detected, the first circuit switch and the second circuit switch are controlled to be turned on, so that the ATE, the single bus protocol conversion processor and the chip to be detected are connected in sequence.

11. The method according to claim 10, characterized in that When the chip to be detected is subjected to the second detection, the first circuit switch and the second circuit switch are controlled to be disconnected, so that the ATE is directly connected to the chip to be detected.

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