High-reliability high-voltage on-chip power supply circuit

Abstract

The invention discloses a high-reliability high-voltage on-chip power supply circuit, which belongs to the field of integrated circuit on-chip power supply anti-electromagnetic interference, and comprises a voltage pre-stabilizing circuit, a low dropout regulator (LDO) circuit, an on-chip power supply dual-detection circuit and a detection judgment circuit, the pre-voltage-stabilizing circuit is electrically connected with the starting circuit and the band-gap reference circuit; the band-gap reference circuit is connected with the error amplifier circuit, the band-gap reference voltage value detection circuit and the internal power supply detection circuit, the error amplifier circuit is connected with the power tube circuit, and the band-gap reference voltage value detection circuit and the internal power supply detection circuit are both connected with the output end of the LDO circuit. The internal power supply detection circuit is connected with the negative feedback circuit, and the band-gap reference voltage value detection circuit and the internal power supply detection circuit are connected with the detection judgment circuit. Interference of interference signals on an internal system is reduced; detection is carried out by using a double-detection design scheme, so that correct realization of chip functions is ensured, and higher robustness and anti-interference performance are achieved.

Description

Technical Field

[0001] The present invention relates to the field of electromagnetic interference resistance of integrated circuit on-chip power supplies, and specifically to a high-reliability high-voltage on-chip power supply circuit, especially designed for the resistance of automotive-grade chips to radio frequency interference. Background Art

[0002] The environments where automotive-grade chips are subject to RF interference in automotive electronic systems are very diverse, as they are exposed to a wide range of electromagnetic spectra during operation, including high-frequency communication signals, switching noise from electric motors and power converters, and radio waves in the environment. Sources of RF interference and countermeasures It is crucial to improve the anti-interference ability of automotive-grade chips. There are many common sources of RF interference, and the electromagnetic environment faced by cars in different usage environments is also different. For example, in urban environments, due to the dense signal towers, Wi-Fi hotspots and other wireless communication devices, electromagnetic interference sources are densely distributed, while in rural and remote areas, there is less environmental electromagnetic interference, but solar activity and lightning weather may generate electromagnetic pulse interference. In the car itself, there are also various electromagnetic disturbances, such as high-frequency communication modules, vehicle-mounted 4G / 5G communication modules, Wi-Fi, Bluetooth, etc. Since these modules transmit and receive high-frequency signals, the frequency is at the GHz level, with strong electromagnetic radiation and reception capabilities, they are prone to electromagnetic interference to other electronic systems. Electric motors and power systems are also sources of a large amount of RF interference, such as DC-DC converters and on-board chargers in cars. High-frequency switching converters will generate a large amount of RF interference, and oscillations and switching noise during motor driving will also generate a large amount of disturbances. Due to the particularity of automotive chips used in transportation vehicles, they have very high requirements for reliability, environmental adaptability, electromagnetic compatibility, and electrical resistance. In order to ensure that automotive chips can function correctly, it is also necessary to design a stable on-chip power supply with high anti-interference capabilities.

[0003] Most of the existing circuit anti-interference solutions are reflected on the layout. Usually, voltage stabilization circuits, LDO and other circuits are used to isolate the external power supply from the internal circuit, and power management units such as LDO are used to generate stable power to power the internal circuit. In addition, the detection module is designed to detect a certain voltage node, such as the output branch of the internal power supply. The problem with a single detection is that the circuit may not work properly but the result indicates that the circuit is normal, that is, there is a possibility of misjudgment of the circuit power supply status, which will affect the operation of other subsequent circuits such as digital circuits, and then affect the normal operation of the entire chip. The robustness of such a designed circuit is poor and needs to be further improved. Summary of the invention

[0004] With regard to the above problems existing in the prior art, the object of the present invention is to provide a high-reliability high-voltage on-chip power supply circuit to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A high-reliability high-voltage on-chip power supply circuit, comprising a pre-regulator and startup circuit, a low-dropout linear regulator LDO circuit, an on-chip power supply dual detection circuit and a detection judgment circuit;

[0007] The pre-stabilization and startup circuit includes a pre-stabilization circuit and a startup circuit. The pre-stabilization circuit is internally provided with a first filter circuit, a second filter circuit, and a third filter circuit for filtering high-frequency clutter; the low-voltage difference linear regulator LDO circuit includes a bandgap reference circuit, an error amplifier circuit, a power tube circuit, and a negative feedback circuit; both the pre-stabilization circuit and the power tube circuit are internally provided with a high-voltage NMOS tube for high-voltage isolation; the on-chip power supply dual detection circuit includes a bandgap reference voltage value detection circuit and an internal power supply detection circuit, and the on-chip power supply dual detection circuit is used to perform dual detection and judgment on the output of the low-voltage difference linear regulator LDO circuit and the bandgap reference circuit; the detection and judgment circuit includes a first AND gate circuit and an RC filter circuit; after the dual detection results are logically judged by an AND gate circuit, the judgment results are filtered by a low-pass filter circuit as the final output judgment result;

[0008] The power input terminal of the pre-stabilizing circuit is connected to the power supply VBAT, and the ground terminal of the pre-stabilizing circuit is grounded; the output terminal of the pre-stabilizing circuit is connected to the power input terminal of the startup circuit and the power input terminal of the bandgap reference circuit; the output terminal of the pre-stabilizing circuit outputs the power supply Vbg_sup;

[0009] The output end of the startup circuit is connected to the input end of the bandgap reference circuit;

[0010] One output end of the bandgap reference circuit is connected to the positive input end of the error amplifier circuit and the input end of the bandgap reference voltage value detection circuit at the same time, and one output end of the bandgap reference circuit outputs a first reference voltage Vbg; another output end of the bandgap reference circuit is connected to the signal input end of the internal power supply detection circuit, and another output end of the bandgap reference circuit outputs a second reference voltage Vbg0; and a ground end of the bandgap reference circuit is grounded;

[0011] The power input end of the error amplifier circuit is connected to the power supply VBAT; the negative input end of the error amplifier circuit is connected to the feedback output end Vfb of the negative feedback circuit; the output end of the error amplifier circuit is connected to the gate of the MOS tube MN0 in the power tube circuit, and the drain of the MOS tube MN0 is connected to the power supply VBAT; the source of the MOS tube MN0 is connected to the negative feedback circuit; the source of the MOS tube MN0 outputs a voltage Vdig; the output end of the error amplifier outputs a voltage Vout_EA; the source of the MOS tube MN0 of the power tube circuit is the voltage output end of the low voltage difference linear regulator LDO circuit;

[0012] The negative feedback circuit includes a resistor R1, a resistor R2, a resistor R3 and a resistor R4, which are connected in series in sequence, one end of the resistor R1 is connected to the source of the MOS tube MN0, and the other end of the resistor R4 is grounded; the feedback output terminal Vfb is between the resistor R1 and the resistor R2;

[0013] The power input end of the bandgap reference voltage value detection circuit and the power input end of the internal power detection circuit are both connected to the source of the MOS tube MN0 in the power tube circuit, and the output voltage of the power tube circuit supplies power to the bandgap reference voltage value detection circuit and the internal power detection circuit;

[0014] The output end of the bandgap reference voltage value detection circuit is connected to the internal power supply detection circuit; the output end of the bandgap reference voltage value detection circuit outputs a signal Vbg_ok as an enable signal of the internal power supply detection circuit; the bandgap reference voltage value detection circuit detects a first reference voltage Vbg outputted by the bandgap reference circuit, and the internal power supply detection circuit is used to detect the output voltage of the low voltage difference linear regulator LDO circuit;

[0015] The input end of the internal power supply detection circuit is connected to the common operation terminal of the single-pole double-throw switch, and the main contact and the auxiliary contact of the single-pole double-throw switch are connected in parallel to the two ends of the resistor R3 of the negative feedback circuit; the two ends of the resistor R3 output the first detection voltage Vdig_porn_L and the second detection voltage Vdig_porn_H respectively; the output end of the bandgap reference voltage value detection circuit is connected to one input end of the AND gate AND of the first AND gate circuit, the output end of the internal power supply detection circuit is connected to the other input end of the AND gate AND of the first AND gate circuit, and the output end of the internal power supply detection circuit outputs a signal Vdig_ok;

[0016] The output end of the AND gate AND of the first AND gate circuit is connected to the input end of the RC filter circuit, and the output end of the RC filter circuit outputs the final control signal V_porn;

[0017] The power input end of the AND gate AND and the RC filter circuit are both connected to the source of the MOS tube MN0 of the power tube circuit.

[0018] As a further solution of the present invention: the pre-stabilization circuit (11) comprises a first filter circuit, a second filter circuit, a third filter circuit, a resistor R0, a resistor R5, a resistor R6, a resistor R7, a MOS transistor MN1, a MOS transistor MN2 and a MOS transistor MN3; the first filter circuit is a filter capacitor C1, the second filter circuit is a filter capacitor C2, and the third filter circuit is a filter capacitor C0;

[0019] One end of the resistor R0 is connected to the power supply VBAT, and the other end of the resistor R0 is simultaneously connected to the gate of the MOS transistor MN1, the gate of the MOS transistor MN3, and the drain of the MOS transistor MN2; the source of the MOS transistor MN2 is grounded; the filter capacitor C1 in the first filter circuit is connected in parallel between the source of the MOS transistor MN2 and the drain of the MOS transistor MN2;

[0020] The source of the MOS transistor MN1 is connected to one end of the resistor R5, the resistors R5, R6 and R7 are connected in series in sequence, the gate of the MOS transistor MN2 is connected to one end of the resistor R7, the other end of the resistor R7 is grounded, and the filter capacitor C2 in the second filter circuit is connected in parallel to both ends of the resistor R7;

[0021] The source of the MOS tube MN3 is connected to one end of the filter capacitor C0 in the third filter circuit, and the other end of the filter capacitor C0 is grounded;

[0022] The drain of the MOS transistor MN1 and the drain of the MOS transistor MN3 are connected to the power supply VBAT.

[0023] As a further solution of the present invention: the error amplifier circuit includes a resistor R8, a resistor R9, a fourth filter circuit, a MOS tube MP0, a MOS tube MP1, a MOS tube MN6, a MOS tube MN7, a MOS tube MN4, and a MOS tube MN5; the fourth filter circuit is a filter capacitor C3;

[0024] One end of the resistor R8 is connected to the power supply VBAT, and the other end of the resistor R8 is connected to the source of the MOS tube MP0; one end of the resistor R9 is connected to the power supply VBAT, and the other end of the resistor R9 is connected to the source of the MOS tube MP1; one end of the filter capacitor C3 in the fourth filter circuit is connected to the power supply VBAT, and the other end of the filter capacitor C3 is connected to the gate of the MOS tube MP0 and the gate of the MOS tube MP1;

[0025] The gate of the MOS tube MP0 is connected to the drain of the MOS tube MP0, the drain of the MOS tube MN6, and the gate of the MOS tube MP1. The drain of the MOS tube MP1 is connected to the drain of the MOS tube MN7. The drain of the MOS tube MP1 is the output end of the error amplifier circuit. The drain of the MOS tube MP1 outputs the voltage Vout_EA.

[0026] The gate of the MOS tube MN6 is connected to the gate of the MOS tube MN7; the source of the MOS tube MN6 is connected to the drain of the MOS tube MN4, and the source of the MOS tube MN7 is connected to the drain of the MOS tube MN5;

[0027] The source of the MOS transistor MN4 and the source of the MOS transistor MN5 are connected to the current source I0 , and the ground terminal of the current source I0 is grounded.

[0028] As a further solution of the present invention: the MOS transistors MP0, MP1, MN1, MN3, MN6 and MN7 are high-voltage transistors, and the MOS transistors MN2, MN4 and MN5 are low-voltage transistors.

[0029] As a further solution of the present invention: the two output terminals of the bandgap reference circuit are connected interchangeably.

[0030] As a further solution of the present invention: the RC filter circuit is replaced by two sets of inverters connected in series, or the RC filter circuit is deleted.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] The pre-stabilizing circuit of the present invention is combined with the working characteristics of the high-voltage NMOS transistor to separate the high interference signal from the internal power supply system, and minimize its interference to the internal system; the internal bandgap reference voltage output is additionally detected by the bandgap reference voltage detection circuit, and a dual detection design scheme is used to replace the traditional single detection scheme. When and only when the bandgap reference voltage detection is accurate and the internal power supply voltage detection is completed at the same time, the final detection signal output is obtained to provide a reset signal for the digital circuit inside the chip, thereby ensuring the correct implementation of the chip function. Therefore, the present invention has higher robustness and anti-interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 The present invention is a schematic diagram of a circuit framework of a high-reliability high-voltage on-chip power supply circuit disclosed in an embodiment.

[0034] Figure 2 The present invention is a specific circuit diagram of a high-reliability high-voltage on-chip power supply circuit disclosed in an embodiment.

[0035] Figure 3 The present invention is a circuit diagram of a pre-voltage regulator circuit in a high-reliability high-voltage on-chip power supply circuit disclosed in an embodiment.

[0036] Figure 4 The present invention is a circuit diagram of an error amplifier circuit in a high-reliability high-voltage on-chip power supply circuit disclosed in an embodiment.

[0037] The reference numerals in the figure are: 1. pre-voltage stabilization and startup circuit; 11. pre-voltage stabilization circuit; 111. first filter circuit; 112. second filter circuit; 113. third filter circuit; 12. startup circuit; 2. low-dropout linear regulator LDO circuit; 21. bandgap reference circuit; 22. error amplifier circuit; 221. fourth filter circuit; 23. power tube circuit; 24. negative feedback circuit; 3. on-chip power supply dual detection circuit; 31. bandgap reference voltage value detection circuit; 32. internal power supply detection circuit; 4. detection and determination circuit; 41. first AND gate circuit; 42. RC filter circuit. DETAILED DESCRIPTION

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention; it is obvious that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", and "connected" should be understood in a broad sense; for example, it can be a fixed connection, a detachable connection, or an integral connection, a mechanical connection, or an electrical connection, a direct connection, or an indirect connection through an intermediate medium, or the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] See also Figure 1-4 , a high-reliability high-voltage on-chip power supply circuit, comprising a pre-regulator and startup circuit 1, a low-dropout linear regulator LDO circuit 2, an on-chip power supply dual detection circuit 3 and a detection determination circuit 4;

[0041] The pre-stabilization and startup circuit 1 includes a pre-stabilization circuit 11 and a startup circuit 12. The pre-stabilization circuit 11 is internally provided with a first filter circuit 111, a second filter circuit 112, and a third filter circuit 113 for filtering high-frequency noise; the low-dropout linear regulator LDO circuit 2 includes a bandgap reference circuit 21, an error amplifier circuit 22, a power tube circuit 23, and a negative feedback circuit 24; the pre-stabilization circuit 11 and the power tube circuit 23 are internally provided with a high-voltage NMOS tube for high-voltage isolation; for the LDO module, since it is a high-voltage circuit design, compared with other on-chip LDO solutions, such as: making the LDO in the low-voltage domain, or combining with a charge pump +LDO, etc. In the structure selected in this paper, the direct error amplifier is directly made in the high-voltage domain, which reduces the design of some circuits and effectively reduces the chip area; the on-chip power dual detection circuit 3 includes a bandgap reference voltage value detection circuit 31 and an internal power detection circuit 32. The on-chip power dual detection circuit 3 is used to perform dual detection and judgment on the output of the low-voltage difference linear regulator LDO circuit 2 and the bandgap reference circuit 21; the detection and judgment circuit 4 includes a first AND gate circuit 41 and an RC filter circuit 42; after the dual detection results are logically judged by an AND gate circuit 41, the judgment results are filtered by a low-pass filter circuit as the final output judgment result;

[0042] The power input terminal of the pre-stabilizing circuit 11 is connected to the power supply VBAT, and the ground terminal of the pre-stabilizing circuit 11 is grounded; the output terminal of the pre-stabilizing circuit 11 is connected to the power input terminal of the startup circuit 12 and the power input terminal of the bandgap reference circuit 21; the output terminal of the pre-stabilizing circuit 11 outputs the power supply Vbg_sup;

[0043] The output end of the start-up circuit 12 is connected to the input end of the bandgap reference circuit 21, and the start-up circuit 12 controls the start-up of the bandgap reference circuit 21, which facilitates the use of the device. The ground end of the start-up circuit 12 is grounded;

[0044] One output end of the bandgap reference circuit 21 is connected to the positive input end of the error amplifier circuit 22 and the input end of the bandgap reference voltage value detection circuit 31 at the same time, and one output end of the bandgap reference circuit 21 outputs the first reference voltage Vbg; the other output end of the bandgap reference circuit 21 is connected to the input end of the internal power supply detection circuit 32, and the other output end of the bandgap reference circuit 21 outputs the second reference voltage Vbg0; the ground end of the bandgap reference circuit 21 is grounded; the bandgap reference circuit 21 generates the first reference voltage Vbg and the second reference voltage Vbg0, which are used as reference voltages for the error amplifier circuit 22 and the internal power supply detection circuit 32 respectively, and the two functions are the same, and the two output ends of the bandgap reference circuit 21 can be interchanged. The second reference voltage Vbg0 is generated by the first reference voltage Vbg, and can continue to generate reference voltage values ​​of other sizes.

[0045] The power input terminal of the error amplifier circuit 22 is connected to the power supply VBAT; the negative input terminal of the error amplifier circuit 22 is connected to the feedback output terminal Vfb of the negative feedback circuit 24; the output terminal of the error amplifier circuit 22 is connected to the gate of the MOS tube MN0 in the power tube circuit 23, and the drain of the MOS tube MN0 is connected to the power supply VBAT; the source of the MOS tube MN0 is connected to the negative feedback circuit 24; the source of the MOS tube MN0 outputs a voltage Vdig; the output terminal of the error amplifier outputs a voltage Vout_EA;

[0046] The source of the MOS tube MN0 of the power tube circuit 23 is the power output terminal of the low voltage difference linear regulator LDO;

[0047] The negative feedback circuit 24 includes a resistor R1, a resistor R2, a resistor R3 and a resistor R4, which are connected in series in sequence, one end of the resistor R1 is connected to the source of the MOS tube MN0, and the other end of the resistor R4 is grounded; the feedback output terminal Vfb is between the resistor R1 and the resistor R2; the source end of the power tube is connected to the negative feedback circuit to obtain a constant output voltage Vdig, which is used as the output of the low-dropout linear regulator LDO circuit 2 to generate a constant voltage, and is used as the power supply inside the chip to power the bandgap reference voltage value detection circuit 31, the internal power supply detection circuit 32 and other modules inside the chip.

[0048] The power input end of the bandgap reference voltage value detection circuit 31 and the power input end of the internal power detection circuit 32 are both connected to the source of the MOS tube MN0 in the power tube circuit 23, and the power tube circuit 23 outputs power to supply power to the bandgap reference voltage value detection circuit 31 and the internal power detection circuit 32;

[0049] The output end of the bandgap reference voltage value detection circuit 31 is connected to the internal power supply detection circuit 32; the output end of the bandgap reference voltage value detection circuit 31 outputs a signal Vbg_ok as an enable signal of the internal power supply detection circuit 32; the bandgap reference voltage value detection circuit 31 detects the first reference voltage Vbg outputted from the bandgap reference circuit 21, and the internal power supply detection circuit 32 detects the second reference voltage Vbg0 outputted from the other end of the bandgap reference circuit 21; when the bandgap reference voltage value detection circuit 31 passes the detection of the first reference voltage Vbg, the internal power supply detection circuit 32 is started to detect the second reference voltage Vbg0; the internal power supply detection circuit 32 detects the output voltage of the LDO;

[0050] The input end of the internal power supply detection circuit 32 is connected to the common operation terminal of the single-pole double-throw switch, and the main contact and the auxiliary contact of the single-pole double-throw switch are connected in parallel to the two ends of the resistor R3 of the negative feedback circuit 24; the two ends of the resistor R3 output the first detection voltage Vdig_porn_L and the second detection voltage Vdig_porn_H respectively; the output end of the bandgap reference voltage value detection circuit 31 is connected to one input end of the AND gate AND of the first AND gate circuit 41, the output end of the internal power supply detection circuit 32 is connected to the other input end of the AND gate AND of the first AND gate circuit 41, and the output end of the internal power supply detection circuit 32 outputs a signal Vdig_ok;

[0051] The output end of the AND gate AND of the first AND gate circuit 41 is connected to the input end of the RC filter circuit 42, and the output end of the RC filter circuit 42 outputs the final control signal V_porn. The bandgap reference voltage detection module 31 and the internal power supply detection module circuit 32 detect the bandgap reference voltage value and the output voltage of the LDO respectively. After the results of the two detections are judged by the first AND gate circuit, the final judgment signal is output through the RC filter circuit 42. The judgment signal is used as a reset signal for the digital circuit inside the chip, affecting the normal operation of the entire chip.

[0052] The power input terminals of the AND gate AND and the RC filter circuit 42 are connected to the source of the MOS tube MN0 of the power tube circuit 23, so as to conveniently supply power to the AND gate AND and the RC filter circuit 42, ensure safety, and facilitate the use of the device.

[0053] The anti-interference scheme includes three approaches at the same time. The first is to use NMOS high-voltage tubes to isolate the external power supply from the internal module; the second is to use filter capacitors to filter high-frequency interference signals; the third is to design an accurate voltage detection module to detect the voltage value generated by the bandgap reference, and design a power detection module to detect the output voltage of the on-chip LDO. The detection result value of the voltage value generated by the bandgap reference is also used as an enable signal for the detection module for the output voltage of the on-chip LDO to control whether the internal power detection module works. The detection results of the above two detections are subjected to the "AND" logic operation through the first AND gate circuit. Only when the judgment results are both high levels, that is, Vbg_ok=1, Vdig_ok=1, it indicates that the internal power supply voltage meets the system requirements. Then, the final judgment signal is output through the RC filter circuit. This signal is used as the reset signal of the digital circuit inside the chip to control whether the digital circuit works normally, and then control whether the entire chip works normally.

[0054] In circuit design, high-voltage NMOS transistors are used in the pre-stabilization circuit and the selection of LDO output power tubes. The power supply voltage is disturbed so that it cannot provide a stable voltage value. After the voltage is input to the drain end of the high-voltage NMOS transistor, the output of the source end of the high-voltage NMOS transistor is less affected, that is, the high-voltage NMOS transistors MN1 and MN3 in the pre-stabilization circuit and the high-voltage NMOS power tube MN0 in the low-voltage difference linear regulator LDO isolate the unstable power supply voltage from the internal circuit, playing the role of isolating power supply interference. When the power supply is powered on, the gate end of the high-voltage NMOS transistor MN1, that is, node A, is pulled up to the power supply, and the source end voltage is pulled down to a low level. A voltage difference VGS1 is generated between the gate and source ends, which is greater than the threshold voltage of the MN1 transistor, so that the MN1 transistor is turned on to generate current. After the current flows through the resistors R1, R2, and R3, the voltage of the node at the upper end of the resistor R3 is increased, and the gate end of the low-voltage NMOS transistor MN2 is connected to the node B at the upper end of the resistor R3, so that the gate-source voltage of the transistor MN2 generates a voltage difference VGS2, which is higher than the threshold voltage of the MN2 transistor Voltage is applied to turn on transistor MN2. When the circuit reaches a stable state, the voltage at node A reaches a stable value, that is, the gate voltage of the high-voltage NMOS transistor MN3 reaches a stable value. A low output voltage Vbg_sup is generated through the source terminal of the high-voltage NMOS transistor. The voltage is obtained by subtracting the threshold voltage VTH3 of MN3 from the gate voltage of the high-voltage NMOS transistor. The output is not affected by power supply voltage disturbances, and supplies power to the startup circuit Startup of the internal bandgap reference and the bandgap reference Bandgap module.

[0055] like Figure 3 As shown, the specific pre-stabilization circuit 11 includes a first filter circuit 111, a second filter circuit 112, a third filter circuit 113, a resistor R0, a resistor R5, a resistor R6, a resistor R7, a MOS transistor MN1, a MOS transistor MN2 and a MOS transistor MN3; the first filter circuit 111 is a filter capacitor C1, the second filter circuit 112 is a filter capacitor C2, and the third filter circuit 113 is a filter capacitor C0;

[0056] One end of the resistor R0 is connected to the power supply VBAT, and the other end of the resistor R0 is simultaneously connected to the gate of the MOS transistor MN1, the gate of the MOS transistor MN3, and the drain of the MOS transistor MN2; the drain of the MOS transistor MN1 and the drain of the MOS transistor MN3 are connected to the power supply VBAT; the source of the MOS transistor MN2 is grounded; the filter capacitor C1 in the first filter circuit 111 is connected in parallel between the source of the MOS transistor MN2 and the drain of the MOS transistor MN2;

[0057] The source of the MOS transistor MN1 is connected to one end of the resistor R5, and the resistors R5, R6, and R7 are connected in series in sequence. The gate of the MOS transistor MN2 is connected to one end of the filter capacitor C2 in the second filter circuit 112, and the other end of the filter capacitor C2 is grounded. The filter capacitor C2 is connected in parallel to both ends of the resistor R7.

[0058] The source of the MOS transistor MN1 is connected to one end of the filter capacitor C0 in the third filter circuit 113, and the other end of the filter capacitor C0 is grounded; the source of the MOS transistor MN1 outputs a voltage Vbg_sup;

[0059] The filter capacitor C0 is connected between the output terminal Vbg_sup of the pre-stabilizing circuit and GND to reduce the disturbance of the output terminal of the pre-stabilizing circuit. The filter capacitor C1 is connected between the gate terminals of the high-voltage NMOS transistors MN1 and MN3, that is, between the node A and GND, to reduce the disturbance of the gate-source voltage difference VGS1 and VGS3 of the high-voltage NMOS transistors MN1 and MN3. The filter capacitor C2 is connected between the resistor R2 and GND to reduce the disturbance of the branch voltage disturbance to the gate-source voltage of the low-voltage NMOS transistor MN 2. Finally, the pre-stabilizing circuit outputs a relatively stable voltage Vbg_sup. The pre-stabilizing circuit adds a first filter circuit, a second filter circuit, and a third filter circuit to filter out interference signals.

[0060] like Figure 4 As shown, the error amplifier circuit 22 includes a resistor R8, a resistor R9, a fourth filter circuit 221, a MOS transistor MP0, a MOS transistor MP1, a MOS transistor MN6, a MOS transistor MN7, a MOS transistor MN4, and a MOS transistor MN5; the fourth filter circuit 221 is a filter capacitor C3;

[0061] One end of the resistor R8 is connected to the power supply VBAT, and the other end of the resistor R8 is connected to the source of the MOS transistor MP0; one end of the resistor R9 is connected to the power supply VBAT, and the other end of the resistor R9 is connected to the source of the MOS transistor MP1; one end of the filter capacitor C3 in the fourth filter circuit 221 is connected to the power supply VBAT, and the other end of the filter capacitor C3 is connected to the gate of the MOS transistor MP0;

[0062] The gate of the MOS transistor MP0 is connected to the drain of the MOS transistor MP0, the drain of the MOS transistor MN6, and the gate of the MOS transistor MP1. The drain of the MOS transistor MP0 is connected to the drain of the MOS transistor MN7. The drain of the MOS transistor MP0 is the output end of the error amplifier circuit 22. The drain of the MOS transistor MP0 outputs a voltage Vout_EA.

[0063] The gate of MOS tube MN6 is connected to the gate of MOS tube MN7; the source of MOS tube MN6 is connected to the drain of MOS tube MN4; the source of MOS tube MN7 is connected to the drain of MOS tube MN5, the source of MOS tube MN4, the source of MOS tube MN5 and current source I0 are connected, and the ground terminal of current source I0 is grounded.

[0064] MOS tube MP0, MOS tube MP1, MOS tube MN1, MOS tube MN3, MOS tube MN6, MOS tube MN7 are high voltage transistors, and MOS tube MN2 is a low voltage transistor;

[0065] A filter capacitor C3 is added to the error amplifier EA module, and the filter capacitor is connected between the gate terminal of the high-voltage PMOS transistors MP0 and MP1 and the power supply VBAT to filter the high-frequency interference signal, so that the source terminal voltage of the high-voltage PMOS transistors MP0 and MP1 is not affected by the power supply voltage disturbance, and the gate-source voltage difference VGS4 and VGS5 are relatively stable, thereby ensuring the stability of the output voltage Vout of the error amplifier EA and providing a stable gate terminal voltage for the high-voltage NMOS power tube of the subsequent LDO. The fourth filter circuit is added to the error amplifier circuit of the LDO to filter out the interference signal.

[0066] The RC filter circuit 42 may be replaced by two sets of inverters connected in series, or the RC filter circuit 42 may be directly deleted.

[0067] The present invention uses a bandgap voltage detection module Vbg_detect to detect the bandgap reference transfer output voltage value Vbg, and uses an internal power supply voltage detection module Vdig_detect to detect the size of the LDO output voltage. The above dual detection is used to determine whether the internal power supply Vdig is working normally. On the basis of both results being established, a final determination signal is generated as a reset control signal for the digital signal inside the chip. When only one detection is established, it is impossible to determine that the system power supply is normal.

[0068] The specific implementation process of the internal detection of the present invention is as follows: First, a precisely designed voltage detection module detects the voltage value Vbg generated by the bandgap reference to obtain the detection result Vbg_ok of the bandgap reference voltage value. When the bandgap reference works normally, it can generate a reference voltage of 1.2V. If the bandgap reference module works normally, the bandgap reference detection module Vbg_detect detects a reference voltage of 1.2V, then the detection output signal Vbg_ok outputs a high level Vbg_ok=1, and the result indicates that the bandgap reference module has worked normally. Otherwise, Vbg_ok outputs a low level Vbg_ok=0, indicating that the bandgap reference module fails to provide a reference voltage value. The output signal Vbg_ok of the bandgap reference detection module is also used as the enable signal Enable of the power detection module. When the output signal Vbg_ok of the bandgap reference detection module is high, the power detection module starts to work and detects the output voltage of the internal power supply LDO. If the output signal Vbg_ok of the bandgap reference detection module is low, the power detection circuit does not work. For the power detection module, its main circuit is implemented by a hysteresis comparator. The output voltage of LDO is divided by a resistor string to obtain two detection voltages Vdig_porn_H and Vdig_porn_L. The two detection voltage values ​​are compared with a certain bandgap reference voltage value Vbg0 to determine whether LDO outputs normally and whether it can provide the power supply voltage required for the normal operation of other modules inside the chip. If the output voltage of LDO meets the system requirements, the detection module outputs Vdig_ok as a high level Vdig_ok=1. If the output voltage of LDO fails to meet the system requirements, the detection module outputs Vdig_ok as a low level Vdig_ok=0. Combined with the output result Vbg_ok of the bandgap reference voltage detection module and the power supply output detection result Vdig_ok, further judgment is made. When and only when both outputs are high levels Vbg_ok=1 and Vdig_ok=1, the final reset signal V_porn outputs a high level V_porn=1, indicating that the bandgap reference circuit and the LDO circuit are both working normally, and the digital circuit and other circuits inside the chip can work normally. If only the bandgap reference voltage detection result is a high level, and the power supply voltage detection result is a low level Vbg_ok=1, Vdig_ok=0, then the reset signal V_porn output is a low level V_porn=0, indicating that only the bandgap reference circuit has been working properly, and the output voltage of the LDO has not met the system requirements, and the chip cannot work properly at this time. If the bandgap reference voltage detection result is a low level, and the power supply voltage detection result is also a low level Vbg_ok=0, Vdig_ok=0, then the reset signal V_porn output is a low level V_porn=0, indicating that the output voltages of the bandgap reference circuit and the LDO are not working properly, and a stable internal power supply cannot be provided at this time, so the chip cannot work properly.

[0069] Based on the above on-chip power supply anti-interference design, the possibility of misjudging the on-chip power supply status caused by using a single detection in the traditional design is avoided. Therefore, the application of this design makes the system more robust and anti-interference.

[0070] The problem that the present invention needs to solve is the design of the anti-electromagnetic interference of the power supply on the integrated circuit chip, and in particular, it involves the anti-interference design of the automotive-grade chip with respect to radio frequency interference. In view of the problems of low judgment accuracy and poor circuit robustness in the existing anti-interference solutions, a further solution is proposed. First, a pre-voltage stabilization circuit is designed, and in combination with the working characteristics of the transistor, a suitable high-voltage NMOS transistor is selected for isolation to separate the high interference signal from the internal power supply system, thereby minimizing its interference to the internal system. In addition, in view of the misjudgment problem existing in a single detection, a bandgap reference voltage detection circuit is designed, and the internal bandgap reference voltage output is additionally detected. A dual detection design scheme is used instead of a traditional single detection scheme. When and only when the bandgap reference voltage detection is accurate and the internal power supply voltage detection is completed at the same time, the final detection signal output is obtained to provide a reset signal for the digital circuit inside the chip, thereby ensuring the correct implementation of the chip function.

[0071] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be considered exemplary and non-restrictive from any point of view. The scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention, and any reference numerals in the claims should not be considered as limiting the claims involved.

[0072] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A high-reliability high-voltage on-chip power supply circuit, characterized in that: It includes a pre-regulator and start-up circuit (1), a low-dropout linear regulator LDO circuit (2), an on-chip power supply dual detection circuit (3) and a detection and determination circuit (4); The pre-stabilization and startup circuit (1) comprises a pre-stabilization circuit (11) and a startup circuit (12); the pre-stabilization circuit (11) is internally provided with a first filter circuit (111), a second filter circuit (112), and a third filter circuit (113) for filtering high-frequency noise; the low-dropout linear regulator (LDO) circuit (2) comprises a bandgap reference circuit (21), an error amplifier circuit (22), a power tube circuit (23), and a negative feedback circuit (24); the pre-stabilization circuit (11) and the power tube circuit (23) are internally provided with a high-voltage NMOS tube for High voltage isolation is performed; the on-chip power supply dual detection circuit (3) comprises a bandgap reference voltage value detection circuit (31) and an internal power supply detection circuit (32), and the on-chip power supply dual detection circuit (3) is used to perform dual detection and judgment on the output of the low voltage difference linear regulator LDO circuit (2) and the bandgap reference circuit (21); the detection and judgment circuit (4) comprises a first AND gate circuit (41) and an RC filter circuit (42); after the dual detection results are logically judged by an AND gate circuit (41), the judgment results are filtered by a low-pass filter circuit and used as the final output judgment results; The power input end of the pre-stabilizing circuit (11) is connected to the power supply VBAT, and the ground end of the pre-stabilizing circuit (11) is grounded; the output end of the pre-stabilizing circuit (11) is connected to the power input end of the start-up circuit (12) and the power input end of the bandgap reference circuit (21); the output end of the pre-stabilizing circuit (11) outputs the power supply Vbg_sup; The output end of the start-up circuit (12) is connected to the input end of the bandgap reference circuit (21); One output end of the bandgap reference circuit (21) is simultaneously connected to the positive input end of the error amplifier circuit (22) and the input end of the bandgap reference voltage value detection circuit (31), and one output end of the bandgap reference circuit (21) outputs a first reference voltage Vbg; another output end of the bandgap reference circuit (21) is connected to the signal input end of the internal power supply detection circuit (32), and another output end of the bandgap reference circuit (21) outputs a second reference voltage Vbg0; a ground end of the bandgap reference circuit (21) is grounded; The power input end of the error amplifier circuit (22) is connected to the power supply VBAT; the negative input end of the error amplifier circuit (22) is connected to the feedback output end Vfb of the negative feedback circuit (24); the output end of the error amplifier circuit (22) is connected to the gate of the MOS tube MN0 in the power tube circuit (23), and the drain of the MOS tube MN0 is connected to the power supply VBAT; the source of the MOS tube MN0 is connected to the negative feedback circuit (24); the source of the MOS tube MN0 outputs a voltage Vdig; the output end of the error amplifier outputs a voltage Vout_EA; the source of the MOS tube MN0 of the power tube circuit (23) is the voltage output end of the low voltage difference linear regulator LDO circuit (2); The negative feedback circuit (24) comprises a resistor R1, a resistor R2, a resistor R3 and a resistor R4, wherein the resistors R1, R2, R3 and R4 are connected in series in sequence, one end of the resistor R1 is connected to the source of the MOS tube MN0, and the other end of the resistor R4 is grounded; a feedback output end Vfb is between the resistor R1 and the resistor R2; The power input end of the bandgap reference voltage value detection circuit (31) and the power input end of the internal power supply detection circuit (32) are both connected to the source of the MOS tube MN0 in the power tube circuit (23), and the output voltage of the power tube circuit (23) supplies power to the bandgap reference voltage value detection circuit (31) and the internal power supply detection circuit (32); The output end of the bandgap reference voltage value detection circuit (31) is connected to the internal power supply detection circuit (32); the output end of the bandgap reference voltage value detection circuit (31) outputs a signal Vbg_ok as an enable signal of the internal power supply detection circuit (32); the bandgap reference voltage value detection circuit (31) detects a first reference voltage Vbg outputted from the bandgap reference circuit (21), and the internal power supply detection circuit (32) is used to detect the output voltage of the low-dropout linear regulator LDO circuit (2); The input end of the internal power detection circuit (32) is connected to the common operation terminal of the single-pole double-throw switch, and the main contact and the auxiliary contact of the single-pole double-throw switch are connected in parallel to the two ends of the resistor R3 of the negative feedback circuit (24); the two ends of the resistor R3 respectively output a first detection voltage Vdig_porn_L and a second detection voltage Vdig_porn_H; the output end of the bandgap reference voltage value detection circuit (31) is connected to one input end of the AND gate AND of the first AND gate circuit (41), the output end of the internal power detection circuit (32) is connected to the other input end of the AND gate AND of the first AND gate circuit (41), and the output end of the internal power detection circuit (32) outputs a signal Vdig_ok; The output end of the AND gate AND of the first AND gate circuit (41) is connected to the input end of the RC filter circuit (42), and the output end of the RC filter circuit (42) outputs a final control signal V_porn; The power input terminals of the AND gate AND and the RC filter circuit (42) are both connected to the source of the MOS tube MN0 of the power tube circuit (23).

2. A high-reliability high-voltage on-chip power supply circuit according to claim 1, characterized in that: The pre-stabilizing circuit (11) comprises a first filtering circuit (111), a second filtering circuit (112), a third filtering circuit (113), a resistor R0, a resistor R5, a resistor R6, a resistor R7, a MOS transistor MN1, a MOS transistor MN2 and a MOS transistor MN3; the first filtering circuit (111) is a filtering capacitor C1, the second filtering circuit (112) is a filtering capacitor C2, and the third filtering circuit (113) is a filtering capacitor C0; One end of the resistor R0 is connected to the power supply VBAT, and the other end of the resistor R0 is simultaneously connected to the gate of the MOS transistor MN1, the gate of the MOS transistor MN3, and the drain of the MOS transistor MN2; the source of the MOS transistor MN2 is grounded; the filter capacitor C1 in the first filter circuit (111) is connected in parallel between the source of the MOS transistor MN2 and the drain of the MOS transistor MN2; The source of the MOS transistor MN1 is connected to one end of the resistor R5, the resistors R5, R6 and R7 are connected in series in sequence, the gate of the MOS transistor MN2 is connected to one end of the resistor R7, the other end of the resistor R7 is grounded, and the filter capacitor C2 in the second filter circuit (112) is connected in parallel to both ends of the resistor R7; The source of the MOS transistor MN3 is connected to one end of a filter capacitor C0 in the third filter circuit (113), and the other end of the filter capacitor C0 is grounded; The drain of the MOS transistor MN1 and the drain of the MOS transistor MN3 are connected to the power supply VBAT.

3. A high-reliability high-voltage on-chip power supply circuit according to claim 2, characterized in that: The error amplifier circuit (22) comprises a resistor R8, a resistor R9, a fourth filter circuit (221), a MOS transistor MP0, a MOS transistor MP1, a MOS transistor MN6, a MOS transistor MN7, a MOS transistor MN4, and a MOS transistor MN5; the fourth filter circuit (221) is a filter capacitor C3; One end of the resistor R8 is connected to the power supply VBAT, and the other end of the resistor R8 is connected to the source of the MOS tube MP0; one end of the resistor R9 is connected to the power supply VBAT, and the other end of the resistor R9 is connected to the source of the MOS tube MP1; One end of the filter capacitor C3 in the fourth filter circuit (221) is connected to the power supply VBAT, and the other end of the filter capacitor C3 is connected to the gate of the MOS transistor MP0 and the gate of the MOS transistor MP1; The gate of the MOS tube MP0 is simultaneously connected to the drain of the MOS tube MP0, the drain of the MOS tube MN6, and the gate of the MOS tube MP1; the drain of the MOS tube MP1 is connected to the drain of the MOS tube MN7; the drain of the MOS tube MP1 is the output end of the error amplifier circuit (22); the drain of the MOS tube MP1 outputs a voltage Vout_EA; The gate of the MOS tube MN6 is connected to the gate of the MOS tube MN7; the source of the MOS tube MN6 is connected to the drain of the MOS tube MN4, and the source of the MOS tube MN7 is connected to the drain of the MOS tube MN5; The source of the MOS transistor MN4 and the source of the MOS transistor MN5 are connected to the current source I0 , and the ground terminal of the current source I0 is grounded.

4. A high-reliability high-voltage on-chip power supply circuit according to claim 3, characterized in that: The MOS transistors MP0, MP1, MN1, MN3, MN6 and MN7 are high-voltage transistors, and the MOS transistors MN2, MN4 and MN5 are low-voltage transistors.

5. A high-reliability high-voltage on-chip power supply circuit according to claim 4, characterized in that: The two output terminals of the bandgap reference circuit (21) are connected interchangeably.

6. A high-reliability high-voltage on-chip power supply circuit according to claim 5, characterized in that: The RC filter circuit (42) is replaced by two sets of inverters connected in series, or the RC filter circuit (42) is deleted.

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