Synchronous FIFO (First In First Out) with register and electronic equipment

Abstract

A synchronous FIFO (First In First Out) with registers is characterized by comprising a head register for receiving first input data and outputting data to the outside; the tail register is used for receiving second input data and transferring the second input data to the head register or the internal register; the internal register is used for receiving the second input data and transferring the second input data to the head register; and the control circuit is connected with the head register, the tail register and the plurality of internal registers, controls input data to be loaded to the head register or the tail register, controls second input data to be transferred from the tail register to the head register or the internal registers, and controls the second input data to be transferred from the tail register to the internal registers. And controlling the second input data to be transferred from the internal register to the head register, and controlling the head register to output data outwards. The method has relatively high stability and data transmission efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of synchronous FIFO, and in particular to a synchronous FIFO with a register. Background Art

[0002] Synchronous FIFO (First In First Out) refers to a buffer that uses logic resources inside the FPGA to store data with a first-in-first-out feature. It is significantly different from ordinary memory in that it has no external read and write address lines, which means that it can only write and read data sequentially. The read clock and write clock of the synchronous FIFO are the same clock, so read and write operations will occur simultaneously when the clock edge arrives.

[0003] Unlike ordinary memories, synchronous FIFOs do not have external read and write address lines. The data address is completed by the internal read and write pointers automatically adding 1. Synchronous FIFOs can only write and read data sequentially, and cannot be randomly accessed like ordinary memories. The read clock and write clock of synchronous FIFOs are the same clock, and the read and write operations occur simultaneously when the clock edge arrives.

[0004] In the CPU, the external circuits that provide the PUSH signal to the FIFO and provide data to the FIFO are usually driven by the same clock signal. The external circuit responds to the rising edge of the previous clock signal, starts the assertion of the PUSH signal and provides data to the FIFO, so the external circuit must be fast enough to provide the PUSH signal and data to the FIFO input port in less than one clock cycle, and the PUSH and data signals appear on the input port in sufficient time before the next rising edge of the same clock signal. If the setup time requirement of the FIFO is very high, then the time for the external circuit to provide the PUSH signal and data is relatively short, which will limit the operating speed of the entire circuit.

[0005] Likewise, from the perspective of the FIFO's output port, there is an external circuit that issues a POP signal and receives a data value from the FIFO in return. If the signal propagation delay in the FIFO is such that the POP signal has a relatively large setup time requirement, then the external circuit has relatively little time to provide the POP signal to the FIFO. If the FIFO's POP setup time is long and or the FIFO's clock-data output propagation delay is large, the entire circuit may operate at a very low speed.

[0006] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of this patent application. In the absence of clear evidence that the above content has been disclosed on the filing date of this patent application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0007] To this end, the synchronous FIFO with registers provided by the present invention has a head register, a tail register and an internal register at the same time, and only the head register can output data to the outside, the head register and the tail register can receive input data, and the internal register is only used to store data. No fan-out circuit is required, the operation speed is fast, and it has high stability and data transmission efficiency.

[0008] The present invention provides a synchronous FIFO with a register, characterized in that it comprises: a head register, a tail register, a plurality of internal registers and a control circuit;

[0009] The header register is used to receive first input data and output data externally;

[0010] The tail register is used to receive the second input data and transfer it to the head register or the internal register;

[0011] The internal register is used to receive the second input data and transfer it to the header register;

[0012] The control circuit is connected to the head register, the tail register and the plurality of internal registers, and controls the input data to be loaded into the head register or the tail register, controls the second input data to be transferred from the tail register to the head register or the internal register, controls the second input data to be transferred from the internal register to the head register, and controls the head register to output data externally.

[0013] Optionally, the synchronous FIFO with register is characterized in that the control circuit comprises:

[0014] an internal write pointer register, used for maintaining and outputting a value WP to indicate a position of the internal register receiving the second input data of the tail register in a next clock cycle;

[0015] an internal read pointer register, used for maintaining and outputting a value RP to indicate a position of the internal register to transfer the second input data to the header register in a next clock cycle;

[0016] A tail valid trigger, used to indicate whether the tail register stores valid data;

[0017] A header valid trigger, used to indicate whether the header register is outputting data;

[0018] A full trigger is used to indicate whether the head register, the tail register and the plurality of internal registers are all currently full.

[0019] Optionally, the synchronous FIFO with register is characterized in that, in a clock cycle, at the effective edge of the clock, the PUSH signal is 1 and the FULL signal is 0, then the input data is captured into the head register or the tail register.

[0020] Optionally, the synchronous FIFO with register is characterized in that when the FULL signal is 1, the FULL signal will be set to 0 in the next clock cycle, and at the same time, in the next clock cycle, the POP signal is set to 1 and the VALID signal is set to 1.

[0021] Optionally, the synchronous FIFO with register is characterized in that if the POP signal is set to 1 and the tail register is not empty, the content of the head register is updated in the next clock cycle.

[0022] Optionally, the synchronous FIFO with registers is characterized in that if within a clock cycle, the tail register is occupied and at least one of the internal registers is not occupied, and the PUSH operation is not performed within the next clock cycle, then within the next clock cycle, the content of the tail register is transferred to the unoccupied internal register.

[0023] Optionally, the synchronous FIFO with register is characterized in that only the data value in the head register can be output to the data output pin.

[0024] Optionally, the synchronous FIFO with register is characterized in that if the head register, the internal register and the tail register are all empty in one clock cycle, when the PUSH operation is performed in the next clock cycle, the input data value is directly written into the head register.

[0025] Optionally, the synchronous FIFO with register is characterized in that after the head register outputs data externally, the control circuit transfers the second oldest input to the head register.

[0026] Optionally, the synchronous FIFO with registers is characterized in that if the head register, the internal register and the tail register are all full, the PUSH operation cannot be performed; if the head register, the internal register and the tail register are all empty, the POP operation cannot be performed; if the head register, the tail register and the internal register are not all full or empty, data can be input and / or output at any valid edge of the clock signal.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention sets a head register, a tail register and an internal register in a synchronous FIFO so that the synchronous FIFO can store more data, and sets only the head register to output data externally, so that the control circuit is more concise and efficient, no fan-out circuit is required, and the propagation delay is small, so that the external circuit has enough time to provide PUSH signals and data, reducing the restrictions on the external circuit, thereby increasing the operating speed of the entire circuit and improving the processing efficiency of the CPU; the present invention can also allow the external circuit that provides the POP signal to have more time, ensuring that the operating speed of the entire circuit is not affected, thereby improving the processing efficiency of the CPU.

[0029] The present invention does not have an output multiplexer, so the change of the data output of the present invention occurs relatively quickly after the effective edge. At the same time, since the present invention only starts to input the data header register and the tail register, the amount of circuitry involved in controlling the register using the PUSH signal is relatively small. Therefore, relative to the effective edge of the clock signal, the setup time required for the present invention to receive the PUSH signal is relatively small. The setup time required for the PUSH signal is less than half of the clock signal CLK period. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings in the following descriptions are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without creative work. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more obvious:

[0031] Figure 1 A schematic diagram of the structure of a synchronous FIFO with a register in an embodiment of the present invention;

[0032] Figure 2 A signal diagram of a synchronous FIFO with a register in an embodiment of the present invention;

[0033] Figure 3 It is a structural schematic diagram of a control circuit in an embodiment of the present invention;

[0034] Figure 4 Schematic diagram of PUSH and POP signal processing within a clock cycle in an embodiment of the present invention;

[0035] Figure 5 Schematic diagram of PUSH and POP signal processing in multiple clock cycles in an embodiment of the present invention;

[0036] Figure 6 A first schematic diagram of executing PUSH and POP instruction processing simultaneously in an embodiment of the present invention;

[0037] Figure 7 This is a second schematic diagram of executing PUSH and POP instruction processing simultaneously in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several variations and improvements may be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0039] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein, for example, can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0040] The embodiment of the present invention provides a synchronous FIFO with a register, aiming to solve the problems existing in the prior art.

[0041] The following specific embodiments are used to describe in detail the technical solutions of the present invention and how the technical solutions of the present application solve the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0042] The synchronous FIFO with register provided by the present invention has a head register, a tail register and an internal register at the same time, and only the head register can output data to the outside, the head register and the tail register can receive input data, and the internal register is only used to store data, does not require a fan-out circuit, has a fast operating speed, and has high stability and data transmission efficiency.

[0043] The register is located in the CPU, and its read and write speed is basically matched with the CPU's operating speed. It can be used to store data and operation results involved in the operation, and to store data and instructions that the CPU needs to access frequently. It can be directly accessed by the CPU, so the access speed is very fast. The present invention ensures the operating speed of the CPU by adopting multiple registers and control circuits.

[0044] Those skilled in the art can understand that, in the embodiments of the present invention, the number of internal registers can be arbitrarily set, and can be 2, 3, 4, 5, 6, 7 or any other positive integer not listed. Those skilled in the art can make corresponding adjustments to this according to the design of the overall circuit or CPU. At the same time, due to the different numbers of internal registers, the internal write pointer register, the internal read pointer register or other pointers or components set according to the number of internal registers can also be set accordingly. For example, the internal write pointer register can be a three-bit register, a four-bit register, a five-bit register or other types of registers. These are all arbitrarily set by those skilled in the art under the guidance of the present invention and are within the scope of protection of the present invention.

[0045] For the convenience of writing, this specification will take three internal registers as an example for explanation without requiring specific explanation. However, those skilled in the art will understand that the number of internal registers is not limited to three, but can be set arbitrarily, and various signals or components such as pointers corresponding to the number of internal registers should be adaptively adjusted without exceeding the scope of protection of the present invention.

[0046] In this specification, "registered FIFO" is used to refer to a synchronous FIFO with registers in an embodiment of the present invention.

[0047] Figure 1 FIG. 1 is a schematic diagram of a structure of a synchronous FIFO with a register in an embodiment of the present invention. Figure 1 As shown, a synchronous FIFO with registers in an embodiment of the present invention includes: a head register, a tail register, multiple internal registers and a control circuit.

[0048] The header register is used to receive first input data and output data externally.

[0049] Specifically, the header register is used to store the data to be read. It is responsible for receiving the first input data and outputting the data to the outside at the appropriate time. The header register is located at the beginning of the registered FIFO. When data is read from the registered FIFO, the content of the header register will be moved out. When the registered FIFO is empty or needs to load new data, the header register first receives the data from the outside or inside (such as after reset). When the registered FIFO is not empty and an external request is made to read data, the data in the header register is output.

[0050] The tail register is used to receive the second input data and transfer the second input data to the head register or the internal register.

[0051] Specifically, the tail register is the location in the registered FIFO for storing the most recently written data. It is responsible for receiving the second input data and transferring the data to the head register or internal register according to the instructions of the control circuit. It should be noted that the first input data and the second input data are just names for the convenience of description, and there is no difference in the data itself. For example, when the second input data is transferred to the head register, the second input data becomes the first input data. Therefore, the first input data refers to all data processed by the head register, and the second input data refers to data that was not stored in the head register at the first time and is not currently stored in the head register. The tail register is located at the end of the registered FIFO, and when new data is written to the registered FIFO, the content of the tail register will be updated.

[0052] The internal register is used to receive the second input data and transfer the second input data to the head register.

[0053] Specifically, the internal registers are the middle locations in the registered FIFO for storing data. They receive the second input data from the tail register and transfer the data to the head register under the guidance of the control circuit. The internal registers are located between the head register and the tail register, and they store data in a first-in, first-out order, ensuring that the order of the data is maintained during the transmission process.

[0054] The control circuit is connected to the head register, the tail register and the plurality of internal registers, and controls the input data to be loaded into the head register or the tail register, controls the second input data to be transferred from the tail register to the head register or the internal register, controls the second input data to be transferred from the internal register to the head register, and controls the head register to output data externally.

[0055] Specifically, the control circuit usually includes logic gates, state machines, or other control logic to ensure that data moves in the registered FIFO in the correct order and prevent error conditions such as overflow or underflow. The control circuit makes decisions based on the current state of the registered FIFO (such as empty, full, partially full, etc.) and external requests (such as PUSH, POP). The control circuit is also responsible for generating empty (EMPTY) and full (FULL) signals to indicate the current state of the registered FIFO.

[0056] Figure 2 The signal diagram of a synchronous FIFO with a register in an embodiment of the present invention. The signals that the registered FIFO can communicate are PUSH 30, POP 31, FULL 35, VALID 36, WRITE_DATA 32, READ_DATA 33, and CLK 34. It should be understood that the PUSH signal is a signal that pushes data from a register or memory into a stack; the POP signal is a stack pop signal; the FULL signal is a signal used to indicate whether the registered FIFO is full; the VALID signal is a signal used to indicate whether the data at the output port of the registered FIFO is valid; the WRITE_DATA signal is a data input signal in a write operation; the READ_DATA signal is a data output signal in a read operation; and the CLK signal is a clock cycle signal. Through these signals, the registered FIFO can interact with external circuits and transmit data in a timely manner in response to the external circuits.

[0057] If the registered FIFO is not full (the FULL signal is digital "0" indicating an "unfull" state), the data value can be entered into the registered FIFO. The data value can be pushed to the registered FIFO in the following ways: 1) Provide a new data value to WRITE DATA, and provide sufficient setup time for the effective edge of the clock signal CLK; 2) Set the PUSH signal on the input to 1, and provide sufficient setup time for the effective edge of the clock signal. At the effective edge of the clock signal, the data value is loaded into the head register or the tail register of the registered FIFO. The effective edge of the clock includes a rising edge and a falling edge, which depends on the design of the registered FIFO. The subsequent part of this specification takes the rising edge as an example for explanation, but it can be understood by those skilled in the art that the rising edge and the falling edge have the same function, and when the effective edge is a falling edge, it still falls within the scope of protection of the present invention.

[0058] If the registered FIFO is not empty (indicated by the VALID signal), then the registered FIFO can be POPed. At the active edge of the clock signal, the data value stored in the head register is changed to the next oldest data value stored in the registered FIFO.

[0059] When the registered FIFO is empty, the input data pushed in one clock cycle can appear in the READ_DATA output of the next clock cycle. When the registered FIFO is empty, the input data pushed in one clock cycle is directly written to the head register, so that the output data operation can be performed in the next clock cycle. While the head register is being written in one clock cycle, it cannot perform output data operation at the same time to avoid data loss or inconsistency.

[0060] When the data that makes the registered FIFO full is read in, the FULL signal will be pulled high at the next clock, indicating that the current registered FIFO is full and the PUSH operation cannot be performed to prevent the data from being overwritten or lost.

[0061] When the FULL signal is 1, the FULL signal will be set to 0 in the next clock cycle. At the same time, in the next clock cycle, the POP signal is set to 1 and the VALID signal is set to 1. When the FULL signal is 1, it means that the registered FIFO is full. In the next cycle, the POP signal is set to 1 to speed up the reading and output a data item from the registered FIFO. At the same time, the VALID signal is set to 1 so that the data in the tail memory can be stored in the internal register, and the data in the internal register can be written into the head register. This embodiment can speed up the reading when the registered FIFO is full, thereby preventing the data from being overwritten or overflowing.

[0062] If the POP signal is set to 1 and the tail register is not empty, the content of the head register is updated in the next clock cycle. When the POP signal is set to 1, the content of the head register is read, and if the tail register is not empty at this time, the oldest data in the tail register or internal register is directly written to the head register, thereby improving efficiency.

[0063] If the VALID signal is set to 1, READ_DATA will be output from the registered FIFO and will be valid at the next valid edge of the clock signal. If the VALID signal is 1, it means that the output port data is valid, then the READ_DATA instruction will output the data of the output port and execute it in the next clock cycle.

[0064] The registered FIFO output data always comes directly from the head register. No multiplexer is used to multiplex one of the multiple register values ​​onto the registered FIFO output signal lines. In a traditional FIFO, the value of any one of the registers in the FIFO can be provided to the data output lines of the FIFO, depending on the current register usage and which register stores the oldest data value. This in turn requires an output multiplexing circuit that can direct the data value from any one of many registers to a set of data lines for output. This output multiplexer circuit is larger, so the propagation delay through it is larger and limits the performance operating speed of the FIFO. But in the registered FIFO, there is no output multiplexer or multiplexing circuit, which greatly improves the operating speed.

[0065] The PUSH signal only controls the head register and the tail register, and the operation of the internal register is not related to the PUSH signal. In a traditional FIFO, the PUSH signal must be fanned out to control the gating and loading of each register of the FIFO. If the number of registers in the FIFO is large, the propagation delay is increased due to the large number of fan-out circuits, thereby reducing the time for the FIFO external circuit to provide the PUSH signal to the FIFO. On the other hand, in a registered FIFO, the PUSH signal does not control the operation of the internal registers, but only the operation of the head register and the tail register is directly affected by the PUSH signal. Therefore, the propagation delay through the PUSH signal is much reduced compared to the signal propagation delay through a large number of PUSH signal fan-out circuits in the traditional FIFO architecture.

[0066] Figure 3 FIG. 1 is a schematic diagram of a control circuit in an embodiment of the present invention. Figure 3 As shown, a control circuit in an embodiment of the present invention includes:

[0067] The internal write pointer register is used to maintain and output a value WP to indicate the position of the internal register that receives the second input data of the tail register in the next clock cycle.

[0068] Specifically, the internal write pointer register (Internal Write Pointer Register) is a three-bit register that maintains a three-bit value indicating the number of five registers (tail, a, b, c, and head) storing data values. Among them, tail represents the tail register, a represents the first internal register, b represents the second internal register, c represents the third internal register, and head represents the head register. If no data is stored in any of the five registers, the three-bit write pointer register is "000".

[0069] The internal read pointer register is used to maintain and output a value RP to indicate the position of the internal register for transferring the second input data to the header register in the next clock cycle.

[0070] Specifically, similar to the internal write pointer register, the internal read pointer register (Internal ReadPointer Register) can also be any number of register types, which can be determined according to the number of internal registers. Taking the number of internal registers as 3, the internal read pointer register is a three-bit register as an example. It stores a number pointing to the next internal register (register a, b or c), and the next register can be written. The only possible WP values ​​are "001", "010" and "011". The WP value "001" indicates that the next internal register that can be written to data is register a. The WP value "010" indicates that the next internal register that can be written to data is register b. The WP value "011" indicates that the next internal register that can be written to data is register c.

[0071] The loading of the internal registers a, b and c is independent of the PUSH signal. A data stored in the tail register is transferred from the tail register to an empty internal register due to the assertion of the TAIL_VALID signal, conditional on one of the internal registers being empty, and this transfer occurs regardless of whether a PUSH operation is in progress. Therefore, if the registered FIFO stores a data in its tail register, and if one of the three internal registers (a, b and c) is empty, and if the PUSH signal is not asserted, thereby indicating that a PUSH operation has not occurred in the next clock cycle, then in the next clock cycle, even if no new data value is PUSHed into the tail register, the data from the tail register will be moved to the next indicated internal register to be written. As a result of this transfer, the tail register is empty, so the TAIL_VALID signal will be deasserted, and as a result of writing to an internal register, the pointer WP of the internal write pointer register is incremented. It should be understood here that the TAIL_VALID signal is used to indicate whether there is valid data in the internal register.

[0072] A tail valid trigger is used to indicate whether the tail register stores valid data.

[0073] Specifically, the Tail Valid Flip-Flop stores a one-bit value indicating whether the tail register stores a data value. This helps the control circuit determine whether the data in the tail register needs to be transferred to the internal register or the head register. If the flip-flop stores a "1", then the tail register stores data. If the flip-flop stores a "0", then the tail register is empty. When new data is written to the tail register, the tail valid flip-flop is set (set to a valid state). Once the data in the tail register is successfully transferred, the flip-flop may be reset (set to an invalid state).

[0074] The header valid trigger is used to indicate whether the header register is outputting data.

[0075] Specifically, the Head Valid Flip-Flop stores a one-bit value that indicates whether the header register stores data. This helps the control circuit determine whether to allow data to be read from the header register and prevents the data from being overwritten before it is completely read. When the data in the header register is selected for output, the Head Valid Flip-Flop is set. Once the data is completely read (or the read operation of the registered FIFO is completed), the flip-flop is reset.

[0076] A full trigger is used to indicate whether the head register, the tail register and the plurality of internal registers are all currently full.

[0077] Specifically, the Full Flip-Flop stores a one-bit value indicating whether each register (tail, a, b, c, and head) stores a data value, that is, all registers of the registered FIFO are "full". If the flip-flop stores a "1" value, then all five registers (tail, a, b, c, and head) store data values. If the flip-flop stores a "0", then at least one of the five registers is empty. The term "empty" here means that no valid data is stored.

[0078] The control circuit in this embodiment ensures that the registered FIFO can efficiently manage the writing, reading and status control of data while maintaining the first-in-first-out order of data through the joint work of multiple registers and triggers.

[0079] In some embodiments, in a clock cycle, at the effective edge of the clock, the PUSH signal is 1 and the FULL signal is 0, then the input data is captured into the head register or the tail register. The combination of the PUSH signal and the effective edge of the clock triggers the data write operation, and the existence of the FULL signal is to prevent new data from being written when the registered FIFO is full, thereby causing data loss or overwriting. In a traditional FIFO architecture, the input data can be loaded into the register of any FIFO according to the current usage. This capability requires a fan-out circuit to provide the input data to one of many receiving registers. If a traditional FIFO has many registers, the fan-out circuit is large, and the propagation delay through the huge fan-out circuit is also large, which limits the operating speed of the FIFO. On the other hand, in a registered FIFO memory, this potential, resource-consuming and high-latency fan-out circuit is unnecessary and not included.

[0080] In some embodiments, if the tail register is occupied in a clock cycle, and at least one of the internal registers is not occupied, and the PUSH operation is not performed in the next clock cycle, then in the next clock cycle, the content of the tail register is transferred to the unoccupied internal register. In this embodiment, when there is no need to write data to the registered FIFO, the data in the tail register is transferred to the internal register, so that the tail register can always be directly written, thereby improving the writing efficiency.

[0081] In some embodiments, only the data value in the head register can be output to the data output pin. This embodiment determines the authority and order between multiple registers, which is of great significance for ensuring a first-in-first-out queue. Controlling the data of the head register controls the order of the registered FIFO, which is a key step in realizing the division of functions of multiple registers, especially when there are multiple registers in this embodiment.

[0082] In some embodiments, if the head register, the internal register, and the tail register are all empty in one clock cycle, when the PUSH operation is performed in the next clock cycle, the input data value is directly written into the head register. Since the input data can be directly loaded into the head register, this embodiment can speed up the reading and writing progress.

[0083] In some embodiments, after the head register outputs data externally, the control circuit transfers the second input which is currently the oldest to the head register. After the head register outputs data externally, only the tail register and the internal register store the second input data, then the oldest data in the second input data, that is, the data written first, is transferred to the head register to achieve a first-in, first-out effect.

[0084] In some embodiments, if the header register, the internal register, and the tail register are all full, a PUSH operation cannot be performed; if the header register, the internal register, and the tail register are all empty, a POP operation cannot be performed; if the header register, the tail register, and the internal register are not all full or empty, data can be input and / or output at any valid edge of the clock signal. In this embodiment, when the header register, the tail register, and the internal register are not all full or empty, data input (PUSH) and data output (POP) operations can be performed simultaneously, or data input or data output operations can be performed separately, thereby ensuring that data can be quickly input or output in various situations.

[0085] Figure 4 FIG. 1 is a schematic diagram of PUSH and POP signal processing within a clock cycle in an embodiment of the present invention. Figure 4 In the table, CLK refers to the clock cycle signal, WRITE DATA refers to the WRITE_DATA signal, PUSH refers to the PUSH signal, READ DATE refers to the READ_DATA signal, POP refers to the POP signal, SETUP TIME refers to the setup time, HOLD TIME refers to the hold time, DATA SUPPLIED TO FIFO INPUTS refers to the input data input to the input pin of the registered FIFO, DATA OUTPUT FROM FIFO OUTPUTS refers to the output data output from the output pin of the registered FIFO, and TIME refers to a clock cycle. Figure 4As shown, at time T2 before the rising edge of the clock signal CLK, there is enough setup time to set the PUSH signal to 1, and WRITE DATA has enough setup time to load into the register of the registered FIFO starting from time T2. In addition, in the example, there is also enough setup time for the POP signal to be set to 1 before time T2. Therefore, in response to the rising edge of the clock signal CLK at time T2, the content of the head register is changed to the second oldest data value stored in the registered FIFO. In one advantageous aspect, the registered FIFO has no output multiplexer, so the change of the data output of the registered FIFO occurs relatively quickly after the rising edge of T2. In another advantageous aspect, since the registered FIFO only loads the input data into the head register and the tail register, the amount of circuitry involved in controlling the register using the PUSH signal is relatively small. Therefore, relative to the rising edge of the clock signal, the setup time required to receive the PUSH signal into the registered FIFO is relatively small. The setup time required for the PUSH signal is less than half of the period of the clock signal CLK.

[0086] Figure 5 FIG. 1 is a schematic diagram of PUSH and POP signal processing in multiple clock cycles in an embodiment of the present invention. Figure 5 In the , WP is a write pointer, which indicates the position of the internal register receiving the second input data of the tail register in the next clock cycle, and is maintained by the internal write pointer register; RP is a read pointer, which indicates the position of the internal register transferring the second input data to the head register in the next clock cycle, and is maintained by the internal read pointer register; TAIL VALID is a tail pointer, which is maintained by a tail valid trigger, to indicate whether the tail register stores a data value; VALID is a head pointer, which is maintained by a head valid trigger, to indicate whether the head register is outputting data; FULL is a full pointer, which is maintained by a full trigger, to indicate whether the head register, the tail register and the multiple internal registers are currently all full; WRITE POINTER is a write status pointer, which indicates the number of data values ​​currently stored in the registered FIFO; PUSH refers to the PUSH signal; POP refers to the POP signal. Figure 5As shown, the PUSH signal is set at the input and the first data D1 is provided at the WRITE DATA input. As a result of the PUSH, the first data value D1 is loaded into the head register. The resulting state of the registered FIFO is in the upper right of the figure. The empty box marked "H" on the left is now shown on the right as containing "D1". The internal pointers WP and RP are not changed because no data value is loaded into any of the three internal registers a, b or c. Because the head register now stores a data value, the valid flip-flop is now set and therefore the signal VALID is set to 1.

[0087] Next, the PUSH signal is set to 1 and the second data value D2 is provided on the WRITE DATA input. As a result of this PUSH, the second data value D2 is loaded into the tail register. Referring to the second row, the first data value D1 is saved in the head register and the second data value D2 is now saved in the tail register. The internal pointers WP and RP are not changed because no data is loaded into any of the three internal registers a, b or c. Because the tail register now stores a data, the flip-flop is set so that the TAIL_VALID signal is set to 1.

[0088] Next, referring to the third row, the third data D3 is loaded into the tail register, and at the same time, as a result of asserting the TAIL_VALID signal, the previous contents of the tail register (D2) are loaded into the next internal register to be written. The next internal register to be written is indicated by the internal WP register. Therefore, because the WP value is "001", register a is loaded with the previous contents of the tail register (D2). The third data value D3 is stored in the tail register, the second data value D2 is stored in register a, and the first data value D1 is still stored in the head register. Every time a value is written to one of the three internal registers, the value of WP increases. Therefore, as a result of the third PUSH, the value of WP increases from "001" to "010". (WP is a counter that goes from "001" to "010" to "011" and then rolls over to "001").

[0089] Next, see the fourth row, the fourth data value D4 is loaded into the tail register, and because the TAIL_VALID signal is asserted, the previous contents of the tail register are loaded into the next internal register to be written. As shown in the internal WP register, the next internal register to be written is register b. Therefore, the previous contents of the tail register (data value D3) are loaded into register b. The fourth data value D4 is stored in the tail register, the second data value D2 is stored in register a, the third data value D3 is stored in register b, and the first data value D1 remains in the head register. Because WP is incremented after writing to one of the three internal registers, the value of WP increases from "010" to "011".

[0090] Next, see row 5, the fifth data value D5 is loaded into the tail register, and since the TAIL_VALID signal is asserted, the previous contents of the tail register (D4) are loaded into the next internal register to be written. As indicated by the internal WP register value "011", the next internal register to be written is register c. Therefore, the previous contents of the tail register (data value D4) are loaded into register c. The fifth data value d5 is stored in the tail register, the second data value D2 is stored in register a, the third data value D3 is stored in register b, the fourth data value D4 is stored in register c, and the first data value D1 remains in the head register. WP is then incremented starting from "011" and rolling over to the new value "001". (As mentioned above, WP is calculated in the order of "001", "010", "011", "001", "010", "011", "001", etc.).

[0091] In response to each PUSH, the WRITE_POINTER value is incremented so that the WRITE_POINTER value always indicates the number of data values ​​currently stored in the registered FIFO. If the WRITE_POINTER value is set to "101" (5), then the flip-flop is set to FULL, thereby asserting the FULL signal. Assertion of the FULL signal indicates that the registered FIFO is full, that is, all five registers are storing data values.

[0092] Next, the POP signal is set to 1 input. Referring to the sixth row, in response to the next rising edge of the clock signal CLK, the next internal register to be read (as indicated by the RP value) is transferred to the head register. The RP value is initially "001", so the contents of register a (D2) are transferred to the head register. Since the TAIL_VALID signal is 1, the previous contents of the tail register (D5) are loaded into the next internal register to be written. As a result of this output data operation, the tail register is empty, the fifth data value D5 is stored in register a, the third data value D3 is still stored in register b, the fourth data value D4 is still stored in register c, and the second data value D2 is now stored in the head register. After one of the three internal registers a, b, and c is transferred to another register, the value of RP is incremented. RP is initially "001", so RP is incremented to "010". Because the tail register is now empty, the TAIL_VALID flip-flop is set to 0.

[0093] Next, see line 7, the next internal register to be read (as indicated by the RP value) is transferred to the head register, and the RP value is "010", so the contents of register b (D3) are transferred to the head register. As a result of the second POP operation, the tail register is empty, the fifth data value D5 is still stored in register a, register b is empty, D4 is still stored in register c, and D3 is now stored in the head register. Because one of the three internal registers a, b, and c is transferred to another register, the value of RP is incremented. Therefore, RP increases to "011".

[0094] Next, referring to row 8, the next internal register to be read (as indicated by the RP value) is transferred into the head register, and the RP value is "011", so the contents of register c (D4) are transferred into the head register. As a result of the third POP operation, the tail register is empty, the fifth data value D5 is still stored in register a, register b is empty, register c is empty, and D4 is now stored in the head register. Because one of the three internal registers a, b, and c has been transferred to another register, the value of RP is incremented. Therefore, RP increases and rolls over to the value "010"

[0095] Next, see row 9, the next internal register to be read (as indicated by the RP value) is transferred into the head register. The RP value is "001", so the contents of register a (D5) are transferred into the head register. As a result of the fourth output data operation, the tail register is empty, registers a, b, and c are empty, and the fifth data value D5 is now stored in the head register.

[0096] Next, referring to the tenth row, the tail register and the three internal registers are all empty, so in response to the next rising edge of the clock signal CLK, the head register is recorded as empty. The valid flip-flop VALID that records the head register as empty is cleared, so the signal VALID is set to zero.

[0097] Figure 6 This is a first schematic diagram of simultaneously executing PUSH and POP instruction processing in an embodiment of the present invention. Figure 6 For the meaning of the terms in Figure 5 Corresponding part description. Figure 6 As shown, the registered FIFO initially stores one data value. If the registered FIFO stores one data, then this data is stored in the head register. If the PUSH input signal and the POP input signal are asserted simultaneously, the new data value D2 is loaded directly into the head register so that D2 replaces the previous D1 value in the head register. The registered FIFO stores the same amount of data before and after the simultaneous PUSH and POP operations. Therefore, the value of the WRITE POINTER after the PUSH and POP operations is the same as the value before the PUSH and POP operations. The WRITE POINTER has a value before and after the PUSH and POP operations.

[0098] Figure 7 This is a second schematic diagram of executing PUSH and POP instruction processing simultaneously in an embodiment of the present invention. Figure 7 For the meaning of the terms in Figure 5 Corresponding section description. The registered FIFO initially stores two data values. If the registered FIFO stores two data values, the oldest data value is stored in the head register and the other data value is stored in the tail register. If the PUSH input signal and the POP input signal are asserted at the same time, the new data value D3 is loaded into the tail register and the previous contents of the tail register (D2) are loaded into the head register. Before the PUSH and POP operations, the value of WRITEPOINTER is 2, and after the push and output data operations, the value of WRITE POINTER is also 2.

[0099] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the embodiments can be referred to each other. The above description of the disclosed embodiments enables professionals and technicians in this field to implement or use the present invention. Various modifications to these embodiments will be obvious to professionals and technicians in this field, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown in this article, but will comply with the widest range consistent with the principles and novel features disclosed herein.

[0100] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art may make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A synchronous FIFO with a register, characterized in that: include: Head register, tail register, multiple internal registers and control circuits; The header register is used to receive first input data and output data externally; The tail register is used to receive the second input data and transfer it to the head register or the internal register; The internal register is used to receive the second input data and transfer it to the header register; The control circuit is connected to the head register, the tail register and the plurality of internal registers, and controls the input data to be loaded into the head register or the tail register, controls the second input data to be transferred from the tail register to the head register or the internal register, controls the second input data to be transferred from the internal register to the head register, and controls the head register to output data externally.

2. A synchronous FIFO with register according to claim 1, characterized in that: The control circuit comprises: an internal write pointer register, used for maintaining and outputting a value WP to indicate a position of the internal register receiving the second input data of the tail register in a next clock cycle; an internal read pointer register, used for maintaining and outputting a value RP to indicate a position of the internal register to transfer the second input data to the header register in a next clock cycle; A tail valid trigger, used to indicate whether the tail register stores valid data; A header valid trigger, used to indicate whether the header register is outputting data; A full trigger is used to indicate whether the head register, the tail register and the plurality of internal registers are all currently full.

3. A synchronous FIFO with register according to claim 1, characterized in that: In a clock cycle, at the effective clock edge, the PUSH signal is 1 and the FULL signal is 0, and the input data is captured into the head register or the tail register.

4. A synchronous FIFO with register according to claim 1, characterized in that: When the FULL signal is 1, the FULL signal will be set to 0 in the next clock cycle. At the same time, in the next clock cycle, the POP signal is set to 1 and the VALID signal is set to 1.

5. A synchronous FIFO with register according to claim 1, characterized in that: If the POP signal is set to 1 and the tail register is not empty, the content of the head register is updated in the next clock cycle.

6. A synchronous FIFO with register according to claim 1, characterized in that: If the tail register is occupied and at least one of the internal registers is not occupied in a clock cycle, and a PUSH operation is not performed in the next clock cycle, then in the next clock cycle, the content of the tail register is transferred to the internal register that is not occupied.

7. A synchronous FIFO with register according to claim 1, characterized in that: Only the data value in the header register can be output to the data output pin.

8. A synchronous FIFO with register according to claim 1, characterized in that: If the head register, the internal register and the tail register are all empty in one clock cycle, when a PUSH operation is performed in the next clock cycle, the input data value is directly written into the head register.

9. A synchronous FIFO with register according to claim 1, characterized in that: After the head register outputs data externally, the control circuit transfers the second input which is currently the oldest to the head register.

10. A synchronous FIFO with register according to claim 1, characterized in that: If the header register, the internal register and the tail register are all full, the PUSH operation cannot be performed; if the header register, the internal register and the tail register are all empty, the POP operation cannot be performed; if the header register, the tail register and the internal register are not all full or empty, data can be input and / or output at any valid edge of the clock signal.

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