Operator implementation method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides an operator implementation method and device, electronic equipment and a storage medium, and relates to the technical field of computers.The method comprises the steps that a to-be-implemented operator is obtained, and the to-be-implemented operator comprises addition operation and memory access operation; the addition operation is used for calculating a first address synthesized by a source address corresponding to the memory access operation and the offset; the memory access operation is used for performing memory access in the first address; configuring a target instruction according to the source address and the offset; the target instruction comprises a first bit field, a second bit field and a third bit field, the first bit field is used for recording memory access data corresponding to memory access operation, the second bit field is used for recording a source address corresponding to the memory access operation, and the third bit field is used for recording offset; the target instruction is used for performing memory access in the address synthesized by the source address and the offset. Addition operation does not need to be configured and executed, the number of instructions executed in the code running process is reduced, and the data processing efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an operator implementation method, device, electronic equipment and storage medium. Background Art

[0002] Assembly language is the fastest and most efficient language provided by computers to users. It is also the only language that can utilize all the hardware features of the computer and can directly control the hardware. The characteristics of assembly language are that it is easy to be recognized and executed by the computer. Using it for programming can reduce the space occupied, increase the running speed, and directly control the hardware.

[0003] In the design of many programs, high-level languages ​​and assembly languages ​​can cross-call each other, pass parameters, and share data information. This is hybrid programming. JIT is a kind of hybrid programming. When a method or code block of an operator runs very frequently, these codes will be identified as "hot spot codes". In order to improve the execution efficiency of hot spot codes, these codes are written into machine codes related to the local platform in assembly language during runtime, and various levels of optimization are performed to improve the performance of the operator. When performing code conversion, many operations of calculating pointer offsets are involved. The implementation method of the prior art is to first calculate the sum of the pointer and the offset through an addition operation, store the calculation result in an intermediate register, and then call the load instruction or store instruction to load or store the data object. However, after the code conversion, each time a load instruction or store instruction is executed, the addition operation needs to be called first, resulting in redundant addition operation calls, which affects the execution efficiency. Summary of the invention

[0004] The embodiments of the present invention provide an operator implementation method, device, electronic device and storage medium, which can solve the problem that memory access operations easily cause redundant addition operation calls.

[0005] In order to solve the above problem, an embodiment of the present invention discloses an operator implementation method, which includes:

[0006] Acquire an operator to be implemented, wherein the operator to be implemented includes an addition operation and a memory access operation; the addition operation is used to calculate a first address synthesized by a source address and an offset corresponding to the memory access operation; and the memory access operation is used to access memory in the first address;

[0007] The target instruction is configured according to the source address and the offset; the target instruction includes a first bit field, a second bit field and a third bit field, the first bit field is used to record the memory access data corresponding to the memory access operation, the second bit field is used to record the source address corresponding to the memory access operation, and the third bit field is used to record the offset; the target instruction is used to access memory at an address synthesized by the source address and the offset.

[0008] Optionally, the target instruction includes a first instruction, and configuring the target instruction according to the source address and the offset includes:

[0009] If the offset satisfies a preset condition, determining an immediate value corresponding to the offset;

[0010] A first instruction is configured according to the source address and the immediate value; a third bit field of the first instruction includes the immediate value.

[0011] Optionally, the target instruction includes a second instruction, and configuring the target instruction according to the source address and the offset includes:

[0012] If the offset does not meet the preset condition, writing the offset into a temporary register;

[0013] A second instruction is configured according to the source address and the register number of the temporary register; a third bit field of the second instruction includes the register number.

[0014] Optionally, if the offset is greater than a first threshold and less than a second threshold, it is determined that the offset meets a preset condition; if the offset is less than the first threshold or greater than the second threshold, it is determined that the offset does not meet the preset condition.

[0015] Optionally, obtaining the operator to be implemented includes:

[0016] Acquire and parse the program to be compiled to obtain an addition operation and a memory access operation; the addition operation includes a fourth bit field, a fifth bit field, and a sixth bit field, and the addition operation is used to add the data recorded in the fifth bit field and the sixth bit field and write the data into the fourth bit field; the memory access operation includes a seventh bit field and an eighth bit field, and the memory access operation is used to load / store the data in the first address recorded in the seventh bit field into the second address recorded in the eighth bit field;

[0017] If the data recorded in the fourth bit field of the addition operation is the first address recorded in the seventh bit field of the memory access operation, the data recorded in the fifth bit field of the addition operation is determined as the source address corresponding to the memory access operation, and the data recorded in the sixth bit field of the addition operation is determined as the offset corresponding to the memory access operation, or the data recorded in the sixth bit field of the addition operation is determined as the source address corresponding to the memory access operation, and the data recorded in the fifth bit field of the addition operation is determined as the offset corresponding to the memory access operation; the data in the second address is determined as the memory access data corresponding to the memory access operation.

[0018] Optionally, the target instruction also includes an opcode field, and the opcode stored in the opcode field is used to distinguish different types of memory access operations; the opcode includes a first opcode or a second opcode, the first opcode is used to indicate a data loading operation, and the second opcode is used to indicate a data storage operation.

[0019] Optionally, for the first opcode and the second opcode, the source address is a memory address, which is stored in a source register, and the memory access data is stored in a destination register; the first bit field is the destination register number, and the second bit field is the source register number.

[0020] On the other hand, an embodiment of the present invention discloses an operator implementation device, the device comprising:

[0021] A data acquisition module, used to acquire an operator to be implemented, wherein the operator to be implemented includes an addition operation and a memory access operation; the addition operation is used to calculate a first address synthesized by a source address and an offset corresponding to the memory access operation; the memory access operation is used to access memory in the first address;

[0022] An instruction configuration module is used to configure a target instruction according to the source address and the offset; the target instruction includes a first bit field, a second bit field and a third bit field, the first bit field is used to record memory access data corresponding to the memory access operation, the second bit field is used to record the source address corresponding to the memory access operation, and the third bit field is used to record the offset; the target instruction is used to access memory at an address synthesized by the source address and the offset.

[0023] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to implement the aforementioned operator.

[0024] An embodiment of the present invention further discloses a readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned operator implementation method.

[0025] The embodiments of the present invention include the following advantages:

[0026] The embodiment of the present invention provides an operator implementation method, which can configure a target instruction according to a source address and an offset corresponding to a memory access operation, wherein the target instruction includes a first bit field, a second bit field, and a third bit field, wherein the first bit field is used to record memory access data corresponding to the memory access operation, the second bit field is used to record a source address corresponding to the memory access operation, and the third bit field is used to record an offset; through the target instruction, memory access can be performed at an address synthesized by the source address and the offset. Compared with the prior art, the embodiment of the present invention does not need to configure and execute an addition operation, and memory access can be achieved at an address synthesized by the source address and the offset only through the target instruction configured in the present invention. The target instruction provided by the embodiment of the present invention is used to perform data loading or storage operations, which reduces the call of the addition operation and is conducive to improving data processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0028] Figure 1 is a flowchart of steps of an operator implementation method embodiment of the present invention;

[0029] Figure 2 is a structural block diagram of an embodiment of an operator implementation device of the present invention;

[0030] Figure 3 It is a structural block diagram of an electronic device for operator implementation provided by an example of the present invention. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] Method Embodiment

[0033] Reference Figure 1 , shows a flowchart of an operator implementation method embodiment of the present invention, and the method may specifically include the following steps:

[0034] Step 101, obtaining an operator to be implemented, wherein the operator to be implemented includes an addition operation and a memory access operation; the addition operation is used to calculate a first address synthesized by a source address and an offset corresponding to the memory access operation; and the memory access operation is used to access memory in the first address.

[0035] Step 102: configure a target instruction according to the source address and the offset, the target instruction comprising a first bit field, a second bit field and a third bit field, the first bit field being used to record memory access data corresponding to a memory access operation, the second bit field being used to record a source address corresponding to the memory access operation, and the third bit field being used to record an offset; the target instruction being used to access memory at an address synthesized by the source address and the offset.

[0036] Among them, the memory access operation can be used to load the data in the address corresponding to the source address + offset into the register, or to store the data in the register into the address corresponding to the source address + offset. The memory access data is the data loaded from the memory address into the register or the data stored from the register into the memory address. The operation object of the memory access operation can be represented by a pointer variable. The pointer variable is a variable used to store the address. The content of the pointer variable stores the first address of the object it points to. The object pointed to can be an entity occupying storage space such as a variable, an array, or a function. In an embodiment of the present invention, if the operation object of the memory access operation is a pointer variable, the source address is the address stored in the pointer variable, that is, the first address of the object pointed to by the pointer, and the offset is the offset of the pointer variable. It can be understood that the offset of the pointer variable is determined by the type of the object pointed to by the pointer variable. The memory access data can be determined by the operation requirements of the memory access operation or the corresponding operation instructions.

[0037] In an embodiment of the present invention, if it is necessary to compile the code corresponding to the memory access operation, such as JIT code, the source address and offset corresponding to the memory access operation can be obtained first, and then the target instruction can be configured according to the source address and offset. Wherein, the target instruction includes a first bit field, a second bit field and a third bit field, the first bit field is used to record the memory access data corresponding to the memory access operation, the second bit field is used to record the source address corresponding to the memory access operation, and the third bit field is used to record the offset. According to the operation type, the target instruction can be divided into a load instruction and a store instruction. For example, a load instruction ld (reg_value, reg_ptr, offset) and a store instruction st (reg_value, reg_ptr, offset). Wherein, reg_value corresponds to the first bit field, records the memory access data corresponding to the memory access operation, reg_ptr corresponds to the second bit field, records the source address corresponding to the memory access operation, and offset corresponds to the third bit field, records the offset. reg_value is the destination register, and reg_ptr is the source register. The source address is stored in the reg_ptr register, and the memory access data is stored in the reg_value register. By executing the ld(reg_value,reg_ptr,offset) instruction, the data in the address [reg_ptr]+offset, which is the composite of the source address and the offset, can be loaded or put into the register reg_value, where [reg_ptr] represents the value stored in the register reg_ptr, i.e., the source address. By executing the st(reg_value,reg_ptr,offset) instruction, the data [reg_value] stored in the register reg_value can be stored in the composite address [reg_ptr]+offset.

[0038] In the prior art, if the data stored in the register is to be stored in the address synthesized by the source address and the offset, or the data in the address synthesized by the source address and the offset is to be loaded into the register, an addition operation needs to be performed first to calculate the sum of the source address and the offset, for example, the addition operation add_imm(ref_tmp_addr, reg_ptr, offset), where ref_tmp_addr = [reg_ptr] + offset. Then, a load instruction or a store instruction is executed, for example, the load instruction ld(reg_value, ref_tmp_addr) loads the data at the address ref_tmp_addr into the register reg_value, and the store instruction st(reg_value, ref_tmp_addr) stores the data stored in the register reg_value into the address ref_tmp_addr.

[0039] Obviously, compared with the prior art, the embodiment of the present invention does not need to configure and execute the addition operation, and can implement the memory access operation on the address synthesized by the source address and the offset only through the target instruction configured in the present invention. The target instruction provided by the embodiment of the present invention is used to implement the memory access operation, which reduces the call of the addition operation and is conducive to improving the data processing efficiency.

[0040] Optionally, the target instruction also includes an opcode field, and the opcode stored in the opcode field is used to distinguish different types of memory access operations; the opcode includes a first opcode or a second opcode, the first opcode is used to indicate a data loading operation, and the second opcode is used to indicate a data storage operation.

[0041] It can be understood that the first bit field, the second bit field and the third bit field all belong to the operand field of the target instruction, which are used to indicate the operation object of the target instruction. The target instruction also includes an operation code field, which is used to indicate the operation type of the target instruction. Specifically, an operation code is stored in the operation code field of the target instruction, and the operation code is used to distinguish different types of operations. In an embodiment of the present invention, the operation code of the target instruction can be divided into a first operation code and a second operation code, wherein the first operation code is used to indicate a data loading operation. If the first operation code is stored in the operation code field of the target instruction, it means that the target instruction is a loading instruction. When the target instruction is executed, the data stored in the address synthesized by the source address and the offset can be loaded into the destination register. The second operation code is used to indicate a data storage operation. If the second operation code is stored in the operation code field of the target instruction, it means that the target instruction is a storage instruction. When the target instruction is executed, the data in the destination register can be stored in the address synthesized by the source address and the offset.

[0042] Optionally, for the first operation code and the second operation code, the source address is a memory address stored in a source register, and the accessed data is stored in a destination register. The first bit field is the destination register number, and the second bit field is the source register number.

[0043] In an optional embodiment of the present invention, the target instruction includes a first instruction, and the step 102 of configuring the target instruction according to the source address and the offset includes:

[0044] Step S11: if the offset satisfies a preset condition, determining an immediate value corresponding to the offset;

[0045] Step S12: configure a first instruction according to the source address and the immediate value; the third bit field of the first instruction includes the immediate value.

[0046] In an embodiment of the present invention, different methods can be selected to configure the target instruction according to the offset and the preset condition. Specifically, if the offset satisfies the preset condition, the first instruction can be configured. The third bit field of the first instruction includes an immediate value, which can be determined according to the offset. For example, the immediate value can be the offset corresponding to the memory access operation.

[0047] When the offset meets the preset conditions, when executing the target instruction, i.e., the first instruction, the offset can be directly determined according to the immediate value in the third bit field without calling the register. Compared with the prior art in which the sum of the source address and the offset calculated by the addition operation is recorded in an intermediate register, the embodiment of the present invention not only reduces the number of addition operations, but also reduces the number of register calls, which is conducive to improving code running efficiency and data processing efficiency.

[0048] Wherein, the preset condition may be a value interval corresponding to the offset, which is used to determine whether the offset meets the preset condition according to the size of the offset. Optionally, if the offset is greater than the first threshold and less than the second threshold, it is determined that the offset meets the preset condition; if the offset is less than the first threshold or greater than the second threshold, it is determined that the offset does not meet the preset condition. It can be understood that the first threshold and the second threshold can be set according to actual needs. For example, the first threshold is -2048 and the second threshold is 2047. When the offset is between -2048 and 2047, it can be determined that the offset meets the preset condition. When the offset is less than -2048 or greater than 2047, it can be determined that the offset does not meet the preset condition. As an example, assuming that the offset is 1028 and meets the preset condition, the configured target instruction, that is, the first instruction in the present invention, can be a load instruction ld (reg_value, reg_ptr, 1028), or a storage instruction st (reg_value, reg_ptr, 1028).

[0049] It should be noted that the immediate number is usually 8 bits, 16 bits or 32 bits. If the offset is large, the offset cannot be recorded by the immediate number. Therefore, in an embodiment of the present invention, the recording method of the offset is distinguished by preset conditions. When the offset meets the preset conditions, it means that the offset is small, so the offset can be recorded by the immediate number, that is, the third bit field of the target instruction is configured as the immediate number corresponding to the offset. If the offset does not meet the preset conditions, it means that the offset is large. At this time, the offset cannot be recorded by the immediate number. A register can be pre-set, and the offset can be recorded in the register. The target instruction reads the offset by calling the register.

[0050] In an optional embodiment of the present invention, the target instruction includes a second instruction, and the step 102 of configuring the target instruction according to the source address and the offset includes:

[0051] Step S21: if the offset does not meet the preset condition, write the offset into a temporary register;

[0052] Step S22: configure a second instruction according to the source address and the register number of the temporary register; the third bit field of the second instruction includes the register number.

[0053] The temporary register is used to record the offset when the offset corresponding to the memory access operation does not meet the preset condition. The temporary register can be a 64-bit register. Of course, the temporary register can also be a 128-bit, 256-bit or other register. The embodiment of the present invention does not specifically limit the size of the storage space of the temporary register.

[0054] In an embodiment of the present invention, if the offset corresponding to the memory access operation does not meet the preset conditions, the offset can be directly written into a temporary register, and when configuring the target instruction, that is, the second instruction in the embodiment of the present invention, the register number of the temporary register is recorded in the third field, so that when executing the target instruction, the temporary register is called and the offset is read, and the data stored in the address synthesized by the source address and the offset is loaded into the register, or the data in the register is stored in the synthesized address. For example, assuming that the offset is 3011, the offset does not meet the preset conditions, and the offset 3011 is stored in the temporary register Rd, then the configured target instruction, that is, the second instruction in the present invention, can be a load instruction ldx(reg_value,reg_ptr,Rd), or stx(reg_value,reg_ptr,Rd).

[0055] Compared with the prior art of first calculating the sum of the source address and the offset through an addition operation and then executing the load / store instruction, the embodiment of the present invention can reduce the number of addition operations executed, which is beneficial to improving code running efficiency and data processing efficiency.

[0056] Moreover, in the present invention, a temporary register needs to be called when and only when the offset does not meet the preset conditions. Compared with the prior art, no matter what the offset value is, an intermediate register needs to be called to read the sum of the source address and the offset. The embodiment of the present invention can effectively reduce the number of register calls, which is conducive to further improving data processing efficiency.

[0057] In an optional embodiment of the present invention, the step 101 of obtaining the operator to be implemented includes:

[0058] Step S31, obtaining a program to be compiled and parsing it to obtain an addition operation and a memory access operation; the addition operation includes a fourth bit field, a fifth bit field, and a sixth bit field, and the addition operation is used to add the data recorded in the fifth bit field and the sixth bit field and write the data into the fourth bit field; the memory access operation includes a seventh bit field and an eighth bit field, and the memory access operation is used to load / store the data in the first address recorded in the seventh bit field into the second address recorded in the eighth bit field;

[0059] Step S32: If the data recorded in the fourth bit field of the addition operation is the first address recorded in the seventh bit field of the memory access operation, the data recorded in the fifth bit field of the addition operation is determined as the source address corresponding to the memory access operation, and the data recorded in the sixth bit field of the addition operation is determined as the offset corresponding to the memory access operation, or the data recorded in the sixth bit field of the addition operation is determined as the source address corresponding to the memory access operation, and the data recorded in the fifth bit field of the addition operation is determined as the offset corresponding to the memory access operation; the data in the second address is determined as the memory access data corresponding to the memory access operation.

[0060] In a possible application scenario, the operator implementation method provided by the embodiment of the present invention can be used to implement the real-time compilation of the program. Real-time compilation refers to compiling the hotspot code of the source program in the host machine into the target program in the client machine, optimizing the hotspot code in the source program in the client machine, and improving the execution efficiency of the hotspot code in the client machine.

[0061] In an embodiment of the present invention, the program to be compiled may be a hotspot code in a source program. The source address and offset corresponding to the memory access operation can be obtained by parsing the program to be compiled. The program to be compiled includes addition operations and memory access operations. Among them, the addition operation includes the fourth bit field, the fifth bit field and the sixth bit field, and the addition operation is used to add the data recorded in the fifth bit field and the sixth bit field and write them into the fourth bit field. For example, the addition operation add_imm(ref_tmp_addr, reg_ptr, offset), wherein ref_tmp_addr corresponds to the fourth bit field, reg_ptr corresponds to the fifth bit field, and offset corresponds to the sixth bit field, ref_tmp_addr = [reg_ptr] + offset. The memory access operation includes the seventh bit field and the eighth bit field, which are used to load / store the data stored in the first address recorded in the seventh bit field to the second address recorded in the eighth bit field. For example, the memory access operation ldr(Rd, addr) is used to load the data in addr into Rd.

[0062] If the data recorded in the fourth bit field of the addition operation in the program to be compiled is the first address recorded in the seventh bit field of the memory access operation, it means that the program to be compiled is used to load or store the data recorded in the first address synthesized by the fifth bit field and the sixth bit field of the addition operation into the second address. In order to reduce the call of the addition operation, the addition operation and the memory access operation in the program to be compiled can be compiled into the target instruction in the present invention. Specifically, the data recorded in the fifth bit field of the addition operation is determined as the source address corresponding to the memory access operation, and the data recorded in the sixth bit field of the addition operation is determined as the offset corresponding to the memory access operation, or the data recorded in the sixth bit field of the addition operation is determined as the source address corresponding to the memory access operation, and the data recorded in the fifth bit field of the addition operation is determined as the offset corresponding to the memory access operation; the data in the second address is determined as the memory access data corresponding to the memory access operation, and then the target instruction is configured according to the source address and the offset. The specific configuration method can refer to the relevant content in the aforementioned embodiment, and the embodiment of the present invention will not be further described here.

[0063] As an example, assume that the program to be compiled is a for loop for depthwise convolution:

[0064] add_imm(reg_tmp_addr,reg_bias,b_off*sizeof(float),

[0065] reg_tmp_imm);

[0066] ldr(zreg_acc,ptr(reg_tmp_addr))

[0067] The addition operation add_imm is used to calculate the sum of the address [reg_bias] and the offset b_off*sizeof(float), reg_tmp_addr=[reg_bias]+b_off*sizeof(float). The memory access operation ldr is used to load the data stored in reg_tmp_addr into zreg_acc.

[0068] The instruction to be compiled is compiled according to the operator implementation method provided in the embodiment of the present invention, the source address corresponding to the data loading operation is [reg_bias], the offset is b_off*sizeof(float), the memory access data is [zreg_acc], and the target instruction obtained after compilation is: uni_ld(zreg_acc, reg_bias, b_off*sizeof(float)).

[0069] After the above compilation, the addition operation can be directly removed. In the JIT hotspot code on one end, removing the addition operation for calculating the offset can reduce the number of instructions by 5% to 20%, effectively reducing the number of instructions executed during code running and improving code execution efficiency.

[0070] In summary, an embodiment of the present invention provides an operator implementation method, which can configure a target instruction according to a source address and an offset corresponding to a memory access operation, wherein the target instruction includes a first bit field, a second bit field, and a third bit field, wherein the first bit field is used to record memory access data corresponding to the memory access operation, the second bit field is used to record the source address corresponding to the memory access operation, and the third bit field is used to record the offset; by executing the target instruction, memory access can be performed at an address synthesized by the source address and the offset. Compared with the prior art, the embodiment of the present invention does not need to configure and execute an addition operation, and memory access can be achieved at an address synthesized by the source address and the offset only through the target instruction configured in the present invention. The target instruction provided by the embodiment of the present invention is used to perform data loading or storage operations, which reduces the call of the addition operation and is conducive to improving data processing efficiency.

[0071] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0072] Device Embodiment

[0073] Reference Figure 2 , shows a structural block diagram of an embodiment of an operator implementation device of the present invention, and the device may specifically include:

[0074] The data acquisition module 201 is used to acquire the operator to be implemented, and the operator to be implemented includes an addition operation and a memory access operation; the addition operation is used to calculate a first address synthesized by a source address and an offset corresponding to the memory access operation; the memory access operation is used to access memory in the first address;

[0075] The instruction configuration module 202 is used to configure a target instruction according to the source address and the offset, the target instruction includes a first bit field, a second bit field and a third bit field, the first bit field is used to record the memory access data corresponding to the memory access operation, the second bit field is used to record the source address corresponding to the memory access operation, and the third bit field is used to record the offset; the target instruction is used to access memory at an address synthesized by the source address and the offset.

[0076] Optionally, the target instruction includes a first instruction, and the instruction configuration module includes:

[0077] An immediate number determination submodule, used for determining an immediate number corresponding to the offset if the offset satisfies a preset condition;

[0078] The first configuration submodule is used to configure a first instruction according to the source address and the immediate value; the third bit field of the first instruction includes the immediate value.

[0079] Optionally, the target instruction includes a second instruction, and the instruction configuration module includes:

[0080] A writing submodule, used for writing the offset into a temporary register if the offset does not meet a preset condition;

[0081] The second configuration submodule is used to configure the second instruction according to the source address and the register number of the temporary register; the third bit field of the second instruction includes the register number.

[0082] Optionally, if the offset is greater than a first threshold and less than a second threshold, it is determined that the offset meets a preset condition; if the offset is less than the first threshold or greater than the second threshold, it is determined that the offset does not meet the preset condition.

[0083] Optionally, the data acquisition module includes:

[0084] The program acquisition submodule is used to acquire and parse the program to be compiled to obtain an addition operation and a memory access operation; the addition operation includes a fourth bit field, a fifth bit field and a sixth bit field, and the addition operation is used to add the data recorded in the fifth bit field and the sixth bit field and write the data into the fourth bit field; the memory access operation includes a seventh bit field and an eighth bit field, and the memory access operation is used to load / store the data in the first address recorded in the seventh bit field into the second address recorded in the eighth bit field;

[0085] A data determination submodule, used for determining the data recorded in the fifth bit field of the addition operation as the source address corresponding to the memory access operation, and determining the data recorded in the sixth bit field of the addition operation as the offset corresponding to the memory access operation if the data recorded in the fourth bit field of the addition operation is the first address recorded in the seventh bit field of the memory access operation, or determining the data recorded in the sixth bit field of the addition operation as the source address corresponding to the memory access operation, and determining the data recorded in the fifth bit field of the addition operation as the offset corresponding to the memory access operation; and determining the data in the second address as the memory access data corresponding to the memory access operation.

[0086] Optionally, the target instruction also includes an opcode field, and the opcode stored in the opcode field is used to distinguish different types of memory access operations; the opcode includes a first opcode or a second opcode, the first opcode is used to indicate a data loading operation, and the second opcode is used to indicate a data storage operation.

[0087] Optionally, for the first opcode and the second opcode, the source address is a memory address, which is stored in a source register, and the memory access data is stored in a destination register; the first bit field is the destination register number, and the second bit field is the source register number.

[0088] In summary, an embodiment of the present invention provides an operator implementation device, which can configure a target instruction according to a source address and an offset corresponding to a memory access operation, wherein the target instruction includes a first bit field, a second bit field, and a third bit field, wherein the first bit field is used to record memory access data corresponding to the memory access operation, the second bit field is used to record the source address corresponding to the memory access operation, and the third bit field is used to record the offset; by executing the target instruction, memory access can be performed at an address synthesized by the source address and the offset. Compared with the prior art, the embodiment of the present invention does not need to configure and execute an addition operation, and memory access can be achieved at an address synthesized by the source address and the offset only through the target instruction configured in the present invention. The use of the target instruction provided by the embodiment of the present invention for data loading or storage operations reduces the call of the addition operation, which is conducive to improving data processing efficiency.

[0089] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0090] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0091] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0092] An embodiment of the present invention provides an electronic device for operator implementation, the electronic device comprising a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors, wherein the one or more programs include instructions for performing the following operations:

[0093] A11. Obtain an operator to be implemented, wherein the operator to be implemented includes an addition operation and a memory access operation; the addition operation is used to calculate a first address synthesized by a source address and an offset corresponding to the memory access operation; and the memory access operation is used to access memory in the first address;

[0094] A12. Configure a target instruction according to the source address and the offset; the target instruction includes a first bit field, a second bit field and a third bit field, the first bit field is used to record the memory access data corresponding to the memory access operation, the second bit field is used to record the source address corresponding to the memory access operation, and the third bit field is used to record the offset; the target instruction is used to access memory at an address synthesized by the source address and the offset.

[0095] Optionally, the target instruction includes a first instruction, and configuring the target instruction according to the source address and the offset includes:

[0096] If the offset satisfies a preset condition, determining an immediate value corresponding to the offset;

[0097] A first instruction is configured according to the source address and the immediate value; a third bit field of the first instruction includes the immediate value.

[0098] Optionally, the target instruction includes a second instruction, and configuring the target instruction according to the source address and the offset includes:

[0099] If the offset does not meet the preset condition, writing the offset into a temporary register;

[0100] A second instruction is configured according to the source address and the register number of the temporary register; a third bit field of the second instruction includes the register number.

[0101] Optionally, if the offset is greater than a first threshold and less than a second threshold, it is determined that the offset meets a preset condition; if the offset is less than the first threshold or greater than the second threshold, it is determined that the offset does not meet the preset condition.

[0102] Optionally, obtaining the operator to be implemented includes:

[0103] Acquire and parse the program to be compiled to obtain an addition operation and a memory access operation; the addition operation includes a fourth bit field, a fifth bit field, and a sixth bit field, and the addition operation is used to add the data recorded in the fifth bit field and the sixth bit field and write the data into the fourth bit field; the memory access operation includes a seventh bit field and an eighth bit field, and the memory access operation is used to load / store the data in the first address recorded in the seventh bit field into the second address recorded in the eighth bit field;

[0104] If the data recorded in the fourth bit field of the addition operation is the first address recorded in the seventh bit field of the memory access operation, the data recorded in the fifth bit field of the addition operation is determined as the source address corresponding to the memory access operation, and the data recorded in the sixth bit field of the addition operation is determined as the offset corresponding to the memory access operation, or the data recorded in the sixth bit field of the addition operation is determined as the source address corresponding to the memory access operation, and the data recorded in the fifth bit field of the addition operation is determined as the offset corresponding to the memory access operation; the data in the second address is determined as the memory access data corresponding to the memory access operation.

[0105] Optionally, the target instruction also includes an opcode field, and the opcode stored in the opcode field is used to distinguish different types of memory access operations; the opcode includes a first opcode or a second opcode, the first opcode is used to indicate a data loading operation, and the second opcode is used to indicate a data storage operation.

[0106] Optionally, for the first opcode and the second opcode, the source address is a memory address, which is stored in a source register, and the memory access data is stored in a destination register; the first bit field is the destination register number, and the second bit field is the source register number.

[0107] Figure 3 6 is a block diagram of an electronic device 600 for operator implementation according to an exemplary embodiment. For example, the electronic device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0108] Reference Figure 3 , the electronic device 600 may include one or more of the following components: a processing component 602 , a memory 604 , a power component 606 , a multimedia component 608 , an audio component 610 , an input / output (I / O) interface 612 , a sensor component 614 , and a communication component 616 .

[0109] The processing component 602 generally controls the overall operation of the electronic device 600, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 602 may include one or more modules to facilitate the interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.

[0110] The memory 604 is configured to store various types of data to support operations on the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phone book data, messages, pictures, videos, etc. The memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0111] The power supply component 606 provides power to the various components of the electronic device 600. The power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 600.

[0112] The multimedia component 608 includes a screen that provides an output interface between the electronic device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the electronic device 600 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and the rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0113] The audio component 610 is configured to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC), and when the electronic device 600 is in an operating mode, such as a call mode, a recording mode, and a voice information processing mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 604 or sent via the communication component 616. In some embodiments, the audio component 610 also includes a speaker for outputting audio signals.

[0114] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0115] The sensor assembly 614 includes one or more sensors for providing various aspects of status assessment for the electronic device 600. For example, the sensor assembly 614 can detect the open / closed state of the electronic device 600, the relative positioning of the components, such as the display and keypad of the device 600, and the sensor assembly 614 can also detect the position change of the electronic device 600 or a component of the electronic device 600, the presence or absence of user contact with the electronic device 600, the orientation or acceleration / deceleration of the electronic device 600, and the temperature change of the electronic device 600. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 614 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0116] The communication component 616 is configured to facilitate wired or wireless communication between the electronic device 600 and other devices. The electronic device 600 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 616 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency information processing (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0117] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0118] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, and the instructions can be executed by a processor 620 of an electronic device 600 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0119] A non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to execute Figure 1 The operator implementation method shown.

[0120] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0121] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0122] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable operator to implement a terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable operator to implement the terminal device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0123] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable operator to implement a terminal device to operate in a predictive manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0124] These computer program instructions can also be loaded onto a computer or other programmable terminal device so that a series of operation steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1The steps for the functions specified in one or more boxes.

[0125] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0126] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0127] The above is a detailed introduction to an operator implementation method, device, electronic device and storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. An operator implementation method, characterized in that: The method comprises: Acquire an operator to be implemented, the operator to be implemented includes an addition operation and a memory access operation; the addition operation is used to calculate a first address synthesized by a source address and an offset corresponding to the memory access operation; the memory access operation is used to access memory in the first address; The target instruction is configured according to the source address and the offset; the target instruction includes a first bit field, a second bit field and a third bit field, the first bit field is used to record the memory access data corresponding to the memory access operation, the second bit field is used to record the source address corresponding to the memory access operation, and the third bit field is used to record the offset; the target instruction is used to access memory at an address synthesized by the source address and the offset.

2. The method according to claim 1, characterized in that The target instruction includes a first instruction, and configuring the target instruction according to the source address and the offset includes: If the offset satisfies a preset condition, determining an immediate value corresponding to the offset; A first instruction is configured according to the source address and the immediate value; a third bit field of the first instruction includes the immediate value.

3. The method according to claim 1, characterized in that The target instruction includes a second instruction, and configuring the target instruction according to the source address and the offset includes: If the offset does not meet the preset condition, writing the offset into a temporary register; A second instruction is configured according to the source address and the register number of the temporary register; a third bit field of the second instruction includes the register number.

4. The method according to claim 2 or 3, characterized in that: If the offset is greater than the first threshold and less than the second threshold, it is determined that the offset meets the preset condition; if the offset is less than the first threshold or greater than the second threshold, it is determined that the offset does not meet the preset condition.

5. The method according to claim 1, characterized in that The obtaining of the operator to be implemented includes: Acquire and parse the program to be compiled to obtain an addition operation and a memory access operation; the addition operation includes a fourth bit field, a fifth bit field, and a sixth bit field, and the addition operation is used to add the data recorded in the fifth bit field and the sixth bit field and write the data into the fourth bit field; the memory access operation includes a seventh bit field and an eighth bit field, and the memory access operation is used to load / store the data in the first address recorded in the seventh bit field into the second address recorded in the eighth bit field; If the data recorded in the fourth bit field of the addition operation is the first address recorded in the seventh bit field of the memory access operation, the data recorded in the fifth bit field of the addition operation is determined as the source address corresponding to the memory access operation, and the data recorded in the sixth bit field of the addition operation is determined as the offset corresponding to the memory access operation, or the data recorded in the sixth bit field of the addition operation is determined as the source address corresponding to the memory access operation, and the data recorded in the fifth bit field of the addition operation is determined as the offset corresponding to the memory access operation; the data in the second address is determined as the memory access data corresponding to the memory access operation.

6. The method according to claim 1, characterized in that The target instruction also includes an opcode field, and the opcode stored in the opcode field is used to distinguish different types of memory access operations; the opcode includes a first opcode or a second opcode, the first opcode is used to indicate a data loading operation, and the second opcode is used to indicate a data storage operation.

7. The method according to claim 6, characterized in that For the first opcode and the second opcode, the source address is a memory address stored in a source register, and the memory access data is stored in a destination register; the first bit field is the destination register number, and the second bit field is the source register number.

8. An operator implementation device, characterized in that: The device comprises: A data acquisition module, used to acquire an operator to be implemented, wherein the operator to be implemented includes an addition operation and a memory access operation; the addition operation is used to calculate a first address synthesized by a source address and an offset corresponding to the memory access operation; the memory access operation is used to access memory in the first address; An instruction configuration module is used to configure a target instruction according to the source address and the offset; the target instruction includes a first bit field, a second bit field and a third bit field, the first bit field is used to record memory access data corresponding to the memory access operation, the second bit field is used to record the source address corresponding to the memory access operation, and the third bit field is used to record the offset; the target instruction is used to access memory at an address synthesized by the source address and the offset.

9. An electronic device, characterized in that: The electronic device comprises a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to execute the operator implementation method according to any one of claims 1 to 7 by one or more processors.

10. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the processor is enabled to execute the operator implementation method as described in any one of claims 1 to 7.

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