Method and system for safely upgrading FPGA (Field Programmable Gate Array) logic configuration file version on line

Abstract

The invention provides a method and a system for online and safely upgrading an FPGA (Field Programmable Gate Array) logic configuration file version, which are characterized in that a basic version, a formal version and a standby version are stored in a flash, the standby version is firstly updated during online upgrading, and if the updating is successful, a jump address in a configuration field is modified to a first row address of the standby version; and after modification is completed, the formal version is updated through online upgrading, and if updating succeeds, the jump address in the configuration field is modified to the first row address of the formal version. By means of the method, the FPGA logic configuration file version is safely upgraded on line, the reliability and safety of the FPGA logic version on-line upgrading can be improved, even if the on-line upgrading fails, it can be guaranteed that the FPGA powered on again has normal functions, and FPGA function loss caused by version faults in flash is avoided.

Description

Technical Field

[0001] The present invention relates to the field of FPGA technology, and in particular to a method and system for online secure upgrading of FPGA logic configuration file versions. Background Art

[0002] Online upgrade of the logic version through FPGA is currently a common upgrade method. The flash is connected to the FPGA. When the version needs to be upgraded, the flash-related area is erased through the FPGA, and the upgrade content is written to the flash-related area through the FPGA. When the device is restarted after powering off, the FPGA will load the upgraded logic version from the flash.

[0003] Through online upgrade, the FPGA upgrades the flash content, avoiding the need for additional external wiring to operate the flash. The operation is simple and efficient. However, if an unexpected situation occurs during the online upgrade, causing the content in the flash to be damaged or the version to be incomplete, the FPGA will not be able to load after power off, and the device will become invalid. To avoid this problem, a common solution is to store two versions in the flash, namely the golden version and the update version, such as Figure 1 As shown. To distinguish between the golden version and the update version, the golden version usually does not have specific functions, but can support online upgrade functions. In the configuration field of the flash header address, set the jump address to the first line address of the update version. When powered on, the FPGA loads data from the flash. When the jump address is detected, it will directly jump to the location of the update version for loading until the end of the update version is detected, ending this loading. At this time, the FPGA will have the update version function. If there is a problem with the update version, when the update version fails to load, the FPGA will jump to the first line address of the flash to reload the golden version. At this time, the FPGA will have the golden version function.

[0004] Based on this design, during the online upgrade process, only the update version is upgraded, and the golden version is not updated. If an unexpected error occurs during the online upgrade process, causing the update version to fail, the FPGA will load the golden version from the flash after powering off and restarting. This version has the online upgrade function and can refresh the update version again.

[0005] This design can avoid the problem of FPGA not working due to online upgrade failure. However, since the golden version does not have specific functions, if the update version fails and cannot be repaired through online upgrade, the FPGA will still not work properly. Summary of the invention

[0006] The purpose of the present invention is to provide a method for online secure upgrading of FPGA logic configuration file version, which can improve the reliability and security of online upgrading of FPGA logic version, avoid FPGA function loss caused by anomalies during the online upgrading process, and prevent normal operation.

[0007] According to a first aspect of the present invention, a method for online secure upgrading of an FPGA logic configuration file version is provided, comprising the following steps:

[0008] The configuration fields and different versions of logic configuration files are stored in the flash, wherein the logic configuration files include a basic version, a formal version, and a backup version that can be loaded into the FPGA, wherein the basic version only has an online upgrade function and does not have a specific logic function; the formal version and the backup version are exactly the same, and both have an online upgrade function and a specific logic function;

[0009] When the FPGA is powered on, the official version is first loaded from the flash. After loading, the official version is used for online upgrade:

[0010] - The backup version will be updated first if it is upgraded first. If the backup version is updated successfully, the jump address in the configuration field will be modified to the first line address of the updated backup version;

[0011] -After the modification is completed, update the official version through online upgrade. If the update is successful, modify the jump address in the configuration field to the first line address of the updated official version;

[0012] After completing the online upgrade of the official version and the backup version, the official version and the backup version in the flash are updated to the upgraded version, and the jump address in the configuration field is the first row address of the official version. When the FPGA is powered off and restarted, the FPGA reads the content from the flash, and loads the upgraded version from the first row address of the official version by reading the jump address in the configuration field until the loading is completed, thereby realizing the update of the FPGA logic function.

[0013] According to a second aspect of the present invention, a system for online secure upgrade of FPGA logic configuration file version is provided, comprising:

[0014] flash, connected to the FPGA, and used to store configuration fields and different versions of logic configuration files, wherein the logic configuration files include a basic version, a formal version, and a backup version that can be loaded into the FPGA, wherein the basic version only has an online upgrade function and does not have a specific logic function; the formal version and the backup version are exactly the same, and both have an online upgrade function and specific logic functions;

[0015] The FPGA is configured to first load the official version from flash after power-on, and then perform an online upgrade using the official version after loading, including:

[0016] - The backup version will be updated first if it is upgraded first. If the backup version is updated successfully, the jump address in the configuration field will be modified to the first line address of the updated backup version;

[0017] -After the modification is completed, update the official version through online upgrade. If the update is successful, modify the jump address in the configuration field to the first line address of the updated official version;

[0018] Among them, after completing the online upgrade of the official version and the backup version, the official version and the backup version in the flash are updated to the upgraded version, and the jump address in the configuration field is set to the first row address of the official version. When the FPGA is powered off and restarted, the FPGA reads the content from the flash, and loads the upgraded version from the first row address of the official version by reading the jump address in the configuration field until the loading is completed, thereby realizing the update of the FPGA logic function.

[0019] In combination with the above system and method of the present invention, three versions, namely the basic version, the formal version and the backup version, are stored in the flash. When upgrading online, the backup version is updated first. If the update is successful, the jump address in the configuration field is modified to the first line address of the backup version. After the modification is completed, the formal version is updated through online upgrading. If the update is successful, the jump address in the configuration field is modified to the first line address of the formal version. Therefore, the present invention can greatly improve the reliability of online upgrading of the FPGA logic version through the above operation. Even if the online upgrade fails, it can ensure that the FPGA has normal functions after powering on again. Therefore, the reliability and security of the online upgrade process can be improved, and the influence of the online upgrade failure on the FPGA function can be effectively avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The present invention is a schematic diagram of storing a golden version and an update version of an FPGA logic configuration file in a flash according to the prior art.

[0021] Figure 2It is a schematic diagram of storing a golden version and an update version of an FPGA logic configuration file in a flash according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to better understand the technical content of the present invention, specific embodiments are given and described as follows in conjunction with the accompanying drawings.

[0023] Various aspects of the present invention are described in this disclosure with reference to the accompanying drawings, in which many illustrative embodiments are shown. The embodiments of the present disclosure are not necessarily intended to include all aspects of the present invention. It should be understood that the various concepts and embodiments introduced above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed by the present invention are not limited to any implementation. In addition, some aspects disclosed by the present invention can be used alone or in any appropriate combination with other aspects disclosed by the present invention.

[0024] {Example 1}

[0025] Combination Figure 2 As shown, the method for online secure upgrading of the FPGA logic configuration file version according to an embodiment of the present invention includes the following steps:

[0026] The configuration fields and different versions of logic configuration files are stored in the flash, wherein the logic configuration files include a basic version, a formal version, and a backup version that can be loaded into the FPGA, wherein the basic version only has an online upgrade function and does not have a specific logic function; the formal version and the backup version are exactly the same, and both have an online upgrade function and a specific logic function;

[0027] When the FPGA is powered on, the official version is first loaded from the flash. After loading, the official version is used for online upgrade:

[0028] - The backup version will be updated first if it is upgraded first. If the backup version is updated successfully, the jump address in the configuration field will be modified to the first line address of the updated backup version;

[0029] -After the modification is completed, update the official version through online upgrade. If the update is successful, modify the jump address in the configuration field to the first line address of the updated official version;

[0030] After completing the online upgrade of the official version and the backup version, the official version and the backup version in the flash are updated to the upgraded version, and the jump address in the configuration field is the first row address of the official version. When the FPGA is powered off and restarted, the FPGA reads the content from the flash, and loads the upgraded version from the first row address of the official version by reading the jump address in the configuration field until the loading is completed, thereby realizing the update of the FPGA logic function.

[0031] As an optional implementation, the configuration field includes a jump address, and when the FPGA reads the flash content and detects the jump address, it jumps to the jump address to load the version until the version end mark is detected, and the loading is completed. The jump address in the configuration field is configured as the first line address of the official version by default.

[0032] As an optional implementation, if the version loaded when jumping to the jump address fails, the address of the first row of the flash is returned to continue reading to load the basic version.

[0033] As an optional implementation method, if an exception occurs during the online upgrade of the backup version, resulting in a failure of the backup version, the FPGA is powered off and restarted, and the content is read from the flash. At this time, the official version stored in the flash can be loaded normally, and the backup version is the faulty version. By reading the jump address in the flash configuration field, the first line address of the official version is obtained, and the formal version is loaded by jumping to the first line address of the official version until the end mark of the official version is detected and the loading is terminated. After loading is completed, the FPGA has the logical function of the official version.

[0034] As an optional implementation method, if an exception occurs during the online upgrade of the official version, resulting in a failure of the official version, the FPGA reads the content from the flash after powering off and restarting. At this time, the backup version stored in the flash is a successfully updated upgraded version and can be loaded normally. The official version is a faulty version. The FPGA reads the jump address in the flash configuration field to obtain the first row address of the updated backup version, that is, the first row address of the upgraded version after the successful update, jumps to the first row address of the backup version to start loading the upgraded version, and ends loading after detecting the end mark of the backup version. After loading is completed, the FPGA has the logical function of the upgraded version.

[0035] {Example 2}

[0036] The system for online secure upgrading of an FPGA logic configuration file version according to an embodiment of the present invention includes a flash and an FPGA connected to the flash and capable of data communication.

[0037] flash, connected to the FPGA, is used to store configuration fields and different versions of logic configuration files, wherein the logic configuration files include a basic version, a formal version, and a backup version that can be loaded into the FPGA, wherein the basic version only has an online upgrade function but does not have a specific logic function; the formal version and the backup version are exactly the same, both having an online upgrade function and a specific logic function.

[0038] The FPGA is configured to first load the official version from flash after power-on, and then perform an online upgrade using the official version after loading, including:

[0039] - The backup version will be updated first if it is upgraded first. If the backup version is updated successfully, the jump address in the configuration field will be modified to the first line address of the updated backup version;

[0040] -After the modification is completed, update the official version through online upgrade. If the update is successful, change the jump address in the configuration field to the first line address of the updated official version.

[0041] Therefore, after completing the online upgrade of the official version and the backup version, the official version and the backup version in the flash are updated to the upgraded version, and the jump address in the configuration field is set to the first row address of the official version. When the FPGA is powered off and restarted, the FPGA reads the content from the flash, and loads the upgraded version from the first row address of the official version by reading the jump address in the configuration field until the loading is completed, thereby realizing the update of the FPGA logic function.

[0042] As an optional implementation, the aforementioned configuration field includes a jump address. When the FPGA reads the flash content and detects the jump address, it jumps to the jump address to load the version until the version end mark is detected, and the loading is completed; wherein the jump address in the configuration field is configured by default as the first line address of the official version.

[0043] As an optional implementation, if the jump to the jump address to load the version fails, then return to the first line address of the flash to continue reading and load the basic version.

[0044] As an optional implementation method, if an exception occurs during the online upgrade of the backup version, resulting in a failure of the backup version, the FPGA is powered off and restarted, and the content is read from the flash. At this time, the official version stored in the flash can be loaded normally, and the backup version is the faulty version. By reading the jump address in the flash configuration field, the first line address of the official version is obtained, and the formal version is loaded by jumping to the first line address of the official version until the end mark of the official version is detected and the loading is terminated. After loading is completed, the FPGA has the logical function of the official version.

[0045] As an optional implementation method, if an exception occurs during the online upgrade of the official version, resulting in a failure of the official version, the FPGA reads the content from the flash after powering off and restarting. At this time, the backup version stored in the flash is a successfully updated upgraded version and can be loaded normally. The official version is a faulty version. The FPGA reads the jump address in the flash configuration field to obtain the first row address of the updated backup version, that is, the first row address of the upgraded version after the successful update, jumps to the first row address of the backup version to start loading the upgraded version, and ends loading after detecting the end mark of the backup version. After loading is completed, the FPGA has the logical function of the upgraded version.

[0046] {Example 3}

[0047] Combination Figure 2 As shown, based on the method for online secure upgrading of the FPGA logic configuration file version in the previous embodiment, we further elaborate on it in this example.

[0048] In the flash, the configuration field, basic version, basic version end, official version, official version end, backup version, and backup version end are written according to the storage content.

[0049] The configuration field contains the jump address information. When the jump address is detected, it will jump to the jump address for loading until the end mark is detected, and the loading is completed.

[0050] If the version loaded by jumping to the jump address fails, it returns to the first line address of the flash and loads the basic version. The jump address in the configuration field defaults to the first line address of the official version (address 1 in the figure).

[0051] The basic version only has the online upgrade function and does not have specific functions, which is equivalent to the golden version in the existing technology.

[0052] The first line address of the official version is address 1, which has online upgrade function and specific logic functions.

[0053] The first line address of the backup version is address 2, and its function is exactly the same as the official version.

[0054] If an online upgrade is required, from version A to version B, the process is as follows:

[0055] Step 1: FPGA is powered on and starts up. FPGA reads content from flash. At this time, the official version and backup version stored in flash are both version A. By reading the jump address in the configuration field, the first line address of the official version is used by default. Address 1 is obtained and jumps to address 1 to load the official version (i.e. version A) until the end mark of the official version is detected. This ends the loading. At this time, FPGA has the function of version A.

[0056] Step 2: FPGA is upgraded online through version A, the backup version data in the flash is erased, and after the erasure is completed, version B is rewritten, thereby updating the backup version from version A to version B;

[0057] Step 3: After the standby version is updated to version B, the jump address in the configuration field is modified to the first line address of the standby version (address 2), which is now configured as the first line address of version B of the standby version;

[0058] Step 4: FPGA is upgraded online through version A, and the data of the official version in the flash is erased, that is, the data of version A stored in the flash is erased, and after the erasure is completed, version B is rewritten, thereby updating the official version from version A to version B;

[0059] Step 5: After the official version is updated to version B, the jump address in the configuration field is modified to the first line address of the official version (address 1). At this time, it is configured as the first line address of version B of the official version.

[0060] Therefore, after the online upgrade is completed, the data of the official version and the backup version in the flash are updated to version B, and the jump address in the configuration field is the address of the first line of the official version. After the FPGA is powered off and restarted, the FPGA loads the version from the flash, obtains address one by reading the jump address in the configuration field, jumps to address one to load the official version B, and ends the loading until the end of the official version is detected. At this time, the FPGA has the version B function.

[0061] In the operation of the above method, step 2 and step 4 are flash version update operations performed through FPGA. This operation is used to update the version content in the flash and is the step with the highest risk in the online upgrade process. If an abnormality occurs during the update process, it will cause version failure in the flash.

[0062] In combination with the above upgrade process and configuration, the method of the present invention can avoid FPGA function loss caused by abnormalities during the online upgrade process.

[0063] Combination Figure 2In step 2, if an exception occurs during the online upgrade of the backup version, resulting in a backup version failure, the FPGA is powered off and restarted, and the content is read from the flash. At this time, the official version (i.e., version A) stored in the flash can be loaded normally, and the backup version is a faulty version (the backup version upgrade is abnormal). By reading the jump address in the flash configuration field, address 1, i.e., the first line address of the official version, is obtained, and then the address is jumped to the first line address of the official version to start loading the official version (i.e., version A) until the end mark of the official version is detected, and the loading is terminated; after loading is completed, the FPGA has the logical function of the official version.

[0064] At this time, the FPGA can have the normal functions of version A and will not affect the normal use of the device.

[0065] Combination Figure 2 In step 4, if an exception occurs during the online upgrade of the official version, resulting in a failure of the official version, the FPGA is powered off and restarted, and the content is read from the flash. At this time, the backup version stored in the flash is the successfully updated upgrade version (i.e., version B), which can be loaded normally, and the official version is a faulty version (the official version data upgrade is abnormal). The FPGA obtains address 2, i.e., the first row address of the updated backup version, by reading the jump address in the flash configuration field, and jumps to the first row address of the backup version to start loading the upgrade version (i.e., version B) until the end mark of the backup version is detected, and the loading is terminated; after loading is completed, the FPGA has the logical function of the upgraded version.

[0066] At this time, the FPGA can have the normal functions of version B and will not affect the normal use of the device.

[0067] Therefore, through the above-mentioned upgrade process and the operation of upgrade exceptions, the reliability of the online upgrade process can be improved, ensuring that after an exception occurs during the upgrade process, the FPGA can still have normal logical functions after being re-powered on and loaded, without affecting the normal use of the equipment, and can effectively avoid the impact of online upgrade failures on FPGA functions.

[0068] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the claims.

Claims

1. A method for online secure upgrade of FPGA logic configuration file version, characterized in that: The following steps are involved: The configuration fields and different versions of logic configuration files are stored in the flash, wherein the logic configuration files include a basic version, a formal version, and a backup version that can be loaded into the FPGA, wherein the basic version only has an online upgrade function and does not have a specific logic function; the formal version and the backup version are exactly the same, and both have an online upgrade function and a specific logic function; When the FPGA is powered on, the official version is first loaded from the flash. After loading, the official version is used for online upgrade: - The backup version will be updated first if it is upgraded first. If the backup version is updated successfully, the jump address in the configuration field will be modified to the first line address of the updated backup version; -After the modification is completed, update the official version through online upgrade. If the update is successful, modify the jump address in the configuration field to the first line address of the updated official version; After completing the online upgrade of the official version and the backup version, the official version and the backup version in the flash are updated to the upgraded version, and the jump address in the configuration field is the first row address of the official version. When the FPGA is powered off and restarted, the FPGA reads the content from the flash, and loads the upgraded version from the first row address of the official version by reading the jump address in the configuration field until the loading is completed, thereby realizing the update of the FPGA logic function.

2. The method for online secure upgrading of FPGA logic configuration file version according to claim 1, characterized in that: The configuration field includes a jump address. When the FPGA reads the flash content and detects the jump address, it jumps to the jump address to load the version until the version end mark is detected, and the loading is completed.

3. The method for online secure upgrading of FPGA logic configuration file version according to claim 2, characterized in that: The jump address in the configuration field is configured by default as the first line address of the official version.

4. The method for online secure upgrading of FPGA logic configuration file version according to claim 2, characterized in that: If the version loaded by jumping to the jump address fails, it returns to the first line address of the flash to continue reading and load the basic version.

5. The method for online secure upgrading of FPGA logic configuration file version according to claim 1, characterized in that: If an exception occurs during the online upgrade process of updating the backup version, resulting in a backup version failure, the FPGA is powered off and restarted, and the content is read from the flash. At this time, the official version stored in the flash can be loaded normally, and the backup version is the faulty version. By reading the jump address in the flash configuration field, the first line address of the official version is obtained, and the official version is loaded by jumping to the first line address of the official version until the end mark of the official version is detected, and the loading is terminated; after loading is completed, the FPGA has the logical function of the official version.

6. The method for online secure upgrading of FPGA logic configuration file version according to claim 1, characterized in that: If an exception occurs during the online upgrade of the official version, resulting in a failure of the official version, the FPGA will be powered off and restarted, and the content will be read from the flash. At this time, the backup version stored in the flash is the successfully updated upgrade version and can be loaded normally. The official version is the faulty version. The FPGA reads the jump address in the flash configuration field to obtain the first row address of the updated backup version, that is, the first row address of the upgraded version after the successful update, jumps to the first row address of the backup version to start loading the upgraded version, and ends loading after detecting the end mark of the backup version. After loading, the FPGA has the logical function of the upgraded version.

7. A system for online secure upgrade of FPGA logic configuration file version, characterized in that: include: flash, connected to the FPGA, and used to store configuration fields and different versions of logic configuration files, wherein the logic configuration files include a basic version, a formal version, and a backup version that can be loaded into the FPGA, wherein the basic version only has an online upgrade function and does not have a specific logic function; the formal version and the backup version are exactly the same, and both have an online upgrade function and specific logic functions; The FPGA is configured to first load the official version from flash after power-on, and then perform an online upgrade using the official version after loading, including: - The backup version will be updated first if it is upgraded first. If the backup version is updated successfully, the jump address in the configuration field will be modified to the first line address of the updated backup version; -After the modification is completed, update the official version through online upgrade. If the update is successful, modify the jump address in the configuration field to the first line address of the updated official version; Among them, after completing the online upgrade of the official version and the backup version, the official version and the backup version in the flash are updated to the upgraded version, and the jump address in the configuration field is set to the first row address of the official version. When the FPGA is powered off and restarted, the FPGA reads the content from the flash, and loads the upgraded version from the first row address of the official version by reading the jump address in the configuration field until the loading is completed, thereby realizing the update of the FPGA logic function.

8. The system for online secure upgrade of FPGA logic configuration file version according to claim 7, characterized in that: The configuration field contains a jump address. When the FPGA reads the flash content and detects the jump address, it jumps to the jump address to load the version until the version end mark is detected, and the loading is completed. The jump address in the configuration field is configured as the first line address of the official version by default.

9. The system for online secure upgrade of FPGA logic configuration file version according to claim 7, characterized in that: If the version loaded by jumping to the jump address fails, it returns to the first line address of the flash to continue reading and load the basic version.

10. The system for online secure upgrade of FPGA logic configuration file version according to claim 7, characterized in that: If an exception occurs during the online upgrade process of updating the backup version, resulting in a backup version failure, the FPGA is powered off and restarted, and the content is read from the flash. At this time, the official version stored in the flash can be loaded normally, and the backup version is the faulty version. By reading the jump address in the flash configuration field, the first line address of the official version is obtained, and the official version is loaded by jumping to the first line address of the official version until the end mark of the official version is detected, and the loading is terminated; after loading is completed, the FPGA has the logical function of the official version.

11. The system for online secure upgrade of FPGA logic configuration file version according to claim 7, characterized in that: If an exception occurs during the online upgrade of the official version, resulting in a failure of the official version, the FPGA will be powered off and restarted, and the content will be read from the flash. At this time, the backup version stored in the flash is the successfully updated upgrade version and can be loaded normally. The official version is the faulty version. The FPGA reads the jump address in the flash configuration field to obtain the first row address of the updated backup version, that is, the first row address of the upgraded version after the successful update, jumps to the first row address of the backup version to start loading the upgraded version, and ends loading after detecting the end mark of the backup version. After loading, the FPGA has the logical function of the upgraded version.

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