A method for handling asynchronous pipeline control hazards based on lock mechanism

Abstract

The invention discloses a method for processing asynchronous pipeline control hazards based on a lock mechanism. The processor adopts a three-level pipeline processor, and the interrupt of its peripherals transmits interrupt information to a data processing center through an on-chip network. The processor core exchanges data with the on-chip network through the data processing center. Lock registers are set between instruction pre-fetching and decoding, between decoding and execution, and between execution and memory access in the processor core. The result of the first-level lock register is realized based on a click asynchronous controller, and its input end is ANDed with a PMT signal after XOR; other-level lock registers adopt a branch structure. When the remaining instructions in the pipeline are executed, the scene is saved, and then all locks are opened. At this time, the instructions taken in advance will enter the decoding stage normally. The invention adopts an asynchronous clock-free circuit design, avoids problems such as clock skew, does not affect normal instructions in the pipeline, and saves the time of value acquisition, and has the potential of low power consumption and high performance.

Description

Technical Field

[0001] The invention belongs to the technical field of microprocessors, and in particular relates to a method for processing asynchronous pipeline control hazards based on a lock mechanism. Background Art

[0002] Traditional synchronous architecture uses a global clock-based design technique, in which all functional units operate synchronously under the control of a global clock. With the advancement of VLSI technology, systems have become larger, faster, and more complex, and timing issues have become increasingly serious, accounting for more and more design and debugging costs. The increase in clock speed has led to significant on-chip clock skew, of which inter-chip skew is a major problem. Clock-related timing issues can be solved by controlling the operating rates of different components using asynchronous design techniques without any global synchronization signals. As the core component of a computer, the performance and power consumption of the processor have always been the focus of the industry. With the development of VLSI technology, the complexity and operating speed of the circuit have continued to increase, resulting in an increase in the power consumption of the circuit. Asynchronous circuits are implemented by events generated by circuit logic and do not rely on the clock generated by the crystal oscillator. The control circuit of the asynchronous circuit is generated locally and only works when data arrives. It has a working mode that can be started and stopped at any time, which fundamentally avoids the power consumption generated by the clock.

[0003] In a traditional von Neumann machine, instructions are executed sequentially from consecutive memory locations unless a control hazard occurs. In a pipelined architecture, if a control hazard occurs, the instructions prefetched after the control hazard must be discarded and cleared before executing new instructions. Pipeline stalls, branch prediction, and delayed branches are technologies designed to solve this problem. In a synchronous pipeline system, the prefetch depth, that is, the number of instructions that enter the processor and must be discarded when a control hazard occurs, is defined by the clock cycle and is therefore deterministic. However, in an asynchronous microprocessor, the prefetch unit is completely autonomous and decoupled from the rest of the processor, and the exact number of prefetched instructions is uncertain and unpredictable. In this case, the prefetch depth depends on the exact moment when the branch target or exception vector address interrupts the prefetch, so the processor must be able to distinguish between instructions originating from the branch or exception target and instructions that have been prefetched but must be discarded when a hazard occurs. Different asynchronous processors use different methods to solve this problem. For example, NSR avoids this problem by letting the instruction fetch unit make control flow decisions based on conditions set in advance by the execution unit. In essence, there is no prefetch. FRED uses instruction windows and scheduling units to implement a two-stage branch model (address generation and sequence change) to avoid revoking prefetched instructions. The AMULET team at the University of Manchester designed an efficient solution for the AMULET1 processor, using a single bit to "color" the state of the processor at a specific moment. Each instruction address sent to memory carries the processor's current operating color, which will be used to mark the corresponding prefetched instructions. When a control hazard (branch or exception) occurs, the processor's color changes, causing the color of the instructions prefetched from the new target address to change. The color bit of the instruction that arrives at the data path for execution is compared with the processor's current color. If a match is found, the instruction belongs to the current valid instruction stream and is therefore executed, otherwise it is discarded; therefore, all instructions prefetched after the hazard are discarded until an instruction from a new valid instruction stream (i.e., branch target) is encountered. In this technology, the change of processor color, the occurrence of control hazards (generation of new transfer addresses), and the decision on whether instructions should be discarded (comparison of corresponding color bits) all occur in the same pipeline stage (ALU). However, if the asynchronous architecture causes control hazards to occur at different stages of the pipeline, then the above mechanism of defining the system state using a single color bit is limited, because the operating color of the system may be modified by multiple stages in a distributed, non-deterministic manner. The root cause of this problem is that in an asynchronous, distributed system, it is difficult to obtain the global state of the system at any specific moment.

[0004] Although some existing improved technologies have solved the above problems, if a control hazard occurs in the last stage of the pipeline, the instructions of the previous stages will still be discarded until the last stage, wasting a lot of resources, because once a control hazard occurs in the later stage of the pipeline, the instructions in the previous pipeline can be judged as invalid instructions, and there is no need to execute them to the last stage before being discarded. In addition, the existing technology only proposes a solution to the control hazard in the asynchronous pipeline processor, and does not accelerate the re-fetching of instructions after the control hazard occurs, so that a lot of time for re-fetching instructions will be wasted every time an interrupt exception occurs. Summary of the invention

[0005] In view of the problems existing in the above-mentioned background technology, the purpose of the present invention is to provide a method for processing asynchronous pipeline control hazards based on a lock mechanism, using a lock mechanism built by an asynchronous controller to realize distributed control hazard processing, and using an asynchronous clock-free circuit design to avoid problems such as clock skew, while providing the potential for low power consumption and high performance, reducing unnecessary power consumption.

[0006] In order to achieve the above object, the present invention adopts the following technical solution:

[0007] A method for handling asynchronous pipeline control hazards based on a lock mechanism comprises the following steps:

[0008] The processor for handling asynchronous pipeline control hazards adopts a three-level pipeline processor. The interrupt of the peripheral in the three-level pipeline processor transmits the interrupt information to the data processing center through the on-chip network. The processor core exchanges data with the on-chip network through the data processing center. The first-level register is set between instruction prefetch and decoding in the processor core, the second-level register is set between decoding and execution, and the third-level register is set between execution and memory access. A lock is set in each level of register. The structure of the lock in the first-level register is implemented based on the click asynchronous controller. The input end of the click asynchronous controller is ANDed with the pmt signal after XOR. PMT is the sign of the switch lock; the locks in the second-level register and the third-level register adopt branch The invention discloses a branch structure, in which when the latter pipeline detects no control hazard, it is determined whether the former instruction stage detects the control hazard. If not, the handshake signal is directly transmitted to the next pipeline stage. If detected, the handshake signal closes the switch of the corresponding inter-stage register through the lock, and the interrupt exception module pre-stacks the PC of the current instruction, and then takes the exception vector to obtain the new PC, so as to fetch the instruction into the instruction cache in advance. At this time, the pre-fetched instruction and the unblocked instructions in the pipeline are executed in parallel; when the latter pipeline detects the control hazard, the lock of this stage is in the closed state, and the handshake signal transmission path is the well; when the remaining instructions in the pipeline are executed, the scene is saved, and then all the locks are opened, and the instructions fetched in advance will enter the decoding stage normally.

[0009] Furthermore, when a rising edge or a falling edge appears at the input end of the click asynchronous controller, a pulse signal is generated. The pulse signal is the handshake signal transmitted to the next level of the pipeline. According to the handshake protocol, when the click asynchronous controller receives the reset signal of the next level of the pipeline, it generates the next pulse signal to start the next level of the pipeline.

[0010] Compared with the shortcomings and deficiencies of the prior art, the present invention has the following beneficial effects:

[0011] (1) The present invention adopts an asynchronous clockless circuit design, which avoids problems such as clock skew, while providing the potential for low power consumption and high performance, and encourages modular design concepts, making incremental technology migration easier;

[0012] (2) The present invention adopts a strategy based on a lock mechanism. After detecting a control hazard, the processor will close the lock of the pipeline at this level to prevent the erroneous instructions from continuing to run, thus avoiding the problem of obtaining the global state;

[0013] (3) The present invention closes all locks of the current level and the previous level according to the control risk of different pipeline levels, thus avoiding unnecessary waste;

[0014] (4) The prior art of the present invention only proposes a method of discarding unnecessary instructions but does not fetch new instructions in advance, and the old instructions are not discarded until they are run to the end, which not only wastes power but also wastes time. However, the present invention directly blocks the unnecessary instructions in the corresponding pipeline after detecting the control hazard without propagating them backwards. At the same time, the right instructions can be fetched in advance and blocked by a lock, which will not affect the normal instructions in the pipeline and saves the time for fetching values. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a circuit overall architecture diagram for processing asynchronous pipeline control hazards based on a lock mechanism provided by an embodiment of the present invention;

[0016] Figure 2 It is a signal transmission schematic diagram of a click asynchronous controller prototype provided by an embodiment of the present invention;

[0017] Figure 3 is a timing diagram of a click asynchronous controller prototype provided by an embodiment of the present invention;

[0018] Figure 4 is a schematic diagram of signal transmission of a lock in a first-level register provided by an embodiment of the present invention;

[0019] Figure 5 is a schematic diagram of signal transmission of locks in the second-level and third-level registers provided by an embodiment of the present invention;

[0020] Figure 6It is a schematic diagram of a process for handling asynchronous pipeline control hazards based on a lock mechanism provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0022] 1. Overall architecture

[0023] In order to solve the problem that it is difficult to obtain the global state of the system at any specific time in an asynchronous and distributed system, the present invention uses the lock mechanism built by the asynchronous controller to implement distributed control risk processing. The overall circuit architecture is as follows Figure 1 As shown, the processor adopts a three-level pipeline processor. The interrupt of the peripheral in the three-level pipeline processor transmits the interrupt information to the data processing center through the on-chip network. The processor core exchanges data with the on-chip network through the data processing center. The first-level register is set between instruction prefetch and decoding in the processor core to refine the interrupt of the peripheral, the second-level register is set between decoding and execution, and the third-level register is set between execution and memory access. A lock is set in each level of register.

[0024] 2. Locking mechanism

[0025] When a three-stage pipeline processor detects a control hazard, the lock mechanism will close the switch of the corresponding inter-stage register to block the pipeline. After blocking the pipeline, the three-stage pipeline processor will push the PC into the stack and then fetch the exception vector to get a new PC, so as to fetch instructions into the instruction cache in advance. At this time, the pre-fetched instructions and the instructions that are not blocked in the pipeline are executed in parallel. When the remaining instructions in the pipeline are executed, the scene is saved, and all locks are opened after the scene is saved. The structure of the lock in the first-stage register in the present invention is implemented based on the click asynchronous controller, and its signal transmission method is as follows: Figure 2 As shown, the timing is Figure 3 As shown, when the input end inR of the click asynchronous controller has a rising edge or a falling edge, a pulse signal fire is generated. The pulse signal fire is the handshake signal transmitted to the next level of the pipeline. According to the handshake protocol, the click asynchronous controller will generate the next pulse signal fire to start the next level of the pipeline only when it receives the response of the next level of the pipeline, that is, the reset signal outA, i.e., the AND gate in the figure. The lock in the first level register of the present invention is realized based on this mechanism. The signal transmission method of the lock in the first level register is as follows Figure 4 As shown, its input terminal inR is ANDed with the pmt signal after XOR, and pmt is the sign of the switch lock. When closing the lock, you only need to set pmt to 0 to lock it.

[0026] The lock in the first-level register can use the above structure. The first-level lock will wait for the handshake signal to arrive or the handshake signal to turn on the switch. After processing the control risk, reopen the lock and set pmt to 1. Figure 4 When the output of the AND gate connected to the pmt is 1, it will regenerate fire to drive the operation of the next stage of the pipeline. The locks in the second-level register and the third-level register adopt a branch structure. Figure 5 When the latter pipeline does not detect a control hazard, it determines whether the previous stage of the instruction detects a control hazard. If not, the handshake signal is directly transmitted to the next pipeline. If detected, the handshake signal closes the switch of the corresponding inter-stage register through the lock. The interrupt exception module pre-stacks the PC of the current instruction, and then takes the exception vector to obtain a new PC, thereby fetching instructions into the instruction cache in advance. At this time, the pre-fetched instructions and the instructions that are not blocked in the pipeline are executed in parallel; when the latter pipeline detects a control hazard, the lock of this stage is in the closed state, and the handshake signal transmission path is a well, which represents the end of the event, which is equivalent to that this instruction has ended and will not be passed backwards. At the same time, the last event pulse is also consumed. Even if the control hazard is processed and pmt is restored to 1, the event that is expected is the next correct instruction.

[0027] There are three paths after the branch structure. The first path is when no control hazard is detected, the second path is when the instruction has detected a control hazard before, and the third path is the well path mentioned above. When the instruction passes through this branch structure, it needs to determine which path to take based on the conditions. If a control hazard has occurred in the subsequent pipeline stage, the lock of this stage should be closed, so the third path is taken. If no control hazard has occurred in the subsequent stage, it is necessary to determine whether a control hazard has occurred in the previous stage of the instruction. If so, take the second path, otherwise take the first path.

[0028] The lock mechanism is responsible for closing or opening the lock of each pipeline level after a control risk occurs. Because the deeper the pipeline level, the higher the priority of the exception, the control conditions of each lock are different. The switch of the previous level must consider both the control risk of the current level and the control risk of the subsequent level. Therefore, the condition of the last level is the simplest and is only responsible for the risk of this level. Assuming that the control risk conditions of each level are p1, p2...pn, the condition for the last lock to open is !pn, the second to last level is !pn-1, and so on. The condition for the first level to open the lock is Pmt1=!(p0|p1|p2|...), which means that no control risk occurs in the first, second, and third levels, and the lock will be closed as long as an exception occurs in one level.

[0029] 3. Division of pipelines and different processing methods

[0030] Reference Figure 6No matter which pipeline level an interrupt occurs, the instruction will still be passed back, but it will not go through the logic circuit of each level. In this way, the instruction will handle the interrupt after the last pipeline level ends. This method does not increase the extra power consumption and solves the problem of not knowing the global state due to the lack of a global clock. As can be seen from the figure, no matter whether an interrupt occurs at the current pipeline level, it will be detected and then sent to the interrupt exception module for centralized processing. It can better determine the priority of each level of control risk and then close the corresponding lock. Only the register between instruction fetch and decoding uses the structure of the above-mentioned click asynchronous controller. The locks of the inter-stage registers after other pipeline levels all have a branch structure.

[0031] After a control hazard is detected, the corresponding lock will be closed and the interrupt exception module will pre-stack the PC of the current instruction and then search and calculate the new PC to complete the pre-fetch of the instruction. Since the lock is closed after the instruction is fetched, the new instruction will not flow to the next level of the pipeline until all normal instructions in the pipeline are executed and the lock is opened. After the last level of the pipeline ends, if no control hazard occurs, it ends normally. If a control hazard is detected or a control hazard occurs before and propagates to the last level through the second path, the interrupt exception module will be accessed to represent that all normal instructions in the pipeline have been executed. At this time, the interrupt exception module will perform a stacking operation to save the scene. After saving the scene, the lock can be reopened so that the previously fetched execution can re-enter the pipeline. It does not matter whether the scene is saved first or the instruction is fetched first because the lock is designed with an AND gate, and the fast one only needs to wait for the slow one.

[0032] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for handling asynchronous pipeline control hazards based on a lock mechanism, characterized in that: The steps include: The processor for handling asynchronous pipeline control hazards adopts a three-level pipeline processor. The interrupt of the peripheral in the three-level pipeline processor transmits the interrupt information to the data processing center through the on-chip network. The processor core exchanges data with the on-chip network through the data processing center. The first-level register is set between instruction prefetch and decoding in the processor core, the second-level register is set between decoding and execution, and the third-level register is set between execution and memory access. A lock is set in each level of register. The structure of the lock in the first-level register is implemented based on the click asynchronous controller. The input end of the click asynchronous controller is ANDed with the pmt signal after XOR. PMT is the sign of the switch lock; the locks in the second-level register and the third-level register A branch structure is adopted. When the latter pipeline does not detect a control hazard, it is determined whether the previous stage of the instruction detects a control hazard. If not, the handshake signal is directly transmitted to the next pipeline. If detected, the handshake signal closes the switch of the corresponding inter-stage register through the lock. The interrupt exception module pre-stacks the PC of the current instruction, and then takes the exception vector to obtain a new PC, thereby fetching instructions into the instruction cache in advance. At this time, the pre-fetched instructions and the instructions that are not blocked in the pipeline are executed in parallel; when the latter pipeline detects a control hazard, the lock of this stage is in a closed state, and the handshake signal transmission path is a well; when the remaining instructions in the pipeline are executed, the scene is saved, and then all the locks are opened. At this time, the instructions fetched in advance will enter the decoding stage normally.

2. The method for handling asynchronous pipeline control hazards based on a lock mechanism as claimed in claim 1, characterized in that: When a rising edge or a falling edge appears at the input end of the click asynchronous controller, a pulse signal is generated. The pulse signal is the handshake signal transmitted to the next level of the pipeline. According to the handshake protocol, when the click asynchronous controller receives the reset signal of the next level of the pipeline, it generates the next pulse signal to start the next level of the pipeline.

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