Task parallel processing method and device, electronic equipment and storage medium
By judging the CPU where the task is located in a multi-core system and migrating it to the auxiliary CPU, the access delay and real-time problems caused by task competition within the same CPU are solved, ensuring the real-time and processing efficiency of the system.
Patent Information
- Application Number
- CN202311748959.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-18
- Publication Date
- 2024-12-13
AI Technical Summary
In a multi-core system, different tasks or device interrupt programs of the same CPU compete for public data, resulting in access delays, affecting the real-time task scheduling of the core CPU, and off-interrupt or off-scheduling operations may delay interrupt responses, affecting the real-time nature of the system.
By determining whether the CPU where the task is located is the core CPU. If it is the core CPU, the task will be moved to the auxiliary CPU before triggering the off interrupt or off scheduling to avoid triggering the off interrupt or off scheduling on the core CPU, ensuring the real-time performance of the system. And migrate auxiliary CPU tasks to the core CPU when the core CPU has no tasks to improve processing efficiency.
It effectively avoids the impact of off-off interrupts or off-scheduling on core CPUs on important tasks, ensures system real-timeness, and improves system processing efficiency.
Smart Images
Figure CN119127412A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of computer technology, and specifically relates to a task parallel processing method, device, electronic equipment and storage medium. Background Art
[0002] In the prior art, when multiple CPUs access the same variable together, it will cause competition between CPUs, which will reduce the efficiency of CPUs. Therefore, the PER-CPU mechanism is introduced to allow each CPU to have its own private data area to accelerate the operation performance of the operating system core data on the Symmetric multiprocessing (SMP) system. Although the PER-CPU technology overcomes the problem of contention for accessing data between multiple CPUs, the following problems still exist, which will cause delays in accessing PER-CPU data.
[0003] Different tasks or device interrupt programs of the same CPU will still compete for the public data of the CPU. Tasks or device interrupt programs need to use the off-scheduling mechanism to achieve mutual exclusive access, which will affect the real-time performance of task scheduling in the core CPU. In addition, PER-CPU data may be accessed in an interrupt. In order to avoid the task or device interrupt program context and the interrupt context accessing PER-CPU data at the same time, it is necessary to perform the off-interrupt operation in the critical section when necessary, which will cause the interrupt response in the core CPU to be delayed, affecting the real-time performance of the system.
[0004] Therefore, how to provide an effective solution to ensure the real-time performance of tasks in the core CPU has become a problem to be solved urgently in the prior art. Summary of the invention
[0005] The purpose of the present invention is to provide a task parallel processing method, device, electronic device and storage medium to solve the above problems existing in the prior art.
[0006] In order to achieve the above object, the present invention adopts the following technical solutions:
[0007] In a first aspect, the present invention provides a task parallel processing method, which is applied to a multi-core system, wherein the multi-core system includes a core CPU and an auxiliary CPU, including:
[0008] When the task needs to disable interruption or scheduling, determine whether the CPU where the task is located is a core CPU;
[0009] If the CPU where the task is located is a core CPU, the task is migrated to an auxiliary CPU.
[0010] Based on the above disclosed content, the present invention determines whether the CPU where the task is located is the core CPU when the task needs to disable interrupts or shut down scheduling; if the CPU where the task is located is the core CPU, the task is migrated to the auxiliary CPU. In this way, by migrating the task that will trigger the shutdown of interrupts or shutdown scheduling on the core CPU to the auxiliary CPU before triggering the shutdown of interrupts or shutdown scheduling, it is possible to avoid the shutdown of interrupts or shutdown scheduling triggered on the core CPU from affecting some important tasks, thereby ensuring the real-time performance of the system.
[0011] Through the above design, the present invention can migrate the tasks that may trigger interrupt shutdown or scheduling shutdown on the core CPU to the auxiliary CPU before triggering interrupt shutdown or scheduling shutdown, thereby avoiding the interrupt shutdown or scheduling shutdown triggered on the core CPU from affecting some important tasks, ensuring the real-time performance of the system, and facilitating practical application and promotion.
[0012] In one possible design, the method further includes:
[0013] If there is no task currently on the core CPU, at least one task on the auxiliary CPU is migrated to the core CPU.
[0014] In one possible design, after migrating at least one task on the auxiliary CPU to the core CPU, the method further includes:
[0015] Before the task migrated to the core CPU triggers interruption or scheduling shutdown, the task or device interrupt program migrated to the core CPU is migrated back to the auxiliary CPU.
[0016] In one possible design, the method further includes:
[0017] Determine whether the tasks on the core CPU need to access public resources;
[0018] If the task on the core CPU needs to access public resources, it is determined that the task on the core CPU needs to disable interrupts or scheduling;
[0019] If the tasks on the core CPU do not need to access common resources, it is determined that the tasks on the core CPU do not need to disable interrupts or disable scheduling.
[0020] In a possible design, migrating the task to the auxiliary CPU includes:
[0021] The process description block of the task is taken out from the task queue and added to the task queue of the auxiliary CPU.
[0022] In one possible design, there are multiple auxiliary CPUs.
[0023] In a second aspect, the present invention provides a task parallel processing device, which is applied to a multi-core system, wherein the multi-core system includes a core CPU and an auxiliary CPU, including:
[0024] A judgment unit, used for judging whether the CPU where the task is located is a core CPU when the task needs to disable interruption or scheduling;
[0025] The migration unit is used to migrate the task to the auxiliary CPU if the CPU where the task is located is the core CPU.
[0026] In a possible design, the migration unit is further configured to migrate at least one task on the auxiliary CPU to the core CPU if there is currently no task on the core CPU.
[0027] In a third aspect, the present invention provides an electronic device comprising a memory, a processor and a transceiver which are communicatively connected in sequence, wherein the memory is used to store a computer program, the transceiver is used to send and receive messages, and the processor is used to read the computer program to execute the task parallel processing method as described in the first aspect or any possible design of the first aspect.
[0028] In a fourth aspect, the present invention provides a computer-readable storage medium having instructions stored thereon, which, when executed on a computer, executes the task parallel processing method described in the first aspect or any possible design of the first aspect.
[0029] In a fifth aspect, the present invention provides a computer program product comprising instructions, which, when executed on a computer, causes the computer to execute the task parallel processing method as described in the first aspect or any possible design of the first aspect.
[0030] Beneficial effects:
[0031] The task parallel processing method, device, electronic device and storage medium provided by the present invention can migrate the tasks that will trigger interruption or scheduling shutdown on the core CPU to the auxiliary CPU before triggering interruption or scheduling shutdown, thereby avoiding the interruption or scheduling shutdown triggered on the core CPU from affecting some important tasks, ensuring the real-time performance of the system, and facilitating practical application and promotion. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 A flowchart of a task parallel processing method provided in an embodiment of the present application;
[0033] Figure 2 A block diagram of a task parallel processing device provided in an embodiment of the present application;
[0034] Figure 3A schematic block diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structure of the drawings is only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.
[0036] It should be understood that although the terms first, second, etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another unit. For example, a first unit can be referred to as a second unit, and similarly, a second unit can be referred to as a first unit without departing from the scope of the exemplary embodiments of the present invention.
[0037] It should be understood that the term "and / or" that may appear in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, B exists alone, and A and B exist at the same time. The term " / and" that may appear in this article describes another type of association object relationship, indicating that two relationships may exist. For example, A / and B can represent two situations: A exists alone, and A and B exist alone. In addition, the character " / " that may appear in this article generally indicates that the previous and next associated objects are in an "or" relationship.
[0038] In order to ensure the real-time performance of tasks in the core CPU, an embodiment of the present application provides a task parallel processing method, device, electronic device and storage medium. The task parallel processing method, device, electronic device and storage medium can avoid interruption or scheduling triggered on the core CPU, which may affect some important tasks and ensure the real-time performance of the system.
[0039] The task parallel processing method provided in the embodiment of the present application can be applied to a multi-core system, and the multi-core system can be, but is not limited to, a user terminal device or a server including a core CPU and an auxiliary CPU. It can be understood that the execution subject does not constitute a limitation on the embodiment of the present application.
[0040] The task parallel processing method provided in the embodiment of the present application is described in detail below.
[0041] like Figure 1As shown, it is a flowchart of the task parallel processing method provided in the first aspect of the embodiment of the present application. The task parallel processing method may include but is not limited to the following steps S101-S102.
[0042] Step S101: When a task needs to disable interruption or scheduling, determine whether the CPU where the task is located is a core CPU.
[0043] In an embodiment of the present application, a multi-core system may include one or more core CPUs and one or more auxiliary CPUs, and a task or device interrupt program may run on a core CPU or an auxiliary CPU.
[0044] During the execution of a task, you can first determine whether the task needs to turn off interrupts or scheduling. Among them, the task may include a device interrupt program. The device interrupt program may refer to certain devices (such as keyboards, network cards) that send an interrupt request to the CPU when receiving a specific electrical signal from the outside world. After receiving the interrupt request, the CPU will jump to the corresponding interrupt program to perform the corresponding operation. Turning off interrupts may refer to setting the CPU flag to allow the CPU to temporarily block the interrupt signal of the external device. Turning off scheduling may refer to temporarily prohibiting the system from performing task scheduling operations. Even if there are high-priority tasks in the current system, they are not allowed to obtain the CPU.
[0045] Specifically, when judging whether a task needs to disable interrupts or scheduling, it can be determined by judging whether the task on the core CPU needs to access public resources (i.e., PER-CPU data). If the task on the core CPU needs to access public resources, then it is determined that the task on the core CPU needs to disable interrupts or scheduling. If the task on the core CPU does not need to access public resources, then it is determined that the task on the core CPU does not need to disable interrupts or scheduling.
[0046] Step S102: If the CPU where the task is located is a core CPU, the task is migrated to an auxiliary CPU.
[0047] If the CPU where the task is located is the core CPU, when the task triggers interrupt or scheduling shutdown, some other important tasks may not be processed in time due to interrupt or scheduling shutdown, thus affecting the real-time performance of these important tasks. Therefore, if it is determined that the CPU where the task is located is the core CPU, the tasks that will trigger interrupt or scheduling shutdown on the core CPU can be migrated to the auxiliary CPU before interrupt or scheduling shutdown is triggered. In this way, the core CPU will not be affected by the interrupt or scheduling shutdown triggered by the task, which will affect the real-time performance of the core CPU in processing data, avoiding the situation where some important tasks cannot be processed in time due to the triggered interrupt or scheduling shutdown, thus ensuring the real-time performance of the system.
[0048] Among them, when migrating a task that needs to disable interrupts or scheduling to the auxiliary CPU, the process description block of the task that needs to trigger the shutdown of interrupts or scheduling can be taken out from the task queue, and then the taken out process description block can be added to the task queue of the auxiliary CPU, so that the task migration can be realized.
[0049] In one or more embodiments, after migrating the task on the core CPU that needs to disable interrupts or scheduling to the auxiliary CPU, there may be no tasks in the task queue of the core CPU, while there may be process description blocks of multiple tasks in the task queue of the auxiliary CPU. To improve the system processing efficiency, when there are currently no tasks on the core CPU, at least one task on the auxiliary CPU can be migrated to the core CPU to achieve multi-task parallel processing and improve the system processing efficiency. If the task migrated to the core CPU needs to disable interrupts or scheduling later, the task migrated to the core CPU can be migrated back to the auxiliary CPU before the task migrated to the core CPU triggers the shutdown of interrupts or scheduling.
[0050] In summary, the task parallel processing method provided in the embodiment of the present application determines whether the CPU where the task is located is the core CPU when the task needs to turn off interrupts or turn off scheduling; if the CPU where the task is located is the core CPU, the task is migrated to the auxiliary CPU. In this way, by migrating the tasks that will trigger the shutdown of interrupts or shutdown of scheduling on the core CPU to the auxiliary CPU before triggering the shutdown of interrupts or shutdown of scheduling, the core CPU will not be affected by the shutdown of interrupts or shutdown of scheduling triggered by the tasks. The real-time performance of the core CPU in processing data is avoided, and some important tasks cannot be processed in time due to the triggered shutdown of interrupts or shutdown of scheduling, thereby ensuring the real-time performance of the system. Similarly, when there are no tasks on the core CPU, the tasks on the auxiliary CPU can also be migrated to the core CPU, thereby improving the system processing efficiency.
[0051] See also Figure 2 According to a second aspect of an embodiment of the present application, a task parallel processing device is provided, which is applied to a multi-core system. The multi-core system includes a core CPU and an auxiliary CPU. The task parallel processing device includes:
[0052] A judgment unit, used for judging whether the CPU where the task is located is a core CPU when the task needs to disable interruption or scheduling;
[0053] The migration unit is used to migrate the task to the auxiliary CPU if the CPU where the task is located is the core CPU.
[0054] In a possible design, the migration unit is further configured to migrate at least one task on the auxiliary CPU to the core CPU if there is currently no task on the core CPU.
[0055] The working process, working details and technical effects of the task parallel processing device provided in the second aspect of this embodiment can be found in the first aspect of the embodiment and will not be described in detail here.
[0056] like Figure 3 As shown, the third aspect of an embodiment of the present application provides an electronic device, comprising a memory, a processor and a transceiver that are communicatively connected in sequence, wherein the memory is used to store computer programs, the transceiver is used to send and receive messages, and the processor is used to read the computer program to execute the task parallel processing method described in the first aspect of the embodiment.
[0057] For specific examples, the memory may include but is not limited to random access memory (RAM), read-only memory (ROM), flash memory, first-in-first-out memory (FIFO) and / or first-in-last-out memory (FILO), etc.; the processor may be but is not limited to a microprocessor of the STM32F105 series, an ARM (Advanced RISC-Machines), an X86 or other architecture processor, or a processor with an integrated NPU (neural-network processing units); the transceiver may be but is not limited to a WiFi (Wireless Fidelity) wireless transceiver, a Bluetooth wireless transceiver, a General Packet Radio Service (GPRS) wireless transceiver, a ZigBee protocol (a low-power local area network protocol based on the IEEE802.15.4 standard, ZigBee) wireless transceiver, a 3G transceiver, a 4G transceiver and / or a 5G transceiver, etc.
[0058] The fourth aspect of this embodiment provides a computer-readable storage medium storing instructions including the task parallel processing method described in the first aspect of the embodiment, that is, the computer-readable storage medium stores instructions, and when the instructions are run on a computer, the task parallel processing method described in the first aspect is executed. The computer-readable storage medium refers to a carrier for storing data, which may include but is not limited to a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash drive and / or a memory stick, etc., and the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
[0059] The fifth aspect of this embodiment provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the task parallel processing method as described in the first aspect of the embodiment, wherein the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.
[0060] It should be understood that certain details are provided in the following description to facilitate a complete understanding of the example embodiments. However, it should be understood by those of ordinary skill in the art that the example embodiments can be implemented without these certain details. For example, the system can be shown in a block diagram to avoid obscuring the example with unnecessary details. In other examples, well-known processes, structures, and techniques may not be shown in unnecessary detail to avoid obscuring the example embodiments.
[0061] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A task parallel processing method, applied to a multi-core system, wherein the multi-core system includes a core CPU and an auxiliary CPU, characterized in that: include: When the task needs to disable interruption or scheduling, determine whether the CPU where the task is located is a core CPU; If the CPU where the task is located is a core CPU, the task is migrated to an auxiliary CPU.
2. The task parallel processing method according to claim 1, characterized in that: The method further comprises: If there is no task currently on the core CPU, at least one task on the auxiliary CPU is migrated to the core CPU.
3. The task parallel processing method according to claim 2, characterized in that: After migrating at least one task on the auxiliary CPU to the core CPU, the method further includes: Before the task migrated to the core CPU triggers interruption or scheduling shutdown, the task migrated to the core CPU is migrated back to the auxiliary CPU.
4. The task parallel processing method according to claim 1, characterized in that: The method further comprises: Determine whether the tasks on the core CPU need to access public resources; If the task on the core CPU needs to access public resources, it is determined that the task on the core CPU needs to disable interrupts or scheduling; If the tasks on the core CPU do not need to access common resources, it is determined that the tasks on the core CPU do not need to disable interrupts or disable scheduling.
5. The task parallel processing method according to claim 1, characterized in that: Migrating the task to the auxiliary CPU includes: The process description block of the task is taken out from the task queue and added to the task queue of the auxiliary CPU.
6. The task parallel processing method according to claim 1, characterized in that: The number of the auxiliary CPUs is multiple.
7. A task parallel processing device, applied to a multi-core system, the multi-core system comprising a core CPU and an auxiliary CPU, characterized in that: include: A judgment unit, used for judging whether the CPU where the task is located is a core CPU when the task needs to disable interruption or scheduling; The migration unit is used to migrate the task to the auxiliary CPU if the CPU where the task is located is the core CPU.
8. The task parallel processing device according to claim 7, characterized in that: The migration unit is further configured to migrate at least one task on the auxiliary CPU to the core CPU if there is no task currently on the core CPU.
9. An electronic device, characterized in that: It comprises a memory, a processor and a transceiver which are communicatively connected in sequence, wherein the memory is used to store a computer program, the transceiver is used to send and receive messages, and the processor is used to read the computer program to execute the task parallel processing method as described in any one of claims 1 to 6.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed on a computer, the task parallel processing method according to any one of claims 1 to 6 is executed.