Atomic operation processing unit, exception processing method, display card and equipment

Abstract

The invention discloses an atomic operation processing unit, an exception processing method, a display card and equipment, and belongs to the field of chips. The atomic operation processing unit comprises an anomaly detection circuit, an atomic operation processing circuit and an anomaly processing circuit. The anomaly detection circuit is connected with the atomic operation processing circuit; the atomic operation processing circuit is connected with the exception processing circuit; the anomaly detection circuit is used for outputting the input data and anomaly information to the atomic operation processing circuit under the condition that the input data is abnormal; the atomic operation processing circuit is used for executing atomic operation based on the input data to obtain an atomic operation result; the atomic operation result and the exception information are output to the exception processing circuit; and the exception handling circuit is used for selectively discarding the atomic operation result or writing the atomic operation result into the storage unit based on the exception information. The atomic operation processing unit supports anomaly detection and anomaly processing in the atomic operation execution process, and the reliability of atomic operation execution can be guaranteed.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to an atomic operation processing unit, an exception handling method, a graphics card and a device. Background Art

[0002] Atomic operations are operations that cannot be interrupted during execution and are one of the important operations in GPU (Graphics Processing Unit). The arithmetic logic unit (ALU) used to perform atomic operations is also called atomic operation processing unit or atomic operation processing circuit, and is one of the important units in GPU.

[0003] In the related art, errors may occur during the execution of atomic operations, causing abnormal operation of the GPU. Summary of the invention

[0004] The present application provides an atomic operation processing unit, an exception handling method, a graphics card and a device, and the technical solution is as follows:

[0005] According to one aspect of the present application, an atomic operation processing unit is provided, the atomic operation processing unit comprising an exception detection circuit, an atomic operation processing circuit and an exception processing circuit; the exception detection circuit is connected to the atomic operation processing circuit; the atomic operation processing circuit is connected to the exception processing circuit;

[0006] The anomaly detection circuit is used to output the input data and anomaly information to the atomic operation processing circuit when an anomaly exists in the input data;

[0007] The atomic operation processing circuit is used to perform an atomic operation based on the input data to obtain an atomic operation result; and output the atomic operation result and the exception information to the exception processing circuit;

[0008] The exception processing circuit is used to select to discard the atomic operation result or write the atomic operation result into a storage unit based on the exception information.

[0009] According to one aspect of the present application, there is provided an exception detection method, the method being performed by an atomic operation processing unit, the atomic operation processing unit comprising an exception detection circuit, an atomic operation processing circuit and an exception processing circuit; the exception detection circuit is connected to the atomic operation processing circuit; the atomic operation processing circuit is connected to the exception processing circuit;

[0010] The method comprises:

[0011] When the input data is abnormal, the abnormality detection circuit outputs the input data and abnormality information to the atomic operation processing circuit;

[0012] The atomic operation processing circuit performs an atomic operation based on the input data to obtain an atomic operation result; and outputs the atomic operation result and the exception information to the exception processing circuit;

[0013] The exception handling circuit selects to discard the atomic operation result or write the atomic operation result into a storage unit based on the exception information.

[0014] According to one aspect of the present application, a graphics card is provided, comprising an atomic operation processing unit.

[0015] According to one aspect of the present application, a computer device is provided, the computer device comprising an atomic operation processing unit.

[0016] The beneficial effects of the technical solution provided by this application include at least:

[0017] An exception detection circuit and an exception handling circuit are added to the atomic operation processing unit to implement exception detection and exception handling during the atomic operation process, thereby improving the reliability of the atomic operations performed by the atomic operation processing unit, and then improving the reliability of the processor in performing atomic operations, thereby avoiding processor operation errors caused by abnormalities in the results of atomic operations. Generally speaking, if a processor has an operation error due to an abnormality in the results of an atomic operation, the processor will need to re-execute the corresponding operation or troubleshoot the cause of the error for the recently executed instructions, which will slow down the processor's operating efficiency. Therefore, the atomic operation processing unit can also indirectly improve the processor's operating efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0020] Figure 2 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0021] Figure 3 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0022] Figure 4 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0023] Figure 5 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0024] Figure 6 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0025] Figure 7 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0026] Figure 8 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0027] Fig. 9 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0028] Fig.10 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0029] Fig.11 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0030] Fig.12 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0031] Fig.13 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0032] Fig.14 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown;

[0033] Fig.15 A flowchart of an exception handling method provided by an exemplary embodiment of the present application is shown;

[0034] Fig.16 A schematic diagram of the architecture of a computer system provided by an exemplary embodiment of the present application is shown;

[0035] Fig.17 A schematic diagram of the architecture of a computer system provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0037] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0038] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0039] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the information such as setting operations involved in this application is obtained with full authorization.

[0040] It should be understood that although the terms first, second, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0041] First, the relevant terms involved in this application are introduced:

[0042] Instruction: It is a command that instructs a computer to perform a certain operation. It is the smallest functional unit of a computer. An instruction is a statement in machine language, and an instruction is a group of meaningful binary codes. The collection of all instructions of a computer constitutes the instruction system of the computer, also known as the instruction set.

[0043] Instruction format: A readable representation of an instruction. An instruction usually includes an opcode and an operand. The opcode is used to describe the type of operation to be performed by the instruction, and the operand provides the data or address of the data required to execute the instruction. The opcode is indispensable in the instruction, but the operand can be absent, one, or two.

[0044] Atomic operation: refers to an operation or a group of operations that only have two states: unexecuted and fully executed. There is no intermediate state for atomic operations. It can also be understood that an atomic operation is an independent and indivisible operation composed of multiple steps. In a single-core environment, threads cannot be switched when performing atomic operations. Thread switching can only be performed before atomic operations or after atomic operations are completed. In a multi-core environment, it can be reflected in that when a core performs an atomic operation on a certain storage unit, it is necessary to ensure that other cores do not change the data of the same storage unit at the same time. In other words, an atomic operation refers to one or more operations that must be completed as a whole. If an atomic operation is interrupted when any step of the operation is not completed, all completed operations must be rolled back to ensure that all operations are not completed or all operations are completed.

[0045] In GPU, the hardware unit that performs atomic operations can be called Arithmetic Logic Unit (ALU), Atomic Operation Processing Unit, Data Processing Unit, etc., and usually requires the input of several atomic operands. For example, atomic operations include xchg, add, sub, and, or, xor, inc, dec, cmp, cmpxchg (Compare and Exchange, also known as cas, the full name of which is Compare-And-Swap), etc.

[0046] Among them, xchg represents a swap operation, which requires the input of an atomic operand. This operation means using the input atomic operand to replace the data at a certain address in a storage unit (such as memory or video memory, etc.).

[0047] Add represents an addition operation, which requires two atomic operands. This operation represents the addition of two input atomic operands.

[0048] sub represents a subtraction operation, which requires two atomic operands. This operation represents subtracting the two input atomic operands.

[0049] and represents an AND operation, which requires two atomic operands. This operation represents the logical AND of the two input atomic operands.

[0050] or represents an OR operation, which requires two atomic operands. This operation represents the logical OR of the two input atomic operands.

[0051] xor represents an exclusive OR operation, which requires two atomic operands. This operation represents performing a logical exclusive OR on the two input atomic operands.

[0052] inc represents a self-increment operation, which requires two atomic operands. This operation first compares the atomic operand passed in from the bus with the atomic operand read from the storage unit. If the atomic operand passed in from the bus is greater than the atomic operand read, it will not be incremented; if the atomic operand passed in from the bus is less than or equal to the atomic operand read, it will be incremented. It should be noted that the above example uses the case where the atomic operand passed in from the bus is equal to the atomic operand read as an example of self-increment. In actual use, if the atomic operand passed in from the bus is less than or equal to the atomic operand read, it may not be incremented. The following decrement is the same and will not be repeated here.

[0053] dec represents a decrement operation, which requires two atomic operands. This operation first compares the atomic operand passed in from the bus with the atomic operand read from the storage unit. If the atomic operand passed in from the bus is less than the atomic operand read, it will not be decremented; if the atomic operand passed in from the bus is greater than or equal to the atomic operand read, it will be incremented.

[0054] cmp represents a comparison operation, which requires two atomic operands. This operation is used to compare the sizes of the two atomic operands.

[0055] float represents floating-point sum and requires two atomic operands. This operation is used to add two atomic operands based on the precision of floating-point numbers.

[0056] cas represents a compare and exchange operation, which requires three atomic operands. Atomic operand 1 and atomic operand 2 are passed in from the bus, and atomic operand 3 is read from the storage unit. This operation is used to compare atomic operand 1 with atomic operand 3. If atomic operand 1 is equal to atomic operand 3, atomic operand 2 is used to replace atomic operand 3 in the storage unit; if atomic operand 1 is not equal to atomic operand 3, no replacement is made.

[0057] Among them, each type of atomic operation can be divided into 16 bits, 32 bits and 64 bits according to the bit width of the atomic operand.

[0058] It should be noted that the above atomic operations and their functions are for illustration only and can be adjusted according to the requirements of different processors during actual use.

[0059] Atomic operation instruction: An instruction used to instruct the execution of an atomic operation.

[0060] Among them, the atomic operands of atomic operations can be divided into original data and read data according to their sources.

[0061] Original data: the atomic operand carried in the atomic operation instruction, or the atomic operand read from the storage unit based on the address carried in the atomic operation instruction but not modified in the atomic operation.

[0062] Read data: The atomic operand that needs to be modified by the atomic operation is read from the storage unit based on the address carried in the atomic operation instruction. In other words, the atomic operand is read from the storage unit based on the address carried in the atomic operation instruction, and the address is the address where the atomic operation result needs to be written after the atomic operation is completed. In other words, the atomic operand is read from the storage unit based on the address carried in the atomic operation instruction, and the address is both a read address and a write address.

[0063] Figure 1 A schematic diagram of an atomic operation processing unit 120 provided by an exemplary embodiment of the present application is shown. The atomic operation processing unit 120 includes an exception detection circuit 10, an atomic operation processing circuit 20 and an exception processing circuit 30. The exception detection circuit 10 is connected to the atomic operation processing circuit 20; the atomic operation processing circuit 20 is connected to the exception processing circuit 30.

[0064] Among them, the exception detection circuit is used to output the input data and exception information to the atomic operation processing circuit when there is an exception in the input data; the atomic operation processing circuit is used to perform atomic operations based on the input data to obtain atomic operation results; and output the atomic operation results and exception information to the exception processing circuit; the exception processing circuit is used to choose to discard the atomic operation results based on the exception information, or write the atomic operation results into a storage unit.

[0065] Optionally, the output end of the exception detection circuit 10 is connected to the input end of the atomic operation processing circuit 20 ; the output end of the atomic operation processing circuit 20 is connected to the input end of the exception processing circuit 30 .

[0066] Optionally, the input end of the exception detection circuit 10 is connected to the processor; the output end of the exception processing circuit 30 is connected to the memory.

[0067] Optionally, the processor inputs an atomic operation instruction to the atomic operation processing unit 120 to control the atomic operation processing unit 120 to perform an atomic operation. The atomic operation instruction is first input to the exception detection circuit 10 to perform exception detection. The exception detection circuit 10 obtains input data based on the atomic operation instruction, and when the input data is abnormal, the input data and exception information are output to the atomic operation processing circuit 20 through the path between the exception detection circuit 10 and the atomic operation processing circuit 20. The atomic operation processing circuit 20 performs the atomic operation to obtain the atomic operation result and exception information, and finally the atomic operation result and exception information are input to the exception processing circuit 30 to perform exception processing.

[0068] In summary, the unit provided in the embodiment of the present application adds an exception detection circuit and an exception handling circuit to the atomic operation processing unit to implement exception detection and exception handling during the atomic operation process, thereby improving the reliability of the atomic operation performed by the atomic operation processing unit, and then improving the reliability of the processor in performing the atomic operation, thereby avoiding operation errors caused by abnormalities in the results of atomic operations. Generally speaking, if an operation error occurs in the processor due to an abnormality in the results of atomic operations, the processor will need to re-execute the corresponding operation or troubleshoot the cause of the error for the recently executed instructions, which will slow down the operation efficiency of the processor. Therefore, the unit can also indirectly improve the operation efficiency of the processor.

[0069] Next, the functions of each circuit in the atomic operation processing unit 120 are described in detail.

[0070] 1. Abnormality detection circuit 10.

[0071] Optionally, the anomaly detection circuit 10 is used to perform anomaly detection on input data. The input data refers to data input to the atomic operation processing circuit 20 for performing atomic operations.

[0072] Optionally, the anomaly detection circuit 10 is further configured to output input data and anomaly information to the atomic operation processing circuit 20 when anomalies exist in the input data.

[0073] Exemplarily, the anomaly detection circuit 10 performs an anomaly detection on the input data, and the anomaly detection result obtained is that the input data has an anomaly or the input data does not have an anomaly. In the case that the input data has an anomaly, the anomaly detection circuit 10 outputs the input data and the anomaly information to the atomic operation processing circuit 20.

[0074] Optionally, the exception information is used to indicate whether an exception exists; and / or, the exception information is used to indicate the cause of the exception; and / or, the exception information is used to indicate the location where the exception occurs; and / or, the exception information is used to instruct the exception handling circuit 30 on how to handle the atomic operation result corresponding to the exception, such as discarding the atomic operation result or writing the atomic operation result into a storage unit.

[0075] Among them, the input data and the exception information are output to the atomic operation processing circuit 20 through different paths; or, the input data and the exception information are output to the atomic operation processing circuit 20 through the same path (or the same path). The input data and the exception information are output to the atomic operation processing circuit 20 through different paths, for example, the input data is output to the atomic operation processing circuit 20 through the first path, and the exception information is output to the atomic operation processing circuit 20 through the second path. The path is a signal transmission path based on hardware implementation, and the signal transmission path includes: at least one of the circuits, caches, and other possible electronic devices in the chip. That is, the path is a signal transmission path composed of at least one of the metal lines, caches, and other possible electronic devices on the chip. The first path is the signal transmission path for the exception detection circuit 10 to output the input data to the atomic operation processing circuit 20, and the second path is the signal transmission path for the exception detection circuit 10 to output the exception information to the atomic operation processing circuit 20. That is, the above-mentioned "the exception detection circuit 10 is also used to output input data and exception information to the atomic operation processing circuit 20 when an exception exists in the input data" can be understood as: "the exception detection circuit 10 is also used to output input data to the atomic operation processing circuit through the first path when an exception exists in the input data, and output exception information to the atomic operation processing circuit 20 through the second path".

[0076] Or, the input data and the exception information are output to the atomic operation processing circuit 20 through the same path. For example, the input data and the exception information are output to the atomic operation processing circuit 20 in the same clock cycle. The input data and the exception information are output to the atomic operation processing circuit 20 through the third path. If the third path supports 32-bit data transmission within one clock cycle, it can be specified that 16 bits are allocated for the exception information and 16 bits are allocated for the input data, such as the first 16 bits represent the exception information and the last 16 bits represent the input data. It should be noted that the above allocation of the third path is only for illustration. The exception information and the input data can occupy the entire third path as shown above, or can occupy part of the third path. If the third path supports 32-bit data transmission, 8 bits can be allocated for the exception information and 8 bits can also be allocated for the input data. In addition, the number of bits occupied by the input data and the exception information can be different, such as allocating 2 bits for the exception information and 16 bits for the input data. In other embodiments, input data and exception information are transmitted through the third path within one clock cycle, such as the several scenarios illustrated above; or, input data and exception information are transmitted through the third path in different clock cycles, such as transmitting exception information in clock cycle 1 and transmitting input data in clock cycle 2.

[0077] In summary, the unit provided in the embodiment of the present application shows the function of the abnormality detection circuit and the transmission process of abnormal information and input data in the atomic operation processing unit. The abnormality detection at the entrance of the atomic operation processing circuit is realized, and the atomic operation processing unit is supported to perform corresponding processing on the abnormal information, thereby ensuring the reliability of the atomic operation processing unit in performing atomic operations.

[0078] 2. Atomic operation processing circuit 20.

[0079] Optionally, the atomic operation processing circuit 20 is used to perform an atomic operation based on the input data to obtain an atomic operation result, and output the atomic operation result and exception information to the exception processing circuit 30. The atomic operation result is obtained by the atomic operation processing circuit 20 performing an atomic operation based on the input data.

[0080] Wherein, in the case where the abnormality detection circuit 10 outputs input data and abnormality information to the atomic operation processing circuit 20 through different paths, the atomic operation processing circuit 20 performs an atomic operation based on the input data to obtain an atomic operation result, and outputs the atomic operation result to the abnormality processing circuit 30, and at the same time, the atomic operation processing circuit 20 outputs abnormality information to the abnormality processing circuit 30. In the case where the abnormality detection circuit 10 outputs input data and abnormality information to the atomic operation processing circuit 20 through the same path, the atomic operation processing circuit 20 performs an atomic operation based on the spliced ​​input data and abnormality information to obtain an atomic operation result; or, after the atomic operation processing circuit 20 performs an atomic operation based on the input data received in one clock cycle to obtain an atomic operation result, the atomic operation result is output to the abnormality processing circuit 30; and the abnormality information received in another clock cycle is output to the abnormality processing circuit 30.

[0081] Exemplarily, the input data and exception information are spliced ​​and output to the atomic operation processing circuit 20. The exception information is 2 bits and the input data is 16 bits. The exception information is spliced ​​with the input data to obtain 18 bits of data which are output to the atomic operation processing circuit 20. When performing atomic processing, the atomic operation processing circuit 20 will ignore the exception information, or separate the exception information and perform atomic processing on the input data separately.

[0082] Exemplarily, there is a path for transmitting abnormal information in the atomic operation processing circuit 20, and the path is used to connect the input end and the output end. Figure 2 As shown, the atomic operation processing circuit 20 includes an abnormal information path 21 and a calculation path 22, and the abnormal information path 21 is used to connect the input end 23 and the output end 24 of the atomic operation processing circuit 20. A calculation unit 25 for performing atomic operations is provided in the calculation path 22. For input data, after being output from the input end 23 to the atomic operation processing circuit 20, the atomic operation result is obtained by the calculation unit 25 through the calculation path 22, and then continued to be output from the output end 24 through the calculation path 22; for abnormal information, after being output from the input end 23 to the atomic operation processing circuit 20, the calculation unit 25 is skipped through the abnormal information path 21 and directly output from the output end 24. Among them, the atomic operation result and the abnormal information will be output together, and the method of common output can refer to the above-mentioned scenario of "the abnormal information and the input data are transmitted through the third path within one clock cycle", that is, the atomic operation result and the abnormal information are spliced ​​and output, which will not be repeated here; or, the atomic operation result and the abnormal information will be output separately.

[0083] Optionally, after the exception detection circuit 10 performs exception detection based on the atomic operation instruction, when the input data indicated by the atomic operation instruction is abnormal, the atomic operation instruction and exception information are output to the atomic operation processing circuit 20. The atomic operation processing circuit 20 is also used to receive the atomic operation instruction, and perform the atomic operation based on the atomic operation instruction to obtain the atomic operation result. The atomic operation instruction includes at least one of an atomic operation code, an atomic operand, and an address of the atomic operand. The atomic operation code is used to indicate the atomic operation to be performed to the atomic operation processing circuit 20, such as the atomic operation is an atomic addition operation (add), an atomic subtraction operation (sub), an atomic logical operation (and), an atomic logical or operation (or), etc. Generally speaking, the atomic operation code is required in the atomic operation instruction, and the atomic operand and the address of the atomic operand are optional. The atomic operand and the address of the atomic operand can be one or more.

[0084] To summarize, the unit provided in the embodiment of the present application illustrates the function of the atomic operation processing circuit. In addition to executing atomic operations, the atomic operation processing circuit also assists in sending exception information and atomic operation results to the exception processing circuit. A transmission path for exception information within the atomic operation processing unit is designed to support the atomic operation processing unit to perform corresponding processing on the exception information, thereby ensuring the reliability of the atomic operation processing unit in executing atomic operations.

[0085] 3. Exception handling circuit 30.

[0086] Optionally, the exception handling circuit 30 is used to select to discard the atomic operation result or write the atomic operation result into a storage unit based on the exception information.

[0087] The exception processing circuit 30 is also used to receive the atomic operation result and exception information output by the atomic operation processing circuit 20 .

[0088] Optionally, the exception information includes a processing method indicated by the exception detection circuit 10; or, the exception information includes a cause of the exception, and the exception processing circuit 30 performs different exception processing for different causes of the exception.

[0089] Optionally, when the exception information and the atomic operation result are output separately, it is agreed that the exception information is output first, and then the atomic operation result is output. That is, the exception information will reach the exception processing circuit 30 before the atomic operation result. Or, when the exception detection circuit 10 outputs the exception information and input data to the atomic operation processing circuit 20, it is agreed that the exception information is output to the atomic operation processing circuit 20 first, and then the input data is output to the atomic operation processing circuit 20; at this time, the atomic operation processing circuit 20 will also prioritize and output the exception information.

[0090] Or, in the case where the exception information and the atomic operation result are output separately, if the exception handling circuit 30 receives the exception information first, then the exception handling is performed on the atomic operation result received later based on the exception information. If the exception handling circuit 30 receives the atomic operation result first, then the first time length is waited; if the exception information is received within the first time length, then the exception handling is performed on the atomic operation result based on the exception information; if the exception information is not received within the first time length, then it is determined that there is no exception in the atomic operation result.

[0091] Optionally, when the exception information and the atomic operation result are output together, the exception handling circuit 30 separates the spliced ​​exception information and the atomic operation to obtain the exception information and the atomic operation result, and performs exception handling on the atomic operation result based on the exception information.

[0092] Optionally, the exception handling circuit 30 is also used to select to discard the atomic operation result, or write the atomic operation result into a storage unit based on the exception information and the exception handling configuration. The exception handling configuration is configuration information or a configuration file set by the user. For example, the exception handling configuration includes the exception cause and the exception handling method corresponding to the exception cause. The exception cause is usually represented by one or more bits (or exception cause codes). For example, the exception cause code includes "0" and "1". The exception handling method corresponding to the exception cause code "0" is to discard the atomic operation result, and the exception handling method corresponding to the exception cause code "1" is to write the atomic operation result into a storage unit. This method supports the user to select the exception handling method. Generally speaking, after discarding the atomic operation result, the atomic operation instruction needs to be executed again. Although the reliability of the atomic operation is improved, the operating efficiency of the processor during the execution of the atomic operation will be reduced; and the choice of writing the atomic operation result into the storage unit is because a small number of errors are allowed in the atomic operation in actual use. For example, when training a large language model, because the training volume itself is large, even if there are a small number of errors, it will not have much impact on the training effect. Therefore, the exception handling circuit 30 is supported to ignore some errors caused by the atomic operation. The exception handling circuit 30 supports the user to select an exception handling method in a targeted manner through exception handling configuration, which can improve the flexibility of the atomic operation processing unit 120 .

[0093] To sum up, the unit provided in the embodiment of the present application illustrates the function of the exception handling circuit, which selects whether to write the atomic operation result to the storage unit based on the exception information, thereby realizing exception handling at the exit of the atomic operation processing circuit and ensuring the reliability of the atomic operation processing unit in performing atomic operations.

[0094] In different atomic operations, the sources of the corresponding atomic operands are different. For example, the input data (also called atomic operands) can include original data and read data. For some atomic operations, the input data only includes original data; for other atomic operations, the input data may include both original data and read data. Atomic operands from different sources will introduce different exceptions. Therefore, it is necessary to set up exception detection circuits for atomic operands from different sources, such as Figure 3 and Figure 4 It should be noted that Figure 3 and Figure 4 The first abnormality detection circuit, the second abnormality detection circuit, and the third abnormality detection circuit shown in FIG. 1 are optional circuits for different implementation scenarios, that is, in some embodiments, only the circuit includes Figure 3 and Figure 4 The first abnormality detection circuit 11 shown in FIG. 1 ; in other embodiments, only the first abnormality detection circuit 11 shown in FIG. Figure 3 and Figure 4 The second abnormality detection circuit 12 shown in FIG. 1; in other embodiments, only includes Figure 3 and Figure 4 The third abnormality detection circuit 13 shown in FIG. 1 ; in some other embodiments, comprising Figure 3 and Figure 4 The first abnormality detection circuit 11 and the second abnormality detection circuit 12 shown in FIG. 1; in some other embodiments, the first abnormality detection circuit 11 and the second abnormality detection circuit 12 shown in FIG. 1 include: Figure 3 and Figure 4 The first abnormality detection circuit 11 and the third abnormality detection circuit 13 shown in FIG. 1; in some other embodiments, the first abnormality detection circuit 11 and the third abnormality detection circuit 13 shown in FIG. 1 include: Figure 3 and Figure 4 The second abnormality detection circuit 12 and the third abnormality detection circuit 13 shown in FIG. 1; in some further embodiments, the Figure 3 and Figure 4 1 , a first abnormality detection circuit 11 , a second abnormality detection circuit 12 , and a third abnormality detection circuit 13 are shown in FIG.

[0095] Optionally, the second abnormality detection circuit 12 and the third abnormality detection circuit 13 are both connected to the second input terminal of the atomic operation processing circuit 20. When the abnormality detection circuit 10 includes the second abnormality detection circuit 12 and the third abnormality detection circuit 13, the atomic operation processing unit 120 further includes a first selection circuit 14. The first selection circuit 14 selects the output of the second abnormality detection circuit 12 or the output of the third abnormality detection circuit 13 based on the first selection signal, and outputs the selected output to the second input terminal of the atomic operation processing circuit 20. Exemplarily, the first selection signal is determined based on the atomic operation instruction.

[0096] Raw data exception:

[0097] First, the connection relationship of the first abnormality detection circuit set for raw data abnormality is shown.

[0098] Optionally, the anomaly detection circuit 10 includes a first anomaly detection circuit 11 ; the first anomaly detection circuit 11 includes an original data input terminal and an original data output terminal; the original data output terminal is connected to the first input terminal of the atomic operation processing circuit 20 .

[0099] The original data input terminal of the abnormality detection circuit 10 is used to receive the original data; the first input terminal of the atomic operation processing circuit 20 is used to receive the original data and the first abnormality information.

[0100] The original data is input from the original data input terminal of the first exception detection circuit 11, and the first exception detection circuit 11 performs exception detection. The original data after exception detection is output from the original data output terminal of the first exception detection circuit 11 to the first input terminal to the atomic operation processing circuit 20.

[0101] Optionally, the atomic operation includes a first type of atomic operation, a second type of atomic operation and a third type of atomic operation. The first type of atomic operation requires 1 atomic operand (such as 1 original data), the second type of atomic operation requires 2 atomic operands (such as 1 original data and 1 read data), and the third type of atomic operation requires 3 atomic operands (such as 2 original data and 1 read data). It should be noted that the source of the atomic operands required for different types of atomic operands is only for illustration, and other combinations of atomic operands can also be used in actual scenarios, such as the second type of atomic operation requires 2 original data or 2 read data, etc., which is not limited in the embodiments of the present application. There are atomic operation processing circuits corresponding to different atomic operation types in the atomic operation processing circuit 20, such as the first type of atomic operation processing circuit 26, the second type of atomic operation processing circuit 27 and the third type of atomic operation processing circuit 28. Optionally, the atomic operation processing unit 120 includes a second selection unit 15, which is used to select the output of the first type atomic operation processing circuit 26, the output of the second type atomic operation processing circuit 27, and the output of the third atomic operation processing circuit 28 based on a second selection signal. Exemplarily, the second selection signal is determined based on the atomic operation instruction.

[0102] Optionally, in a scenario where the atomic operation requires at least two original data, the at least two original data are transmitted in one clock cycle, or the at least two original data are transmitted in different clock cycles. In the case where the at least two original data are transmitted in one clock cycle, the first anomaly detection circuit 11 performs anomaly detection based on the at least two original data, or the first anomaly detection circuit 11 performs anomaly detection based on the data stream that transmits the at least two original data.

[0103] Alternatively, if Figure 3 As shown, the first abnormality detection circuit 11 performs abnormality detection based on the received data stream of one clock cycle, and outputs the data stream to the atomic operation processing circuit 20. Specifically, as Figure 5 As shown, when the data stream 40 is input to the first abnormality detection circuit 11, the first abnormality detection circuit 11 performs abnormality detection based on the data stream 40, and outputs the data stream 40 and abnormality information 41 to the input end of the atomic operation processing circuit 20 when the original data in the data stream 40 is abnormal; when the original data in the data stream 40 is not abnormal, only the data stream 40 is output to the input end of the atomic operation processing circuit 20;

[0104] or, as Figure 4 As shown, the first abnormality detection circuit 11 performs abnormality detection based on the received data stream of one clock cycle, and extracts the original data from the data stream and outputs it to the atomic operation processing circuit 20. Specifically, as Figure 6 As shown, after the data stream 40 is input to the first abnormality detection circuit 11, the first abnormality detection circuit 11 performs abnormality detection based on the data stream 40 and extracts the original data 42 from the data stream 40; when the original data 42 is abnormal, the original data 42 and the abnormality information 41 are output to the input end of the atomic operation processing circuit 20; when the original data 42 is not abnormal, only the original data 42 is input to the atomic operation processing circuit 20. In the case where the data stream 40 includes multiple original data and the atomic operation processing circuit 20 is provided with multiple input ends for inputting the original data, as shown in FIG. Figure 7 As shown, after the data stream 40 is input to the first abnormality detection circuit 11, the first abnormality detection circuit 11 performs abnormality detection based on the data stream 40, and extracts the original data 42 and the original data 43 from the data stream 40; when the original data 42 is abnormal, the original data 42 and the abnormality information 41 are output to the input end of the atomic operation processing circuit 20; when the original data 42 is not abnormal, the original data 42 is only output to one input end of the atomic operation processing circuit 20; when the original data 43 is abnormal, the original data 43 and the abnormality information 44 are output to the other input end of the atomic operation processing circuit 20; when the original data 43 is not abnormal, the original data is only input to the other input end of the atomic operation processing circuit. Among them, the abnormality information 41 and the abnormality information 44 are the same abnormality information, or the abnormality information 41 and the abnormality information 44 are different abnormality information. It should be noted that the above embodiment is described by taking the data stream 40 including 2 original data as an example, but the data stream 40 can also include 3, 4 or even more original data, and the embodiment of the present application is not limited to this.

[0105] It should be noted that the above embodiment is described by taking the example of the first abnormality detection circuit 11 performing abnormality detection based on the data stream 40. It can also be said that the first abnormality detection circuit 11 performs abnormality detection based on the original data in the data stream 40. The embodiment of the present application does not limit this.

[0106] In summary, the unit mentioned in the embodiment of the present application shows the structure of the first abnormality detection circuit for the original data abnormality. The first abnormality detection circuit is used to receive and detect the original data abnormality, so that the atomic operation processing unit can identify the original data abnormality. Thereby avoiding the abnormality of the atomic operation result caused by the original data abnormality, and improving the reliability of the atomic operation processing unit in performing the atomic operation.

[0107] Next, the process of the first abnormality detection circuit detecting the abnormality of the original data is shown.

[0108] Optionally, the first exception detection circuit is used to output the original data and first exception information to the atomic operation processing circuit when the first bit width is different from the second bit width, the first exception information is used to indicate that the original data is abnormal, the first bit width is the bit width indicated by the atomic operation instruction, and the second bit width is the bit width indicated by the bus that transmits the original data.

[0109] The first bit width is the bit width indicated by the atomic operation instruction, or the first bit width is the bit width of the atomic operation, or the first bit width is the bit width of the atomic operand, or the first bit width is the bit width of the original data. There is a first indicator bit in the atomic operation instruction, which is used to indicate the first bit width. If the atomic operation can be divided into 16 bits, 32 bits and 64 bits according to the bit width of the atomic operand, the first indicator bit can include 2 bits. If the first indicator bit is 00, it means that the first bit width is 16 bits; if the first indicator bit is 01, it means that the first bit width is 32 bits; if the first indicator bit is 10, it means that the first bit width is 64 bits.

[0110] Since the transmission of raw data in the processor is based on electrical signal transmission, that is, it is transmitted with a high level representing 1 and a low level representing 0, a strobe signal (also referred to as an enable signal, a selection signal, an indication signal, etc.) needs to be set. The second bit width is the bit width indicated by the bus transmitting the raw data, or the second bit width is the bit width of the raw data indicated by the bus, or the second bit width is the bit width of the raw data indicated by the strobe signal.

[0111] The difference between the first bit width and the second bit width means that there is a conflict between the bit width indicated by the processor and the bit width indicated by the bus, that is, there is a conflict between the atomic operation instruction indicated by the processor and the bus protocol. In this case, the atomic operation processing unit 120 may not be able to extract the correct original data, so that the atomic operation result obtained by executing the atomic operation is wrong.

[0112] Exemplarily, the second bit width is indicated by a strobe signal, such as a strobe signal that is a strb (Strobe) signal, and the strb signal is used to indicate the validity of the data on the bus. For example: a bus with a data bit width of 256 bits requires a 32-bit strb signal to indicate whether each 1-bit strb signal indicates whether each 8-bit data on the bus is valid. In the case where the input data includes 1 original data, the first abnormality detection circuit only needs to determine whether the valid data on the bus (i.e., the second bit width) matches the bit width of the atomic operation (i.e., the first bit width). Taking the input data bit width transmitted by the bus as 256 bits as an example, different strb signal formats are set for atomic operations of different bit widths (such as 16-bit, 32-bit, and 64-bit atomic operations), as shown in Table 1.

[0113] Table 1.1 strb format corresponding to the original data

[0114]

[0115] Among them, 0xF represents "1111", 0x0 represents "0000", 0xC represents "1100", and 0x3 represents "0011".

[0116] Taking the atomic operation bit width of 64 bits as an example, the strb signal format is explained. For a 256-bit bus, a 32-bit strb signal is required to indicate the validity of the data within a clock cycle; for 64-bit raw data, an 8-bit strb signal is required to indicate, and each letter in the strb signal format represents a 4-bit strb signal. Therefore, the 64-bit atomic operand corresponds to two bits in the strb signal format, that is, "AA", "BB", "CC" and "DD" respectively represent possible raw data. Figure 8 As shown in the figure, "AA" corresponds to bits 192 to 255 of the 256-bit bus; "BB" corresponds to bits 128 to 191 of the 256-bit data bus; "CC" corresponds to bits 64 to 127 of the 256-bit data bus; and "DD" corresponds to bits 0 to 63 of the 256-bit bus. When both A and D are 0xF, that is, AABB_CCDD is "1111 11110000 0000_0000 0000 1111 1111", two original data are sent on the bus, which are bits 192 to 255 and bits 0 to 63 respectively.

[0117] Optionally, in the case where the input data includes at least two original data, at least two original data can be selected to be transmitted by the bus within one clock cycle, and at least two original data are indicated by a selection signal. The first exception detection unit 11 is also used to determine at least two original data and a second bit width of at least two original data based on the selection signal. That is, the first exception detection unit 11 can determine the bit width of the original data based on the selection signal while determining the original data. For example, it is agreed that the value of a bit in the selection signal is 1 to indicate that the corresponding data bit has original data, and continuous bits with a value of 1 indicate a complete original data; and it is agreed that at least two original data are transmitted non-continuously, with the above Figure 8 For example, the format of the selection signal is AABB_CCDD, and the value is 1111 1111 0000 0000_0000 0000 1111 1111. If it is known that the consecutive bits with the value of 1 indicate a complete original data, two original data can be determined, namely the original data corresponding to the AA bit and the original data corresponding to the DD bit. At the same time, the second bit width of the two original data can also be determined based on the selection signal, which is 64 bits.

[0118] The selection signal is used to indicate whether each original data transmitted in one clock cycle of the bus is carrying original data, and the number of bits included in the data bit is determined based on the bit width of the original data. This method supports the transmission of multiple original data in one clock cycle, improves the transmission efficiency of the original data, and further improves the execution efficiency of the atomic operation.

[0119] Exemplarily, the number of bits included in the data bit is equal to the bit width of the original data. The data bit is the bit that carries the original data, and one data bit carries one original data. Still taking the above atomic operation bit width of 64 bits as an example, at this time, one original data bit includes 64 bits, that is, Figure 8 The 192th to 255th bits are the first data bit, the 128th to 191st bits are the second data bit, the 64th to 127th bits are the third data bit, and the 0th to 63rd bits are the fourth data bit.

[0120] Optionally, the selection signal includes multiple indicator bits, the number of bits included in each of the multiple indicator bits is determined based on the bit width of the original data, each indicator bit is used to indicate whether the data bit corresponding to the indicator bit carries the original data, or each indicator bit is used to indicate the original data type carried by the data bit corresponding to the indicator bit, the original data type includes the first original data, the second original data, ..., the nth original data and invalid data, where n is a positive integer.

[0121] Among them, there is a one-to-one correspondence between the indicator bit and the data bit. The number of bits included in the indicator bit is determined based on the bit width of the original data, that is, the number of bits included in the indicator bit is related to the bit width of the original data. Generally speaking, the number of bits included in the indicator bit is proportional to the bit width of the original data. For example, the number of bits included in the indicator bit is one eighth of the bit width of the original data, and the number of bits included in the data bit is equal to the bit width of the original data, that is, 1 bit in the indicator bit is used to indicate 8 bits in the original data bit.

[0122] In some embodiments, each indicator bit is used to indicate whether the original data bit corresponding to the indicator bit carries original data. The values ​​of the bits in the indicator bit are all 0, or all 1. For example, if the values ​​of the bits in the indicator bit are all 0, it means that the original data bit corresponding to the indicator bit does not carry original data (or carries invalid data); if the values ​​of the bits in the indicator bit are all 1, it means that the original data bit corresponding to the indicator bit carries original data. Figure 8 In the scenario shown, "AA", "BB", "CC" and "DD" are four indicator bits.

[0123] In other embodiments, each indicator bit is used to indicate that the data bit corresponding to the indicator bit carries the original data as the first original data or the second original data. That is, at least two original data include the first original data and the second original data. The indicator bit with the first value in the selection signal is used to indicate that the original data carried by the data bit corresponding to the indicator bit is the first original data; the indicator bit with the second value in the selection signal is used to indicate that the original data carried by the data bit corresponding to the indicator bit is the second original data. The first abnormality detection unit 11 is also used to determine the second bit width of the first original data and the first original data based on the indicator bit with the first value; and determine the second bit width of the second original data and the second original data based on the indicator bit with the second value. Indicator bits with different values ​​are used to indicate different original data, rather than just indicating whether the original data is included. This method can support atomic operations that require two original data to receive two original data in one clock cycle, without receiving them separately in two clock cycles, especially for atomic operations that need to distinguish the uses of the original data, such as the first original data in the above-mentioned cas operation is the original data for comparison, and the second original data is the original data for exchange. Receiving two original data in one clock cycle can shorten the transmission time of the original data, thereby improving the execution efficiency of the atomic operation.

[0124] Optionally, after determining the second bit width of the first original data and the second bit width of the second original data, the first exception detection unit 11 determines whether the first bit width is the same as the second bit width of the first original data, and outputs first exception information when the first bit width is different from the second bit width of the first original data; and determines whether the first bit width is the same as the second bit width of the second original data, and outputs first exception information when the first bit width is different from the second bit width of the second original data. In some embodiments, the first exception information is also used to indicate the original data in which the exception occurs. For example, the first exception information is used to indicate that the first original data is abnormal, or the first exception information is used to indicate that the second original data is abnormal.

[0125] Optionally, the indicator bit with the first value is on the first side of the indicator bit with the second value, and the indicator bit with the first value is adjacent to the indicator bit with the second value, and the first side can be the left side or the right side. That is, the indicator bit with the second value is the indicator bit adjacent to the left side of the indicator bit with the first value; or, the indicator bit with the second value is the indicator bit adjacent to the right side of the indicator bit with the first value. The embodiment of the present application will be illustrated by taking the indicator bit with the second value as the indicator bit adjacent to the left side of the indicator bit with the first value, but this is not limited. The positional relationship between the indicator bits indicating the first original data and the indicator bits indicating the second original data is agreed upon here, so that the atomic operation processing unit 120 can confirm the first original data and the second original data based on this, further ensuring the reliability of transmitting the two original data within one clock cycle, and improving the execution efficiency of the atomic operation.

[0126] Exemplarily, the indicator bit with the first value is that the values ​​of the bits in the indicator bit are all 1, and the indicator bit with the second value is that the values ​​of the bits in the indicator bit are all 0; or, the indicator bit with the first value is that the values ​​of the bits in the indicator bit are all 0, and the indicator bit with the second value is that the values ​​of the bits in the indicator bit are all 1. In addition, if the number of bits included in the indicator bit is 4, the value of the indicator bit with all bit values ​​1 (1111) can be expressed as a hexadecimal value, that is, 0xF; the value of the indicator bit with all bit values ​​0 (0000) can be expressed as a hexadecimal value, that is, 0x0. If the number of bits included in the indicator bit is 2, the value of the indicator bit with all bit values ​​1 is 11, and the value of the indicator bit with all bit values ​​0 is 00. The indicator bit can be expressed as a hexadecimal value alone, and can also be converted into a hexadecimal value in the selection signal. If the selection signal is 8 bits and the number of bits included in the indicator bit is 2, then the selection signal 00 (3rd indicator bit) 11 (2nd indicator bit) 11 (1st indicator bit) 11 (0th indicator bit) can be expressed as 0x3F.

[0127] Optionally, the atomic operation instruction includes an odd atomic operation instruction and an even atomic operation instruction. The atomic operation indicated by the odd atomic operation instruction can be called an odd operation, and the atomic operation indicated by the even atomic operation instruction can be called an even operation. In the case where the atomic operation instruction is an odd operation instruction, the indicator bit with the first value is located at the odd bit of the selection signal; in the case where the atomic operation instruction is an even operation instruction, the indicator bit with the first value is located at the even bit of the selection signal. Among them, the indicator bit with the first value is located at the odd bit of the selection signal, which can be called the indicator bit with the first value is the odd-numbered indicator bit of the selection signal; the indicator bit with the first value is located at the even bit of the selection signal, which can be called the indicator bit with the first value is the even-numbered indicator bit of the selection signal. The atomic operation instructions are distinguished into odd operation instructions and even operation instructions, which facilitates alignment according to the category of the atomic operation instruction when the bus transmits at least two original data, and facilitates the reading, writing and transmission of data.

[0128] Optionally, when the atomic operation instruction is an odd operation instruction, the indicator bit with the second value is located at an odd bit of the selection signal; when the atomic operation instruction is an even operation instruction, the indicator bit with the second value is located at an even bit of the selection signal.

[0129] Optionally, the position of the indicator bit in the selection signal is numbered from right to left and starts from zero. For example, the selection signal 00 (the 3rd indicator bit) 11 (the 2nd indicator bit) 11 (the 1st indicator bit) 11 (the 0th indicator bit). In addition, it can be agreed that the 0th bit is an even bit. It should be noted that the embodiment of the present application does not limit the position numbering of the selection signal, and it can also be numbered from left to right, and the starting number can also start from one.

[0130] In the case where the input data includes 2 original data, the 2 original data can be sent simultaneously in one clock cycle. In order to distinguish the two original data, the following format design is made. The first original data is recorded as original data 1, the second original data is recorded as original data 2, 1 bit in the indicator bit corresponds to 8 bits in the data bit, the first value is that the value of the bit is all 1, and the second value is that the value of the bit is all 0. Odd operation refers to the atomic operation of the indicator bit of original data 1 in the odd bit of the strb signal, and even operation refers to the atomic operation of the indicator bit of original data 1 in the even bit of the strb signal. In the odd operation and even operation, the valid data bit indicated by the strb signal is taken as original data 1, and the invalid data bit indicated by the strb signal on the left is taken as original data 2. Taking the input data bit width transmitted by the bus as 256 bits as an example, different strb signal formats are set for atomic operations of different bit widths (such as atomic operations of 16 bits, 32 bits and 64 bits), as shown in Table 2.

[0131] Table 2.2 strb formats corresponding to the original data

[0132]

[0133] For the 64-bit atomic operation bit width, the indicator bits of the original data include 8 bits, that is, the following division method should be adopted, taking the even operation as an example: "00 (the 3rd indicator bit) AA (the 2nd indicator bit) _00 (the 1st indicator bit) BB (the 0th indicator bit)". For the 32-bit atomic operation bit width, the indicator bits of the original data include 4 bits, that is, the following division method should be adopted, taking the odd operation as an example: "A (the 7th indicator bit) 0 (the 6th indicator bit) B (the 5th indicator bit) 0 (the 4th indicator bit) _C (the 3rd indicator bit) 0 (the 2nd indicator bit) D (the 1st indicator bit) 0 (the 0th indicator bit)". For the 16-bit atomic operation bit width, the indicator bits of the original data include 2 bits. Taking the even operation as an example, each bit shown in the strb signal format can be expressed as "00 (the odd indicator bit) 00 (the even indicator bit)".

[0134] First, we need to explain the definition of "left side". Take the strb signal format under the even operation corresponding to the above 32-bit atomic operation as an example. Fig. 9 As shown, each bit in "0A0B_0C0D" is numbered from right to left, namely the 0th indicator bit to the 7th indicator bit. If the D of the 0th indicator bit is 0xF, it means that the corresponding data bit is a valid data bit, that is, the original data 1, then the invalid data bit in the 1st indicator bit adjacent to the left side of the 0th indicator bit represents the original data 2 transmitted together with the original data 1. Similarly, if the data bit corresponding to the C of the 2nd indicator bit is a valid data bit, then the invalid data bit corresponding to the 3rd bit adjacent to its left side represents another original data; if the data bit corresponding to the C of the 2nd indicator bit is an invalid data bit, then the 3rd indicator bit adjacent to its left side also corresponds to an invalid data bit. Taking the strb signal format under the odd operation corresponding to the 32-bit atomic operation as an example, Fig.10 As shown, each bit in "A0B0_C0D0" is numbered from right to left, namely the 0th indicator bit to the 7th indicator bit. If D of the 1st indicator bit is 0xF, it means that the corresponding data bit is a valid data bit, that is, the original data 1, and the invalid data bit in the 2nd indicator bit adjacent to the left side of the 1st indicator bit indicates the original data 2 transmitted together with the original data 1; the same is true for C of the 3rd indicator bit and B of the 5th indicator bit; and if A of the 7th indicator bit is 0xF, it means that the corresponding data bit is a valid data bit, that is, the original data 1, and the invalid data bit in the 0th indicator bit adjacent to the left side of the 7th indicator bit indicates the original data 2 transmitted together with the original data 1. That is, the bit adjacent to the left side of the 7th indicator bit is the 0th indicator bit.

[0135] Taking the atomic operation bit width of 32 bits as an example, the strb signal format is explained. For a 256-bit bus, a 32-bit strb signal is required to indicate the validity of the data within a clock cycle; for 32-bit raw data, an 8-bit strb signal is required to indicate, and each letter in the strb signal format represents a 4-bit strb signal, so the 32-bit atomic operand corresponds to one bit in the strb signal format, that is, "A", "B", "C", and "D" represent possible raw data respectively. For even operations, such as Fig.11 As shown, "A" corresponds to bits 192 to 223 in the 256-bit bus; "B" corresponds to bits 128 to 159 in the 256-bit data bus; "C" corresponds to bits 64 to 95 in the 256-bit data bus; and "D" corresponds to bits 0 to 31 in the 256-bit bus. When both A and D are 0xF, that is, "0A0B_0C0D" is "00001111 0000 0000_0000 0000 0000 1111", two groups of original data are sent on the bus. One group of original data is transmitted from bit 0 to bit 63, bit 0 to bit 31 is original data 1, and bit 32 to bit 63 is original data 2; another group of original data is transmitted from bit 192 to bit 255, bit 192 to bit 223 is original data 1, and bit 224 to bit 255 is original data 2.

[0136] For odd operations, such as Fig.12 As shown, "A" corresponds to the 224th to 255th bits in the 256-bit bus; "B" corresponds to the 160th to 191st bits in the 256-bit data bus; "C" corresponds to the 96th to 127th bits in the 256-bit data bus; "D" corresponds to the 32nd to 63rd bits in the 256-bit bus. When both A and D are 0xF, that is, A0B0_C0D0 is "1111 0000 0000 0000_0000 00001111 0000", two groups of original data are sent on the bus. One group of original data is transmitted from the 32nd to the 95th bit, the 32nd to the 63rd bit is original data 1, and the 34th to the 95th bit is original data 2; another group of original data is transmitted from the 224th to the 255th bit and from the 0th to the 31st bit, the 224th to the 255th bit is original data 1, and the 0th to the 31st bit is original data 2.

[0137] Optionally, the atomic operation processing circuit 20 is further used to output the atomic operation result and the first exception information to the exception processing circuit 30. In the case where the atomic operation processing module 120 includes a first exception detection circuit, the atomic operation processing circuit 20, in addition to being used to perform the atomic operation based on the original data to obtain the atomic operation result, is also used to output the first exception information input from the first exception detection circuit 11 and the atomic operation result from the output end to the exception processing circuit 30.

[0138] For detailed information about the atomic operation processing circuit 20 , please refer to the above “2. Atomic operation processing circuit 20 ”, which will not be described in detail here.

[0139] Optionally, the exception handling circuit 30 is further configured to select to discard the atomic operation result, or to write the atomic operation result into a storage unit based on the first exception information.

[0140] For detailed information about the exception handling circuit 30 , please refer to the above “3. Exception handling circuit 30 ”, which will not be described in detail here.

[0141] To summarize, the unit provided in the embodiment of the present application shows the exception detection process of the first exception detection circuit, which detects whether there is an original data exception by confirming the bit width indicated by the atomic operation instruction and the bit width indicated by the bus, that is, confirming whether there is an original data reading error caused by a conflict between the bus protocol and the atomic operation instruction indicated by the processor, thereby avoiding abnormal atomic operation results caused by abnormal original data and improving the reliability of the atomic operation processing unit in performing atomic operations.

[0142] Read data abnormality:

[0143] First, the connection relationship of the second abnormality detection circuit provided for read data abnormality is shown.

[0144] Optionally, the abnormality detection circuit includes a second abnormality detection circuit 12 ; the second abnormality detection circuit 12 includes a read data input terminal and a read data output terminal; the read data output terminal is connected to the second input terminal of the atomic operation processing circuit 20 .

[0145] Optionally, the atomic operation processing unit 120 reads read data from the storage unit based on the atomic operation instruction, and the read data can also be called read return data. The atomic operation instruction indicates the address of reading the read data. For the atomic operation, the address also indicates the write address of the atomic operation result; that is, the address of the read data is the write address of the atomic operation result. In other words, during the atomic operation process, the read data is read from the address of the read data indicated by the atomic operation instruction, and after performing the atomic operation on the read data based on the atomic operation instruction, the atomic operation result is obtained, and the atomic operation result is written to the address of the read data indicated by the atomic operation instruction.

[0146] In summary, the unit provided in the embodiment of the present application shows the structure of the second abnormality detection circuit for read abnormality. The second abnormality detection circuit is used to receive and detect read data abnormality, so that the atomic operation processing unit can identify the read data abnormality. Thereby avoiding the abnormality of the atomic operation result caused by the read data abnormality, and improving the reliability of the atomic operation processing unit in performing the atomic operation.

[0147] Next, the process of detecting read data abnormality by the second abnormality detection circuit 12 is shown.

[0148] Optionally, the second exception detection circuit 12 is used to output the read data and second exception information to the atomic operation processing circuit 20 when there is an exception in the read data, and the second exception information is used to indicate that the read data is abnormal, and the read data is data read from the storage unit based on the atomic operation instruction.

[0149] Optionally, the atomic operation processing unit 120 reads read data from the storage unit based on the atomic operation instruction, that is, the atomic operation processing unit 120 sends a read request to the storage unit through the bus, and the storage unit reads the read data according to the read request, and returns the read data to the atomic operation processing unit 120 through the read data path in the bus. Among them, the read data path is also used to transmit exception information. Optionally, the exception information transmitted in the read data path is generated in the process of reading the read data, such as read timeout, decoding error, etc. Generally speaking, the control unit in the processor captures the exception and generates exception information. The second exception detection circuit 12 is used to detect whether there is exception information in the read data path. When there is exception information in the read data path, it is confirmed that there is an exception in the read data, and the second exception information is output to the atomic operation processing circuit 20; when there is no exception information in the read data path, it is confirmed that there is no exception in the read data.

[0150] Optionally, the read data abnormality also includes other situations, such as the bit width of the read data is different from the first bit width; or the bit width of the read data is different from the second bit width, etc.

[0151] Optionally, the atomic operation processing circuit 20 is further used to output the atomic operation result and the second exception information to the exception processing circuit. In the case where the atomic operation processing module 120 includes a second exception detection circuit, the atomic operation processing circuit 20, in addition to being used to perform the atomic operation based on the read data to obtain the atomic operation result, is also used to output the second exception information input from the second exception detection circuit 12 and the atomic operation result to the exception processing circuit 30.

[0152] For detailed information about the atomic operation processing circuit 20 , please refer to the above “2. Atomic operation processing circuit 20 ”, which will not be described in detail here.

[0153] Optionally, the exception handling circuit 30 is further configured to select to discard the atomic operation result, or to write the atomic operation result into a storage unit based on the second exception information.

[0154] For detailed information about the exception handling circuit 30 , please refer to the above “3. Exception handling circuit 30 ”, which will not be described in detail here.

[0155] To sum up, the unit provided in the embodiment of the present application shows the abnormality detection process of the second abnormality detection circuit, which detects whether there is a read data abnormality by confirming whether there is abnormal information in the read data path, thereby avoiding abnormal atomic operation results caused by read data abnormality and improving the reliability of the atomic operation processing unit in performing atomic operations.

[0156] The atomic operation processing circuit 20 also includes a same address processing path for connecting the output terminal and the second input terminal. The same address processing path is used to return the i-th atomic operation result corresponding to the i-th instruction to the second input terminal when the i-th instruction and the i+1-th instruction correspond to the same address, and participate in the execution of the i+1-th instruction.

[0157] Optionally, after the atomic operation corresponding to the i-th instruction is executed, the atomic operation processing circuit 20 returns the i-th atomic operation result to the second input terminal through the same address processing path, and outputs the i-th atomic operation result to the exception processing circuit 30; or, after the atomic operation corresponding to the i-th instruction is executed, the atomic operation processing circuit 20 only returns the i-th atomic operation result to the second input terminal through the same address processing path, but does not output the i-th atomic operation result to the exception processing circuit 30; until the atomic operation corresponding to the j-th instruction is executed, the j-th atomic operation result is output to the exception processing circuit 30. The i-th instruction to the j-th instruction all correspond to the same address, but the j+1-th instruction and the j-th instruction correspond to different addresses, i and j are both positive integers, j>i.

[0158] Exemplarily, the atomic operation processing circuit 20 will process four atomic operation instructions, namely instruction 1, instruction 2, instruction 3 and instruction 4, wherein instruction 1, instruction 2 and instruction 3 correspond to the same address, and instruction 4 corresponds to different addresses from instruction 3. Then, when the atomic operation processing circuit 20 performs an atomic operation, it first obtains an atomic operation result 1 based on instruction 1. Since instruction 2 corresponds to the same address as instruction 1, the atomic operation result 1 is returned to the second input terminal through the same address processing path; the atomic operation processing circuit 20 performs an atomic operation based on instruction 2 and atomic operation result 1 to obtain an atomic operation result 2. Since instruction 3 corresponds to the same address as instruction 2, the atomic operation result 2 is returned to the second input terminal through the same address processing path; the atomic operation processing circuit 20 performs an atomic operation based on instruction 3 and atomic operation result 2 to obtain an atomic operation result 3. Since instruction 4 corresponds to different addresses from instruction 3, the atomic operation processing circuit 20 outputs the atomic operation result 3 to the exception handling circuit 30; the atomic operation processing circuit 20 performs an atomic operation based on instruction 4 to obtain an atomic operation result 4.

[0159] In the second scenario shown above, that is, "after the atomic operation corresponding to the ith instruction is executed, the atomic operation processing circuit 20 only returns the ith atomic operation result to the second input terminal through the same address processing path, but does not output the ith atomic operation result to the exception handling circuit 30; until the atomic operation corresponding to the jth instruction is executed, the jth atomic operation result is input into the exception handling circuit 30", because the ith atomic operation result will not be output to the exception handling circuit 30 for exception handling, but the final result obtained by multiple atomic operation instructions with the same address is output to the exception handling circuit 30, if the atomic operation result corresponding to the atomic operation instruction executed in the middle has an exception, but the atomic operation result corresponding to the last atomic operation instruction does not have an exception, at this time, the exception handling circuit 30 will only judge whether it carries exception information based on the atomic operation result corresponding to the last atomic operation instruction, which may still cause the processor to read erroneous information. Therefore, a third exception handling circuit is set in the same address processing path.

[0160] Optionally, the abnormality detection circuit 10 includes: a third abnormality detection circuit 13 arranged on the same address processing path, the same address processing path is connected to the output end and the second input end of the atomic operation processing circuit 20; the third abnormality detection circuit 13 includes a processing result input end and a processing result output end; the processing result input end is connected to the output end through the same address processing path, and the processing result output end is connected to the second input end through the same address processing path. Wherein, the same address processing path is located inside the atomic operation processing circuit 20.

[0161] In summary, the unit provided in the embodiment of the present application shows the structure of the third exception detection circuit for the same address processing path. The third exception detection circuit is used to return the atomic operation result and the abnormal information it carries to the second input terminal, thereby avoiding the abnormal atomic operation result caused by the original data abnormality and improving the reliability of the atomic operation processing unit in performing the atomic operation.

[0162] Next, the process of abnormality detection performed by the third abnormality detection circuit 13 is described.

[0163] The atomic operation processing circuit 20 will execute multiple consecutive operations with the same address, that is, execute n atomic operation instructions, which correspond to the same address. The n+1th atomic operation instruction executed by the atomic operation processing circuit corresponds to a different address than the nth atomic operation instruction.

[0164] Optionally, the i-th instruction is one of the n atomic operation instructions received by the atomic operation processing circuit 20, and i is not equal to 1 or n, n is an integer greater than 1, and the n atomic operation instructions correspond to the same write address; the atomic operation processing circuit 20 is also used to perform an atomic operation based on the i-1th atomic operation result and the i-th instruction to obtain the i-th atomic operation result, and the i-1th atomic operation result is obtained by performing an atomic operation based on the first i-1 instructions among the n atomic operation instructions; the third exception detection circuit 13 is used to output the i-th atomic operation result and the exception information to the second input terminal through the same address processing path when the i-th atomic operation result carries exception information.

[0165] Among them, the method for judging whether the atomic operation result carries exception information can refer to the process of receiving the atomic operation result and exception information in the above-mentioned "3. Exception processing circuit 30", which will not be repeated here.

[0166] That is, for the atomic operation instruction executed in the middle, the corresponding atomic operation result and exception information are not output to the exception handling module 30, but are returned to the second input end through the third exception detection circuit 13 via the same address processing path.

[0167] Optionally, the abnormal information detected by the third abnormality detection circuit 13 is the first abnormal information and / or the second abnormal information. In other embodiments, the third abnormality detection circuit 13 is used to detect abnormalities generated when the input data passes through the atomic operation processing circuit 20, such as calculation errors caused by the atomic operation processing circuit 20.

[0168] Optionally, the nth instruction is the last one of n atomic operation instructions received by the atomic operation processing circuit 20, n is a positive integer, and the n atomic operation instructions correspond to the same write address; the atomic operation processing circuit 20 is also used to perform an atomic operation based on the n-1th atomic operation result and the nth instruction to obtain the nth atomic operation result, and the n-1th atomic operation result is obtained by performing an atomic operation based on the first n-1 instructions among the n instructions; the exception handling circuit 30 is also used to select to discard the nth atomic operation result, or to write the nth atomic operation result into a storage unit when the nth atomic operation result carries exception information.

[0169] In addition, for the first instruction, the atomic operation processing circuit 20 performs the atomic operation based on the first instruction to obtain the first atomic operation result.

[0170] In summary, the unit provided by the embodiment of the present application shows an exception detection process for the same address processing path. In the case where multiple atomic operation instructions of the same address are not fully executed, the third exception detection circuit is used to return the atomic operation result and the exception information carried by it to the second input end, and the atomic operation result and the exception information output value are not sent to the exception processing module, which can reduce the processing time of multiple atomic operation instructions of the same address and improve the execution efficiency of atomic operations; and there will be no loss of exception information of the atomic operation instructions executed in the middle due to the failure to perform exception processing on the atomic operation results of the atomic operation instructions executed in the middle, thereby avoiding the abnormal atomic operation results caused by the special processing of the atomic operation instructions of the same address, and improving the reliability of the atomic operation processing unit in performing atomic operations.

[0171] Optionally, the atomic operation processing unit 120 includes an exception reporting function in addition to exception detection and exception handling. The atomic operation processing unit 120 also includes an exception reporting unit connected to the exception detection circuit 20; or, the atomic operation processing unit 120 also includes an exception reporting unit connected to the exception handling circuit 30. The exception reporting unit is used to report exception information to the processor.

[0172] The exception information includes the first exception information and / or the second exception information. The exception information also includes other exception information, such as exception information caused by an error in the atomic operation processing circuit 20 executing the atomic operation.

[0173] In summary, the atomic operation processing unit 120 also includes an exception reporting function. After detecting an exception or executing exception processing, the exception information is reported to the processor, so that the processor can resend the atomic operation instruction that caused the exception based on the exception information, or other instructions to indicate the subsequent actions of the atomic operation processing unit 20. In addition, in the case where the exception processing is to choose to write the atomic operation result with an exception into the storage unit, the processor can avoid operating errors caused by not knowing that the atomic operation result has an exception, which indirectly improves the operating efficiency of the processor.

[0174] Fig.13 A schematic diagram of an atomic operation processing unit provided by an exemplary embodiment of the present application is shown. The atomic operation processing unit 120 includes a first exception detection circuit 11, a second exception detection circuit 12, a third exception detection circuit 13, an atomic operation processing circuit 20, and an exception processing circuit 30. The first exception detection circuit 11 is used to determine whether the original data is abnormal based on the signal received from the bus, the second exception detection circuit 12 is used to determine whether the read data is abnormal, and the third exception detection circuit 13 is used to determine whether there is an abnormality in the same address processing path.

[0175] The signals involved in the atomic operation processing unit 120 include at least one of the following:

[0176] wdata_vld: used to indicate whether the write data is valid. wdata_vld is 1, indicating that the write data is valid, that is, the original data is being transmitted on the current bus; wdata_vld is 0, indicating that the write data is invalid, that is, the original data is not being transmitted on the current bus.

[0177] type_is_atomic: used to indicate whether the instruction is an atomic operation instruction. type_is_atomic is 1, indicating that the instruction is an atomic operation instruction; type_is_atomic is 0, indicating that the instruction is not an atomic operation instruction.

[0178] atb_width_illegal: used to indicate whether the bit width indicated by the atomic operation instruction is illegal. If the bit width in the atomic operation instruction is an illegal (or undefined) bit width (such as 8), atb_width_illegal is 1; if the bit width in the atomic operation instruction is a legal bit width, atb_width_illegal is 0.

[0179] atb_opcode_illegal: used to indicate whether the opcode indicated by the atomic operation instruction is illegal. Similar to atb_width_illegal, if the opcode indicated by the atomic operation instruction is an illegal (or undefined) bit width (such as 8), atb_opcode_illegal is 1; if the opcode indicated by the atomic operation instruction is a legal bit width, atb_opcode_illegal is 0.

[0180] type_is_npost_atomic: used to indicate that the instruction is an atomic operation instruction that needs to return read data, or an atomic operation instruction that does not need to return read data. type_is_npost_atomic is 1, indicating that the instruction is an atomic operation instruction that needs to return read data; type_is_npost_atomic is 0, indicating that the instruction is an atomic operation instruction that does not need to return read data.

[0181] burst_len_is_nonzero: used to indicate whether the burst length is non-zero. burst_len_is_nonzero is 1, indicating that the burst length is non-zero; burst_len_is_nonzero is 0, indicating that the burst length is zero.

[0182] atb_width_is_64bit: used to indicate whether the bit width of the atomic operand indicated in the atomic operation instruction is 64 bits. If atb_width_is_64bit is 1, it means that the bit width of the atomic operand indicated in the atomic operation instruction is 64 bits; if atb_width_is_64bit is 0, it means that the bit width of the atomic operand indicated in the atomic operation instruction is not 64 bits.

[0183] axi_strb_unmatch_64bit: used to indicate whether the data validity indicated by the strb signal on the axi bus meets the 64-bit data format requirements. axi_strb_unmatch_64bit is 1, indicating that the data validity indicated by the strb signal on the axi bus does not meet the 64-bit data format requirements; axi_strb_unmatch_64bit is 1, indicating that the data validity indicated by the strb signal on the axi bus meets the 64-bit data format requirements.

[0184] atb_width_is_32bit: used to indicate whether the bit width of the atomic operand indicated in the atomic operation instruction is 32 bits. If atb_width_is_32bit is 1, it means that the bit width of the atomic operand indicated in the atomic operation instruction is 32 bits; if atb_width_is_32bit is 0, it means that the bit width of the atomic operand indicated in the atomic operation instruction is not 32 bits.

[0185] axi_strb_unmatch_32bit: used to indicate whether the data validity indicated by the strb signal on the axi bus meets the 32-bit data format requirements. axi_strb_unmatch_32bit is 1, indicating that the data validity indicated by the strb signal on the axi bus does not meet the 32-bit data format requirements; axi_strb_unmatch_32bit is 1, indicating that the data validity indicated by the strb signal on the axi bus meets the 32-bit data format requirements.

[0186] atb_width_is_16bit: used to indicate whether the bit width of the atomic operand indicated in the atomic operation instruction is 16 bits. If atb_width_is_16bit is 1, it means that the bit width of the atomic operand indicated in the atomic operation instruction is 16 bits; if atb_width_is_16bit is 0, it means that the bit width of the atomic operand indicated in the atomic operation instruction is not 16 bits.

[0187] axi_strb_unmatch_16bit: used to indicate whether the data validity indicated by the strb signal on the axi bus meets the 16-bit data format requirements. axi_strb_unmatch_16bit is 1, indicating that the data validity indicated by the strb signal on the axi bus does not meet the 16-bit data format requirements; axi_strb_unmatch_16bit is 1, indicating that the data validity indicated by the strb signal on the axi bus meets the 16-bit data format requirements.

[0188] atb_opcode_is_cas: used to indicate whether the atomic opcode indicated in the atomic operation instruction is a cas operation. If atb_opcode_is_cas is 1, it means that the atomic opcode indicated in the atomic operation instruction is a cas operation; if atb_opcode_is_cas is 0, it means that the atomic opcode indicated in the atomic operation instruction is not a cas operation.

[0189] axi_strb_unmatch_cas: used to indicate whether the data validity indicated by the strb signal on the axi bus meets the data format requirements of cas. axi_strb_unmatch_cas is 1, indicating that the data validity indicated by the strb signal on the axi bus does not meet the data format requirements of the cas operation; axi_strb_unmatch_cas is 1, indicating that the data validity indicated by the strb signal on the axi bus meets the data format requirements of the cas operation.

[0190] atomic_wdata_err: used to indicate whether there is an abnormality in the write data (i.e., the original data). If atomic_wdata_err is 1, it means that there is an abnormality in the original data; if atomic_wdata_err is 0, it means that there is no abnormality in the original data.

[0191] axi_rresp[1:0]: used to indicate the axi response signal.

[0192] atomic_rdata_err: used to indicate whether there is a data read exception. atomic_rdata_err is 1, indicating that there is a data read exception; atomic_rdata_err is 0, indicating that there is no data read exception.

[0193] atomic_in_err: Used to indicate whether there is an exception with the atomic operand. atomic_in_err is 1, indicating that there is an exception with the atomic operand; atomic_in_err is 0, indicating that there is no exception with the atomic operand.

[0194] fwd: used to indicate whether the i-th instruction (also called the previous instruction) and the i+1-th instruction (also called this instruction) correspond to the same address. fwd is 1, indicating that the i-th instruction and the i+1-th instruction correspond to the same address; fwd is 0, indicating that the i-th instruction and the i+1-th instruction do not correspond to the same address, i is a positive integer.

[0195] result_err: used to indicate whether the anomaly detection result is an anomaly. If result_err is 1, it means that the anomaly detection result is an anomaly; if result_err is 0, it means that the anomaly detection result is no anomaly.

[0196] cfg_discard_errdata: used to indicate whether to configure exception detection. If cfg_discard_errdata is 1, it means that exception detection is required; if cfg_discard_errdata is 0, it means that exception detection is not required.

[0197] For the first abnormality detection circuit 11:

[0198] atb_width_is_64bit is 1 and axi_strb_unmatch_64bit is 0, which means that the first bit width is 64 bits and the second bit width is also 64 bits, that is, the original data is normal. atb_width_is_32bit is 1 and axi_strb_unmatch_32bit is 0, which means that the first bit width is 32 bits and the second bit width is also 32 bits, that is, the original data is normal. atb_width_is_16bit is 1 and axi_strb_unmatch_16bit is 0, which means that the first bit width is 16 bits and the second bit width is also 16 bits, that is, the original data is normal. atb_width_is_64bit is 1 and axi_strb_unmatch_64bit is 1, which means that the first bit width is 64 bits and the second bit width is not 64 bits, that is, the original data is abnormal. If atb_width_is_32bit is 1 and axi_strb_unmatch_32bit is 1, it means that the first bit width is 32 bits, but the second bit width is not 32 bits, that is, the original data is abnormal. If atb_width_is_16bit is 1 and axi_strb_unmatch_16bit is 1, it means that the first bit width is 16 bits, but the second bit width is not 16 bits, that is, the original data is abnormal.

[0199] In addition, the first abnormality detection circuit 11 is valid only when the original data is input (i.e., wdata_vld is 1). When the bit width and / or operation code indicated by the atomic operation instruction (i.e., atb_width_illegal is 1 and / or atb_opcode_illegal is 1) are abnormal, the first abnormality detection circuit 11 will also detect the original data abnormality.

[0200] In other embodiments, the first exception detection circuit 11 will also determine whether the read data needs to be returned. If the read data does not need to be returned but the burst length is non-zero (ie, type_is_npost_atomic is 1 and burst_len_is_nonzero is 1), the first exception detection circuit 11 will detect that the original data is abnormal.

[0201] Optionally, the first abnormality detection circuit 11 includes a first pin and a second pin, the first pin is used to input an indication signal of the first bit width, the second pin is used to input an indication signal of the second bit width, and the first pin is connected to the second pin through an AND gate. For example, the indication signal of the first bit width is at least one of the above-mentioned axi_strb_unmatch_64bit, axi_strb_unmatch_32bit, axi_strb_unmatch_16bit, and atb_opcode_is_cas, and the indication signal of the second bit width is at least one of the above-mentioned axi_strb_unmatch_64bit, axi_strb_unmatch_32bit, axi_strb_unmatch_16bit, and axi_strb_unmatch_cas. When both the first pin and the second pin are input with 1, it indicates that the first bit width is different from the second bit width, that is, there is an original data abnormality; when the first pin is input with 1 and the second pin is input with 0, it indicates that the first bit width is the same as the second bit width, that is, there is no original data abnormality. For any pair of the four pairs of signals shown above (such as axi_strb_unmatch_64bit, axi_strb_unmatch_64bit), if the first pin inputs 0 and the second pin inputs 1, it can be considered that the first bit width and the second bit width are not indicated by the pins corresponding to the pair of signals; if the first pin inputs 0 and the second pin inputs 0, it can also be considered that the first bit width and the second bit width are not indicated by the pins corresponding to the pair of signals.

[0202] For the second abnormality detection circuit 12:

[0203] The corresponding values ​​of the response signal are 00, 01, 10, and 11. Except for the case where the response signal is 00, all other scenarios are data read abnormalities.

[0204] The second abnormality detection circuit 12 is used to determine whether the read data is abnormal based on the received response signal. That is, the 0th bit and the 1st bit of the response signal are input together into an OR gate of the second abnormality detection circuit 12, and when the output result of the OR gate is 1, it indicates that the read data is abnormal; when the output result of the OR gate is 0, it indicates that the read data is not abnormal.

[0205] For the third abnormality detection circuit 13:

[0206] The third exception detection circuit 13 is used to return the exception information output by the atomic operation processing circuit 20 to the input end of the atomic operation processing circuit 20 when the i-th instruction (also called the previous instruction) and the i+1-th instruction (also called this instruction) correspond to the same address. Therefore, a judgment unit is responsible for judging the fwd signal, and when fwd indicates that the i-th instruction and the i+1-th instruction correspond to the same address, the exception information is returned to the input end; when fwd indicates that the i-th instruction and the i+1-th instruction do not correspond to the same address, the exception information is output to the exception processing circuit 30.

[0207] For the exception handling circuit 30:

[0208] The exception handling circuit 30 is used to confirm the exception handling method, including considering the atomic operation result to be an abnormal result (that is, when the electrical signal input to the exception handling circuit is 1) and directly writing the atomic operation result into the storage unit (that is, when the electrical signal input to the exception handling circuit is 0, the atomic operation result can be artificially regarded as a normal result).

[0209] Optionally, even if the original operation result is an abnormal result, the abnormality handling circuit 30 may choose to discard the atomic operation result or write the atomic operation result into a storage unit.

[0210] It should be noted that the circuit structures and connection methods of the first abnormality detection circuit 11, the second abnormality detection circuit 12, the third abnormality detection circuit 13, the atomic operation processing circuit 20 and the abnormality processing circuit 30 in the atomic operation processing unit 120 may also be as follows: Fig.14 That is, the second abnormality detection circuit 12 and the third abnormality detection circuit 13 first pass through a first selection circuit 14, and then the first selection circuit 14 inputs the selected result to an input end of the atomic operation processing circuit 20, instead of inputting the outputs of the second abnormality detection circuit 12 and the third abnormality detection circuit 13 to different input ends of the atomic operation processing circuit 20 respectively.

[0211] Fig.15 A flowchart of an exception detection method provided by an exemplary embodiment of the present application is shown. The method is executed by the atomic operation processing unit provided by each of the above embodiments, and the atomic operation processing unit includes an exception detection circuit, an atomic operation processing circuit and an exception processing circuit; the exception detection circuit is connected to the atomic operation processing circuit; the atomic operation processing circuit is connected to the exception processing circuit. The method includes:

[0212] Step 1: When there is an abnormality in the input data, the abnormality detection circuit outputs the input data and abnormality information to the atomic operation processing circuit.

[0213] In some embodiments, step 1 performs the functions performed by the above-mentioned abnormality detection circuit 10, which will not be repeated here.

[0214] Step 2: The atomic operation processing circuit performs an atomic operation based on the input data to obtain an atomic operation result; and outputs the atomic operation result and exception information to the exception processing circuit.

[0215] In some embodiments, step 2 executes the functions performed by the atomic operation processing circuit 20 described above, which will not be described in detail here.

[0216] Step 3: The exception handling circuit chooses to discard the atomic operation result or write the atomic operation result into a storage unit based on the exception information.

[0217] In some embodiments, step 3 performs the functions performed by the above-mentioned exception handling circuit 30, which will not be described in detail here.

[0218] In different atomic operations, the sources of the corresponding atomic operands are different. For example, the input data (also called atomic operands) can include original data and read data. For some atomic operations, the input data only includes original data; for other atomic operations, the input data may include both original data and read data. Atomic operands from different sources will introduce different exceptions. Therefore, it is necessary to set up exception detection circuits for atomic operands from different sources.

[0219] For example, a first abnormality detection circuit is set for the original data abnormality.

[0220] Optionally, the abnormality detection circuit includes a first abnormality detection circuit.

[0221] Among them, when there is an abnormality in the input data, the exception detection circuit outputs the input data and exception information to the atomic operation processing circuit, including: when the first bit width is different from the second bit width, the first exception detection circuit outputs the original data and the first exception information to the atomic operation processing circuit, the first exception information is used to indicate that the original data is abnormal, the first bit width is the bit width indicated by the atomic operation instruction, and the second bit width is the bit width indicated by the bus that transmits the original data.

[0222] The atomic operation processing circuit outputs the atomic operation result and the exception information to the exception processing circuit, including: the atomic operation processing circuit outputs the atomic operation result and the first exception information to the exception processing circuit.

[0223] The exception handling circuit selects to discard the atomic operation result based on the exception information, or writes the atomic operation result into the storage unit, including: the exception handling circuit selects to discard the atomic operation result based on the first exception information, or writes the atomic operation result into the storage unit.

[0224] In some embodiments, for the scenario of multiple original data, if each original data is transmitted separately in multiple clock cycles, it may cause the processing time of the atomic operation to be too long, thereby reducing the efficiency of the atomic operation. Therefore, the following design can be used to transmit multiple original data in one clock cycle.

[0225] Optionally, the input data includes at least two original data; the at least two original data are transmitted by the bus within one clock cycle; the method also includes: the first abnormality detection unit determines the at least two original data and the second bit width of the at least two original data based on the selection signal.

[0226] Optionally, the selection signal includes multiple indicator bits, the number of bits included in each of the multiple indicator bits is determined based on the bit width of the original data, and each indicator bit is used to indicate that the original data carried by the data bit corresponding to the indicator bit is the first original data or the second original data; the method also includes: the first abnormality detection unit determines the first original data and the second bit width of the first original data based on the indicator bit with the first value; determines the second original data and the second bit width of the second original data based on the indicator bit with the second value.

[0227] Optionally, the indicator bit with the first value is located on a first side of the indicator bit with the second value, and the indicator bit with the first value is adjacent to the indicator bit with the second value.

[0228] Optionally, the atomic operation instruction includes an odd atomic operation instruction and an even atomic operation instruction; when the atomic operation instruction is an odd operation instruction, the indicator bit with the first value is located at an odd bit of the selection signal; when the atomic operation instruction is an even operation instruction, the indicator bit with the first value is located at an even bit of the selection signal.

[0229] A second abnormality detection circuit is provided for read data abnormality.

[0230] Optionally, the abnormality detection circuit includes a second abnormality detection circuit.

[0231] Among them, when there is an abnormality in the input data, the exception detection circuit outputs the input data and exception information to the atomic operation processing circuit, including: when there is an abnormality in the read data, the second exception detection circuit outputs the read data and second exception information to the atomic operation processing circuit, and the second exception information is used to indicate that the read data is abnormal, and the read data is data read from the storage unit based on the atomic operation instruction.

[0232] The atomic operation processing circuit outputs the atomic operation result and the abnormality information to the abnormality processing circuit, including: the atomic operation processing circuit outputs the atomic operation result and the second abnormality information to the abnormality detection circuit.

[0233] The exception handling circuit selects to discard the atomic operation result based on the exception information, or writes the atomic operation result into the storage unit, including: the exception handling circuit selects to discard the atomic operation result based on the second exception information, or writes the atomic operation result into the storage unit.

[0234] A third abnormality detection circuit is provided for abnormalities in a plurality of consecutive instructions with the same address.

[0235] Optionally, the exception detection circuit includes: a third exception detection circuit arranged on the same address processing path; the same address processing path is used to connect the output end and the second input end of the atomic operation processing circuit; the i-th instruction is one of the n atomic operation instructions received by the atomic operation processing circuit, and i is not equal to 1 or n, n is an integer greater than 1, and the n atomic operation instructions correspond to the same write address.

[0236] Among them, when there is an exception in the input data, the exception detection circuit outputs the input data and exception information to the atomic operation processing circuit, including: the atomic operation processing circuit performs an atomic operation based on the i-1th atomic operation result and the i-th instruction to obtain the i-th atomic operation result, and the i-1th atomic operation result is obtained by performing an atomic operation based on the first i-1 instructions among n atomic operation instructions.

[0237] The atomic operation processing circuit outputs the atomic operation result and exception information to the exception processing circuit, including: when the i-th atomic operation result carries exception information, the third exception detection circuit outputs the i-th atomic operation result and exception information to the second input end through the same address processing path.

[0238] Optionally, the abnormality detection circuit includes: a third abnormality detection circuit arranged on the same address processing path; the same address processing path is used to connect the output end and the second input end of the atomic operation processing circuit; the nth instruction is the last one of the n atomic operation instructions received by the atomic operation processing circuit, n is a positive integer, and the n atomic operation instructions correspond to the same write address;

[0239] The atomic operation processing circuit outputs the atomic operation result and exception information through the output end, including: the atomic operation processing circuit performs an atomic operation based on the n-1th atomic operation result and the nth instruction to obtain the nth atomic operation result, and the n-1th atomic operation result is obtained by performing an atomic operation based on the first n-1 instructions among the n instructions.

[0240] The exception handling circuit chooses to discard the atomic operation result or write the atomic operation result into a storage unit based on the exception information, including: when the nth atomic operation result carries the exception information, the exception handling circuit chooses to discard the nth atomic operation result or write the nth atomic operation result into a storage unit.

[0241] Optionally, the atomic operation processing unit also includes an exception reporting unit connected to the exception detection circuit; the method also includes: the exception reporting unit reports exception information to the processor. In summary, the method provided in the embodiment of the present application adds an exception detection circuit and an exception handling circuit in the atomic operation processing unit to implement exception detection and exception handling during the atomic operation process, thereby improving the reliability of the atomic operation, and then improving the reliability of the processor in executing the atomic operation, thereby avoiding operation errors of the processor caused by abnormalities in the results of the atomic operation. Generally speaking, if an operation error occurs in the processor due to an abnormality in the result of the atomic operation, the processor will need to re-execute the corresponding operation or check the cause of the error for the recently executed instructions, which will slow down the operation efficiency of the processor. Therefore, the unit can also indirectly improve the operation efficiency of the processor.

[0242] Fig.16 and Fig.17 The computer system architecture diagram provided by an exemplary embodiment of the present application is shown. The computer system includes a processor 100 and a storage unit 200.

[0243] The processor 100 includes an atomic operation processing unit 120. The atomic operation processing unit 120 is used to perform atomic operations based on atomic operation instructions.

[0244] Optionally, the processor 100 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 100 may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field Programmable Gate Array), or a PLA (Programmable Logic Array). The processor 100 may be a CPU (Central Processing Unit). In some embodiments, the processor 100 may be a GPU (Graphics Processing Unit). In other embodiments, the processor 100 may also be an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning. The embodiment of the present application is described by taking the processor 100 as a GPU as an example.

[0245] In the case where the processor includes a plurality of cores, each of the plurality of cores or a portion of the cores may include an atomic operation processing unit 120 .

[0246] The storage unit 200 is used to store instructions and data, and is also used to provide input data to the atomic operation processing unit 120 in the processor 100 .

[0247] In some embodiments, Fig.16 As shown, the processor 100 and the storage unit 200 are directly connected.

[0248] In other embodiments, Fig.17 As shown, the processor 100 and the storage unit 200 are connected via a bus 300 .

[0249] In some other embodiments, the processor 100 and the storage unit 200 are connected via a network on chip (NoC).

[0250] On the other hand, an embodiment of the present application provides an atomic operation processing unit, the atomic operation processing unit comprising an exception detection circuit, an atomic operation processing circuit and an exception processing circuit; the exception detection circuit is connected to the atomic operation processing circuit; the atomic operation processing circuit is connected to the exception processing circuit. Exemplarily, the atomic operation processing unit is as follows: Figure 1 shown.

[0251] On the other hand, an embodiment of the present application provides a graphics card, which includes the atomic operation processing unit described in the above embodiments.

[0252] On the other hand, an embodiment of the present application provides a computer device, the computer device comprising the atomic operation processing unit as described above. Optionally, the processor is a GPU. The computer device may be at least one of a portable computer, a desktop computer, a server, a server cluster, an artificial intelligence (AI) computing cluster, and a cloud computing cluster. Among them, the AI ​​computing cluster may also be referred to as an intelligent computing cluster or a smart computing cluster.

[0253] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application are not limited to this.

[0254] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An atomic operation processing unit, characterized in that: The atomic operation processing unit comprises an abnormality detection circuit, an atomic operation processing circuit and an abnormality processing circuit; the abnormality detection circuit is connected to the atomic operation processing circuit; the atomic operation processing circuit is connected to the abnormality processing circuit; The anomaly detection circuit is used to output the input data and anomaly information to the atomic operation processing circuit when an anomaly exists in the input data; The atomic operation processing circuit is used to perform an atomic operation based on the input data to obtain an atomic operation result; and output the atomic operation result and the exception information to the exception processing circuit; The exception processing circuit is used to select to discard the atomic operation result or write the atomic operation result into a storage unit based on the exception information.

2. The unit according to claim 1, characterized in that The abnormality detection circuit includes a first abnormality detection circuit; The first abnormality detection circuit includes an original data input terminal and an original data output terminal; the original data output terminal is connected to the first input terminal of the atomic operation processing circuit.

3. The unit according to claim 2, characterized in that The first exception detection circuit is used to output the original data and first exception information to the atomic operation processing circuit when the first bit width is different from the second bit width, the first exception information is used to indicate that the original data is abnormal, the first bit width is the bit width indicated by the atomic operation instruction, and the second bit width is the bit width indicated by the bus transmitting the original data; The atomic operation processing circuit is further configured to output the atomic operation result and the first exception information to the exception processing circuit; The exception handling circuit is further used to select to discard the atomic operation result or write the atomic operation result into a storage unit based on the first exception information.

4. The unit according to claim 3, characterized in that The input data includes at least two original data; the at least two original data are transmitted by the bus within one clock cycle; The first abnormality detection unit is further configured to determine the at least two original data and a second bit width of the at least two original data based on a selection signal.

5. The unit according to claim 4, characterized in that The selection signal includes a plurality of indicator bits, the number of bits included in each of the plurality of indicator bits is determined based on the bit width of the original data, and each indicator bit is used to indicate whether the original data carried by the data bit corresponding to the indicator bit is the first original data or the second original data; The first abnormality detection unit is further used to determine the first original data and a second bit width of the first original data based on the indicator bit having a first value; The second original data and a second bit width of the second original data are determined based on the indicator bit having a second value.

6. The unit according to claim 5, characterized in that In the selection signal, the indication bit having the first value is located on a first side of the indication bit having the second value, and the indication bit having the first value is adjacent to the indication bit having the second value.

7. The unit according to claim 5, characterized in that The atomic operation instructions include odd-numbered atomic operation instructions and even-numbered atomic operation instructions; In the case where the atomic operation instruction is the odd-numbered operation instruction, the indication bit having the first value is located at an odd-numbered bit of the selection signal; When the atomic operation instruction is the even-numbered operation instruction, the indication bit having the first value is located at an even-numbered bit of the selection signal.

8. The unit according to claim 1, characterized in that The abnormality detection circuit includes a second abnormality detection circuit; The second abnormality detection circuit includes a read data input terminal and a read data output terminal; the read data output terminal is connected to the second input terminal of the atomic operation processing circuit.

9. The unit according to claim 8, characterized in that The second abnormality detection circuit is used to output the read data and second abnormality information to the atomic operation processing circuit when the read data is abnormal, wherein the second abnormality information is used to indicate that the read data is abnormal, and the read data is data read from the storage unit based on the atomic operation instruction; The atomic operation processing circuit is further configured to output the atomic operation result and the second exception information to the exception processing circuit; The exception handling circuit is further used to select to discard the atomic operation result or write the atomic operation result into a storage unit based on the second exception information.

10. The unit according to any one of claims 1 to 9, characterized in that The abnormality detection circuit comprises: a third abnormality detection circuit arranged on the same address processing path; the same address processing path is used to connect the output end and the second input end of the atomic operation processing circuit; The third abnormality detection circuit includes a processing result input terminal and a processing result output terminal; the processing result input terminal is connected to the output terminal through the same address processing path, and the processing result output terminal is connected to the second input terminal through the same address processing path.

11. The unit according to claim 10, characterized in that The i-th instruction is one of n atomic operation instructions received by the atomic operation processing circuit, and i is not equal to 1 or n, n is an integer greater than 1, and the n atomic operation instructions correspond to the same write address; The atomic operation processing circuit is further used to perform an atomic operation based on the i-1th atomic operation result and the i-th instruction to obtain an i-th atomic operation result, wherein the i-1th atomic operation result is obtained by performing an atomic operation based on the first i-1 instructions among the n atomic operation instructions; The third exception detection circuit is used to output the i-th atomic operation result and the exception information to the second input end through the same address processing path when the i-th atomic operation result carries the exception information.

12. The unit according to claim 10, characterized in that The nth instruction is the last one of the n atomic operation instructions received by the atomic operation processing circuit, n is a positive integer, and the n atomic operation instructions correspond to the same write address; The atomic operation processing circuit is further used to perform an atomic operation based on the n-1th atomic operation result and the n-1th instruction to obtain an n-th atomic operation result, wherein the n-1th atomic operation result is obtained by performing an atomic operation based on the first n-1 instructions among the n instructions; The exception handling circuit is further used to select to discard the nth atomic operation result or write the nth atomic operation result into a storage unit when the nth atomic operation result carries the exception information.

13. A unit according to any one of claims 1 to 9, characterized in that The atomic operation processing unit also includes an abnormality reporting unit connected to the abnormality detection circuit; The exception reporting unit is used to report the exception information to the processor.

14. An anomaly detection method, characterized in that: The method is performed by an atomic operation processing unit, which includes an exception detection circuit, an atomic operation processing circuit and an exception processing circuit; The abnormality detection circuit is connected to the atomic operation processing circuit; The atomic operation processing circuit is connected to the exception processing circuit; The method comprises: When the input data is abnormal, the abnormality detection circuit outputs the input data and abnormality information to the atomic operation processing circuit; The atomic operation processing circuit performs an atomic operation based on the input data to obtain an atomic operation result; and outputs the atomic operation result and the exception information to the exception processing circuit; The exception handling circuit selects to discard the atomic operation result or write the atomic operation result into a storage unit based on the exception information.

15. An atomic operation processing unit, characterized in that: The atomic operation processing unit includes an exception detection circuit, an atomic operation processing circuit and an exception processing circuit; The abnormality detection circuit is connected to the atomic operation processing circuit; the atomic operation processing circuit is connected to the abnormality processing circuit.

16. A graphics card, characterized in that: The graphics card comprises the atomic operation processing unit as described in any one of claims 1 to 13, or the atomic operation processing unit as described in claim 15.

17. A computer device, characterized in that: The computer device comprises the atomic operation processing unit as described in any one of claims 1 to 13, or the atomic operation processing unit as described in claim 15.

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