Data transmission method and device based on Type-C

Abstract

The invention discloses a Type-C-based data transmission method and device, and the method comprises the steps: starting a power supply channel in response to an access signal of a male interface, and transmitting a verification request to the male interface through a first verification module, so as to enable the male interface to transmit verification data; if the first verification module receives the verification data within a preset time, matching the verification data with preset standard data, and if the matching is successful, starting a data transmission channel and a debugging communication channel; performing data transmission with the male interface based on the data transmission channel; and performing debugging analysis based on the debugging communication channel and the male interface. According to the invention, the functions of power supply, high-speed data transmission and encryption debugging communication can be simultaneously realized based on one Type-C interface, and the security of data transmission is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a data transmission method and device based on Type-C. Background Art

[0002] Type-C is a universal serial bus (USB) hardware interface that can effectively replace existing USB interface types to provide faster and more efficient charging and data transmission solutions. In the field of embedded development, each Type-C interface is only used as a single function such as power supply interface, data transmission interface and debug information interface. Therefore, in embedded devices, it is often necessary to design three or more circuits to realize the functions of power supply, data transmission and debug respectively.

[0003] For the power supply circuit based on Type-C, it only needs to be powered by USB, so all lines related to data transmission are deleted, and only VBUS, GND, CC1 and CC2 lines are retained in the circuit. Figure 1 and Figure 2 As shown, Figure 1 A data transmission circuit based on Type-C is designed, which deletes the following Figure 2 The TX1 / 2 and RX1 / 2 ports of USB3.0 shown in the figure retain the VBUS, DP and DN of Type-C as the relevant interfaces of USB2.0 to realize data transmission, such as firmware download and burning, communication, etc. Figure 3 As shown, Figure 3 A debug serial port circuit based on Type-C is designed in this paper. It does not have the ability of power supply and data transmission, and only serves as a serial port device to realize the output and input of information.

[0004] It can be seen that the circuits based on Type-C to realize power supply, data transmission and debug functions are not unified. Therefore, three wiring harnesses need to be connected to the embedded device at the same time to realize the corresponding functions. In addition, the above communication method cannot guarantee the security of data. Ordinary users can obtain debugging information through the ordinary serial port at any time to access the underlying data of the system. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a data transmission method and device based on Type-C, which can realize power supply, data transmission and serial port debugging functions on the same interface and ensure the security of data transmission.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A data transmission method based on Type-C, comprising:

[0008] In response to an access signal of the male interface, the power supply channel is started, and a first verification module sends a verification request to the male interface so that the male interface sends verification data;

[0009] If the first verification module receives the verification data within a preset time, the verification data is matched with the preset standard data, and if the match is successful, the data transmission channel and the debugging communication channel are started;

[0010] Performing data transmission based on the data transmission channel and the male interface;

[0011] Debug analysis is performed based on the debug communication channel and the male interface.

[0012] In order to solve the above technical problems, another technical solution adopted by the present invention is:

[0013] A data transmission device based on Type-C, comprising a first interface unit and a second interface unit;

[0014] The first interface unit includes a processor, a power management chip, a power supply circuit, a debugging communication circuit, a data transmission circuit and a Type-C female interface, and the debugging communication circuit is provided with a first verification module;

[0015] The first data terminal of the processor is connected to the input control terminal of the power management chip, the output control terminal of the power management chip is connected to one end of the power supply circuit, and the other end of the power supply circuit is connected to the power supply pin of the Type-C female connector;

[0016] The second data terminal of the processor is connected to one end of the data transmission circuit, and the other end of the data transmission circuit is connected to the data pin of the Type-C female connector;

[0017] The third data terminal of the processor is connected to one end of the debug communication circuit, and the other end of the debug communication circuit is connected to the power supply pin and the configuration pin of the Type-C female interface;

[0018] The second interface unit includes a Type-C male interface;

[0019] The processor is configured to execute each step in the above-mentioned Type-C-based data transmission method.

[0020] The beneficial effect of the present invention is that when the male interface is connected to the female interface, the female interface directly starts the power supply channel to realize the power supply function of the device. At the same time, because the female interface starts the power supply channel to power on the first verification module, the female interface can send a verification request to the male interface by the first verification module at this time so that the male interface sends verification data. If the male interface returns the verification data within the preset time, and the verification data successfully matches the standard data, the data transmission channel and the debugging communication channel are started in this way to prevent the access of illegal devices or incorrect data transmission, thereby ensuring data security. In addition, the present invention integrates the power supply channel, the data transmission channel and the debugging communication channel in the female interface at the same time, realizes multiple functions in one interface, effectively simplifies the interface circuit of the device, and reduces the production cost of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A circuit schematic diagram of a data transmission circuit based on Type-C in the prior art;

[0022] Figure 2 The TX1 / 2 and RX1 / 2 ports in the Type-C interface of the prior art are used for USB3.0 transmission;

[0023] Figure 3 It is a circuit schematic diagram of a debug serial port circuit based on Type-C in the prior art;

[0024] Figure 4 A flow chart of a data transmission method based on Type-C provided by an embodiment of the present invention;

[0025] Figure 5 A structural block diagram of a Type-C based data transmission device provided in an embodiment of the present invention;

[0026] Figure 6 A circuit schematic diagram of a data transmission circuit provided by an embodiment of the present invention;

[0027] Figure 7 A circuit schematic diagram of a debugging communication circuit provided by an embodiment of the present invention;

[0028] Figure 8 An internal structure diagram of a first verification module provided by an embodiment of the present invention;

[0029] Fig. 9 A structural block diagram of another Type-C-based data transmission device provided in an embodiment of the present invention;

[0030] Fig.10 A structural block diagram of another data transmission device based on Type-C provided in an embodiment of the present invention;

[0031] Fig.11 A circuit schematic diagram of a first interface unit provided by an embodiment of the present invention;

[0032] Description of labels:

[0033] 100. A data transmission device based on Type-C; 101. A first interface unit; 102. A second interface unit; 1011. A processor; 1012. A power management chip; 1013. A power supply circuit; 1014. A debugging communication circuit; 1015. A data transmission circuit; 1016. A Type-C female interface; 1021. A Type-C male interface; 1022. A Type-A interface; 1023. A serial communication module. DETAILED DESCRIPTION

[0034] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.

[0035] An embodiment of the present invention provides a data transmission method based on Type-C, including:

[0036] In response to an access signal of the male interface, the power supply channel is started, and a first verification module sends a verification request to the male interface so that the male interface sends verification data;

[0037] If the first verification module receives the verification data within a preset time, the verification data is matched with the preset standard data, and if the match is successful, the data transmission channel and the debugging communication channel are started;

[0038] Performing data transmission based on the data transmission channel and the male interface;

[0039] Debug analysis is performed based on the debug communication channel and the male interface.

[0040] From the above description, it can be seen that the beneficial effect of the present invention is that when the male interface is connected to the female interface, the female interface directly starts the power supply channel to realize the power supply function of the device. At the same time, because the female interface starts the power supply channel to power on the first verification module, the female interface can send a verification request to the male interface by the first verification module at this time so that the male interface sends verification data. If the male interface returns the verification data within the preset time, and the verification data successfully matches the standard data, the data transmission channel and the debugging communication channel are started in this way to prevent the access of illegal devices or incorrect data transmission, thereby ensuring data security. In addition, the present invention integrates the power supply channel, the data transmission channel and the debugging communication channel in the female interface at the same time, realizes multiple functions in one interface, effectively simplifies the interface circuit of the device, and reduces the production cost of the device.

[0041] Further, the sending of a verification request by the first verification module to the male interface so that the male interface sends verification data includes:

[0042] If the male interface is provided with a second verification module, the first verification module sends a verification request to the second verification module, so that the second verification module sends verification data.

[0043] From the above description, it can be seen that when the male interface is provided with a second verification module, it indicates that the male interface uses a dedicated wiring harness to connect to the female interface. Therefore, the corresponding verification data has been solidified in the second verification module of the male interface at this time. Therefore, the first verification module can directly obtain the verification data from the second verification module for subsequent verification and matching, thereby improving data security.

[0044] Further, the sending of a verification request by the first verification module to the male interface so that the male interface sends verification data includes:

[0045] If the male interface is not provided with a second verification module, the first verification module sends a verification request to a host computer connected to the male interface, so that the host computer sends verification data generated based on the device serial number.

[0046] From the above description, it can be seen that when the male interface is not provided with the second verification module, it indicates that the male interface is not connected to the female interface using a dedicated wiring harness, so at this time, the host computer receives the device serial number written by the user to generate verification data, and sends it to the first verification module after receiving the verification request sent by the first verification module. In this way, the compatibility between different wiring harnesses and the female interface and the host computer can be improved, thereby improving efficient and reliable communication and debugging functions.

[0047] Furthermore, if the male interface is provided with a second verification module, before the first verification module sends a verification request to the second verification module, it also includes:

[0048] The host computer connected to the male interface detects whether verification data is preset in the second verification module. If verification data is not preset, the host computer generates verification data according to the acquired device serial number and writes the verification data into the second verification module.

[0049] It can be seen from the above description that the verification data in the second verification module can be updated by the host computer, thereby improving the compatibility of the male interface with different devices.

[0050] Further, the data transmission based on the data transmission channel and the male interface includes:

[0051] Detecting the connection status and signal status of each data pin under the data transmission channel;

[0052] Switching the data transmission mode of the data transmission channel according to the connection state and signal state of each data pin, wherein the data transmission mode includes a high-speed transmission mode and a low-speed transmission mode;

[0053] The target data in the preset data partition is read and written based on the data transmission mode, and data transmission is performed with the male interface.

[0054] From the above description, it can be seen that by detecting the connection status and signal status of each data pin, the most suitable data transmission mode can be selected according to the actual connection status and signal stability, thereby enhancing the compatibility and stability of device data transmission and improving the user experience.

[0055] Another embodiment of the present invention provides a Type-C-based data transmission device, including a first interface unit and a second interface unit;

[0056] The first interface unit includes a processor, a power management chip, a power supply circuit, a debugging communication circuit, a data transmission circuit and a Type-C female interface, and the debugging communication circuit is provided with a first verification module;

[0057] The first data terminal of the processor is connected to the input control terminal of the power management chip, the output control terminal of the power management chip is connected to one end of the power supply circuit, and the other end of the power supply circuit is connected to the power supply pin of the Type-C female connector;

[0058] The second data terminal of the processor is connected to one end of the data transmission circuit, and the other end of the data transmission circuit is connected to the data pin of the Type-C female connector;

[0059] The third data terminal of the processor is connected to one end of the debug communication circuit, and the other end of the debug communication circuit is connected to the power supply pin and the configuration pin of the Type-C female interface;

[0060] The second interface unit includes a Type-C male interface;

[0061] The processor is configured to execute each step in the above-mentioned Type-C-based data transmission method.

[0062] From the above description, it can be seen that the beneficial effect of the present invention is that when the male interface is connected to the female interface, the female interface directly starts the power supply channel to realize the power supply function of the device. At the same time, because the female interface starts the power supply channel to power on the first verification module, the female interface can send a verification request to the male interface by the first verification module at this time so that the male interface sends verification data. If the male interface returns the verification data within the preset time, and the verification data successfully matches the standard data, the data transmission channel and the debugging communication channel are started in this way to prevent the access of illegal devices or incorrect data transmission, thereby ensuring data security. In addition, the present invention integrates the power supply channel, the data transmission channel and the debugging communication channel in the female interface at the same time, realizes multiple functions in one interface, effectively simplifies the interface circuit of the device, and reduces the production cost of the device.

[0063] Furthermore, the data pins of the Type-C female interface include two groups of high-speed differential signal pairs and one group of low-speed differential signal pairs;

[0064] The second data end of the processor is respectively connected to the two groups of high-speed differential signal pairs and the group of low-speed differential signal pairs; the processor implements a high-speed transmission mode based on the two groups of high-speed differential signal pairs, and the processor implements a low-speed transmission mode based on the group of low-speed differential signal pairs.

[0065] From the above description, it can be seen that by detecting the connection status and signal status of each data pin, the most suitable data transmission mode can be selected according to the actual connection status and signal stability, thereby enhancing the compatibility and stability of device data transmission and improving the user experience.

[0066] Further, the configuration pins of the Type-C female interface include a CC pin and an SBU pin;

[0067] The verification power supply end of the first verification module is connected to the power supply pin of the Type-C female connector;

[0068] The communication data terminal of the first verification module is connected to the third data terminal of the processor;

[0069] The verification control end of the first verification module is respectively connected to the CC pin and the SBU pin of the Type-C female connector;

[0070] The verification control terminal of the first verification module and the communication data terminal of the first verification module are connected in a strobe manner.

[0071] From the above description, it can be seen that if the male interface returns the verification data within the preset time and the verification data matches the standard data successfully, the first verification module selects the third data terminal connecting the processor and the CC pin and SBU pin of the Type-C female interface, thereby turning on the debugging communication circuit, and then starting the data transmission circuit through the processor, thereby preventing illegal equipment from accessing or incorrect data transmission, thereby ensuring data security.

[0072] Furthermore, the second interface unit further includes a second verification module and a Type-A interface;

[0073] The Type-C male interface is respectively connected to the communication data end of the second verification module and the first data end of the Type-A interface;

[0074] The check control terminal of the second check module is connected to the second data terminal of the Type-A interface.

[0075] From the above description, it can be seen that the second verification module is set in the second interface unit, so the first verification module can directly obtain the verification data from the second verification module for subsequent verification matching, thereby improving the connection efficiency while ensuring data security.

[0076] Furthermore, the second interface unit also includes a serial communication module;

[0077] The verification control end of the second verification module is connected to one end of the serial communication module, and the other end of the serial communication module is connected to the second data end of the Type-A interface.

[0078] It can be seen from the above description that a serial communication module is provided in the second interface unit to provide debugging capability.

[0079] The embodiment of the present invention provides a data transmission method and device based on Type-C, which can be applied to embedded devices, realizes power supply, high-speed data transmission and encrypted debugging communication functions based on a Type-C interface, and ensures the security of data transmission. The following is an explanation through specific embodiments:

[0080] Please refer to Figure 4 , Embodiment 1 of the present invention is:

[0081] A data transmission method based on Type-C, comprising:

[0082] S1. In response to an access signal of a male interface, a power supply channel is started, and a first verification module sends a verification request to the male interface so that the male interface sends verification data.

[0083] In some embodiments, when the male interface is connected to the female interface of the device, the female interface of the device starts the power supply channel, thereby powering the first verification module in the female interface. After the first verification module is powered, the first verification module sends a verification request to the male interface so that the male interface sends verification data to the female interface. In this way, the first verification module is started to perform verification negotiation on the male interface.

[0084] In an optional implementation, in step S1, the first verification module sending a verification request to the male interface so that the male interface sends verification data includes:

[0085] S11a. If the male interface is provided with a second verification module, the first verification module sends a verification request to the second verification module, so that the second verification module sends verification data.

[0086] In some embodiments, when the male interface is connected to the communication port of the host computer, the host computer will determine the wiring harness type of the male interface by detecting the access signal of the male interface, wherein the wiring harness type of the male interface includes a first wiring harness type provided with a second verification module and a second wiring harness type not provided with the second verification module. That is, if it is determined that the wiring harness type of the current male interface is the first wiring harness type, it is determined that the male interface is provided with the second verification module, and if it is determined that the wiring harness type of the current male interface is the second wiring harness type, it is determined that the male interface is not provided with the second verification module.

[0087] In some embodiments, if the male interface is provided with a second verification module, the operator may solidify the verification data in the second verification module.

[0088] In some embodiments, the verification data is a characteristic code calculated based on the device serial number of the device.

[0089] In an optional implementation, if the male interface is provided with a second verification module, before the first verification module sends a verification request to the second verification module, the method further includes:

[0090] S10a, the host computer connected to the male interface detects whether verification data is pre-installed in the second verification module. If verification data is not pre-installed, the host computer generates verification data according to the acquired device serial number and writes the verification data into the second verification module.

[0091] In an optional implementation, in step S1, the first verification module sending a verification request to the male interface so that the male interface sends verification data includes:

[0092] S11b. If the male interface is not provided with a second verification module, the first verification module sends a verification request to a host computer connected to the male interface, so that the host computer sends verification data generated based on the device serial number.

[0093] In some embodiments, the first verification module and the second verification module are CC chips.

[0094] S2. If the first verification module receives the verification data within a preset time, the verification data is matched with preset standard data. If the match is successful, the data transmission channel and the debugging communication channel are started.

[0095] In some embodiments, the standard data is also a feature code calculated based on the device serial number of the device end, and the standard data is preset in advance and solidified in the first verification module of the female connector.

[0096] In some embodiments, after the first verification module sends a verification request to the male interface, the second verification module or the host computer needs to respond to the verification request within 2 milliseconds to send the verification data to the first verification module. The entire response process needs to be completed in a very short time to ensure the rapid response of the device and the accurate matching of the feature code. In this way, the device end and the host end can quickly establish a communication path to ensure that the next debugging operation can be quickly performed after the match is successful. This ensures the real-time nature of the entire verification process.

[0097] In some embodiments, the verification data is matched with the standard data. If the match fails, the current number of matching failures is accumulated and the match is retried. If the number of matching failures reaches a preset maximum number, the current male interface is permanently disconnected until the next time the male interface is reconnected.

[0098] In some embodiments, when the verification data successfully matches the standard data, the first verification module controls the switching of the hardware switch based on a matching success signal, thereby starting the data transmission channel and the debugging communication channel.

[0099] It can be seen from this that if the second verification data is not solidified in the male interface, the upper computer connected to the male interface will first request to connect to the target server according to the device serial number of the device end being debugged, so as to obtain the encrypted information, that is, the verification data, and write it into the CC chip in the male interface. When the male interface is connected to the female interface, the power supply channel is started, thereby starting the system of the device end. At this time, the female interface sends a verification request to the male interface by the first verification module so that the male interface sends the verification data. Since the verification data is generated using the device serial number, only the allowed device end can be decrypted at the bottom layer. Therefore, only after the verification data matches successfully, the data transmission channel and the debugging communication channel can be started to ensure data security. In this way, the male interface can repeatedly debug multiple device ends. At the same time, if the verification data fails to match, the data transmission channel and the debugging communication channel will not be started, but the power supply channel will not be affected. At this time, the device end can still start normally.

[0100] S3. Perform data transmission based on the data transmission channel and the male interface.

[0101] Specifically, step S3 includes:

[0102] S31, detecting the connection state and signal state of each data pin in the data transmission channel.

[0103] S32, switching the data transmission mode of the data transmission channel according to the connection state and signal state of each data pin, wherein the data transmission mode includes a high-speed transmission mode and a low-speed transmission mode.

[0104] In some embodiments, the processor of the female interface automatically detects the connection status of each data pin in the data transmission channel, and sets the most suitable data transmission mode according to the successfully connected data pin.

[0105] In some embodiments, the signal state of the successfully connected data pin is detected to evaluate the signal stability of the current data pin. During the evaluation process, the processor of the female interface will give priority to the data transmission mode with stable signal to ensure the reliability of data transmission and communication stability.

[0106] S33, reading and writing target data in the preset data partition based on the data transmission mode, and performing data transmission with the male interface.

[0107] In some embodiments, after the first verification module starts the data transmission channel, the processor of the female interface is powered on and the above steps S31 to S33 are completed within 50 milliseconds after power-on to ensure fast selection of the data transmission mode.

[0108] S4. Perform debugging analysis based on the debugging communication channel and the male interface.

[0109] Please refer to Figures 5 to 11 , Embodiment 2 of the present invention is:

[0110] like Figure 5 As shown, a data transmission device 100 based on Type-C includes a first interface unit 101 and a second interface unit 102. Specifically, the first interface unit 101 includes a processor 1011, a power management chip 1012, a power supply circuit 1013, a debugging communication circuit 1014, a data transmission circuit 1015 and a Type-C female interface 1016, and the debugging communication circuit 1014 is provided with a first verification module U1; the first data end of the processor 1011 is connected to the input control end of the power management chip 1012, the output control end of the power management chip 1012 is connected to one end of the power supply circuit 1013, and the other end of the power supply circuit 1013 is connected to the power supply pin of the Type-C female interface 1016; the processor The second data end of 1011 is connected to one end of the data transmission circuit 1015, and the other end of the data transmission circuit 1015 is connected to the data pin of the Type-C female interface 1016; the third data end of the processor 1011 is connected to one end of the debug communication circuit 1014, and the other end of the debug communication circuit 1014 is connected to the power supply pin and configuration pin of the Type-C female interface 1016; the second interface unit 102 includes a Type-C male interface 1021; the processor 1011 is configured to execute each step in a Type-C-based data transmission method as described in Example 1.

[0111] It should be noted that the present invention is implemented based on a full-function 24-pin Type-C interface. In the Type-C interface, the power supply function, the data transmission function with compatibility, and the debugging communication function with security verification are realized by multiplexing the CC pin and the SBU pin, and the three functions can be integrated into one Type-C interface. Among them, the power supply circuit 1013 is the power supply channel of the above-mentioned embodiment 1, and the power management chip 1012 is used to start, shut down and manage the power supply circuit 1013; the debugging communication circuit 1014 is the debugging communication channel of the above-mentioned embodiment 1, and the security verification is realized based on the first verification module in the debugging communication circuit 1014; the data transmission circuit 1015 is the data transmission channel of the above-mentioned embodiment 1, which is compatible with the high-speed transmission mode and the low-speed transmission mode. A specific connection method between the processor 1011, the debugging communication circuit 1014, the data transmission circuit 1015 and the Type-C female interface 1016 is given below.

[0112] like Figure 6As shown, the data pins of the Type-C female interface 1016 include two groups of high-speed differential signal pairs and one group of low-speed differential signal pairs. Specifically, the second data end of the processor 1011 is connected to the two groups of high-speed differential signal pairs and the one group of low-speed differential signal pairs respectively; the processor 1011 implements a high-speed transmission mode based on the two groups of high-speed differential signal pairs, and the processor 1011 implements a low-speed transmission mode based on the one group of low-speed differential signal pairs.

[0113] In some embodiments, the high-speed transmission mode is the USB 3.0 transmission mode, and the low-speed transmission mode is the USB 2.0 transmission mode.

[0114] In some embodiments, the Type-C female interface 1016 uses a connector with the model TYPE-C 24P QCHT, where 24P represents 24 pins. The Type-C female interface 1016 includes two groups of high-speed differential signal pairs and one group of low-speed differential signal pairs, wherein the two groups of high-speed differential signal pairs are RX1 / TX1 signals and RX2 / TX2 signals respectively; one group of low-speed differential signal pairs is D+ / D- signals. Specifically, when the two groups of high-speed differential signal pairs of the Type-C female interface 1016 are successfully connected to the corresponding pins of the Type-C male interface, the processor 1011 switches the current data transmission mode to the USB3.0 transmission mode. When only one group of low-speed differential signal pairs of the Type-C female interface is successfully connected to the corresponding pins of the Type-C male interface, the processor 1011 switches the current data transmission mode to the USB2.0 transmission mode.

[0115] In some embodiments, Figure 6 As shown, when the processor 1011 switches the current data transmission mode to the USB3.0 transmission mode, in the Type-C female interface 1016, TX1 and TX2 in the two groups of high-speed differential signal pairs are respectively connected to the USB3.0_OTG0_SSRXN signal and the USB3.0_OTG0_SSRXP signal in the second data end of the processor 1011, RX1 and RX2 in the two groups of high-speed differential signal pairs are respectively connected to the USB3.0_OTG0_SSTXN signal and the USB3.0_OTG0_SSTXP signal in the second data end of the processor 1011, the D+ in the low-speed differential signal pair is connected to the USB3.0_OTG0_DM signal in the second data end of the processor 1011, and the D- in the low-speed differential signal pair is connected to the USB3.0_OTG0_DP signal in the second data end of the processor 1011.

[0116] like Figure 7As shown, the configuration pins of the Type-C female interface 1016 include a CC pin and an SBU pin. Specifically, the check power supply end of the first check module U1 is connected to the power supply pin of the Type-C female interface 1016; the communication data end of the first check module U1 is connected to the third data end of the processor 1011; the check control end of the first check module U1 is respectively connected to the CC pin and the SBU pin of the Type-C female interface 1016; the check control end of the first check module U1 and the communication data end of the first check module U1 are connected in a strobe connection.

[0117] In some embodiments, Figure 7 As shown, the verification power supply end of the first verification module U1 includes an IN1 pin, the communication data end of the first verification module U1 includes a D0 pin, a D1 pin, a VSNS pin, and an ILIM pin, and the verification control end of the first verification module U1 includes an OUT pin and an IN2 pin. The IN1 pin in the first verification module U1 is connected to the power supply pin VBUS of the Type-C female interface 1016, the D0 pin in the first verification module U1 is connected to the UART_TX signal in the third data end of the processor 1011, the D1 pin in the first verification module U1 is connected to the UART_RX signal in the third data end of the processor 1011, the VSNS pin in the first verification module U1 is connected to the DATA_RX signal in the third data end of the processor 1011, the ILIM pin in the first verification module U1 is connected to the DATA_TX signal in the third data end of the processor 1011, the OUT pin in the first verification module U1 is connected to the CC pin of the Type-C female interface 1016, and the IN2 pin in the first verification module U1 is connected to the SBU pin of the Type-C female interface.

[0118] In some embodiments, Figure 8As shown, the first verification module U1 is a gating chip. When the gating switch 2 of the first verification module U1 is closed at 3, the OUT pin and IN2 pin of the first verification module U1 can send and receive verification data to the Type-C male interface 1021 through the SCL pin and SDA pin inside it. When the first verification module U1 successfully matches based on the verification data, the first verification module U1 controls the gating switch 2 to close at 1, so that the OUT pin of the first verification module U1 is connected to the D1 pin of the processor 1011, and the IN2 pin of the first verification module U1 is connected to the D0 pin of the processor 1011, thereby connecting the CC pin of the Type-C female interface 1016 to the UART_TX signal of the processor 1011, and connecting the SBU pin of the Type-C female interface 1016 to the UART_RX signal of the processor 1011, thereby starting the debugging communication circuit 1014. At the same time, the chip enables the VSNS pin and the ILIM pin, so that the VSNS pin starts the DATA_RX signal and the ILIM pin starts the DATA_TX signal, thereby starting the data transmission circuit.

[0119] In some embodiments, the first verification module U1 may store a 64-bit feature code inside, and the feature code is fixed inside at the factory for subsequent communication verification.

[0120] like Fig. 9 As shown, the second interface unit 102 also includes a second verification module U2 and a Type-A interface 1022. Specifically, the Type-C male interface 1021 is connected to the communication data end of the second verification module U2 and the first data end of the Type-A interface 1022 respectively; the verification control end of the second verification module U2 is connected to the second data end of the Type-A interface 1022.

[0121] like Fig.10 As shown, the second interface unit 102 further includes a serial communication module 1023. Specifically, the verification control end of the second verification module U2 is connected to one end of the serial communication module 1023, and the other end of the serial communication module 1023 is connected to the second data end of the Type-A interface 1022.

[0122] like Fig.11As shown, the working principle of the device is specifically as follows: when the Type-C male interface is connected to the Type-C female interface, the Type-C female interface detects the access signal based on the CC pin, so that the power management chip directly controls the VBUS pin to start the power supply channel to realize the power supply function of the device. At the same time, the VBUS pin of the Type-C female interface powers on the first verification module, the first verification module sends a verification request to the Type-C male interface through the OUT pin, and the first verification module receives the verification data sent by the Type-C male interface through the IN2 pin. After the first verification module successfully matches the verification data, the first verification module closes the selection switch to the D0 pin and the D1 pin, and connects the UART signal of the processor to the configuration pin of the Type-C female interface, thereby starting the debugging communication circuit and enabling the DATA signal of the processor to start the data transmission circuit, so that the processor detects the RX / TX signal and the D+ / D- signal to select the data transmission mode.

[0123] In summary, the present invention provides a data transmission method and device based on Type-C. When the Type-C male interface is connected to the Type-C female interface, the Type-C female interface directly starts the power supply channel by the VBUS pin to realize the power supply function of the device, that is, the power supply function can be realized as long as it is connected. At the same time, since the Type-C female interface starts the power supply channel to power on the first verification module, the Type-C female interface can send a verification request to the Type-C male interface by the first verification module at this time so that the Type-C male interface sends verification data. If the Type-C male interface successfully returns the verification data, and the verification data matches the standard data successfully, the data transmission channel and the debugging communication channel are started, that is, the data transmission function and the debugging communication function need to be successfully verified to be realized. In this way, the access of illegal devices or incorrect data transmission is prevented, thereby ensuring data security. At the same time, in the data transmission channel, based on the detection and evaluation of the data pin by the processor, the best data transmission mode is dynamically selected, while improving the compatibility of the data transmission mode, the stability and effectiveness of the data transmission are effectively guaranteed. The present invention integrates a power supply channel, a data transmission channel, and a debugging communication channel in the Type-C female interface, realizes multiple functions in one interface, effectively simplifies the interface circuit of the device, and reduces the production cost of the device.

[0124] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A data transmission method based on Type-C, It is characterized in that include: In response to an access signal of the male interface, the power supply channel is started, and a first verification module sends a verification request to the male interface so that the male interface sends verification data; If the first verification module receives the verification data within a preset time, the verification data is matched with the preset standard data, and if the match is successful, the data transmission channel and the debugging communication channel are started; Performing data transmission based on the data transmission channel and the male interface; Debug analysis is performed based on the debug communication channel and the male interface.

2. According to a data transmission method based on Type-C according to claim 1, It is characterized in that The sending of a verification request by the first verification module to the male interface so that the male interface sends verification data includes: If the male interface is provided with a second verification module, the first verification module sends a verification request to the second verification module, so that the second verification module sends verification data.

3. According to a data transmission method based on Type-C according to claim 1, It is characterized in that The sending of a verification request by the first verification module to the male interface so that the male interface sends verification data includes: If the male interface is not provided with a second verification module, the first verification module sends a verification request to a host computer connected to the male interface, so that the host computer sends verification data generated based on the device serial number.

4. According to a data transmission method based on Type-C according to claim 2, It is characterized in that If the male interface is provided with a second verification module, before the first verification module sends a verification request to the second verification module, the method further includes: The host computer connected to the male interface detects whether verification data is preset in the second verification module. If verification data is not preset, the host computer generates verification data according to the acquired device serial number and writes the verification data into the second verification module.

5. According to a data transmission method based on Type-C according to claim 1, It is characterized in that The performing data transmission based on the data transmission channel and the male interface includes: Detecting the connection status and signal status of each data pin under the data transmission channel; Switching the data transmission mode of the data transmission channel according to the connection state and signal state of each data pin, wherein the data transmission mode includes a high-speed transmission mode and a low-speed transmission mode; The target data in the preset data partition is read and written based on the data transmission mode, and data transmission is performed with the male interface.

6. A data transmission device based on Type-C, It is characterized in that comprising a first interface unit and a second interface unit; The first interface unit includes a processor, a power management chip, a power supply circuit, a debugging communication circuit, a data transmission circuit and a Type-C female interface, and the debugging communication circuit is provided with a first verification module; The first data terminal of the processor is connected to the input control terminal of the power management chip, the output control terminal of the power management chip is connected to one end of the power supply circuit, and the other end of the power supply circuit is connected to the power supply pin of the Type-C female connector; The second data terminal of the processor is connected to one end of the data transmission circuit, and the other end of the data transmission circuit is connected to the data pin of the Type-C female connector; The third data terminal of the processor is connected to one end of the debug communication circuit, and the other end of the debug communication circuit is connected to the power supply pin and the configuration pin of the Type-C female interface; The second interface unit includes a Type-C male interface; The processor is configured to execute each step in a Type-C based data transmission method as described in any one of claims 1 to 5.

7. A data transmission device based on Type-C according to claim 6, It is characterized in that The data pins of the Type-C female interface include two groups of high-speed differential signal pairs and one group of low-speed differential signal pairs; The second data end of the processor is respectively connected to the two groups of high-speed differential signal pairs and the group of low-speed differential signal pairs; the processor implements a high-speed transmission mode based on the two groups of high-speed differential signal pairs, and the processor implements a low-speed transmission mode based on the group of low-speed differential signal pairs.

8. A data transmission device based on Type-C according to claim 6, It is characterized in that The configuration pins of the Type-C female interface include a CC pin and an SBU pin; The verification power supply end of the first verification module is connected to the power supply pin of the Type-C female connector; The communication data terminal of the first verification module is connected to the third data terminal of the processor; The verification control end of the first verification module is respectively connected to the CC pin and the SBU pin of the Type-C female connector; The verification control terminal of the first verification module and the communication data terminal of the first verification module are connected in a strobe manner.

9. A data transmission device based on Type-C according to claim 6, It is characterized in that The second interface unit also includes a second verification module and a Type-A interface; The Type-C male interface is respectively connected to the communication data end of the second verification module and the first data end of the Type-A interface; The check control terminal of the second check module is connected to the second data terminal of the Type-A interface.

10. A data transmission device based on Type-C according to claim 9, It is characterized in that The second interface unit also includes a serial communication module; The verification control end of the second verification module is connected to one end of the serial communication module, and the other end of the serial communication module is connected to the second data end of the Type-A interface.

Images