Chip layout detection method and device, equipment, storage medium and program product
By detecting the graphical geometric relationship of the chip layout, we judge whether the etching compensation is in place, and determining the area based on the edge of inadequate compensation, the problem of low detection efficiency in the prior art is solved, and efficient etching compensation detection is achieved.
Patent Information
- Application Number
- CN202411253331.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-06
- Publication Date
- 2024-12-13
AI Technical Summary
During the chip manufacturing process, the detection efficiency of whether the etching compensation is in place is low, which is mainly due to the complexity of the design layout, and the existing methods rely on complex calculations of mask manufacturability rules, which are inefficient.
By obtaining the graphic geometric relationship between the initial design layout, the first compensation layout and the second compensation layout, it is determined whether the second compensation layout meets the etch compensation target. If it is not satisfied, it is determined based on the dimension information of the graphic edge. and determine the area where it is located as a compensation area that is not in place, simplifies the detection steps and reduces the amount of calculation.
It improves the detection efficiency of whether the etching compensation is in place, reduces the detection calculation amount, simplifies the detection process, and can quickly identify areas that are not in place to compensate, improving the detection efficiency.
Smart Images
Figure CN119129521A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of semiconductor detection technology, and in particular, relates to a chip layout detection method, device, equipment, storage medium and program product. Background Art
[0002] In the chip manufacturing process, there is usually a deviation between the size of the pattern on the photoresist and the size of the pattern on the substrate after etching, which is called etching deviation. Figure 1 Usually, etching compensation needs to be performed on the etched pattern. In order to ensure the effect of etching compensation, it is necessary to detect whether the etching compensation is in place.
[0003] In the existing method, the compensated layout is usually calculated in sequence according to the mask rule check (MRC) in the etching compensation process, so as to identify whether there is a situation where the compensation is stopped prematurely because the MRC rule is not met and the compensation is not in place.
[0004] However, due to the complexity of the design layout, the amount of calculation required when detecting whether the etching compensation is in place is huge, resulting in low efficiency in detecting whether the etching compensation is in place. Summary of the invention
[0005] The embodiments of the present application provide a chip layout detection method, device, equipment, storage medium and program product, which can improve the efficiency of detecting whether etching compensation is in place.
[0006] In one aspect of an embodiment of the present application, a method for detecting a chip layout is provided, comprising:
[0007] Acquire an initial design layout, a first compensation layout, and a second compensation layout, wherein the first compensation layout is a layout in which etching compensation correction is performed on the initial design layout without considering mask manufacturability rules, and the second compensation layout is a layout in which etching compensation correction is performed on the initial design layout with mask manufacturability rules considered;
[0008] Determining whether the second compensation layout meets the etching compensation target according to the graphic geometric relationship among the initial design layout, the first compensation layout and the second compensation layout;
[0009] In the case where the second compensation layout does not meet the etching compensation target, determining the uncompensated edge of the pattern edge where the etching compensation is not in place according to the size information of the pattern edge of the second compensation layout;
[0010] Determining a first non-overlapping area between the first compensation layout and the second compensation layout according to a geometric relationship between the first compensation layout and the second compensation layout;
[0011] The first non-overlapping area where the under-compensation edge is located is determined as the under-compensation area of the second compensation pattern.
[0012] In one aspect of an embodiment of the present application, a device for detecting a chip layout is provided, comprising:
[0013] A layout acquisition module, used to acquire an initial design layout, a first compensation layout and a second compensation layout, wherein the first compensation layout is a layout in which etching compensation correction is performed on the initial design layout without considering mask manufacturability rules, and the second compensation layout is a layout in which etching compensation correction is performed on the initial design layout with mask manufacturability rules considered;
[0014] A layout judgment module, used to determine whether the second compensation layout meets the etching compensation target according to the graphic geometric relationship between the initial design layout, the first compensation layout and the second compensation layout;
[0015] An edge determination module, used to determine, when the second compensation layout does not meet the etching compensation target, the inadequately compensated edge of the pattern edge where the etching compensation is not in place according to the size information of the pattern edge of the second compensation layout;
[0016] A layout comparison module, used for determining a first non-overlapping area between the first compensation layout and the second compensation layout according to a geometric relationship between the first compensation layout and the second compensation layout;
[0017] The area determination module is used to determine the first non-overlapping area where the under-compensation edge is located as the under-compensation area of the second compensation layout.
[0018] In one aspect of an embodiment of the present application, an electronic device is provided, which includes: a memory and a program or instruction stored in the memory and executable on a processor, wherein when the program or instruction is executed by the processor, a chip layout detection method as provided in any aspect of the above-mentioned embodiment of the present application is implemented.
[0019] In one aspect of an embodiment of the present application, a readable storage medium is provided, on which a program or instruction is stored. When the program or instruction is executed by a processor, a chip layout detection method provided in any aspect of the above-mentioned embodiment of the present application is implemented.
[0020] In one aspect of an embodiment of the present application, a computer program product is provided. When instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes a chip layout detection method provided in any aspect of the above-mentioned embodiment of the present application.
[0021] In the chip layout detection method provided in the embodiment of the present application, whether the second compensation layout meets the etching compensation target is determined based on the geometric relationship between the initial design layout, the first compensation layout and the second compensation layout. Figure 3 By using the relationship between the three and the geometric relationship of the graphics, it is possible to determine whether the second compensation layout is fully compensated without a lot of calculations. And in the case where it is determined that the compensation is in place, there is no need to continue the process of determining the area where compensation is not in place, which can simplify the detection steps, thereby improving the detection efficiency of whether the etching compensation is in place. Then, in the case where it is determined that the compensation is not in place, it is only necessary to detect and calculate the size information of the edge of the graphic in the second compensation layout, and obtain the uncompensated edge where the etching compensation is not in place in the edge of the graphic, and the uncompensated area of the second compensation layout can be determined based on the uncompensated edge. In this way, there is no need to use the manufacturability rules of each mask to detect and calculate each part of the second compensation layout separately. It is only necessary to detect and calculate the edge of the graphic, which can greatly reduce the amount of calculation during detection, thereby improving the detection efficiency of whether the etching compensation is in place. In summary, the embodiments of the present application can improve the detection efficiency of whether the etching compensation is in place. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0023] Figure 1 It is a schematic flow chart of a chip layout detection method provided by an embodiment of the present application;
[0024] Figure 2 is a schematic diagram of the overlap of a first compensation pattern and a second compensation pattern provided by an embodiment of the present application;
[0025] Figure 3 It is an overlapping schematic diagram of an initial design layout, a first compensation layout and a second compensation layout provided by an embodiment of the present application;
[0026] Figure 4 is a schematic diagram of a target edge of a second non-overlapping area provided by an embodiment of the present application;
[0027] Figure 5 It is a structural schematic diagram of a chip layout detection device provided by an embodiment of the present application;
[0028] Figure 6 It is a structural schematic diagram of a chip layout detection device provided in one embodiment of the present application. DETAILED DESCRIPTION
[0029] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.
[0030] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0031] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application are in compliance with the relevant provisions of national laws and regulations.
[0032] It should be noted that in the embodiments of the present application, certain software, components, models and other existing solutions in the industry may be mentioned, and they should be regarded as exemplary. Their purpose is only to illustrate the feasibility of implementing the technical solution of the present application, but it does not mean that the applicant has or will necessarily use the solution.
[0033] In the existing methods, the compensated layout is usually calculated in sequence according to the MRC rules in the etching compensation process, so as to identify whether there is a situation where the compensation is not in place and the MRC rules are not met. However, due to the complexity of the design layout, the amount of calculation is huge when detecting whether the etching compensation is in place, resulting in low efficiency in detecting whether the etching compensation is in place.
[0034] The purpose of the present application is to provide a chip layout detection method, device, equipment, storage medium and program product. In the chip layout detection method provided in the embodiment of the present application, according to the geometric relationship between the initial design layout, the first compensation layout and the second compensation layout, it is determined whether the second compensation layout meets the etching compensation target. Figure 3 By using the relationship between the three and the geometric relationship of the graphics, it is possible to determine whether the second compensation layout is fully compensated without a lot of calculations. And in the case where it is determined that the compensation is in place, there is no need to continue the process of determining the area where compensation is not in place, which can simplify the detection steps, thereby improving the detection efficiency of whether the etching compensation is in place. Then, in the case where it is determined that the compensation is not in place, it is only necessary to detect and calculate the size information of the edge of the graphic in the second compensation layout, and obtain the uncompensated edge where the etching compensation is not in place in the edge of the graphic, and the uncompensated area of the second compensation layout can be determined based on the uncompensated edge. In this way, there is no need to use the manufacturability rules of each mask to detect and calculate each part of the second compensation layout separately. It is only necessary to detect and calculate the edge of the graphic, which can greatly reduce the amount of calculation during detection, thereby improving the detection efficiency of whether the etching compensation is in place. In summary, the embodiments of the present application can improve the detection efficiency of whether the etching compensation is in place.
[0035] The following describes the specific embodiments of the chip layout detection method, device, equipment, storage medium and program product provided by the embodiments of the present application. The following first introduces the chip layout detection method.
[0036] Figure 1 A schematic flow chart of a chip layout detection method is provided. The chip layout detection method can be applied to a server. The chip layout detection method can include the following S101 to S105.
[0037] S101, obtaining an initial design layout, a first compensation layout and a second compensation layout, wherein the first compensation layout is a layout in which etching compensation correction is performed on the initial design layout without considering mask manufacturability rules, and the second compensation layout is a layout in which etching compensation correction is performed on the initial design layout with mask manufacturability rules considered.
[0038] In this embodiment, the initial design layout is a layout without etching compensation, which has a certain etching deviation.
[0039] The first compensation layout is a layout that directly performs etching compensation on the initial design layout without considering the MRC rule. It is not restricted by complex MRC rules and can achieve the designed etching compensation target.
[0040] The second compensation layout takes the MRC rule into consideration when performing etching compensation on the initial design layout. However, due to the limitation of MRC, the designed etching compensation target cannot be achieved, and etching compensation may not be in place.
[0041] As an example, the server obtains an initial design layout, and performs etching compensation correction on the initial design layout without considering the MRC rule to obtain a first compensation layout, and performs etching compensation correction on the initial design layout while considering the MRC rule to obtain a second compensation layout.
[0042] S102, determining whether the second compensation layout meets the etching compensation target according to the geometric relationship among the initial design layout, the first compensation layout and the second compensation layout.
[0043] In this embodiment, the etching compensation target is used to represent a pre-designed etching compensation amount.
[0044] The geometric relationship of graphics is used to characterize the relative positional relationship between graphics. For example, the relative positional relationship between graphics can be the overlap between graphics.
[0045] As an example, the server compares the initial design layout with the first compensation layout to obtain the area where the initial design layout and the first compensation layout do not overlap. The non-overlapping area is the area where the first compensation layout has performed etching compensation relative to the initial design layout, and the area can be determined to be equal to the pre-designed etching compensation amount.
[0046] Then the second compensation layout is compared with the non-overlapping area to determine whether the second compensation layout covers the non-overlapping area. If the second compensation layout has covered the non-overlapping area, it can be determined that the second compensation layout has met the etching compensation target; if the second compensation layout does not cover the non-overlapping area, it can be determined that the second compensation layout does not meet the etching compensation target.
[0047] S103, when the second compensation layout does not meet the etching compensation target, determine the under-compensated edges of the pattern edges where the etching compensation is not in place according to the size information of the pattern edges of the second compensation layout.
[0048] In this embodiment, the size information of the graphic edge is used to represent the numerical data of the geometric size and geometric size relationship of the graphic edge in the layout. For example, the size information of the graphic edge may include the border size of the graphic edge, the line width of the graphic edge, and the spacing between the graphic edges.
[0049] In the case that the second compensation layout does not meet the etching compensation target, the server further determines whether the size information of the pattern edge of the second compensation layout meets the MRC rule.
[0050] By way of example, the MRC rules may include a minimum allowed spacing between graphic edges (min_space_edge_to_edge), a minimum width requirement between graphic edges (min_width_edge_to_edge), a minimum allowed spacing between graphic corners (min_space_corner_to_corner), and a minimum width requirement between graphic corners (min_width_corner_to_corner).
[0051] Then, the edges of the graphic edges that do not meet the MRC rule are marked as uncompensated edges. For example, the second compensation layout is a rectangular layout, which has graphic edges in the four directions of the top, bottom, left and right of the center of the layout. If the size information of the lower graphic edge does not meet the MRC rule, the lower graphic edge is marked as an uncompensated edge.
[0052] S104, determining a first non-overlapping area between the first compensation layout and the second compensation layout according to a geometric relationship between the first compensation layout and the second compensation layout.
[0053] In this embodiment, the first non-overlapping area is the area where the first compensation layout and the second compensation layout do not overlap, that is, the area where the designed etching compensation amount is not actually reached. There are two reasons for this: the first is that the etching compensation is not in place, and the second is that compensation cannot be continued due to the restriction of the MRC rule.
[0054] As an example, Figure 2 As shown, a schematic diagram of the overlap of the first compensation layout and the second compensation layout is provided. Specifically, the server compares the first compensation layout 201 with the second compensation layout 202, and performs an XOR operation on the first compensation layout 201 and the second compensation layout 202 to obtain a first non-overlapping area. The first non-overlapping area includes a first upper non-overlapping area 203 located above the second compensation layout 202 and a first lower non-overlapping area 204 located below the second compensation layout 202.
[0055] S105, determining the first non-overlapping area where the under-compensation edge is located as the under-compensation area of the second compensation pattern.
[0056] In this embodiment, if Figure 2 As shown, after obtaining the first non-overlapping area, the service end further screens the first non-overlapping area, and determines that the first lower non-overlapping area 204 where the under-compensation edge 205 is located is the under-compensation area formed due to under-compensation of etching, and the first upper non-overlapping area 203 is the area that cannot be further compensated due to the restriction of the MRC rule.
[0057] In the chip layout detection method provided in this embodiment, whether the second compensation layout meets the etching compensation target is determined based on the geometric relationship between the initial design layout, the first compensation layout and the second compensation layout. Figure 3 By using the relationship between the three and the geometric relationship of the graphics, it is possible to determine whether the second compensation layout is fully compensated without a lot of calculations. And in the case where it is determined that the compensation is in place, there is no need to continue the process of determining the area where compensation is not in place, which can simplify the detection steps, thereby improving the detection efficiency of whether the etching compensation is in place. Then, in the case where it is determined that the compensation is not in place, it is only necessary to detect and calculate the size information of the edge of the graphic in the second compensation layout, and obtain the uncompensated edge where the etching compensation is not in place in the edge of the graphic, and the uncompensated area of the second compensation layout can be determined based on the uncompensated edge. In this way, there is no need to use the manufacturability rules of each mask to detect and calculate each part of the second compensation layout separately. It is only necessary to detect and calculate the edge of the graphic, which can greatly reduce the amount of calculation during detection, thereby improving the detection efficiency of whether the etching compensation is in place. In summary, the embodiments of the present application can improve the detection efficiency of whether the etching compensation is in place.
[0058] As an optional embodiment, S102 may specifically include:
[0059] Determining a second non-overlapping area between the initial design layout and the first compensation layout according to a geometric relationship between the initial design layout and the first compensation layout;
[0060] According to the geometric relationship between the second compensation layout and the second non-overlapping area, determining whether the edge of the pattern of the second compensation layout coincides with the corresponding target edge in the second non-overlapping area to obtain a determination result;
[0061] When the judgment result indicates that the edge of the pattern coincides with the target edge, determining that the second compensation layout satisfies the etching compensation target;
[0062] When the judgment result indicates that the pattern edge does not coincide with the target edge, it is determined that the second compensation layout does not meet the etching compensation target.
[0063] In this embodiment, the second overlapping area is the area where the initial design layout and the first compensation layout do not overlap, that is, the area where the first compensation layout performs etching compensation relative to the initial design layout.
[0064] The target edge is an edge in the second non-overlapping region that matches an edge of a pattern in the second compensation layout.
[0065] As an example, Figure 3As shown, a schematic diagram of the overlap of the initial design layout, the first compensation layout and the second compensation layout is provided. Specifically, the server compares the initial design layout 301 with the first compensation layout 201, and performs an XOR operation on the initial design layout 301 and the first compensation layout 201 to obtain the second non-overlapping area. The second non-overlapping area includes a second upper non-overlapping area 302 located above the initial design layout 301 and a second lower non-overlapping area 303 located below the initial design layout 301.
[0066] Then, the graphic edges of the second compensation layout 202 are compared with the corresponding target edges in the second non-overlapping area. When the graphic edges of the second compensation layout 202 and the corresponding target edges in the second non-overlapping area completely overlap, it can be determined that the second compensation layout 202 has met the etching compensation target; when there is an edge of the graphic edge of the second compensation layout 202 that does not overlap with the corresponding target edge in the second non-overlapping area, it can be determined that the second compensation layout 202 does not meet the etching compensation target.
[0067] Specifically, according to Figure 3 It can be seen that among the graphic edges of the second compensation layout 202, the upper graphic edge does not overlap with the corresponding target edge in the second non-overlapping area, so the second compensation layout 202 does not meet the etching compensation target.
[0068] Through this embodiment, the second non-overlapping area between the initial design layout and the first compensation layout is first determined, and then whether the second compensation layout meets the etching compensation target can be accurately determined based on whether the pattern edge of the second compensation layout coincides with the corresponding target edge in the second non-overlapping area. In this way, this embodiment can determine whether the layout meets the etching compensation target by simply judging the relative position relationship between the layouts, without the need for a large amount of calculations, thereby improving the detection efficiency of whether the layout meets the etching compensation target.
[0069] As an optional embodiment, when the compensation method of the second non-overlapping area is to enlarge the pattern size, the target edge is the edge of the second non-overlapping area farthest from the target position, and the target position is the position of any point in the overlapping area between the initial design layout and the first compensation layout;
[0070] When the compensation method of the second non-overlapping area is to reduce the size of the pattern, the target edge is the edge in the second non-overlapping area that is closest to the target position.
[0071] In this embodiment, the second non-overlapping area includes a corresponding compensation method, and the compensation method is one of enlarging the graphic size (space method) and reducing the graphic size (width method). Specifically, when the graphic size of the first compensation layout is larger than the graphic size of the initial design layout, the compensation method of the second non-overlapping area is the space method; when the graphic size of the first compensation layout is smaller than the graphic size of the initial design layout, the compensation method of the second non-overlapping area is the width method.
[0072] The target position is the position of any point selected from the overlapping area of the initial design layout and the first compensation layout. For example, the target position can be the center point position of the overlapping area of the initial design layout and the first compensation layout.
[0073] As an example, Figure 4 As shown, a schematic diagram of the target edge of the second non-overlapping area is provided. Specifically, the server first determines the compensation method of the second non-overlapping area 401 according to the graphic size of the first compensation layout 201 and the initial design layout 301. Among them, the graphic size of the first compensation layout 201 is larger than the graphic size of the initial design layout 301, that is, the compensation method of the second non-overlapping area 401 is the space method.
[0074] Then, when the compensation mode of the second non-overlapping area 401 is the space mode, the edge farthest from the target position 402 in the second non-overlapping area is selected as the target edge in the second non-overlapping area 401 that matches the edge of the pattern of the second compensation layout. Figure 4 The graphic edge where the second non-overlapping area 401 overlaps with the first compensation layout 201 is the target edge that matches the graphic edge of the second compensation layout.
[0075] Through this embodiment, according to the compensation method of the second non-overlapping area, a suitable edge in the second non-overlapping area is selected as the target edge in the second non-overlapping area that matches the edge of the pattern of the second compensation layout. This helps to accurately identify whether the second compensation layout meets the etching compensation target based on the target edge, thereby improving the detection efficiency of whether the layout meets the etching compensation target.
[0076] As an optional embodiment, S103 may specifically include:
[0077] When the second compensation layout does not meet the etching compensation target, the size of the pattern edge of the second compensation layout is compared with the size threshold of the corresponding target mask manufacturability rule to obtain a comparison result;
[0078] According to the comparison result, determine whether the etching compensation of the edge of the pattern is in place;
[0079] The edge of the pattern where etching compensation is not in place is marked as an uncompensated edge.
[0080] In this embodiment, according to the reason why the pattern edge does not meet the etching compensation target, it can be analyzed whether the etching compensation of the pattern edge is in place.
[0081] Specifically, when the compensation cannot be continued due to the restriction of MRC rules, resulting in the pattern edge not meeting the etching compensation target, at this time, due to the restriction of the rules, the compensation cannot be continued in theory, so it can be considered that the pattern edge compensation is in place at this time.
[0082] In the case where the MRC rule is not restricted and the edge of the pattern still does not meet the etching compensation target, there is no restriction on any rule at this time, and compensation should continue in theory, so it can be considered that the edge compensation of the pattern is not in place at this time.
[0083] As an example, when the second compensation layout does not meet the etching compensation target, the size of each graphic edge in the second compensation layout is obtained, and the size of each graphic edge in the second compensation layout is compared with the size threshold of the corresponding target mask manufacturability rule to obtain a comparison result.
[0084] According to the comparison results, an analysis is performed to determine whether the edge of the pattern does not meet the etching compensation target due to the limitation of the MRC rule and the inability to continue compensation.
[0085] Finally, the edges of the graphics that do not meet the etching compensation target due to the limitation of the MRC rule and cannot be compensated are determined and marked as uncompensated edges.
[0086] Through this embodiment, the size of each graphic edge of the second compensation layout is compared with the size threshold of the corresponding target mask manufacturability rule, so as to accurately identify the uncompensated edges of the graphic edges that do not meet the etching compensation target due to the limitation of the MRC rule and the inability to continue compensation. In this way, by accurately identifying the uncompensated edges, it is helpful to quickly locate the uncompensated areas according to the uncompensated edges, and the detection efficiency of the uncompensated areas can be improved.
[0087] As an optional embodiment, before comparing the size of the pattern edge of the second compensation layout with the size threshold of the corresponding target mask manufacturability rule and obtaining the comparison result, the chip layout detection method may further include:
[0088] Acquire a non-overlapping edge in the graphic edge of the second compensation layout that does not overlap with the target edge corresponding to the second non-overlapping area;
[0089] Comparing the size of the pattern edge of the second compensation layout with the size threshold of the corresponding target mask manufacturability rule to obtain a comparison result may specifically include:
[0090] The size of the non-overlapping edge is compared with a size threshold of a corresponding target mask manufacturability rule to obtain a comparison result.
[0091] In this embodiment, when the second compensation layout does not meet the etching compensation target, the server can further obtain non-overlapping edges of the graphic edges of the second compensation layout that do not overlap with the target edges corresponding to the second non-overlapping area.
[0092] At this time, the edge that overlaps with the target edge corresponding to the second non-overlapping area means that the etching compensation target has been met, so it is impossible that the etching compensation is not in place. Only the non-overlapping edge that does not overlap with the target edge corresponding to the second non-overlapping area may have the situation of inadequate etching compensation, so it is only necessary to compare the size of the non-overlapping edge with the size threshold of the corresponding target mask manufacturability rule.
[0093] Through this embodiment, the non-overlapping edges in the graphic edges of the second compensation layout that do not overlap with the target edges corresponding to the second non-overlapping area are first screened out, and then the size of the non-overlapping edge is compared with the size threshold of the corresponding target mask manufacturability rule. It is no longer necessary to compare all the graphic edges, thereby further reducing the amount of calculation and improving the detection efficiency of the edges that are not compensated in place.
[0094] As an optional embodiment, before comparing the size of the pattern edge of the second compensation layout with the size threshold of the corresponding target mask manufacturability rule and obtaining the comparison result, the chip layout detection method may further include:
[0095] Determine the compensation method corresponding to the graphic edge of the second compensation layout according to the positional relationship between the graphic edge of the second compensation layout and the second non-overlapping area and the compensation method of the second non-overlapping area;
[0096] A mask manufacturability rule that matches the compensation method corresponding to the pattern edge of the second compensation layout is determined as a target mask manufacturability rule.
[0097] In this embodiment, the server can determine the compensation method corresponding to each graphic edge of the second compensation layout by using the positional relationship between each graphic edge of the second compensation layout and the second non-overlapping area and the compensation method of the second non-overlapping area.
[0098] Then, the mask manufacturability rule matching the compensation mode is determined as the target mask manufacturability rule. Specifically, the mask manufacturability rule can be divided into two categories: mask manufacturability rules corresponding to the space mode and mask manufacturability rules corresponding to the width mode.
[0099] For example, Figure 3 As shown, when the pattern edge of the second compensation layout 202 is located in the second upper non-overlapping area 302 of the second non-overlapping area, and the compensation method of the second non-overlapping area is the space method, it means that the pattern edge of the second compensation layout 202 also enlarges the pattern size relative to the initial design layout, that is, the compensation method of the pattern edge of the second compensation layout 202 is also the space method.
[0100] Then, a mask manufacturability rule matching the space mode is selected as a target mask manufacturability rule corresponding to the pattern edge of the second compensation layout.
[0101] Through this embodiment, the corresponding target mask manufacturability rule is determined according to the compensation method corresponding to the pattern edge of the second compensation layout. In this way, it is only necessary to compare the size of the pattern edge with the size threshold of the corresponding target mask manufacturability rule in the future, and it is no longer necessary to compare with the size threshold of all mask manufacturability rules, thereby further reducing the amount of calculation and improving the detection efficiency of the edge that is not compensated in place.
[0102] As an optional embodiment, determining whether the etching compensation of the edge of the pattern is in place according to the comparison result may specifically include:
[0103] When the comparison result indicates that the size of the edge of the graphic is less than or equal to the size threshold, determining that the etching compensation of the edge of the graphic is in place;
[0104] When the comparison result indicates that the size of the pattern edge is greater than the size threshold, it is determined that the etching compensation of the pattern edge is not in place.
[0105] In this embodiment, when the size of the graphic edge is equal to the size threshold, it indicates that the constraint of the MRC rule has been reached, so it will be restricted by the MRC rule and cannot continue to be compensated, that is, the graphic edge etching compensation is in place.
[0106] When the size of the graphic edge is smaller than the size threshold, it indicates that it has exceeded the constraint of the MRC rule, so it will inevitably be restricted by the MRC rule and cannot be compensated further, that is, the graphic edge etching compensation is in place.
[0107] When the size of the graphic edge is larger than the size threshold, it indicates that it has not yet reached the constraint of the MRC rule. Therefore, it is not because of the limitation of the MRC rule that compensation cannot be continued, that is, the etching compensation of the graphic edge is not in place.
[0108] Through this embodiment, whether the size of the pattern edge is greater than the size threshold is determined to determine whether the pattern edge etching compensation is in place, which helps to accurately identify the under-compensated edge, thereby helping to accurately locate the under-compensated area based on the under-compensated edge.
[0109] Detection method based on chip layout. Accordingly, the present application also provides a specific embodiment of a detection device for chip layout.
[0110] like Figure 5 As shown, the chip layout detection device provided in the embodiment of the present application includes a layout acquisition module 510, a layout judgment module 520, an edge determination module 530, a layout comparison module 540 and an area determination module 550.
[0111] The layout acquisition module 510 is used to acquire an initial design layout, a first compensation layout, and a second compensation layout, wherein the first compensation layout is a layout in which etching compensation correction is performed on the initial design layout without considering the mask manufacturability rule, and the second compensation layout is a layout in which etching compensation correction is performed on the initial design layout with considering the mask manufacturability rule;
[0112] The layout judgment module 520 is used to determine whether the second compensation layout meets the etching compensation target according to the geometric relationship between the initial design layout, the first compensation layout and the second compensation layout;
[0113] The edge determination module 530 is used to determine the under-compensation edge of the pattern edge where the etching compensation is not in place according to the size information of the pattern edge of the second compensation layout when the second compensation layout does not meet the etching compensation target;
[0114] A layout comparison module 540 is used to determine a first non-overlapping area between the first compensation layout and the second compensation layout according to a geometric relationship between the first compensation layout and the second compensation layout;
[0115] The region determination module 550 is used to determine the first non-overlapping region where the under-compensation edge is located as the under-compensation region of the second compensation layout.
[0116] As an optional embodiment, the layout determination module 520 specifically includes the following units:
[0117] A layout comparison unit, used to determine a second non-overlapping area between the initial design layout and the first compensation layout according to a geometric relationship between the graphics of the initial design layout and the first compensation layout;
[0118] An edge judgment unit, used to judge whether the edge of the graphic of the second compensation layout coincides with the corresponding target edge in the second non-overlapping area according to the graphic geometric relationship between the second compensation layout and the second non-overlapping area, and obtain a judgment result;
[0119] A result determination unit, configured to determine that the second compensation layout satisfies the etching compensation target when the judgment result indicates that the edge of the pattern coincides with the target edge;
[0120] The result determination unit is further used to determine that the second compensation layout does not meet the etching compensation target when the judgment result indicates that the edge of the pattern does not overlap with the target edge.
[0121] As an optional embodiment, the edge determination module specifically includes the following units:
[0122] A result generating unit is used to compare the size of the pattern edge of the second compensation layout with the size threshold of the corresponding target mask manufacturability rule to obtain a comparison result when the second compensation layout does not meet the etching compensation target;
[0123] An edge determination unit, used to determine whether the etching compensation of the pattern edge is in place according to the comparison result;
[0124] The edge marking unit is used to mark the edge of the pattern where the etching compensation is not in place as the edge where the compensation is not in place.
[0125] As an optional embodiment, before comparing the size of the pattern edge of the second compensation layout with the size threshold of the corresponding target mask manufacturability rule and obtaining the comparison result, the edge determination module further includes the following units:
[0126] An edge acquisition unit, used for acquiring non-overlapping edges of the graphic edges of the second compensation layout that do not overlap with the target edges corresponding to the second non-overlapping area;
[0127] The result generation unit is specifically used for:
[0128] The size of the non-overlapping edge is compared with a size threshold of a corresponding target mask manufacturability rule to obtain a comparison result.
[0129] As an optional embodiment, before comparing the size of the pattern edge of the second compensation layout with the size threshold of the corresponding target mask manufacturability rule and obtaining the comparison result, the chip layout detection device further includes the following modules:
[0130] A method determination module, used to determine the compensation method corresponding to the graphic edge of the second compensation layout according to the positional relationship between the graphic edge of the second compensation layout and the second non-overlapping area and the compensation method of the second non-overlapping area;
[0131] The rule determination module is used to determine the mask manufacturability rule that matches the compensation method corresponding to the pattern edge of the second compensation layout as the target mask manufacturability rule.
[0132] As an optional embodiment, the edge determination unit specifically includes the following subunits:
[0133] An edge determination subunit, used to determine that the etching compensation of the edge of the graphic is in place when the comparison result indicates that the size of the edge of the graphic is less than or equal to the size threshold;
[0134] The edge determination subunit is further used to determine that the etching compensation of the edge of the graphic is not in place when the comparison result indicates that the size of the edge of the graphic is greater than the size threshold.
[0135] Detection method based on chip layout. Accordingly, the present application also provides a specific embodiment of a detection device for chip layout.
[0136] Figure 6 A schematic diagram of the hardware structure of a chip layout detection device provided in an embodiment of the present application is shown.
[0137] The chip layout detection device may include a processor 601 and a memory 602 storing computer program instructions.
[0138] Specifically, the processor 601 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.
[0139] The memory 602 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 602 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 602 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 602 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 602 is a non-volatile solid-state memory.
[0140] The processor 601 implements any one of the chip layout detection methods in the above embodiments by reading and executing computer program instructions stored in the memory 602 .
[0141] In one example, the chip layout detection device may further include a communication interface 603 and a bus 610. Figure 6 As shown, the processor 601, the memory 602, and the communication interface 603 are connected via a bus 610 and communicate with each other.
[0142] The communication interface 603 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.
[0143] Bus 610 includes hardware, software or both, and the parts of the detection equipment of chip layout are coupled to each other.For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In suitable cases, bus 610 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the application considers any suitable bus or interconnection.
[0144] In addition, in combination with the chip layout detection method in the above embodiment, the embodiment of the present application can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by the processor, any chip layout detection method in the above embodiment is implemented.
[0145] In addition, in combination with the chip layout detection method in the above-mentioned embodiment, the embodiment of the present application can provide a computer program product for implementation. When the instructions in the computer program product are executed by the processor of an electronic device, the electronic device executes the chip layout detection method provided in any aspect of the above-mentioned embodiment of the present application.
[0146] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.
[0147] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.
[0148] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.
[0149] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.
[0150] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.
Claims
1. A chip layout detection method, characterized in that: include: Acquire an initial design layout, a first compensation layout, and a second compensation layout, wherein the first compensation layout is a layout in which etching compensation correction is performed on the initial design layout without considering mask manufacturability rules, and the second compensation layout is a layout in which etching compensation correction is performed on the initial design layout with mask manufacturability rules considered; Determining whether the second compensation layout meets an etching compensation target according to a graphic geometric relationship among the initial design layout, the first compensation layout, and the second compensation layout; In the case where the second compensation layout does not meet the etching compensation target, determining the uncompensated edge of the edge of the pattern where the etching compensation is not in place according to the size information of the edge of the pattern of the second compensation layout; Determining a first non-overlapping area between the first compensation layout and the second compensation layout according to a geometric relationship between the first compensation layout and the second compensation layout; The first non-overlapping area where the under-compensation edge is located is determined as the under-compensation area of the second compensation pattern.
2. The method according to claim 1, characterized in that The step of determining whether the second compensation layout meets the etching compensation target according to the geometric relationship among the initial design layout, the first compensation layout, and the second compensation layout includes: Determining a second non-overlapping area between the initial design layout and the first compensation layout according to a geometric relationship between the initial design layout and the first compensation layout; According to the graphic geometric relationship between the second compensation layout and the second non-overlapping area, determining whether a graphic edge of the second compensation layout coincides with a corresponding target edge in the second non-overlapping area to obtain a determination result; When the judgment result indicates that the edge of the pattern coincides with the target edge, determining that the second compensation layout satisfies the etching compensation target; When the judgment result indicates that the pattern edge does not overlap with the target edge, it is determined that the second compensation layout does not meet the etching compensation target.
3. The method according to claim 2, characterized in that When the compensation method of the second non-overlapping area is to enlarge the pattern size, the target edge is the edge of the second non-overlapping area farthest from the target position, and the target position is the position of any point in the overlapping area between the initial design layout and the first compensation layout; When the compensation method of the second non-overlapping area is to reduce the size of the graphic, the target edge is the edge in the second non-overlapping area that is closest to the target position.
4. The method according to claim 2 or 3, characterized in that: The method of determining, when the second compensation layout does not meet the etching compensation target, the inadequately compensated edge of the edge of the pattern where the etching compensation is not in place according to the size information of the edge of the pattern of the second compensation layout, comprises: When the second compensation layout does not meet the etching compensation target, the size of the pattern edge of the second compensation layout is compared with the size threshold of the corresponding target mask manufacturability rule to obtain a comparison result; According to the comparison result, determining whether the etching compensation of the edge of the pattern is in place; The edge of the pattern where etching compensation is not in place is marked as an uncompensated edge.
5. The method according to claim 4, characterized in that Before comparing the size of the pattern edge of the second compensation layout with the size threshold of the corresponding target mask manufacturability rule to obtain the comparison result, the method further includes: Acquire a non-overlapping edge of the graphic edge of the second compensation layout that does not overlap with a target edge corresponding to the second non-overlapping area; The step of comparing the size of the pattern edge of the second compensation layout with the size threshold of the corresponding target mask manufacturability rule to obtain a comparison result includes: The size of the non-overlapping edge is compared with a size threshold of a corresponding target mask manufacturability rule to obtain a comparison result.
6. The method according to claim 4, characterized in that Before comparing the size of the pattern edge of the second compensation layout with the size threshold of the corresponding target mask manufacturability rule to obtain the comparison result, the method further includes: Determine a compensation method corresponding to the graphic edge of the second compensation layout according to a positional relationship between the graphic edge of the second compensation layout and the second non-overlapping area and a compensation method for the second non-overlapping area; The mask manufacturability rule that matches the compensation method corresponding to the pattern edge of the second compensation layout is determined as the target mask manufacturability rule.
7. The method according to claim 4, characterized in that Determining whether the etching compensation of the edge of the pattern is in place according to the comparison result includes: When the comparison result indicates that the size of the edge of the graphic is less than or equal to the size threshold, determining that the etching compensation of the edge of the graphic is in place; When the comparison result indicates that the size of the pattern edge is greater than the size threshold, it is determined that the etching compensation of the pattern edge is not in place.
8. A chip layout detection device, characterized in that: include: A layout acquisition module, used to acquire an initial design layout, a first compensation layout, and a second compensation layout, wherein the first compensation layout is a layout in which etching compensation correction is performed on the initial design layout without considering mask manufacturability rules, and the second compensation layout is a layout in which etching compensation correction is performed on the initial design layout with mask manufacturability rules considered; A layout judgment module, used to determine whether the second compensation layout meets the etching compensation target according to the graphic geometric relationship between the initial design layout, the first compensation layout and the second compensation layout; An edge determination module, used for determining, when the second compensation layout does not meet the etching compensation target, an uncompensated edge of the edge of the pattern where the etching compensation is not in place according to the size information of the edge of the pattern of the second compensation layout; A layout comparison module, configured to determine a first non-overlapping area between the first compensation layout and the second compensation layout according to a geometric relationship between the first compensation layout and the second compensation layout; The area determination module is used to determine the first non-overlapping area where the under-compensation edge is located as the under-compensation area of the second compensation layout.
9. An electronic device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the chip layout detection method according to any one of claims 1 to 7 is implemented.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the chip layout detection method according to any one of claims 1 to 7 is implemented.
11. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the chip layout detection method as described in any one of claims 1 to 7.
Citation Information
Cited By
Layout processing method, device and medium
CN119761297A