Image processing acceleration method based on parallel acceleration

Abstract

The invention relates to an image processing acceleration method based on parallel acceleration. The method comprises the following steps: S1, receiving image data from a user or other sources; s2, carrying out denoising, contrast adjustment and normalization preprocessing on the image; s3, carrying out image blocking; s4, dynamically distributing the small image blocks to different processing units according to system resources and load conditions; s5, each processing unit receives the starting level of the small image blocks and carries out parallel processing; S6, the working state of each processing unit in the step S5 is monitored in real time, and task distribution is dynamically adjusted; s7, collecting small block results processed by each processing unit, and splicing a complete output image by using a merging algorithm; s8, improving the quality of the spliced image; and S9, outputting the image. The system has the advantages of low cost, reliable performance and high expansibility.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and in particular to an image processing acceleration method based on parallel acceleration. Background Art

[0002] Most traditional image processing methods use single-threaded or CPU-based serial methods for calculations, which has some obvious defects and limitations:

[0003] (1) Single-threaded serial processing cannot fully utilize parallel computing resources such as multi-core CPUs and GPUs in modern computer systems, resulting in image processing efficiency that cannot meet the requirements of real-time and high throughput. In particular, for images with high resolution and large amounts of data, the single-threaded processing speed is often far behind, resulting in low processing efficiency.

[0004] (2) Due to the limitation of processing efficiency, traditional serial image processing methods often cannot meet the demand for real-time response and perform poorly in scenarios such as intelligent video analysis and machine vision detection. Delayed image processing results may lead to slow decision-making, affecting the performance of the overall system and resulting in poor real-time performance.

[0005] (3) This method mainly relies on the computing power of general-purpose CPUs and cannot fully utilize the parallel advantages of dedicated hardware (such as GPUs, FPGAs, etc.), resulting in low utilization of computing resources.

[0006] In addition, in order to improve the image processing speed, some existing technical solutions have adopted hardware accelerators, such as: GPU acceleration, FPGA / ASIC acceleration, dedicated image processing chips and some suppliers provide dedicated image processing chips or acceleration cards, but they also have the defects of high cost and poor versatility.

[0007] The above-mentioned existing technical solutions are either inefficient or expensive and inflexible. Therefore, there is an urgent need for a new image processing acceleration technology that can effectively utilize general hardware parallel computing resources and maintain good flexibility and cost controllability to meet real-time and high throughput requirements. Summary of the invention

[0008] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by this patent application is how to provide an image processing acceleration method based on parallel acceleration with low cost, reliable performance and strong scalability.

[0009] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0010] An image processing acceleration method based on parallel acceleration includes the following steps: S1: receiving image data from a user or other source; S2: pre-processing the image by denoising, adjusting contrast, and normalizing; S3: image segmentation; S4: dynamically allocating small image blocks to different processing units according to system resources and load conditions; S5: each processing unit receives a small image block and starts parallel processing; S6: real-time monitoring of the working status of each processing unit in step S5, and dynamically adjusting task allocation; S7: collecting small block results processed by each processing unit, and using a merging algorithm to splice a complete output image; S8: improving the quality of the spliced ​​image; S9: outputting the image.

[0011] As an optimization, in step S1, supported image formats include but are not limited to JPEG, PNG, and BMP.

[0012] As an optimization, in step S2, Gaussian filtering is used to denoise the image, and the formula is as follows:

[0013]

[0014] Among them, G(i,j) is the Gaussian kernel function;

[0015] Contrast adjustment makes the bright and dark areas of the image more distinct, using histogram equalization, the formula is as follows:

[0016]

[0017] Among them, rk and sk are the pixel values ​​of the original image and the equalized one respectively, nk is the number of pixels of gray level k, and n is the total number of pixels;

[0018] Normalization is used to adjust the image pixel values ​​to a range of values ​​(usually 0 to 1), using zero mean normalization, which is shown as follows:

[0019]

[0020] Among them, μ and σ are the mean and standard deviation of the image pixel values, respectively.

[0021] As an optimization, in step S3, the block size is determined according to the image size and the number of processing units.

[0022] As an optimization, when small blocks of the image are dynamically allocated to different processing units, a strategy is used to allocate tasks. During the processing, dynamic detection is implemented. If it is detected that a processing unit is overloaded, its unprocessed tasks are reallocated to other processing units with lighter loads. The strategies include polling scheduling, shortest queue priority, and load balancing strategy. Any one of them is used for allocation. Among them, polling scheduling is to allocate tasks to each processing unit in turn in a cycle. Short queue priority is to monitor the length of the task queue of each processing unit and give priority to allocating new tasks to the processing unit with the least tasks. The load balancing strategy is to make dynamic adjustments based on the real-time load conditions of the processing unit (such as CPU usage, memory usage, etc.) to ensure load balance.

[0023] As an optimization, in step S5, the processing unit includes but is not limited to a CPU core, a GPU, and a dedicated hardware accelerator.

[0024] As an optimization, in step S6, when monitoring each processing unit, a system monitoring tool is used to obtain the real-time status of each processing unit, including CPU usage, memory usage, and task queue length; and status data is collected regularly and fed back to the task scheduler; and the task allocation strategy is adjusted in real time based on the monitoring data.

[0025] As an optimization, in step S7, when merging, edge pixels need to be processed to ensure that there are no obvious traces in the spliced ​​image.

[0026] As an optimization, in step S8, the process of improving the image quality adopts methods including but not limited to edge pixel interpolation and image quality enhancement.

[0027] As an optimization, in step S9, the output image is output to a designated storage location or display device according to the instruction.

[0028] The present invention has the following effects:

[0029] 1) Significant performance improvement

[0030] By making full use of parallel computing resources, a near-linear acceleration ratio can be achieved in theory, and the processing speed is several to dozens of times faster than single-threaded serial processing, meeting real-time and high-throughput requirements.

[0031] 2) Good cost controllability

[0032] There is no need to purchase expensive GPU acceleration cards or dedicated acceleration chips. It can run on general hardware platforms (such as servers, workstations, etc.), reducing the overall system cost.

[0033] 3) Excellent scalability

[0034] Processing capabilities can be expanded at any time by increasing the number of CPU cores, GPU resources, etc. to meet the performance requirements of different application scenarios and avoid the fixed defects of dedicated acceleration hardware.

[0035] 4) Development-Friendliness

[0036] Developers only need to develop based on standard parallel programming interfaces (such as OpenMP, CUDA, etc.) without having to understand the underlying hardware details, which significantly reduces the difficulty of development.

[0037] 5) Wide range of application scenarios

[0038] It can be widely used in various image processing intensive fields such as intelligent video analysis, machine vision detection, medical image analysis, etc., providing strong support for the technological development in related fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 The present invention is a flowchart of an image processing acceleration method based on parallel acceleration. DETAILED DESCRIPTION

[0040] The present invention is further described in detail below in conjunction with the accompanying drawings. In the description of the present invention, it should be understood that the directions or positional relationships indicated by directional words such as "upper, lower" and "top, bottom" are usually based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description. Unless otherwise stated, these directional words do not indicate or imply that the devices or components referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present invention; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0041] like Figure 1 As shown, an image processing acceleration method based on parallel acceleration, S1: receiving image data from a user or other source; S2: pre-processing the image by denoising, contrast adjustment, and normalization; S3: image segmentation; S4: dynamically allocating small image blocks to different processing units according to system resources and load conditions; S5: each processing unit receives a small image block and starts parallel processing; S6: real-time monitoring of the working status of each processing unit in step S5, and dynamically adjusting task allocation; S7: collecting small block results processed by each processing unit, and using a merging algorithm to splice a complete output image; S8: improving the quality of the spliced ​​image; S9: outputting the image.

[0042] In this embodiment, in step S1, supported image formats include but are not limited to JPEG, PNG, and BMP.

[0043] In this embodiment, in step S2, Gaussian filtering is used to denoise the image, and the formula is as follows:

[0044]

[0045] Among them, G(i,j) is the Gaussian kernel function;

[0046] Contrast adjustment makes the bright and dark areas of the image more distinct, using histogram equalization, the formula is as follows:

[0047]

[0048] Among them, rk and sk are the pixel values ​​of the original image and the equalized one respectively, nk is the number of pixels of gray level k, and n is the total number of pixels;

[0049] Normalization is used to adjust the image pixel values ​​to a range of values ​​(usually 0 to 1), using zero mean normalization, which is shown as follows:

[0050]

[0051] Among them, μ and σ are the mean and standard deviation of the image pixel values, respectively.

[0052] In this embodiment, in step S3, the block size is determined according to the image size and the number of processing units.

[0053] Specifically, determining the block size includes the following steps:

[0054] A1: Get image and processing unit information;

[0055] A2: Calculate the initial block size;

[0056] A3: Adjust the tile size to fit the image size.

[0057] Specifically, in A1, obtain the width W and height H of the image; and obtain the number N of available processing units.

[0058] Specifically, in step A2, the calculation is performed according to the following process:

[0059] Calculate the pixel load P of each processing unit using the following formula:

[0060]

[0061] Calculate the side length S of the block using the following formula:

[0062]

[0063] Take the nearest integer as the width Sw and height Sh of the block, using the following formula:

[0064]

[0065] In this embodiment, in step S4, when the small blocks of the image are dynamically allocated to different processing units, a strategy is adopted to allocate tasks. During the processing, dynamic detection is implemented. When it is detected that the load of a processing unit is too high, its unprocessed tasks are reallocated to other processing units with lighter loads. The strategies include polling scheduling, shortest queue priority, and load balancing strategy. Any one of them is adopted for allocation. Among them, polling scheduling is to allocate tasks to each processing unit in turn in a cycle. Short queue priority is to monitor the length of the task queue of each processing unit and give priority to allocating new tasks to the processing unit with the least tasks. The load balancing strategy is to make dynamic adjustments according to the real-time load conditions of the processing unit (such as CPU utilization, memory utilization, etc.) to ensure load balance.

[0066] In this embodiment, in step S5, the processing unit includes but is not limited to a CPU core, a GPU, and a dedicated hardware accelerator.

[0067] In this embodiment, in step S6, when monitoring each processing unit, a system monitoring tool is used to obtain the real-time status of each processing unit, including CPU usage, memory usage, and task queue length; and status data is collected regularly and fed back to the task scheduler; and the task allocation strategy is adjusted in real time based on the monitoring data.

[0068] Specifically, when it is detected that a certain processing unit is overloaded, the reallocation of some of its tasks is initiated.

[0069] Specifically, the priority and allocation of the tasks are adjusted according to the priority of the tasks and the current status of the processing unit.

[0070] In this embodiment, in step S7, when merging, edge pixels need to be processed to ensure that the spliced ​​image has no obvious traces.

[0071] Specifically, after each processing unit processes a small block of the image, it returns the result to the central management unit (master control node); after the processing unit completes the task, it notifies the central management unit through a message queue or callback function; the central management unit maintains a result buffer to store all completed small block results.

[0072] Specifically, when merging:

[0073] If the image blocks do not overlap, they are directly stitched in order;

[0074] If there are overlapping areas in the image blocks, weighted averaging, transition fusion and other methods are used to process the overlapping areas to ensure seamless splicing of the images;

[0075] During the splicing process, the edges between blocks are smoothed to reduce splicing marks.

[0076] In this embodiment, in step S8, the process of improving the image quality adopts methods including but not limited to edge pixel interpolation and image quality enhancement.

[0077] Specifically, the stitched images may be post-processed by edge smoothing and denoising to improve image quality.

[0078] In this embodiment, in step S9, the output image is output to a designated storage location or display device according to the instruction.

[0079] The present invention has the following effects:

[0080] 1) Significant performance improvement

[0081] By making full use of parallel computing resources, a near-linear acceleration ratio can be achieved in theory, and the processing speed is several to dozens of times faster than single-threaded serial processing, meeting real-time and high-throughput requirements.

[0082] 2) Good cost controllability

[0083] There is no need to purchase expensive GPU acceleration cards or dedicated acceleration chips. It can run on general hardware platforms (such as servers, workstations, etc.), reducing the overall system cost.

[0084] 3) Excellent scalability

[0085] Processing capabilities can be expanded at any time by increasing the number of CPU cores, GPU resources, etc. to meet the performance requirements of different application scenarios and avoid the fixed defects of dedicated acceleration hardware.

[0086] 4) Development-Friendliness

[0087] Developers only need to develop based on standard parallel programming interfaces (such as OpenMP, CUDA, etc.) without having to understand the underlying hardware details, which significantly reduces the difficulty of development.

[0088] 5) Wide range of application scenarios

[0089] It can be widely used in various image processing intensive fields such as intelligent video analysis, machine vision detection, medical image analysis, etc., providing strong support for the technological development in related fields.

[0090] Finally, it should be noted that those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An image processing acceleration method based on parallel acceleration, characterized in that: The following steps are involved: S1: receiving image data from a user or other source; S2: Preprocess the image by denoising, contrast adjustment and normalization; S3: Image segmentation; S4: Dynamically allocate image blocks to different processing units based on system resources and load conditions; S5: Each processing unit receives a small image block and starts parallel processing; S6: monitor the working status of each processing unit in step S5 in real time and dynamically adjust task allocation; S7: Collect the small block results processed by each processing unit, and use a merging algorithm to stitch the complete output image; S8: Improve the quality of stitched images S9: Output image.

2. The image processing acceleration method based on parallel acceleration according to claim 1, characterized in that: In step S1, supported image formats include but are not limited to JPEG, PNG, and BMP.

3. The image processing acceleration method based on parallel acceleration according to claim 2, characterized in that: In step S2, Gaussian filtering is used to denoise the image, and the formula is as follows: Among them, G(i,j) is the Gaussian kernel function; Contrast adjustment makes the bright and dark areas of the image more distinct, using histogram equalization, the formula is as follows: Among them, rk and sk are the pixel values ​​of the original image and the equalized one respectively, nk is the number of pixels of gray level k, and n is the total number of pixels; Normalization is used to adjust the image pixel values ​​to a range of values ​​(usually 0 to 1), using zero mean normalization, which is shown as follows: Among them, μ and σ are the mean and standard deviation of the image pixel values, respectively.

4. The image processing acceleration method based on parallel acceleration according to claim 3, characterized in that: In step S3, the block size is determined according to the image size and the number of processing units.

5. The image processing acceleration method based on parallel acceleration according to claim 4, characterized in that: When dynamically allocating small image blocks to different processing units, a strategy is used to allocate tasks. During the processing, dynamic detection is implemented. When a processing unit is detected to be overloaded, its unprocessed tasks are reallocated to other processing units with lighter loads. The strategies include round-robin scheduling, shortest queue priority, and load balancing strategy. Any one of them is used for allocation. Among them, round-robin scheduling is to allocate tasks to each processing unit in turn in a cyclic allocation. Short queue priority is to monitor the length of the task queue of each processing unit and preferentially allocate new tasks to the processing unit with the least tasks. The load balancing strategy is to make dynamic adjustments based on the real-time load conditions of the processing unit (such as CPU usage, memory usage, etc.) to ensure load balancing.

6. The image processing acceleration method based on parallel acceleration according to claim 5, characterized in that: In step S5, the processing unit includes but is not limited to a CPU core, a GPU, and a dedicated hardware accelerator.

7. The image processing acceleration method based on parallel acceleration according to claim 6, characterized in that: In step S6, when monitoring each processing unit, a system monitoring tool is used to obtain the real-time status of each processing unit, including CPU usage, memory usage, and task queue length; And regularly collect status data and feed it back to the task scheduler; adjust the task allocation strategy in real time based on the monitoring data.

8. The image processing acceleration method based on parallel acceleration according to claim 7, characterized in that: In step S7, when merging, edge pixels need to be processed to ensure that there are no obvious traces in the spliced ​​image.

9. The image processing acceleration method based on parallel acceleration according to claim 8, characterized in that: In step S8, the process of improving the image quality adopts methods including but not limited to edge pixel interpolation and image quality enhancement.

10. The image processing acceleration method based on parallel acceleration according to claim 9, characterized in that: In step S9, the output image is output to a designated storage location or display device according to the instruction.

Images