Light-emitting control circuit, display panel and light-emitting control method

Abstract

The embodiment of the invention discloses a light-emitting control circuit, a display panel and a light-emitting control method, the light-emitting control circuit comprises a plurality of cascaded light-emitting control sub-circuits, each light-emitting control sub-circuit correspondingly controls a row of sub-pixels, each light-emitting control sub-circuit comprises two input ends and two output ends, wherein the first output end is used for outputting a stage transmission signal to the next-stage light-emitting control sub-circuit and outputting a light-emitting control signal to the sub-pixel, and the second output end is used for outputting the stage transmission signal to the next-stage light-emitting sub-circuit, so that the first output end of the next-stage light-emitting sub-circuit normally outputs the stage transmission signal and the light-emitting control signal.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a light-emitting control circuit, a display panel and a light-emitting control method. Background Art

[0002] The brightness of an organic light emitting diode (OLED) display panel can be adjusted by the duty cycle of a light emitting control signal. In the current light emitting control signal generation circuit, since the transistor cannot be completely turned off and leakage occurs, the output signal of the stage transmission cannot effectively output a low potential, which in turn causes the output light emitting control signal to be inconsistent with the input signal pulse width. Summary of the invention

[0003] The embodiments of the present application provide a light emitting control circuit, a display panel and a light emitting control method, so as to at least solve the problem that the pulse width of the output light emitting control signal does not match the pulse width of the input signal.

[0004] In a first aspect, an embodiment of the present application provides a light-emitting control circuit, comprising a plurality of cascaded light-emitting control sub-circuits, each of the light-emitting control sub-circuits corresponding to controlling a row of sub-pixels, and each of the light-emitting control sub-circuits comprising: a first control signal terminal, configured to receive a first clock signal; a second control signal terminal, configured to receive a second clock signal; a first input terminal, configured to receive a first input signal; a second input terminal, configured to receive a second input signal; a first output terminal, configured to output a first output signal to a first input terminal of a next-level light-emitting control sub-circuit and a pixel driving circuit of a corresponding sub-pixel; and a second output terminal, configured to output a second output signal to a second input terminal of a next-level light-emitting control sub-circuit; wherein the first clock signal and the second clock signal have opposite phases, the first input signal and the second input signal have opposite phases, and the first output signal and the second output signal have opposite phases.

[0005] In one embodiment, the light-emitting control subcircuit also includes: a pull-up unit, which is connected to a preset high potential, electrically connected to the first output terminal and the second output terminal, and connected to a first node, so as to turn on or off the path between the preset high potential and the first output terminal according to the potential of the first node; a pull-up control unit, which is electrically connected to the second input terminal, and is connected to the first clock signal and the second clock signal, so as to control the potential of the first node according to the first clock signal and the second input signal; a pull-down unit, which is connected to a preset low potential, and is electrically connected to the second node and the first output terminal, so as to turn on or off the path between the preset low potential and the first output terminal according to the potential of the second node; and a pull-down control unit, which is electrically connected to the first input terminal and the second node, and is connected to the first clock signal, so as to control the potential of the second node according to the first clock signal and the first input signal.

[0006] In one embodiment, the pull-up unit includes: a first transistor, including a control electrode connected to the first pull-up control unit and the second output terminal, a first electrode connected to the preset high potential, and a second electrode connected to the first output terminal; and a first capacitor, including a first end connected to the preset high potential and a second end connected to the control electrode of the first transistor.

[0007] In one embodiment, the pull-up control unit includes: a second transistor, including a control electrode connected to the first clock signal, a first electrode connected to the second input terminal, and a second electrode connected to the first node; a second capacitor, including a first terminal connected to the first node and a second terminal connected to a third node; a third transistor, including a control electrode connected to the first node, a first electrode connected to the second clock signal, and a second electrode connected to the third node; and a fourth transistor, including a control electrode connected to the second clock signal, a first electrode connected to the second output terminal, and a second electrode connected to the third node.

[0008] In one embodiment, the pull-down control unit includes: a fifth transistor including a control electrode connected to the first clock signal, a first electrode connected to the first input terminal, and a second electrode connected to the second node.

[0009] In one embodiment, the pull-down unit includes: a sixth transistor, including a control electrode connected to the second node, a first electrode connected to the preset low potential, and a second electrode connected to the first output terminal; a seventh transistor, including a control electrode connected to the second node, a first electrode connected to the second clock signal, and a second electrode connected to the fourth node; and a third capacitor, including a first end connected to the second node and a second end connected to the fourth node.

[0010] In one embodiment, the light emitting control subcircuit further includes: a pull-up maintaining transistor including a control electrode connected to the first node, a first electrode connected to the fourth node, and a second electrode connected to the preset high potential.

[0011] In one embodiment, the light emitting control subcircuit further includes: a pull-down sustaining transistor including a control electrode connected to the second node, a first electrode connected to the preset high potential, and a second electrode connected to the second output terminal.

[0012] In one embodiment, the light emitting control subcircuit further includes: a voltage dividing transistor including a control electrode connected to the preset low potential, a first electrode connected to the pull-down control unit, and a second electrode connected to the second node.

[0013] In one embodiment, the light emitting control subcircuit further includes: a first reset transistor, wherein a control electrode of the first reset transistor is connected to a reset signal, a first electrode is connected to the preset high potential, and a second electrode is connected to the second node.

[0014] In one embodiment, the light emitting control subcircuit further includes: a second reset transistor, wherein a control electrode of the second reset transistor is connected to a reset signal, a first electrode is connected to the preset high potential, and a second electrode is connected to the first output terminal.

[0015] In a second aspect, an embodiment of the present application further provides a display panel, comprising any of the light emitting control circuits described above.

[0016] In a third aspect, an embodiment of the present application further provides a light-emitting control method for controlling the above-mentioned display panel, the method comprising: inputting a first clock signal to a first control signal terminal, and inputting a second clock signal to a second control signal terminal; wherein the first clock signal and the second clock signal are inverted and have the same period, and are divided into time periods according to half a period of the first clock signal; in a first time period, a first input signal of a first potential is input to a first input terminal and a second input signal of a second potential is input to a second input terminal, so that the second output terminal outputs the second potential and the first output terminal outputs the first potential; in a second time period, the first input signal of the second potential is input to the first input terminal and the second input signal of the first potential is input to the second input terminal, so that the second output terminal outputs the second potential and the first output terminal outputs the first potential; in a third time period, the first input signal of the second potential is input to the first input terminal An input signal is input and the second input signal of the first potential is input to the second input terminal, so that the second output terminal outputs the first potential and the first output terminal outputs the second potential; in a fourth time period, the first input signal of the second potential is input to the first input terminal and the second input signal of the first potential is input to the second input terminal, so that the second output terminal outputs the first potential and the first output terminal outputs the second potential; in a fifth time period, the first input signal of the first potential is input to the first input terminal and the second input signal of the second potential is input to the second input terminal, so that the second output terminal outputs the first potential and the first output terminal outputs the second potential; in a sixth time period, the first input signal of the first potential is input to the first input terminal and the second input signal of the second potential is input to the second input terminal, so that the second output terminal outputs the first potential and the first output terminal outputs the second potential.

[0017] The beneficial effects provided by the embodiments of the present application include at least:

[0018] The embodiment of the present application provides a light-emitting control circuit, a display panel and a light-emitting control method, wherein the light-emitting control circuit includes a plurality of cascaded light-emitting control subcircuits, each light-emitting control subcircuit corresponding to a row of sub-pixels, and each light-emitting control subcircuit includes two input terminals and two output terminals, wherein the first output terminal is used to output a level transmission signal to the next level light-emitting control subcircuit and output a light-emitting control signal to the sub-pixel, and the second output terminal is used to output a level transmission signal to the next level light-emitting subcircuit so that the first output terminal of the next level light-emitting subcircuit normally outputs the level transmission signal and the light-emitting control signal. Through the setting of dual input and dual output, the problem of failure of the light-emitting control circuit due to the inability to effectively level transmit the level light-emitting control signal caused by transistor leakage is avoided, and the effectiveness and accuracy of the output signal of the light-emitting control circuit are effectively improved.

[0019] Other beneficial effects of the embodiments of the present application will be further described in the following specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic structural diagram of a display panel provided in an optional embodiment of the present application;

[0021] Figure 2 is a schematic diagram of a cascade structure of a light emitting control circuit provided in an optional embodiment of the present application;

[0022] Figure 3 is a structural schematic diagram of a light emitting control circuit provided in an optional embodiment of the present application;

[0023] Figure 4 is a timing diagram of a light emitting control method provided in an optional embodiment of the present application;

[0024] Figure 5 is a structural schematic diagram of another light emitting control circuit provided in an optional embodiment of the present application;

[0025] Figure 6 is a structural schematic diagram of another light emitting control circuit provided in an optional embodiment of the present application;

[0026] Figure 7 is a structural schematic diagram of another light emitting control circuit provided in an optional embodiment of the present application;

[0027] Figure 8 is a structural schematic diagram of another light emitting control circuit provided in an optional embodiment of the present application;

[0028] Fig. 9 is a structural schematic diagram of another light emitting control circuit provided in an optional embodiment of the present application;

[0029] Fig.10 It is a flow chart of a light emitting control method provided in an optional embodiment of the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0032] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0034] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. As another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of the embodiments of the present application.

[0035] The various embodiments provided in this application are similar, and features in different embodiments may be combined with each other.

[0036] The use of "configured to" in the embodiments of the present application is meant to be open and inclusive language, which does not exclude devices adapted for or configured to perform additional tasks or steps.

[0037] The order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0038] Reference Figure 1 As shown, an embodiment of the present application provides a display panel 1000, which can be integrated in a display device, which can be a TV, a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, etc., but is not limited thereto. A display panel refers to a component for displaying an image, which may include many pixel units, each of which may emit light, display a color, or reflect light to produce an image. The type of display panel can be set according to actual conditions. For example, the display panel may be a liquid crystal panel (LCD), an organic light-emitting diode panel (OLED), a mini light-emitting diode display panel (Mini-LED), or a micro light-emitting diode display panel (Micro-LED). The embodiments of the present application are not limited here. The pixel units included in the display panel may exist in the form of rows and / or columns.

[0039] The display panel 1000 includes an effective display area AA and a peripheral area NA located around the effective display area AA. A circuit board 1100 is provided in the peripheral area of ​​the display panel 1000 for providing a clock signal to the circuit inside the display panel 1000. The above-mentioned effective display area AA includes a plurality of sub-pixels 1500. For the convenience of explanation, the above-mentioned plurality of sub-pixels 1500 in the present application are described as an example of a matrix arrangement. In this case, the sub-pixels arranged in a row along the first direction (X direction) are called a row of sub-pixels, and the sub-pixels arranged in a row along the second direction (Y direction) are called a column of sub-pixels. A row of sub-pixels can be connected to a gate signal line GL and a light-emitting control signal line EM, and a column of sub-pixels can be connected to a data line DL, and the X direction intersects the Y direction perpendicularly.

[0040] Each sub-pixel 1500 may include a pixel driving circuit 1510 and a light emitting device 1520. The light emitting device 1520 may emit at least three primary colors, for example, red (Red, R), green (Green, G) and blue (Blue, B).

[0041] The display panel 1000 also includes a gate driving circuit 1200, a data driving circuit 1300 and a light emitting control circuit 1400 arranged in the NA region. The gate driving circuit 1200 includes a plurality of cascaded gate driving sub-circuits 1210, and the light emitting control circuit 1400 includes a plurality of cascaded light emitting control sub-circuits 1410. Each column of sub-pixels is connected to the data driving circuit 1300 via at least one DL, each row of sub-pixels is connected to at least one gate driving sub-circuit 1210 via at least one GL, and each row of sub-pixels is connected to at least one light emitting control sub-circuit 1410 via at least one EM. It should be noted that, according to different circuit application scenarios, a row of sub-pixels can be connected to two or three or more gate driving sub-circuits via two or three or more GLs, and a row of sub-pixels can be connected to two or three or more light emitting control sub-circuits via two or three or more EMs. Figure 1 Only one signal line is used as an example for illustrative description, which is not intended to limit the scope of the present application.

[0042] In some embodiments, the light emitting device 1520 may be an organic light emitting diode (OLED), and its luminous efficiency is positively correlated with the magnitude of the current (or current density) flowing through the light emitting device 1520. That is, when the magnitude of the current flowing through the light emitting device 1520 is small, the luminous efficiency of the light emitting device 1520 is low, and when the magnitude of the current flowing through the light emitting device 1520 is large, the luminous efficiency of the light emitting device 1520 is high. In order to improve the luminous efficiency of the light emitting device 1520 when displaying a low gray scale, the luminous time of the light emitting device 1520 may be modulated (i.e., pulse width modulation: Pulse Width Modulation, referred to as PWM) by the light control signal EM to change the luminous duty cycle of the light emitting device 1520 within a frame, thereby shortening the luminous time of the light emitting device 1520. By shortening the luminous time of the light emitting device 1520 and increasing the magnitude of the current flowing through the light emitting device 1520 during the luminous process of the light emitting device 1520, the luminous efficiency of the light emitting device 1520 may be improved.

[0043] The pixel driving circuit 1510 , the gate driving circuit 1200 , and the data driving circuit 1300 in the embodiment of the present application can be implemented using any circuit in the art that can realize corresponding functions, and will not be elaborated on in detail.

[0044] Reference Figure 2As shown, an embodiment of the present application provides a light emitting control circuit, including a plurality of cascaded light emitting control subcircuits (EM subcircuits) 1410, each of which controls a row of subpixels. For the sake of simplicity, the following signal ports and corresponding received or transmitted signals are described using the same reference numerals, for example, the first control signal terminal and the first clock signal are both represented by CK, and the second control signal terminal and the second clock signal are both represented by XCK.

[0045] Each light-emitting control subcircuit 1410 includes: a first control signal terminal CK, configured to receive a first clock signal CK; a second control signal terminal XCK, configured to receive a second clock signal XCK; a first input terminal IN1, configured to receive a first input signal IN1 (wherein the first-stage EM subcircuit receives a frame start signal STV1); a second input terminal IN2, configured to receive a second input signal IN2 (wherein the first-stage EM subcircuit receives a frame start signal STV2); a first output terminal OUT1, configured to output a first output signal OUT1 to a first input terminal of a next-stage light-emitting control subcircuit and a pixel driving circuit of a corresponding sub-pixel; and a second output terminal OUT2, configured to output a second output signal OUT2 to a second input terminal of a next-stage light-emitting control subcircuit. For example, the first-stage EM subcircuit is E1, the second-stage EM subcircuit is E2, and the third-stage EM subcircuit is E3. The input signals received by E1 are STV1 and STV2 respectively, and the output signals are out11 and out12, wherein out11 is respectively input to the first input terminal in21 of E2 and the light-emitting signal control terminal of the first row of sub-pixels, and out12 is input to the second input terminal in22 of E2. The signals output by E2 are out21 and out22, wherein out21 is respectively input to the first input terminal in31 of E3 and the light-emitting signal control terminal of the second row of sub-pixels, and out22 is input to the second input terminal in32 of E3.

[0046] The first clock signal CK and the second clock signal XCK have opposite phases, the first input signal IN1 and the second input signal IN2 have opposite phases, the second output terminal outputs the second output signal OUT2 according to the two clock signals and the two input signals, the first output terminal outputs the first output signal OUT1 according to the two clock signals, the two input signals and the second output signal OUT2, and the phases of OUT1 and OUT2 are opposite.

[0047] In summary, the light-emitting control circuit provided in the embodiment of the present application includes a plurality of cascaded light-emitting control subcircuits, each light-emitting control subcircuit corresponding to a row of sub-pixels, and each light-emitting control subcircuit includes two input terminals and two output terminals, wherein the first output terminal is used to output a level transmission signal to the next level light-emitting control subcircuit and output a light-emitting control signal to the sub-pixel, and the second output terminal is used to output a level transmission signal to the next level light-emitting subcircuit so that the first output terminal of the next level light-emitting subcircuit can normally output the level transmission signal and the light-emitting control signal. Through the setting of dual input and dual output, the light-emitting control subcircuit realizes level transmission through the output signal, and through the inverted setting of the two output signals, OUT1 can directly turn on the pull-up transistor under the action of OUT2 to realize the output of a preset high potential, and then output the EM signal to the sub-pixel, thereby avoiding the problem that the light-emitting control signal cannot be effectively level-transmitted due to the leakage of some transistors in the light-emitting control circuit, thereby causing failure, and effectively improving the effectiveness and accuracy of the output signal of the light-emitting control circuit.

[0048] Reference Figure 3 As shown, in one embodiment, the light-emitting control subcircuit 1410 further includes: a pull-up unit 1411, which is connected to a preset high potential VGH, electrically connected to the first output terminal OUT1 and the second output terminal OUT1, and connected to the first node N1, so as to turn on or off the path between the preset high potential VGH and the first output terminal OUT1 according to the potential of the first node N1; a pull-up control unit 1412, which is electrically connected to the second input terminal OUT2, and is connected to the first clock signal CK and the second clock signal XCK, so as to control the potential of the first node N1 according to the first clock signal CK and the second input signal IN2; a pull-down unit 1414, which is connected to a preset low potential VGL, and is electrically connected to the second node N2 and the first output terminal OUT1, so as to turn on or off the path between the preset low potential VGL and the first output terminal OUT1 according to the potential of the second node N2; and a pull-down control unit 1413, which is electrically connected to the first input terminal OUT1 and the second node N2, and is connected to the first clock signal CK, so as to control the potential of the second node N2 according to the first clock signal CK and the first input signal IN1.

[0049] It should be noted that the transistors used in all embodiments of the present application may be thin film transistors (TFT), field effect transistors (MOS), or other devices with the same characteristics, and the embodiments of the present application are not limited to this.

[0050] Exemplarily, the transistor may be a TFT. The TFT may be manufactured using an a-Si process, an oxide semiconductor process, a low temperature polysilicon (LTPS) process, or a high temperature polysilicon (HTPS) process. The embodiments of the present application are not limited thereto.

[0051] The embodiments of the present application do not limit the type of transistor. The transistor may be an N-type transistor, or a P-type transistor, or an enhancement-type transistor, or a depletion-type transistor. In the embodiments of the present application, the present application is exemplarily described by taking all transistors as P-type transistors as an example. The P-type transistor is turned on by a low-level voltage signal and turned off by a high-level voltage signal; that is, the operating voltage of the P-type transistor is a low-level voltage, and the turn-off voltage is a high-level voltage.

[0052] In the embodiments of the present application, the gate of the transistor is the control electrode. At the same time, in order to distinguish the two electrodes of the transistor other than the gate, one of the electrodes is directly described as the first electrode and the other electrode is the second electrode. At this time, the first electrode of the transistor can be one of the source and the drain of the transistor, and the second electrode can be the other of the source and the drain of the transistor. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain can be indistinguishable in structure.

[0053] The capacitor in the embodiment of the present application can be a capacitor device made separately through a process, for example, a capacitor device is realized by making a special capacitor electrode, and each capacitor electrode (first plate and second plate) of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. The capacitor can also be a parasitic capacitor between transistors, or realized by the transistor itself and other devices and circuits, or by using the parasitic capacitor between the circuits of the circuit itself.

[0054] Each of the above transistors may also include at least one switch connected in parallel with each of the transistors. The embodiments of the present application are merely examples of the pixel driving circuit and the gate driving circuit, and other structures with the same functions as the pixel driving circuit and the gate driving circuit are not described one by one, but should all fall within the protection scope of the present application.

[0055] The “first node”, “second node”, etc. in the embodiments of the present application do not represent actual existing components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0056] In one embodiment, the pull-up unit 1411 includes: a first transistor T1, including a control electrode connected to the first pull-up control unit 1412 and the second output terminal OUT2, a first electrode connected to a preset high potential, and a second electrode connected to the first output terminal OUT1; and a first capacitor C1, including a first terminal connected to a preset high potential VGH and a second terminal connected to the control electrode of the first transistor T1. T1 in the pull-up unit 1411 is turned on when the gate potential is low, and VGH can be transmitted to OUT1, that is, OUT1 outputs a high potential.

[0057] In one embodiment, the pull-up control unit 1412 includes: a second transistor T2, including a control electrode connected to the first clock signal CK, a first electrode connected to the second input terminal IN2, and a second electrode connected to the first node N1; a second capacitor C2, including a first end connected to the first node N1 and a second end connected to the third node N3; a third transistor T3, including a control electrode connected to the first node N1, a first electrode connected to the second clock signal XCK, and a second electrode connected to the third node N3; and a fourth transistor T4, including a control electrode connected to the second clock signal XCK, a first electrode connected to the second output terminal OUT2, and a second electrode connected to the third node N3. When CK is low, T2 is turned on, when IN2 is high, the potential of the N1 node is high, C2 stores electric energy, when XCK is low, T4 is turned on, so that the high potential is transmitted to T1, T1 is turned off, the path between VGH and OUT1 is turned off, and at the same time, IN1 is low, the potential of the N2 node is low, T6 is turned on, and OUT1 outputs VGL, that is, OUT1 outputs a low potential.

[0058] In one embodiment, the pull-down control unit 1413 includes: a fifth transistor T5 including a control electrode connected to the first clock signal CK, a first electrode connected to the first input terminal IN1, and a second electrode connected to the second node N2.

[0059] In one embodiment, the pull-down unit 1414 includes: a sixth transistor T6, including a control electrode connected to the second node N2, a first electrode connected to a preset low potential VGL, and a second electrode connected to the first output terminal OUT1; a seventh transistor T7, including a control electrode connected to the second node N2, a first electrode connected to the second clock signal XCK, and a second electrode connected to the fourth node N4; and a third capacitor C3, including a first end connected to the second node N2 and a second end connected to the fourth node N4.

[0060] In one embodiment, the light emitting control subcircuit 1410 further includes: a pull-up maintaining transistor T8 including a control electrode connected to the first node N1, a first electrode connected to the fourth node N4, and a second electrode connected to a preset high potential VGH.

[0061] In one embodiment, the light emitting control subcircuit 1410 further includes: a pull-down sustaining transistor T9 including a control electrode connected to the second node N2, a first electrode connected to a preset high potential VGH, and a second electrode connected to the second output terminal OUT.

[0062] Reference Figure 4 As shown, the working sequence of the above-mentioned light-emitting control subcircuit 1410 when receiving an input signal may include 6 time periods, each of which corresponds to half a cycle of the clock signal.

[0063] In the first time period t1, the first clock signal is at a high level, the second clock signal is at a low level, the first input signal is at a low level, the second input signal is at a high level, the second node is at a low potential, the pull-up sub-circuit cuts off the path between the preset high potential and the first output terminal, the pull-down sub-circuit turns on the path between the preset low potential and the first output terminal, the second output terminal outputs a high level, and the first output terminal outputs a low level.

[0064] In the second time period t2, the first clock signal is at a low level, the second clock signal is at a high level, the first input signal is at a high level, the second input signal is at a low level, the first node is at a low potential, the second node is at a high potential, the second output terminal maintains an output high level, and the first output terminal maintains an output low level.

[0065] In the third time period t3, the first clock signal is high, the second clock signal is low, the first input signal is high, the second input signal is low, the second output terminal outputs a low level, the second node is high potential, and the first output terminal outputs a high level.

[0066] In the fourth time period t4, the first clock signal is at a low level, the second clock signal is at a high level, the first input signal is at a high level, the second input signal is at a low level, the first node is at a low potential, the second node is at a high potential, the second output terminal outputs a high level, and the first output terminal outputs a low level.

[0067] In the fifth time period t5, the first clock signal is high, the second clock signal is low, the first input signal is low, the second input signal is high, the second output terminal outputs a low level, the second node is high potential, and the first output terminal outputs a high level.

[0068] In the sixth time period t6, the first clock signal is low, the second clock signal is high, the first input signal is low, the second input signal is high, the second node is low potential, the second output terminal outputs a high level, and the first output terminal outputs a low level.

[0069] If no new input signal is received during the t7 period, the state of the t6 period is maintained.

[0070] Reference Figure 5 As shown, in one embodiment, the light emitting control subcircuit 1410 further includes: a voltage dividing transistor T10 including a control electrode connected to a preset low potential VGL, a first electrode connected to the pull-down control unit, and a second electrode connected to the second node N2.

[0071] Among them, the gate of T10 is always connected to VGL, so T10 is in a normally open state, that is, a conducting state. When the potential of N2 is very low, the voltage transmitted to T5 is the potential of N4 minus the threshold voltage of T10, which can effectively reduce the source-drain voltage difference of T5 and avoid failure of T5 due to excessive source-drain voltage difference.

[0072] Reference Figure 6 As shown, in one embodiment, the light emitting control subcircuit 1410 further includes: a first reset transistor T11, the control electrode of the first reset transistor T11 is connected to the reset signal RST, the first electrode is connected to the preset high potential VGH, and the second electrode is connected to the second node N2.

[0073] When RST is turned on, the N2 node is directly pulled high, and the OUT1 output is high, which can force all the light-emitting control sub-circuits to output high potentials, so that the display area does not display. It is usually used in the power-on and power-off stages of the display to avoid screen flickering caused by unstable power-on and power-off timing.

[0074] Reference Figure 7 As shown, in one embodiment, T10 and T11 can coexist in the same circuit.

[0075] Reference Figure 8 As shown, in one embodiment, the light emitting control subcircuit further includes: a second reset transistor T12, the control electrode of the second reset transistor is connected to the reset signal, the first electrode is connected to the preset high potential VGH, and the second electrode is connected to the first output terminal OUT1.

[0076] When RST is turned on, OUT1 outputs high, which can force all the light-emitting control subcircuits to output high potential, so that the display area does not display. It is usually used in the power-on and power-off stages of the display to avoid screen flickering caused by unstable power-on and power-off timing.

[0077] Reference Fig. 9As shown, in one embodiment, T10 and T12 can coexist in the same circuit.

[0078] Reference Fig.10 As shown, through the light-emitting control circuit provided by any of the above embodiments of the present application, the EM signal output by OUT1 of the last stage is consistent with the initial input signal pulse width and is a valid output signal.

[0079] According to another embodiment of the present application, a light emitting control method is also provided, which is applied to the light emitting control circuit described in any of the above embodiments to control the above display panel 1000. The circuit structure that has been described is not repeated here. The method includes:

[0080] Step S1101, inputting a first clock signal to a first control signal terminal, and inputting a second clock signal to a second control signal terminal; wherein the first clock signal and the second clock signal are inverted and have the same period, and the time period is divided according to half of the period of the first clock signal;

[0081] Step S1102, in a first time period, inputting a first input signal of a first potential to the first input terminal and inputting a second input signal of a second potential to the second input terminal, so that the second output terminal outputs the second potential and the first output terminal outputs the first potential;

[0082] Step S1103, in a second time period, inputting the first input signal of the second potential to the first input terminal and inputting the second input signal of the first potential to the second input terminal, so that the second output terminal outputs the second potential and the first output terminal outputs the first potential;

[0083] Step S1104, in a third time period, inputting the first input signal of the second potential to the first input terminal and inputting the second input signal of the first potential to the second input terminal, so that the second output terminal outputs the first potential and the first output terminal outputs the second potential;

[0084] Step S1105, in a fourth time period, inputting the first input signal of the second potential to the first input terminal and inputting the second input signal of the first potential to the second input terminal, so that the second output terminal outputs the first potential and the first output terminal outputs the second potential;

[0085] Step S1106, in a fifth time period, inputting the first input signal of the first potential to the first input terminal and inputting the second input signal of the second potential to the second input terminal, so that the second output terminal outputs the first potential and the first output terminal outputs the second potential;

[0086] Step S1107, in a sixth time period, input the first input signal of the first potential to the first input terminal and input the second input signal of the second potential to the second input terminal, so that the second output terminal outputs the first potential and the first output terminal outputs the second potential.

[0087] The embodiment of the present application provides a light-emitting control circuit, a display panel and a light-emitting control method, wherein the light-emitting control circuit includes a plurality of cascaded light-emitting control subcircuits, each light-emitting control subcircuit corresponding to a row of sub-pixels, and each light-emitting control subcircuit includes two input terminals and two output terminals, wherein the first output terminal is used to output a level transmission signal to the next level light-emitting control subcircuit and output a light-emitting control signal to the sub-pixel, and the second output terminal is used to output a level transmission signal to the next level light-emitting subcircuit so that the first output terminal of the next level light-emitting subcircuit normally outputs the level transmission signal and the light-emitting control signal. Through the setting of dual input and dual output, the problem of failure of the light-emitting control circuit due to the inability to effectively level transmit the level light-emitting control signal caused by transistor leakage is avoided, and the effectiveness and accuracy of the output signal of the light-emitting control circuit are effectively improved.

[0088] In the embodiments of the present application, specific examples are used to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

[0089] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A light emitting control circuit, characterized in that: The light emitting control circuit includes a plurality of cascaded light emitting control sub-circuits, each of which controls a row of sub-pixels, and each of which includes: A first control signal terminal configured to receive a first clock signal; A second control signal terminal configured to receive a second clock signal; A first input terminal configured to receive a first input signal; A second input terminal configured to receive a second input signal; A first output terminal configured to output a first output signal to a first input terminal of a light emitting control sub-circuit of a next stage and a pixel driving circuit of a corresponding sub-pixel; and A second output terminal is configured to output a second output signal to a second input terminal of a next-level light-emitting control subcircuit; The first clock signal and the second clock signal have opposite phases, the first input signal and the second input signal have opposite phases, and the first output signal and the second output signal have opposite phases.

2. The light emitting control circuit according to claim 1, characterized in that: The light emitting control subcircuit further includes: a pull-up unit connected to a preset high potential, electrically connected to the first output terminal and the second output terminal, and connected to a first node, so as to turn on or off a path between the preset high potential and the first output terminal according to the potential of the first node; A pull-up control unit, electrically connected to the second input terminal and connected to the first clock signal and the second clock signal, so as to control the potential of the first node according to the first clock signal and the second input signal; a pull-down unit connected to a preset low potential and electrically connected to a second node and the first output terminal, so as to open or close a path between the preset low potential and the first output terminal according to the potential of the second node; and The pull-down control unit is electrically connected to the first input terminal and the second node and receives the first clock signal to control the potential of the second node according to the first clock signal and the first input signal.

3. The light emitting control circuit according to claim 2, characterized in that: The pull-up unit comprises: A first transistor includes a control electrode connected to the first pull-up control unit and the second output terminal, a first electrode connected to the preset high potential, and a second electrode connected to the first output terminal; and The first capacitor includes a first end connected to the preset high potential and a second end connected to the control electrode of the first transistor.

4. The light emitting control circuit according to claim 2, characterized in that: The pull-up control unit comprises: A second transistor includes a control electrode connected to the first clock signal, a first electrode connected to the second input terminal, and a second electrode connected to the first node; a second capacitor including a first end connected to the first node and a second end connected to a third node; a third transistor including a control electrode connected to the first node, a first electrode connected to the second clock signal, and a second electrode connected to the third node; and The fourth transistor includes a control electrode connected to the second clock signal, a first electrode connected to the second output terminal, and a second electrode connected to the third node.

5. The light emitting control circuit according to claim 2, characterized in that: The pull-down control unit comprises: The fifth transistor includes a control electrode connected to the first clock signal, a first electrode connected to the first input terminal, and a second electrode connected to the second node.

6. The light emitting control circuit according to claim 2, characterized in that: The pull-down unit comprises: a sixth transistor, comprising a control electrode connected to the second node, a first electrode connected to the preset low potential, and a second electrode connected to the first output terminal; a seventh transistor, comprising a control electrode connected to the second node, a first electrode connected to the second clock signal, and a second electrode connected to the fourth node; and The third capacitor includes a first end connected to the second node and a second end connected to the fourth node.

7. The light emitting control circuit according to claim 6, characterized in that: The light emitting control subcircuit further includes: The pull-up maintaining transistor includes a control electrode connected to the first node, a first electrode connected to the fourth node, and a second electrode connected to the preset high potential.

8. The light emitting control circuit according to claim 2, characterized in that: The light emitting control subcircuit further includes: The pull-down maintaining transistor includes a control electrode connected to the second node, a first electrode connected to the preset high potential, and a second electrode connected to the second output terminal.

9. The light emitting control circuit according to claim 2, characterized in that: The light emitting control subcircuit further includes: The voltage-dividing transistor includes a control electrode connected to the preset low potential, a first electrode connected to the pull-down control unit, and a second electrode connected to the second node.

10. The light emitting control circuit according to claim 2, characterized in that: The light emitting control subcircuit further includes: A first reset transistor, wherein a control electrode of the first reset transistor is connected to a reset signal, a first electrode is connected to the preset high potential, and a second electrode is connected to the second node.

11. The light emitting control circuit according to claim 2, characterized in that: The light emitting control subcircuit further includes: A second reset transistor, wherein a control electrode of the second reset transistor is connected to the reset signal, a first electrode is connected to the preset high potential, and a second electrode is connected to the first output terminal.

12. A display panel, characterized in that: The light emitting control circuit comprises the light emitting control circuit according to any one of claims 1 to 11.

13. A light emission control method, characterized in that: For controlling the display panel according to claim 12, the method comprises: Input a first clock signal to the first control signal terminal, and input a second clock signal to the second control signal terminal; wherein the first clock signal and the second clock signal are inverted and have the same period, and the time period is divided according to half of the period of the first clock signal; In a first period, a first input signal of a first potential is input to the first input terminal and a second input signal of a second potential is input to the second input terminal, so that the second output terminal outputs the second potential and the first output terminal outputs the first potential; In a second period, the first input signal of a second potential is input to the first input terminal and the second input signal of a first potential is input to the second input terminal, so that the second output terminal outputs the second potential and the first output terminal outputs the first potential; In a third period, the first input signal of the second potential is input to the first input terminal and the second input signal of the first potential is input to the second input terminal, so that the second output terminal outputs the first potential and the first output terminal outputs the second potential; In a fourth period, the first input signal of the second potential is input to the first input terminal and the second input signal of the first potential is input to the second input terminal, so that the second output terminal outputs the first potential and the first output terminal outputs the second potential; In a fifth period, the first input signal of the first potential is input to the first input terminal and the second input signal of the second potential is input to the second input terminal, so that the second output terminal outputs the first potential and the first output terminal outputs the second potential; In a sixth period, the first input signal of a first potential is input to the first input terminal and the second input signal of a second potential is input to the second input terminal, so that the second output terminal outputs the first potential and the first output terminal outputs the second potential.

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