Chip packaging method, semiconductor packaging assembly and chip packaging assembly

Abstract

The invention discloses a chip packaging method, a semiconductor packaging assembly and a chip packaging assembly. The chip packaging method comprises the steps of obtaining a lead frame; the lead frame comprises a plurality of chip base islands and a plurality of base island connecting ribs, and the plurality of chip base islands are connected through the base island connecting ribs; a cutting channel is arranged between the adjacent chip base islands, and the width of the cutting channel is less than or equal to 0.1 mm; mounting a chip on each chip base island; performing plastic package on the plurality of chips and the lead frame to form a plastic package body; the plastic package body covers the plurality of chips, the plurality of chip base islands and the plurality of base island connecting ribs; a first conductive column is formed between the plastic package body and the surface of the side, away from the chip base island, of the chip, and a first conductive circuit covering the first conductive column is formed on the surface of the side, close to the chip, of the plastic package body, so that the chip is electrically connected with the first conductive circuit; and cutting the lead frame based on the cutting channels to obtain a plurality of chip packaging assemblies. According to the invention, the jointed board utilization rate of the lead frame and the yield of packaged products can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a chip packaging method, a semiconductor packaging component, and a chip packaging component. Background Art

[0002] The rib cutting process is an important step in semiconductor packaging technology, which refers to separating the packaging units on the lead frame.

[0003] In the prior art, the lead frame usually includes a chip base island, base island connecting ribs, chip pads, pin connecting ribs, dams and cutting paths. The dams are metal grids arranged on the periphery of the chip base island and are located in the cutting paths. The base island connecting ribs are used to connect the chip base island and the dams. The pin connecting ribs are used to connect the pads and the dams so that the chip base island and the pads are electrically connected. After each chip is packaged, the cutting paths are cut by a rib cutting process to remove the dams at the same time during cutting, thereby obtaining a single chip package assembly.

[0004] However, the dam usually has a preset width, and the cutting path needs to set a cutting margin while covering the dam width. On the one hand, this results in a larger cutting path width, thereby reducing the panel utilization rate of the lead frame; on the other hand, larger burrs are generated during the cutting process, resulting in a lower yield of the sealed product. Summary of the invention

[0005] The main technical problem solved by the present application is to provide a chip packaging method, a semiconductor packaging component and a chip packaging component, which can solve the problems of low panel utilization and low packaging product yield caused by existing packaging methods.

[0006] To solve the above technical problems, the first technical solution adopted in the present application is to provide a chip packaging method, comprising: obtaining a lead frame; wherein the lead frame comprises a plurality of chip base islands and a plurality of base island connecting ribs, and the plurality of chip base islands are connected by the base island connecting ribs; a cutting path is arranged between adjacent chip base islands, and the width of the cutting path is less than or equal to 0.1 mm; a chip is mounted on each chip base island; a plurality of chips and a lead frame are plastic-sealed to form a plastic-sealed body; wherein the plastic-sealed body covers a plurality of chips, a plurality of chip base islands and a plurality of base island connecting ribs; a first conductive column is formed between the plastic-sealed body and a surface of the chip on one side away from the chip base island, and a first conductive circuit covering the first conductive column is formed on a surface of the plastic-sealed body on a side close to the chip, so that the chip is electrically connected to the first conductive circuit; the lead frame is cut based on the cutting path to obtain a plurality of chip packaging components.

[0007] The step of obtaining the lead frame includes: obtaining a metal substrate of a preset thickness; wherein the preset thickness is 100 to 210 μm; etching the metal substrate to form a plurality of chip base islands and a plurality of base island connecting ribs.

[0008] Among them, after etching the metal substrate to form multiple chip base islands and multiple base island connecting ribs, it includes: half-etching the base island connecting ribs to form a half-etched structure; wherein the thickness of the half-etched structure is 40% to 60% of the thickness of the chip base island.

[0009] Among them, the steps of forming a first conductive column and a first conductive circuit on the plastic package, and connecting the first conductive column to the pin of the chip and the first conductive circuit respectively so that the chip is electrically connected to the first conductive circuit include: drilling the plastic package, drilling through the plastic package until the chip is exposed to form a first blind hole; forming a first conductive column in the first blind hole, and forming a first conductive circuit covering the first conductive column on a side surface of the plastic package close to the chip.

[0010] Among them, the steps of forming a first conductive column in the first blind hole and forming a first conductive circuit covering the first conductive column on the surface of the plastic package body close to the chip include: forming a first conductor film on the bottom and wall of the first blind hole and on the surface of the plastic package body close to the chip; electroplating the entire plate with the first conductor film to form the first conductive column in the first blind hole and a first conductive layer on the surface of the plastic package body close to the chip; and pattern etching the first conductive layer to form a first conductive circuit.

[0011] Among them, after the steps of forming a first conductive column in the first blind hole and forming a first conductive circuit covering the first conductive column on a side surface of the plastic package body close to the chip, the method includes: forming an insulating layer on a side surface of the first conductive circuit away from the chip and a side surface of the plastic package body close to the chip; drilling the insulating layer to drill through the insulating layer until the first conductive circuit is exposed to form a second blind hole; forming a second conductive column in the second blind hole, and forming a second conductive circuit covering the second conductive column on a side surface of the insulating layer away from the first conductive circuit to electrically connect the chip to the second conductive circuit.

[0012] After the steps of forming a second conductive column in the second blind hole and forming a second conductive circuit on a surface of the insulating layer away from the first conductive circuit, the method further comprises: forming a protective layer on the second conductive circuit.

[0013] In order to solve the above technical problems, the second technical solution adopted by the present application is to provide a semiconductor packaging component, including: a lead frame, including multiple chip base islands and multiple base island connecting ribs, and multiple chip base islands are connected by base island connecting ribs; a cutting path is set between adjacent chip base islands, and the width of the cutting path is less than or equal to 0.1mm; multiple chips are respectively set on each chip base island; a plastic package body, covering multiple chips, multiple chip base islands and multiple base island connecting ribs; a first blind hole is set on the plastic package body, and the bottom of the first blind hole is the side surface of the chip away from the chip base island; a first conductive column is set in the first blind hole and connected to the pin of the chip; a first conductive circuit is set on the side surface of the plastic package body close to the chip and covers the first conductive column. Wherein, the chip and the first conductive circuit are electrically connected through the first conductive column.

[0014] To solve the above technical problems, the third technical solution adopted in the present application is to provide a chip packaging component, including: a chip base island; wherein base island connecting ribs are arranged on the periphery of the chip base island; a chip, which is arranged on the chip base island; a plastic package, which covers the chip, the chip base island and the base island connecting ribs; a first blind hole, which is arranged on the plastic package, and the bottom of the first blind hole is the side surface of the chip away from the chip base island; a first conductive column, which is arranged in the first blind hole and connected to the pin of the chip; a first conductive circuit, which is arranged on the side surface of the plastic package close to the chip and covers the first conductive column; wherein the chip and the first conductive circuit are electrically connected through the first conductive column.

[0015] The chip packaging assembly further includes: an insulating layer, which is arranged on a side surface of the first conductive circuit away from the chip and on a side surface of the plastic package body close to the chip; a second blind hole, which is arranged on the insulating layer, and the bottom of the second blind hole is the first conductive circuit; a second conductive column, which is arranged in the second blind hole; a second conductive circuit, which is arranged on a side surface of the insulating layer away from the first conductive circuit and covers the second conductive column; wherein the chip and the second conductive circuit are electrically connected through the first conductive column, the first conductive circuit and the second conductive column; and a protective layer, which covers the second conductive circuit.

[0016] The beneficial effects of the present application are as follows: Different from the prior art, the present application provides a chip packaging method, a semiconductor packaging component, and a chip packaging component. By making the lead frame include multiple chip base islands and multiple base island connecting ribs, and connecting the multiple chip base islands through the base island connecting ribs, a dam-free lead frame can be formed, so that the width of the cutting path is not limited by the dam, thereby effectively reducing the width of the cutting path, and then improving the panel utilization rate of the lead frame. Furthermore, since the width of the cutting path is less than or equal to 0.1 mm, the friction between the blade and the cutting path can be reduced during cutting, thereby reducing the generation of burrs, and then improving the yield of the packaged product. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 It is a schematic diagram of the process of the first implementation mode of the chip packaging method of the present application;

[0019] Figure 2 It is a schematic flow chart of the second embodiment of the chip packaging method of the present application;

[0020] Figure 3 is a top view of an implementation mode of the lead frame obtained in S203;

[0021] Figure 4 yes Figure 3 Schematic diagram of the cross-sectional structure of the lead frame along line AA;

[0022] Figure 5 is a structural schematic diagram of an implementation method of a packaging structure obtained in S204;

[0023] Figure 6 is a structural schematic diagram of an implementation method of a packaging structure obtained in S206;

[0024] Figure 7 is a structural schematic diagram of an implementation method of a packaging structure obtained in S207;

[0025] Figure 8 is a structural schematic diagram of an implementation method of a packaging structure obtained in S209;

[0026] Fig. 9 It is a structural schematic diagram of an embodiment of a semiconductor packaging assembly of the present application;

[0027] Fig.10 Based on the cutting path Fig. 9 Schematic diagram of cutting a semiconductor package component;

[0028] Fig.11 It is a schematic structural diagram of an implementation scheme of a chip packaging assembly of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0030] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless otherwise clearly indicated above, and "multiple" generally includes at least two, but does not exclude the inclusion of at least one.

[0031] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0032] It should be understood that the terms "include", "comprises" or any other variations used herein are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "includes..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0033] In the prior art, the lead frame usually includes a chip base island, a base island connecting rib, a chip pad, a pin connecting rib, a dam and a cutting path. The dam is a metal grid arranged on the peripheral side of the chip base island and is located in the cutting path. The base island connecting rib is used to connect the chip base island and the dam, and the pin connecting rib is used to connect the pad and the dam, so that the chip base island and the pad are electrically connected. After the packaging of each chip is completed, the cutting path is cut by a rib cutting process to remove the dam at the same time during cutting, thereby obtaining a single chip package assembly. However, the dam usually has a preset width (0.16 to 0.18 mm), and the cutting path needs to set a cutting margin (related to the cutting blade width and the cutting machine accuracy) while covering the dam width. On the one hand, the width of the cutting path is large (greater than or equal to 0.3 mm), thereby reducing the utilization rate of the lead frame panel; on the other hand, large burrs will be generated during the cutting process, resulting in a low yield of the sealed product.

[0034] Based on the above situation, the present application provides a chip packaging method, a semiconductor packaging component and a chip packaging component, which can solve the problems of low panel utilization and low packaging product yield caused by existing packaging methods.

[0035] The present application is described in detail below with reference to the accompanying drawings and implementation methods.

[0036] See also Figure 1 , Figure 1 1 is a flow chart of a first embodiment of a chip packaging method of the present application. In this embodiment, the method includes:

[0037] S11: Obtain a lead frame; wherein the lead frame includes a plurality of chip base islands and a plurality of base island connecting ribs, and the plurality of chip base islands are connected by the base island connecting ribs; a cutting path is arranged between adjacent chip base islands, and a width of the cutting path is less than or equal to 0.1 mm.

[0038] In this embodiment, the lead frame is a frame obtained by etching a metal substrate.

[0039] In some embodiments, the metal substrate is a copper substrate.

[0040] In this embodiment, the chip island is a region for mounting a chip, and the island connecting rib is a connecting portion connecting adjacent chip islands.

[0041] In this embodiment, the cutting lines are located between adjacent chip islands, and the lead frame is cut along the cutting lines to obtain a single chip island.

[0042] It can be understood that since the lead frame in this embodiment is a dam-free design, the cutting path is only affected by the width of the cutting blade and the accuracy of the cutting machine, and is not limited by the dam. Therefore, the width of the cutting path can be reduced from 0.3mm in the prior art to 0.1mm, thereby effectively improving the panel utilization rate of the lead frame and then reducing the preparation cost.

[0043] It can be understood that if the width of the cutting blade and the precision of the cutting machine are further reduced, the width of the cutting lane can be further reduced to below 0.1 mm, thereby further improving the panel utilization rate of the lead frame.

[0044] It can be understood that since no chip pad is provided in the lead frame without dams, the size of the chip island can be increased accordingly.

[0045] S12: Mount a chip on each chip base island.

[0046] In this embodiment, an adhesive is applied to a designated area of ​​each chip island, and a chip is mounted on the adhesive.

[0047] In some implementations, the designated area is a middle area of ​​the chip island.

[0048] In some embodiments, the adhesive is a thermally conductive adhesive. In some specific embodiments, the adhesive is a substance such as solder paste or silver paste.

[0049] In some implementations, the pin region of the chip is disposed on a surface of the chip that is away from the chip base island.

[0050] It can be understood that, since the lead frame does not include a chip pad, the lead frame does not perform the electrical interconnection function, but only serves to fix the chip position and act as a heat sink for the chip.

[0051] In some embodiments, the chip includes a large-size chip or a high-power chip, such as a silicon carbide (SiC) chip or a gallium nitride (GaN) chip, which is not limited in the present application.

[0052] It is understandable that since the chip base island is relatively large, a relatively large chip can be mounted. At the same time, since the relatively large chip base island can achieve a better heat dissipation effect, the heat dissipation requirements of high-power chips can be met.

[0053] S13: plastic-encapsulating the plurality of chips and the lead frame to form a plastic-encapsulated body; wherein the plastic-encapsulated body covers the plurality of chips, the plurality of chip base islands, and the plurality of base island connecting ribs.

[0054] In this embodiment, a plastic packaging material is obtained, and the plastic packaging material is pressed together with a plurality of chips and a lead frame to form a plastic packaging body.

[0055] In some implementations, the molding material includes one or more of epoxy resins, phenolic resins, polyimides, BTs, ABFs, and ceramic-based materials, which is not limited in the present application.

[0056] S14: forming a first conductive column between the plastic package and a surface of the chip away from the chip island, and forming a first conductive circuit covering the first conductive column on a surface of the plastic package close to the chip, so as to electrically connect the chip to the first conductive circuit.

[0057] In this embodiment, the bottom end of the first conductive column is connected to the pin region of the chip, and the top end of the first conductive column is covered by the first conductive circuit.

[0058] The first conductive pillar can form an electrical connection between the I / O port (input / output port) of the chip and the first conductive line, thereby realizing the fan-out of the chip signal.

[0059] It can be understood that since the active surface of the chip is a side surface away from the chip base island and located above, and the first conductive column is also arranged above the active surface of the chip, it is equivalent to realizing flip-chip packaging of the chip through a face-up process.

[0060] In the prior art, in order to realize flip-chip packaging of a chip, a copper pillar is usually pre-processed on the active surface of the chip so as to connect the copper pillar with the pad during packaging. This makes the chip preparation process more complicated and the processing cycle longer.

[0061] Different from the prior art, since the first conductive column in this embodiment is formed after the chip is mounted without the need to pre-process the copper column, the difficulty of preparing the chip is reduced, thereby reducing the chip processing cycle and further reducing the difficulty of flip chip packaging.

[0062] S15: Cutting the lead frame based on the cutting paths to obtain a plurality of chip packaging components.

[0063] In this embodiment, the lead frame is cut based on the cutting lines to cut off the island connection ribs connecting the adjacent chip islands, thereby obtaining a plurality of chip packaging components.

[0064] It can be understood that, since the width of the cutting road is less than or equal to 0.1 mm, the friction between the cutting blade and the cutting road can be reduced during cutting, thereby reducing the generation of burrs and further improving the yield of the packaged product.

[0065] Different from the prior art, this embodiment can form a damless lead frame by making the lead frame include multiple chip base islands and multiple base island connecting ribs, and connecting the multiple chip base islands through the base island connecting ribs, so that the width of the cutting path is not limited by the dam, thereby effectively reducing the width of the cutting path, thereby improving the panel utilization rate of the lead frame. Furthermore, since the width of the cutting path is less than or equal to 0.1 mm, the friction between the blade and the cutting path can be reduced during cutting, thereby reducing the generation of burrs, thereby improving the yield of the packaged product.

[0066] See also Figure 2 , Figure 2 : is a schematic diagram of a second embodiment of the chip packaging method of the present application. In this embodiment, the method includes:

[0067] S201: Obtain a metal substrate of a preset thickness; wherein the preset thickness is 100 to 210 μm.

[0068] In some embodiments, the metal substrate is a copper substrate. In other embodiments, the metal substrate is an iron substrate or a nickel substrate, which is not limited in the present application.

[0069] It can be understood that using a metal substrate to make a lead frame can not only effectively ensure the strength of the lead frame, but also improve the heat dissipation capacity of the chip.

[0070] S202: etching the metal substrate to form a plurality of chip base islands and a plurality of base island connecting ribs.

[0071] In this embodiment, a cutting line is arranged between adjacent chip islands, and the width of the cutting line is less than or equal to 0.1 mm.

[0072] In some implementations, the chip base island and the base island connecting ribs are integrally formed during the etching process.

[0073] S203: half-etching the base island connecting ribs to form a half-etched structure; wherein the thickness of the half-etched structure is 40% to 60% of the thickness of the chip base island.

[0074] In some specific embodiments, the thickness of the half-etched structure is 50% of the thickness of the chip base island. In other specific embodiments, the thickness of the half-etched structure is 45% of the thickness of the chip base island. In still other specific embodiments, the thickness of the half-etched structure is 55% of the thickness of the chip base island, which is not limited in this application.

[0075] It can be understood that by half-etching the base island connecting ribs to form a half-etched structure, the thickness of the base island connecting ribs can be reduced, and the friction between the blade and the metal can be further reduced during subsequent cutting, which can not only reduce the generation of burrs, but also effectively reduce the probability of blade wear, thereby improving the yield of the packaged products while extending the service life of the cutting tool and reducing the preparation cost.

[0076] Specifically, see Figure 3 and Figure 4 , Figure 3 is a top view of an embodiment of the lead frame obtained in S203, Figure 4 yes Figure 3 Schematic diagram of the cross-sectional structure of the lead frame along the AA line. In this embodiment, the lead frame 100 includes a plurality of chip base islands 10 and a plurality of base island connecting ribs 11, and the plurality of chip base islands 10 are connected by the base island connecting ribs 11. A cutting path 12 is provided between adjacent chip base islands 10, and the width of the cutting path 12 is less than or equal to 0.1 mm. Among them, the base island connecting rib 11 is a half-etched structure, and the thickness of the base island connecting rib 11 is 50% of the thickness of the chip base island 10.

[0077] S204: Mount a chip on each chip base island.

[0078] For the specific mounting process, please refer to the description in S12 and will not be repeated here.

[0079] S205: plastic-encapsulating the plurality of chips and the lead frame to form a plastic-encapsulated body; wherein the plastic-encapsulated body covers the plurality of chips, the plurality of chip base islands, and the plurality of base island connecting ribs.

[0080] For the specific mounting process, please refer to the description in S12 and will not be repeated here.

[0081] Specifically, see Figure 5 , Figure 5 It is a structural schematic diagram of an implementation method of a packaging structure obtained in S204. In this implementation method, the packaging structure 200 includes a lead frame 100, a plurality of chips 20, and a plastic package 30. The lead frame 100 includes a plurality of chip base islands 10 and a plurality of base island connecting ribs 11, and the plurality of chip base islands 10 are connected by the base island connecting ribs 11. A plurality of chips 20 are respectively arranged on each chip base island 10, and the chips 20 are mounted on the chip base island 10 by an adhesive 21. The plastic package 30 covers the plurality of chips 20, the plurality of chip base islands 10, and the plurality of base island connecting ribs 11.

[0082] S206: drilling the plastic package body, drilling through the plastic package body until the chip is exposed, so as to form a first blind hole.

[0083] In this embodiment, the plastic package body is drilled by laser.

[0084] In this embodiment, the bottom of the first blind hole is the pin area of ​​the chip.

[0085] Specifically, see Figure 6 , Figure 6 It is a structural schematic diagram of an implementation method of a packaging structure obtained in S206. In this implementation method, the packaging structure 300 includes a lead frame 100, a plurality of chips 20, a plastic package 30, and a plurality of first blind holes 40. The lead frame 100 includes a plurality of chip base islands 10 and a plurality of base island connecting ribs 11, and the plurality of chip base islands 10 are connected by the base island connecting ribs 11. A plurality of chips 20 are respectively arranged on each chip base island 10, and the chip 20 is mounted on the chip base island 10 by an adhesive 21. The plastic package 30 covers the plurality of chips 20, the plurality of chip base islands 10, and the plurality of base island connecting ribs 11. The first blind hole 40 is arranged on the plastic package 30, and the bottom of the first blind hole 40 is a side surface of the chip 20 away from the chip base island 10. Among them, the bottom of the first blind hole 40 is the pin area of ​​the chip 20.

[0086] S207: forming a first conductive column in the first blind hole, and forming a first conductive circuit covering the first conductive column on a surface of the plastic package body on one side close to the chip.

[0087] In this embodiment, a first conductive film is first formed on the bottom and wall of the first blind hole and the surface of the plastic package body close to the chip, wherein the first conductive film is a conductive seed layer formed by sputtering or chemical deposition, which is convenient for subsequent copper electroplating.

[0088] Furthermore, the entire plate formed with the first conductor film is electroplated to form a first conductive column in the first blind hole and a first conductive layer on the surface of the plastic package body close to the chip.

[0089] Furthermore, the first conductive layer is pattern-etched to form a first conductive circuit.

[0090] In some implementations, the first conductive layer is patterned by photolithography, development, and etching.

[0091] Specifically, see Figure 7 , Figure 7 It is a structural schematic diagram of an embodiment of a packaging structure obtained in S207. In this embodiment, the packaging structure 400 includes a lead frame 100, a plurality of chips 20, a plastic package 30, a plurality of first blind holes 40, a plurality of first conductive pillars 41 and a first conductive line 50. The lead frame 100 includes a plurality of chip base islands 10 and a plurality of base island connecting ribs 11, and the plurality of chip base islands 10 are connected by the base island connecting ribs 11. A plurality of chips 20 are respectively arranged on each chip base island 10, and the chip 20 is mounted on the chip base island 10 by an adhesive 21. The plastic package 30 covers a plurality of chips 20, a plurality of chip base islands 10 and a plurality of base island connecting ribs 11. The first blind hole 40 is arranged on the plastic package 30, and the bottom of the first blind hole 40 is a side surface of the chip 20 away from the chip base island 10. Among them, the bottom of the first blind hole 40 is the pin area of ​​the chip 20. The first conductive pillar 41 is arranged in the first blind hole 40 and is connected to the pin of the chip 20. The first conductive circuit 50 is disposed on a surface of the plastic package 30 close to the chip 20 and covers the first conductive column 41 . The chip 20 and the first conductive circuit 50 are electrically connected through the first conductive column 41 .

[0092] S208: forming an insulating layer on a surface of the first conductive circuit that is away from the chip and a surface of the plastic package that is close to the chip.

[0093] In this embodiment, an insulating material is obtained and pressed together with a surface of the first conductive circuit that is away from the chip and a surface of the plastic package that is close to the chip to form an insulating layer.

[0094] In some embodiments, the insulating material includes one or more of prepreg (PP), polyimide (PI) and FR-4 grade material, which is not limited in the present application.

[0095] It can be understood that the insulating layer can increase the overall product structural rigidity and buffer welding stress.

[0096] S209: drilling the insulating layer to drill through the insulating layer until the first conductive line is exposed, so as to form a second blind hole.

[0097] In this embodiment, the insulating layer is drilled by laser.

[0098] Specifically, see Figure 8 , Figure 8 It is a structural schematic diagram of an implementation method of a packaging structure obtained in S209. In this implementation method, the packaging structure 500 includes a lead frame 100, a plurality of chips 20, a plastic package 30, a plurality of first blind holes 40, a plurality of first conductive pillars 41, a first conductive line 50, an insulating layer 60 and a plurality of second blind holes 70. The lead frame 100 includes a plurality of chip base islands 10 and a plurality of base island connecting ribs 11, and the plurality of chip base islands 10 are connected by the base island connecting ribs 11. A plurality of chips 20 are respectively arranged on each chip base island 10, and the chip 20 is mounted on the chip base island 10 by an adhesive 21. The plastic package 30 covers the plurality of chips 20, the plurality of chip base islands 10 and the plurality of base island connecting ribs 11. The first blind hole 40 is arranged on the plastic package 30, and the bottom of the first blind hole 40 is a side surface of the chip 20 away from the chip base island 10. Among them, the bottom of the first blind hole 40 is the pin area of ​​the chip 20. The first conductive column 41 is arranged in the first blind hole 40 and connected to the pin of the chip 20. The first conductive circuit 50 is arranged on a side surface of the plastic package 30 close to the chip 20 and covers the first conductive column 41. The chip 20 and the first conductive circuit 50 are electrically connected through the first conductive column 41. The insulating layer 60 is arranged on a side surface of the first conductive circuit 50 away from the chip 20 and on a side surface of the plastic package 30 close to the chip 20. The second blind hole 70 is arranged on the insulating layer 60, and the bottom of the second blind hole 70 is the first conductive circuit 50.

[0099] S210: forming a second conductive column in the second blind hole, and forming a second conductive circuit covering the second conductive column on a surface of the insulating layer away from the first conductive circuit, so as to electrically connect the chip to the second conductive circuit.

[0100] In this embodiment, a second conductor film is first formed on the bottom and wall of the second blind hole and the surface of the insulating layer away from the first conductive line. The second conductor film is a conductive seed layer formed by sputtering or chemical deposition, which is convenient for subsequent copper electroplating.

[0101] Furthermore, the entire plate formed with the second conductor film is electroplated to form a second conductive column in the second blind hole and a second conductive layer on the surface of the insulating layer away from the first conductive line.

[0102] Furthermore, the second conductive layer is pattern-etched to form a second conductive circuit.

[0103] In some implementations, the second conductive layer is patterned by photolithography, development, and etching.

[0104] In this embodiment, the I / O port of the chip and the second conductive circuit can be electrically connected through the first conductive pillar, the first conductive circuit and the second conductive pillar, thereby realizing the fan-out of the chip signal.

[0105] It can be understood that since an insulating layer is provided above the active surface of the chip, the stress transmitted to the active surface of the chip during the welding process can be greatly relieved, thereby meeting the stress release requirements of stress-sensitive analog chips. Furthermore, by providing the first conductive circuit and the second conductive circuit, the number of wiring layers can be increased, so that the fan-out of the chip is not restricted by the number of wires and the wire diameter, thereby increasing the flexibility of chip design and further improving the current carrying capacity of the overall package assembly.

[0106] S211: forming a protective layer on the second conductive circuit.

[0107] In this embodiment, a protection layer is formed on the second conductive line by surface treatment to prevent oxidation of the pad and improve solderability.

[0108] Specifically, see Fig. 9 , Fig. 91 is a schematic diagram of the structure of an embodiment of a semiconductor package assembly of the present application. In this embodiment, the semiconductor package assembly 600 includes a lead frame 100, a plurality of chips 20, a plastic package 30, a plurality of first blind holes 40, a plurality of first conductive pillars 41, a first conductive line 50, an insulating layer 60, a plurality of second blind holes 70, a plurality of second conductive pillars 71, a second conductive line 80 and a protective layer 90. The lead frame 100 includes a plurality of chip base islands 10 and a plurality of base island connecting ribs 11, and the plurality of chip base islands 10 are connected by the base island connecting ribs 11. A plurality of chips 20 are respectively arranged on each chip base island 10, and the chip 20 is mounted on the chip base island 10 by an adhesive 21. The plastic package 30 covers the plurality of chips 20, the plurality of chip base islands 10 and the plurality of base island connecting ribs 11. The first blind hole 40 is arranged on the plastic package 30, and the bottom of the first blind hole 40 is the side surface of the chip 20 away from the chip base island 10. Among them, the bottom of the first blind hole 40 is the pin area of ​​the chip 20. The first conductive column 41 is arranged in the first blind hole 40 and connected to the pin of the chip 20. The first conductive line 50 is arranged on a side surface of the plastic package 30 close to the chip 20 and covers the first conductive column 41. The chip 20 and the first conductive line 50 are electrically connected through the first conductive column 41. The insulating layer 60 is arranged on a side surface of the first conductive line 50 away from the chip 20 and on a side surface of the plastic package 30 close to the chip 20. The second blind hole 70 is arranged on the insulating layer 60, and the bottom of the second blind hole 70 is the first conductive line 50. The second conductive column 71 is arranged in the second blind hole 70. The second conductive line 80 is arranged on a side surface of the insulating layer 60 away from the first conductive line 50 and covers the second conductive column 71. The chip 20 is electrically connected to the second conductive line 80 through the first conductive column 41, the first conductive line 50 and the second conductive column 71. The protective layer 90 covers the second conductive line 80.

[0109] S212: Cut the lead frame based on the cutting paths to obtain a plurality of chip packaging components.

[0110] In this embodiment, a cutting machine is used to cut the lead frame based on cutting lanes to obtain a plurality of chip packaging components.

[0111] Specifically, see Fig.10 and Fig.11 , Fig.10 Based on the cutting path Fig. 9 Schematic diagram of cutting semiconductor packaging components. Fig.11 It is a schematic structural diagram of an implementation scheme of a chip packaging assembly of the present application.

[0112] In this embodiment, the lead frame 100 is cut based on the cutting lines 12 to cut off the island connecting ribs 11 connecting adjacent chip islands 10 , thereby obtaining a plurality of chip packaging components 800 .

[0113] In this embodiment, the chip packaging component 800 includes a chip base island 10, a base island connecting rib 11, a chip 20, a plastic package 30, a first blind hole 40, a first conductive column 41, a first conductive line 50, an insulating layer 60, a second blind hole 70, a second conductive column 71, a second conductive line 80 and a protective layer 90. The base island connecting rib 11 is arranged on the periphery of the chip base island 10. The chip 20 is arranged on the chip base island 10. The plastic package 30 covers the chip 20, the chip base island 10 and the base island connecting rib 11. The first blind hole 40 is arranged on the plastic package 30, and the bottom of the first blind hole 40 is a side surface of the chip 20 away from the chip base island 10. The first conductive column 41 is arranged in the first blind hole 40 and connected to the pin of the chip 20. The first conductive line 50 is arranged on a side surface of the plastic package 30 close to the chip 20 and covers the first conductive column 41. The chip 20 and the first conductive line 50 are electrically connected through the first conductive column 41. The insulating layer 60 is disposed on a side surface of the first conductive circuit 50 away from the chip 20 and on a side surface of the plastic package body 30 close to the chip 20. The second blind hole 70 is disposed on the insulating layer 60, and the bottom of the second blind hole 70 is the first conductive circuit 50. The second conductive column 71 is disposed in the second blind hole 70. The second conductive circuit 80 is disposed on a side surface of the insulating layer 60 away from the first conductive circuit 50 and covers the second conductive column 71. The chip 20 and the second conductive circuit 80 are electrically connected through the first conductive column 41, the first conductive circuit 50 and the second conductive column 71. The protective layer 90 covers the second conductive circuit 80.

[0114] Different from the prior art, the present application forms a damless lead frame by making the lead frame include multiple chip base islands and multiple base island connecting ribs, and connecting the multiple chip base islands through the base island connecting ribs, so that the width of the cutting path is not limited by the dam, thereby effectively reducing the width of the cutting path, and then improving the panel utilization rate of the lead frame. Furthermore, since the width of the cutting path is less than or equal to 0.1 mm, the friction between the blade and the cutting path can be reduced during cutting, thereby reducing the generation of burrs, and then improving the yield of the packaged product. At the same time, by half-etching the base island connecting ribs to form a half-etched structure, the thickness of the base island connecting ribs can be reduced, and the friction between the blade and the metal can be further reduced during subsequent cutting, thereby improving the yield of the packaged product while extending the service life of the cutting tool and reducing the preparation cost. Furthermore, by arranging a first conductive circuit, an insulating layer and a second conductive circuit above the active surface of the chip, the stress transmitted to the active surface of the chip during the welding process can be relieved through the insulating layer, thereby meeting the stress release requirements of stress-sensitive analog chips; and by increasing the number of wiring layers, the fan-out of the chip is not restricted by the number of wires and wire diameters, thereby increasing the flexibility of chip design and subsequently improving the current-carrying capacity of the overall packaging component.

[0115] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A chip packaging method, characterized in that: include: A lead frame is obtained; wherein the lead frame comprises a plurality of chip base islands and a plurality of base island connecting ribs, and the plurality of chip base islands are connected by the base island connecting ribs; a cutting path is provided between adjacent chip base islands, and a width of the cutting path is less than or equal to 0.1 mm; Mounting the chip on each chip base island; Plastic-encapsulating the plurality of chips and the lead frame to form a plastic-encapsulated body; wherein the plastic-encapsulated body covers the plurality of chips, the plurality of chip base islands and the plurality of base island connecting ribs; A first conductive column is formed between the plastic package and a surface of the chip away from the chip base island, and a first conductive circuit covering the first conductive column is formed on a surface of the plastic package close to the chip, so that the chip is electrically connected to the first conductive circuit; The lead frame is cut based on the cutting paths to obtain a plurality of chip packaging components.

2. The chip packaging method according to claim 1, characterized in that: The step of obtaining the lead frame includes: Obtaining a metal substrate of a preset thickness; wherein the preset thickness is 100 to 210 μm; The metal substrate is etched to form a plurality of chip base islands and a plurality of base island connecting ribs.

3. The chip packaging method according to claim 2, characterized in that: After the step of etching the metal substrate to form a plurality of chip base islands and a plurality of base island connecting ribs, the method further comprises: The base island connecting ribs are half-etched to form a half-etched structure; wherein the thickness of the half-etched structure is 40% to 60% of the thickness of the chip base island.

4. The chip packaging method according to claim 1, characterized in that: The step of forming a first conductive column between the plastic package and a surface of the chip away from the chip base island, and forming a first conductive circuit covering the first conductive column on a surface of the plastic package close to the chip to electrically connect the chip to the first conductive circuit includes: Performing a drilling process on the plastic package body, drilling through the plastic package body until the chip is exposed, so as to form a first blind hole; The first conductive column is formed in the first blind hole, and a first conductive circuit covering the first conductive column is formed on a surface of the plastic package body on one side close to the chip.

5. The chip packaging method according to claim 4, characterized in that: The step of forming the first conductive column in the first blind hole and forming a first conductive circuit covering the first conductive column on a surface of the plastic package body close to the chip comprises: forming a first conductor film on the bottom and wall of the first blind hole and on the surface of one side of the plastic package body close to the chip; Performing whole-plate electroplating on the plate having the first conductor film formed thereon, so as to form the first conductive column in the first blind hole and to form a first conductive layer on a surface of the plastic package body on one side close to the chip; The first conductive layer is pattern-etched to form the first conductive line.

6. The chip packaging method according to claim 4, characterized in that: After the step of forming the first conductive column in the first blind hole and forming a first conductive circuit covering the first conductive column on a surface of the plastic package body close to the chip, the method includes: An insulating layer is formed on a surface of the first conductive circuit that is away from the chip and a surface of the plastic package that is close to the chip; Performing a drilling process on the insulating layer, drilling through the insulating layer until the first conductive line is exposed, so as to form a second blind hole; A second conductive column is formed in the second blind hole, and a second conductive circuit covering the second conductive column is formed on a surface of the insulating layer away from the first conductive circuit, so that the chip is electrically connected to the second conductive circuit.

7. The chip packaging method according to claim 6, characterized in that: After the steps of forming a second conductive column in the second blind hole and forming a second conductive circuit on a surface of the insulating layer on a side away from the first conductive circuit, the method comprises: A protection layer is formed on the second conductive line.

8. A semiconductor package assembly, characterized in that: include: A lead frame, comprising a plurality of chip base islands and a plurality of base island connecting ribs, wherein the plurality of chip base islands are connected by the base island connecting ribs; A cutting path is provided between adjacent chip base islands, and the width of the cutting path is less than or equal to 0.1 mm; A plurality of chips are respectively arranged on each of the chip base islands; A plastic package body, covering the plurality of chips, the plurality of chip base islands and the plurality of base island connecting ribs; A first blind hole is arranged on the plastic package body, and the bottom of the first blind hole is a surface of the chip away from the chip base island; A first conductive column, disposed in the first blind hole and connected to a pin of the chip; A first conductive circuit is arranged on a surface of the plastic package body close to the chip and covers the first conductive column; wherein the chip and the first conductive circuit are electrically connected through the first conductive column.

9. A chip packaging assembly, characterized in that: include: A chip base island; wherein the chip base island is provided with base island connecting ribs on the periphery of the chip base island; A chip is arranged on the chip base island; A plastic package body, covering the chip, the chip base island and the base island connecting ribs; A first blind hole is arranged on the plastic package body, and the bottom of the first blind hole is a surface of the chip away from the chip base island; A first conductive column, disposed in the first blind hole and connected to a pin of the chip; A first conductive circuit is arranged on a surface of the plastic package body close to the chip and covers the first conductive column; wherein the chip and the first conductive circuit are electrically connected through the first conductive column.

10. The chip package assembly according to claim 9, characterized in that: The chip packaging assembly also includes: An insulating layer is provided on a surface of the first conductive circuit which is away from the chip and a surface of the plastic package which is close to the chip; A second blind hole is arranged on the insulating layer, and the bottom of the second blind hole is the first conductive line; A second conductive column is disposed in the second blind hole; A second conductive circuit is arranged on a surface of the insulating layer away from the first conductive circuit and covers the second conductive column; wherein the chip and the second conductive circuit are electrically connected through the first conductive column, the first conductive circuit and the second conductive column; A protective layer covers the second conductive circuit.

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