Array substrate, display panel and electronic equipment

Abstract

The invention provides an array substrate, a display panel and electronic equipment, the array substrate comprises a display area and a non-display area at least partially surrounding the display area, the display area comprises at least one arc angle edge, and the non-display area comprises a first frame area corresponding to the arc angle edge in position; the array substrate comprises a plurality of gate driving units located in a non-display area, and each gate driving unit comprises at least two sub-circuits; the grid driving unit comprises at least one first grid driving unit located in the first frame area, at least two sub-circuits in the same first grid driving unit are arranged in an arc shape along the contour of the arc angle edge, and in the structure, the at least two sub-circuits of the first grid driving unit are arranged in an arc shape along the contour of the arc angle edge. The width of the first frame area can be reduced, and the arc angle bending point of the first frame area can be reduced, so that the array substrate is more attractive.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and an electronic device. Background Art

[0002] With the development of display device manufacturing technology, Active Matrix Organic Light Emitting Diode (AMOLED) is widely used because it combines the advantages of Active Matrix and Organic Light Emitting Diode (OLED). However, the frame of the current foldable AMOLED display panel has problems such as too large arc radius and the overall display effect is not beautiful enough. Summary of the invention

[0003] In order to overcome the above-mentioned shortcomings in the prior art, the object of the present application is to provide an array substrate, the array substrate comprising a display area and a non-display area at least partially surrounding the display area, the display area comprising at least one arc angle edge, the non-display area comprising a first frame area corresponding to the position of the arc angle edge;

[0004] The array substrate comprises a plurality of gate driving units located in the non-display area, and each of the gate driving units comprises at least two sub-circuits;

[0005] The plurality of gate driving units include at least one first gate driving unit located in the first border area, and at least two sub-circuits in the same first gate driving unit are arranged in an arc shape along the contour of the arc angle edge.

[0006] In a possible implementation, the display area further includes a straight edge connected to the arc-angle edge, and the non-display area includes a second frame area corresponding to the position of the straight edge; the plurality of gate driving units further include at least one second gate driving unit located in the second frame area, and at least two of the sub-circuits in the second gate driving unit are arranged in a direction perpendicular to the straight edge and away from the display area;

[0007] Preferably, a plurality of the second gate driving units located in the second border area are arranged along the extending direction of the straight side.

[0008] In a possible implementation, the plurality of gate driving units further include at least one third gate driving unit, and at least two of the sub-circuits in the third gate driving unit are arranged along a direction in which the radius of the arc angle side is away from the display area;

[0009] Preferably, the plurality of third gate driving units located in the first border area are arranged along an extending direction of the arc angle edge.

[0010] In a possible implementation, along the extension direction of the arc angle edge, the first gate driving unit is located at an end of the first border area away from the second border area, and the third gate driving unit is located at an end of the first border area close to the second border area.

[0011] In a possible implementation manner, the array substrate includes a dummy driving unit located in the first border area, and the dummy driving unit is located between two adjacent third gate driving units.

[0012] In a possible implementation, along the extension direction of the arc angle edge, in at least one of the first gate driving units away from the second border area, each of the sub-circuits is arranged along the extension direction of the arc angle edge; in at least one of the third gate driving units close to the second border area, at least two of the sub-circuits are arranged along the direction away from the display area.

[0013] In a possible implementation, the array substrate includes a plurality of rows of pixel driving units located in the display area; each sub-circuit in one gate driving unit is respectively connected to the pixel driving units in the same row;

[0014] The pixel driving unit includes a plurality of different switching devices, and each of the sub-circuits of the gate driving unit is electrically connected to different switching devices in the pixel driving unit through different signal routings.

[0015] In a possible implementation, the sub-circuit of the gate driving unit includes a light emitting control circuit and at least one scanning control circuit;

[0016] Preferably, the sub-circuit of the gate driving unit includes a light emitting control circuit, a first scanning control circuit and a second scanning control circuit.

[0017] Another object of the present application is to provide a display panel, which includes the array substrate provided in the present application.

[0018] Another object of the present application is to provide an electronic device, which includes the display panel provided in the present application.

[0019] Compared with the prior art, this application has the following beneficial effects:

[0020] The embodiments of the present application provide an array substrate, a display panel and an electronic device. By arranging at least two sub-circuits of a first gate driving unit in an arc shape along the contour of an arc angle edge, the width of a first border area can be reduced, and the bending point of the arc angle of the first border area can be lowered, thereby making the array substrate more beautiful. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 is a schematic diagram of the structure of an array substrate in the prior art;

[0023] Figure 2 One of the structural schematic diagrams of the array substrate provided in the embodiment of the present application;

[0024] Figure 3 One of the structural schematic diagrams of the first border area provided in the embodiment of the present application;

[0025] Figure 4 A second structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0026] Figure 5 The third structural schematic diagram of the array substrate provided in the embodiment of the present application;

[0027] Figure 6 A fourth structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0028] Figure 7 A second structural diagram of the first border area provided in an embodiment of the present application;

[0029] Figure 8 The third structural diagram of the first border area provided in the embodiment of the present application;

[0030] Fig. 9 A fourth structural diagram of the first border area provided in an embodiment of the present application;

[0031] Fig.10 A fifth structural diagram of the first border area provided in an embodiment of the present application;

[0032] Fig.11 The sixth structural diagram of the first border area provided in the embodiment of the present application;

[0033] Fig.12 The seventh structural diagram of the first border area provided in the embodiment of the present application.

[0034] Icon: 100-display area; 200-non-display area; 110-first straight edge; 120-second straight edge; 130-third straight edge; 140-fourth straight edge; 210-first border area; 220-second border area; 230-third border area; 310-first gate driving unit; 320-second gate driving unit; 330-third gate driving unit; 340-dummy driving unit; 400-pixel driving unit; 301-sub-circuit. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0036] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0037] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0038] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0039] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0040] The inventor has found that Figure 1Some display panels typically include a display area 100' and a non-display area 200' (such as a frame area) that at least partially surrounds the display area 100'. The non-display area 200' may include a plurality of gate driving units 320', and the display area includes a plurality of rows of pixel driving units 400'. Each gate driving unit 320' is connected to a row of pixel driving units 400'.

[0041] The display area 100' may include at least one arc angle edge, and the non-display area 200' may include a first frame area corresponding to the position of the arc angle edge. The first frame area includes a plurality of gate driving units 320' arranged in an arc shape along the contour of the arc angle edge. Since the plurality of gate driving units 320' are rotated and placed in the first frame area, the number of gate driving units 320' in the first frame area will be greater than the number of rows of pixel driving units 400' in the display area 100'. Therefore, it is necessary to set the redundant gate driving units 320' as dummy driving units 340'.

[0042] However, such an arrangement of the gate driving unit 320 ′ may result in an excessively large arc radius of the arc angle of the first border region, and a relatively wide width of the first border region.

[0043] In view of this, the present embodiment provides a solution that can reduce the width of the arc corner frame. The solution provided by the present embodiment is described in detail below.

[0044] Please refer to Figure 2 , Figure 2 The schematic diagram of the structure of the array substrate provided in this embodiment is illustrated. The array substrate may include a display area 100 and a non-display area 200 at least partially surrounding the display area 100. The display area 100 may include at least one arc angle edge, and the non-display area 200 may include a first frame area 210 corresponding to the position of the arc angle edge. For example, the first frame area 210 may be a sector extending along the arc angle edge of the display 100.

[0045] Optionally, in some possible implementations, the display area 100 may be in a rectangular shape with curved edges, and the display area 100 may further include straight edges connected to the curved edges.

[0046] Specifically, the display area 100 may include a first straight side 110, a second straight side 120, a third straight side 130 and a fourth straight side 140, the third straight side 130 is parallel to the first straight side 110, the second straight side 120 is parallel to the fourth straight side 140, and the straight line where the first straight side 110 extends is perpendicular to the straight line where the second straight side 120 extends. The display area 100 includes four arc angle edges, and the four arc angle edges are respectively located between the first straight side 110 and the second straight side 120, between the second straight side 120 and the third straight side 130, between the third straight side 130 and the fourth straight side 140, and between the fourth straight side 140 and the first straight side 110.

[0047] In this case, the non-display area 200 may include a second frame area 220 and a third frame area 230 corresponding to the straight edge position.

[0048] Specifically, the non-display area 200 may include two second frame areas 220 corresponding to the positions of the first straight edge 110 and the third straight edge 130, and two third frame areas 230 corresponding to the positions of the second straight edge 120 and the fourth straight edge 140. The non-display area 200 also includes four first frame areas 210 corresponding to the positions of the four arc corner edges.

[0049] The shape of the second border area 220 is different from that of the first border area 210 . The shape of the second border area 220 may be a rectangle extending along the first straight edge 110 or the third straight edge 130 of the display area 100 .

[0050] Optionally, the shape of the third border area 230 is different from that of the first border area 210 , and the shape of the third border area 230 may be a rectangle extending along the second straight side 120 or the fourth straight side 140 of the display area 100 .

[0051] The array substrate may include a plurality of gate driving units located in the non-display area 200, and each of the gate driving units may include at least two sub-circuits 301. For example, at least two of the sub-circuits 301 may include a light emitting control circuit and at least one scanning control circuit. The light emitting control circuit is used to provide a light emitting control signal to the pixel driving unit 400 located in the display area 100, and the scanning control circuit is used to provide a scanning signal to the pixel driving unit 400 located in the display area 100.

[0052] Please refer to Figure 3The plurality of gate driving units may include at least one first gate driving unit 310 located in the first border area 210, and at least two sub-circuits 301 in the same first gate driving unit 310 are arranged in an arc shape along the contour of the arc angle edge.

[0053] Optionally, when at least two first gate driving units 310 are provided in the first border area 210, the at least two first gate driving units 310 are arranged in an arc shape along the contour of the arc angle side. That is, each of the first gate driving units 310 located in the first border area 210 can be rotated clockwise by a certain angle compared with the previous first gate driving unit 310 in sequence, so as to realize the first gate driving unit 310 being rotated and placed in the first border area 210.

[0054] It should be noted that, when the display area 100 includes multiple arc-angle edges, and the non-display area 200 includes multiple first border areas 210 corresponding to the positions of the multiple arc-angle edges, the first gate driving unit 310 may be located only in part of the first border area 210. For example, if the non-display area 200 includes four first border areas 210, the first gate driving unit 310 may be located only in two of the first border areas 210.

[0055] Alternatively, when the display area 100 includes a plurality of the arc angle edges, and the non-display area 200 includes a plurality of the first border areas 210 respectively corresponding to the positions of the plurality of the arc angle edges, each of the first border areas 210 may be provided with the first gate driving unit, such as Figure 4 shown.

[0056] Based on the above design, in the array substrate provided in this embodiment, by arranging at least two of the sub-circuits 301 of the first gate driving unit 310 in an arc shape along the contour of the arc angle edge, the width of the first border area 210 can be reduced, and the bending point of the arc angle of the first border area 210 can be lowered, thereby making the array substrate more beautiful.

[0057] In a possible implementation, the plurality of gate driving units may further include at least one second gate driving unit 320 located in the second border area 220. Figure 5 , the plurality of second gate driving units 320 located in the second border area 220 are arranged along the extending direction of the straight edge.

[0058] In this embodiment, please refer to Figure 6 , an arrangement of the sub-circuits 301 in the second gate driving unit 320 is different from an arrangement of the sub-circuits 301 in the first gate driving unit 310 .

[0059] For example, the sub-circuits 301 in the second gate driving unit 320 are arranged in a direction away from the display area 100. That is, in this embodiment, the arrangement direction of the sub-circuits 301 in the second gate driving unit 320 may be perpendicular to the extension direction of the straight edge.

[0060] In one possible implementation, see Figure 7 The multiple gate driving units may further include at least one third gate driving unit 330, and at least two of the sub-circuits 301 in the third gate driving unit 330 are arranged in a direction away from the display area. For example, the arrangement direction of each of the sub-circuits 301 in the third gate driving unit 330 is the radius extension direction of the arc angle edge.

[0061] Preferably, the plurality of third gate driving units 330 located in the first border area 210 are arranged along the extending direction of the arc angle edge.

[0062] In this embodiment, the first border area 210 may further include the third gate driving unit 330, and each of the third gate driving units 330 located in the first border area 210 may be rotated clockwise by a certain angle compared with the previous third gate driving unit 330 in turn, thereby realizing the rotational placement of the third gate driving unit 330 in the first border area 210.

[0063] Specifically, when the display area 100 is shaped like a rectangle with arc-angled edges, and the non-display area includes four first border areas 210, two second border areas 220 and two third border areas 230, the four first border areas 210 can include at least one first gate driving unit 310 and at least one third gate driving unit 330, the two second border areas 220 corresponding to the positions of the first straight edge 110 and the third straight edge 130 respectively may include at least one second gate driving unit 320, and the two third border areas 230 corresponding to the positions of the second straight edge 120 and the fourth straight edge 140 respectively may not include the first gate driving unit 310, the second gate driving unit 320 and the third gate driving unit 330.

[0064] In one possible implementation, please refer again to Figure 3 , along the extending direction of the arc angle edge, the first gate driving unit 310 is located at an end of the first border area 210 away from the second border area 220 , and the third gate driving unit 330 is located at an end of the first border area 210 close to the second border area 220 .

[0065] In this embodiment, the first gate driving unit 310 can be located at one end of the first border area 210 close to the third border area 230, and the third gate driving unit 330 can be located at one end of the first border area 210 close to the second border area 220. Since at least two of the sub-circuits 301 in the first gate driving unit 310 are arranged in an arc shape along the contour of the arc angle edge, the width of the first border area 210 close to the third border area 230 can be effectively reduced, and the arc angle bending point of the first border area 210 can also be reduced.

[0066] At the junction of the first border area 210 and the second border area 220, the third gate driving unit 330 located in the first border area 210 contacts the second gate driving unit 320 located in the second border area 220, and the third gate driving unit 330 located in the first border area 210 can be rotated clockwise by a certain angle compared to the adjacent second gate driving unit 320 located in the second border area 220 when placed.

[0067] In another possible implementation, see Figure 8 The first border area 210 may include only the first gate driving unit 310, and at least two of the sub-circuits 301 in the first gate driving unit 310 are arranged in an arc shape along the contour of the arc angle edge.

[0068] In one possible implementation, see Fig. 9 The array substrate may include a dummy driving unit 340 located in the first border area 210 , and the dummy driving unit 340 is located between two adjacent third gate driving units 330 .

[0069] In this embodiment, the dummy driving unit 340 can be a gate driving unit that is not connected to the pixel driving unit 400. The dummy driving unit 340 can be used to fill the excess space in the first border area 210 caused by the rotation of the third gate driving unit 330, thereby improving the uniformity of the etching environment during circuit etching in the first border area 210 and the uniformity of subsequent reflection effects.

[0070] In one possible implementation, please refer again to Figure 7 , along the extension direction of the arc angle edge, in at least one of the first gate driving units 310 that is relatively farther away from the second border area 220, each of the sub-circuits 301 is arranged along the extension direction of the arc angle edge; in at least one of the third gate driving units 330 that is relatively closer to the second border area 220, at least two of the sub-circuits 301 are arranged in a direction away from the display area 100.

[0071] In this embodiment, the first border area 210 may include at least one of the first gate driving units 310 and at least one of the third gate driving units 330. The first gate driving unit 310 may be located at an end of the first border area 210 away from the second border area 220, and the third gate driving unit 330 may be located at an end of the first border area 210 close to the second border area 220. The first gate driving unit 310 and the third gate driving unit 330 are both arranged along the extension direction of the arc angle edge, and the sub-circuits 301 of the first gate driving unit 310 located in the first border area 210 are arranged along the extension direction of the arc angle edge, and the sub-circuits 301 of the third gate driving unit 330 are arranged in a direction away from the display area 100.

[0072] In one possible implementation, please refer again to Fig. 9 The array substrate includes a plurality of rows of pixel driving units 400 located in the display area 100; each sub-circuit 301 in one gate driving unit is respectively connected to the pixel driving units 400 in the same row.

[0073] The pixel driving unit 400 may include a plurality of different switching devices, and each of the sub-circuits 301 of the gate driving unit may be electrically connected to different switching devices in the pixel driving unit 400 through different signal routings. That is, at least two of the sub-circuits in the first gate driving unit 310 that are arranged in an arc shape along the contour of the arc angle edge may be electrically connected to different switching devices in the pixel driving unit 400 through different signal routings, and at least two of the sub-circuits 301 in the second gate driving unit 320 that are arranged in a direction perpendicular to the straight edge and away from the display area may also be electrically connected to different switching devices in the pixel driving unit 400 through different signal routings.

[0074] For example, when the first gate driving unit 310 includes a light emitting control circuit 301-EM and a scanning control circuit 301-Scan arranged in an arc shape along the contour of the arc angle edge, the light emitting control circuit 301-EM can be connected to the light emitting control signal wiring, and the scanning control circuit 301-Scan can be connected to the scanning signal wiring. In this case, in the pixel driving units 400 in the same row, the transistors for performing light emitting signal control in each of the pixel driving units 400 are all electrically connected to the light emitting control signal wiring, and the transistors for performing scanning control are all electrically connected to the scanning signal wiring.

[0075] In this embodiment, the number of the gate driving units may be equal to the number of rows of the pixel driving units 400 , each of the gate driving units is connected to the pixel driving unit 400 , and the dummy driving unit 340 is not connected to the pixel driving unit 400 .

[0076] In one possible implementation, see Fig.10 The sub-circuit 301 of the gate driving unit may include a light emitting control circuit 301-EM and at least one scanning control circuit 301-Scan.

[0077] In a possible implementation, the first gate driving unit 310 may include a light emitting control circuit 301-EM and a scanning control circuit 301-Scan. At one end of the first border area 210 away from the second border area 220, the light emitting control circuit 301-EM and the scanning control circuit 301-Scan of the first gate driving unit 310 may be arranged in an arc shape along the contour of the arc angle edge.

[0078] It should be noted that, at the end of the first border area 210 away from the second border area 220, the first gate driving unit 310 may also include two other sub-circuits, for example, may include a sub-circuit composed of the light emitting control circuit 301-EM and the first scanning control circuit 301-ScanP and a sub-circuit composed of the second scanning control circuit 301-ScanN, and the two sub-circuits 301 are arranged in a direction away from the display area 100.

[0079] Preferably, please refer to Fig.11 The sub-circuit 301 of the gate driving unit includes a light emitting control circuit 301-EM, a first scanning control circuit 301-ScanP and a second scanning control circuit 301-ScanN.

[0080] In this embodiment, the light emitting control circuit 301-EM, the first scanning control circuit 301-ScanP and the second scanning control circuit 301-ScanN of one gate driving unit are respectively connected to the pixel driving unit 400 in the same row, and the gate driving unit is used to input a driving signal to the pixel driving unit 400.

[0081] In a possible implementation, the first gate driving unit 310 may include a light-emitting control circuit 301-EM, a first scanning control circuit 301-ScanP and a second scanning control circuit 301-ScanN. At one end of the first border area 210 away from the second border area 220, the light-emitting control circuit 301-EM, the first scanning control circuit 301-ScanP and the second scanning control circuit 301-ScanN of each of the first gate driving units 310 may be arranged in an arc shape along the contour of the arc angle edge; and in the extension direction of the arc angle edge, the light-emitting control circuit 301-EM, the first scanning control circuit 301-ScanP and the second scanning control circuit 301-ScanN 301-ScanP and the second scanning control circuit 301-ScanN are arranged in sequence. Specifically, the light-emitting control circuit 301-EM of the first gate driving unit 310 can be located at one end of the first border area 210 relatively close to the second border area 220, the second scanning control circuit 301-ScanN of the first gate driving unit 310 can be located at one end of the first border area 210 relatively far from the second border area 220, and the first scanning control circuit 301-ScanP of the first gate driving unit 310 can be located between the light-emitting control circuit 301-EM and the second scanning control circuit 301-ScanN.

[0082] In another possible implementation, please refer to Fig.12 The first scanning control circuit 301-ScanP may also include a first scanning module 301-ScanP1 and a second scanning module 301-ScanP2, and the second scanning control circuit 301-ScanN may also include a third scanning module 301-ScanN1 and a fourth scanning module 301-ScanN2. At one end of the first border area 210 away from the second border area 220, the light-emitting control circuit 301-EM, the first scanning module 301-ScanP1, the second scanning module 301-ScanP2, the third scanning module 301-ScanN1 and the fourth scanning module 301-ScanN2 of each of the first gate driving units 310 may be arranged in an arc shape along the contour of the arc angle edge.

[0083] It should be noted that the first scanning control circuit 301 -ScanP and the second scanning control circuit 301 -ScanN may further include more scanning modules, which may be selected according to actual needs.

[0084] The embodiment of the present application further provides a display panel, which may include the array substrate provided in the embodiment, and may further include a light-emitting functional film layer or a light-emitting device located on one side of the array substrate.

[0085] An embodiment of the present application further provides an electronic device, which may include the above-mentioned display panel provided by this embodiment.

[0086] In summary, the embodiments of the present application provide an array substrate, a display panel and an electronic device. By arranging at least two sub-circuits of the first gate driving unit in an arc shape along the contour of the arc angle edge, the width of the first border area can be reduced and the bending point of the arc angle of the first border area can be lowered, thereby making the array substrate more beautiful.

[0087] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises a display area and a non-display area at least partially surrounding the display area, the display area comprises at least one arc angle edge, and the non-display area comprises a first frame area corresponding to the position of the arc angle edge; The array substrate comprises a plurality of gate driving units located in the non-display area, and each of the gate driving units comprises at least two sub-circuits; The plurality of gate driving units include at least one first gate driving unit located in the first border area, and at least two sub-circuits in the same first gate driving unit are arranged in an arc shape along the contour of the arc angle edge.

2. The array substrate according to claim 1, characterized in that: The display area further includes a straight edge connected to the arc angle edge, and the non-display area includes a second frame area corresponding to the position of the straight edge; the plurality of gate driving units further include at least one second gate driving unit located in the second frame area, and at least two of the sub-circuits in the second gate driving unit are arranged in a direction perpendicular to the straight edge and away from the display area; Preferably, a plurality of the second gate driving units located in the second border area are arranged along the extending direction of the straight side.

3. The array substrate according to claim 2, characterized in that: The plurality of gate driving units further include at least one third gate driving unit, and at least two of the sub-circuits in the third gate driving unit are arranged along a direction in which the radius of the arc angle side is away from the display area; Preferably, the plurality of third gate driving units located in the first border area are arranged along an extending direction of the arc angle edge.

4. The array substrate according to claim 3, characterized in that: Along the extending direction of the arc angle edge, the first gate driving unit is located at an end of the first border area away from the second border area, and the third gate driving unit is located at an end of the first border area close to the second border area.

5. The array substrate according to claim 4, characterized in that: The array substrate includes a dummy driving unit located in the first border area, and the dummy driving unit is located between two adjacent third gate driving units.

6. The array substrate according to claim 4, characterized in that: Along the extension direction of the arc angle edge, in at least one of the first gate driving units away from the second border area, each of the sub-circuits is arranged along the extension direction of the arc angle edge; in at least one of the third gate driving units close to the second border area, at least two of the sub-circuits are arranged along the direction away from the display area.

7. The array substrate according to claim 1, characterized in that: The array substrate comprises a plurality of rows of pixel driving units located in the display area; each sub-circuit in one of the gate driving units is respectively connected to the pixel driving units in the same row; Preferably, the pixel driving unit comprises a plurality of different switching devices, and each of the sub-circuits of the gate driving unit is electrically connected to different switching devices in the pixel driving unit through different signal wirings.

8. The array substrate according to claim 1, characterized in that: The sub-circuit of the gate driving unit includes a light emitting control circuit and at least one scanning control circuit; Preferably, the sub-circuit of the gate driving unit includes a light emitting control circuit, a first scanning control circuit and a second scanning control circuit.

9. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises the display panel according to claim 9.

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