Chip packaging structure and preparation method thereof
By etching grooves between the through-silicon via structures and filling low dielectric constant materials, the problem of low signal transmission performance of the through-silicon chip is solved, and the effect of reducing parasitic capacitance and improving signal transmission performance is achieved.
Patent Information
- Application Number
- CN202411174681.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-23
- Publication Date
- 2024-12-13
AI Technical Summary
The through-silicon chip will generate large parasitic capacitance when transmitting AC signals, resulting in a reduced chip signal transmission performance.
The grooves are etched between the through-silicon structures and filled with materials with dielectric constants less than the chip layer, such as air, to reduce parasitic capacitance between the through-silicon vias.
It effectively reduces the parasitic capacitance between the through-silicon holes and improves the signal transmission performance of the chip. The groove is located inside the chip, without increasing the packaging volume and no additional external structure is required.
Smart Images
Figure CN119133089A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip packaging structure and a preparation method thereof. Background Art
[0002] In recent years, the planar size of chips has been reduced to the limit, and three-dimensional stacking packaging technology provides a new solution for reducing the size of chips. Among them, one of the 3D stacking packaging technologies is to use silicon vias to construct chip stacking structures. However, when AC signals pass through the silicon vias, large parasitic capacitance will be generated between the silicon vias, reducing the signal transmission performance of the chip.
[0003] Therefore, a solution is needed to reduce the parasitic capacitance between the through silicon via and the chip in the chip packaging structure and improve the signal transmission performance of the chip. Summary of the invention
[0004] Therefore, the present invention provides a chip packaging structure and a preparation method thereof to solve the problem that when an AC signal passes through the existing through silicon via chip structure, a large parasitic capacitance is generated between the through silicon vias, thereby reducing the signal transmission performance of the chip.
[0005] The present invention provides a chip packaging structure, comprising:
[0006] A chip, wherein the chip comprises a chip layer and a passivation layer, wherein a surface of the chip layer facing away from the passivation layer is a first surface, and a surface of the passivation layer facing away from the chip layer is a second surface; and a plurality of PADs of the chip are arranged in the passivation layer;
[0007] A plurality of through silicon vias, wherein the through silicon vias are perpendicular to the first surface and extend from the first surface into the passivation layer to connect the PAD;
[0008] An RDL layer, covering the inner wall of the through silicon via, connecting the PAD, and extending to the first surface;
[0009] The groove is located between adjacent through silicon vias, and the groove extends from the first surface to the passivation layer and penetrates the chip layer.
[0010] Optionally, the dielectric constant of the filling material inside the groove is smaller than the dielectric constant of the chip layer.
[0011] Optionally, the groove is filled with air.
[0012] Optionally, also include:
[0013] a substrate, located on the second surface;
[0014] A first insulating layer, located between the RDL layer and the chip layer;
[0015] A second insulating layer covers a surface of the RDL layer facing away from the chip layer and completely fills the through silicon via;
[0016] The metal bump is located on a side of the second insulating layer facing away from the first surface.
[0017] Optionally, the chip layer is silicon;
[0018] The first insulating layer is an inorganic dielectric layer;
[0019] The second insulating layer is a polyimide layer.
[0020] The present invention also provides a method for preparing a chip packaging structure, which is characterized by comprising the following steps:
[0021] A chip is provided, wherein the chip comprises a chip layer and a passivation layer, wherein a surface of the chip layer facing away from the passivation layer is a first surface, and a surface of the passivation layer facing away from the chip layer is a second surface; and a plurality of PADs of the chip are arranged in the passivation layer;
[0022] A plurality of through silicon vias are formed on the first surface; the through silicon vias are perpendicular to the first surface and extend from the first surface into the passivation layer to connect the PAD;
[0023] Forming an RDL layer on the inner wall of the through silicon via and the first surface, wherein the RDL layer is connected to the PAD;
[0024] A groove is formed between adjacent through silicon vias; the groove extends from the first surface to the passivation layer and penetrates the chip layer.
[0025] Optionally, before the step of forming a plurality of through silicon vias on the first surface, the method further includes:
[0026] A substrate is provided, and the substrate is connected and fixed to the second surface of the chip; the substrate is used to support the chip.
[0027] Optionally, before the step of forming an RDL layer on the inner wall of the through silicon via and the first surface, the method further includes:
[0028] A first insulating layer is formed on the inner wall of the through silicon via and the first surface, and the first insulating layer is located between the RDL layer and the chip layer.
[0029] Optionally, before the step of forming grooves between adjacent through silicon vias, the method further includes:
[0030] A second insulating layer is formed, wherein the second insulating layer covers a surface of the RDL layer facing away from the chip layer and completely fills the through silicon via.
[0031] Optionally, forming a groove between adjacent through silicon vias includes:
[0032] Coating a photoresist on a side of the second insulating layer facing away from the first surface, and etching the photoresist to form openings of the grooves between the through silicon vias;
[0033] The groove is formed according to the opening of the groove by dry etching.
[0034] The technical solution of the present invention has the following advantages:
[0035] (1) The chip packaging structure provided by the present invention, on the one hand, can reduce the parasitic capacitance between the through silicon via structures when the chip is connected to an AC signal by etching grooves between the through silicon via structures, thereby improving the transmission performance of the chip. On the other hand, the grooves are located inside the chip, which does not increase the packaging volume, and the effect of reducing the parasitic capacitance can be achieved without the need for additional external structures.
[0036] (2) The dielectric constant of the filling material inside the groove of the chip packaging structure provided by the present invention is smaller than the dielectric constant of the chip layer, which can be regarded as replacing a part of the chip layer with a filling material with a lower dielectric constant, thereby reducing the dielectric constant of the area between the silicon through vias, thereby reducing the parasitic capacitance between the silicon through vias and improving the transmission performance of the chip.
[0037] (3) The chip packaging structure provided by the present invention fills the groove with air. Since the dielectric constant of air is approximately 1, and the chip layer is composed of silicon, and the relative dielectric constant of silicon is 11.9, the dielectric constant of the filling material inside the groove is much smaller than the dielectric constant of the chip layer. Therefore, the parasitic capacitance between silicon vias can be effectively reduced, and the transmission performance of the chip can be improved. The parasitic capacitance between silicon vias can be reduced by about 50%.
[0038] The chip packaging structure preparation method provided by the present invention can prepare the chip packaging structure provided by the present invention. On the one hand, by etching grooves between the through silicon via structures, the parasitic capacitance between the through silicon via structures can be reduced when an AC signal passes through, thereby improving the transmission performance of the chip. On the other hand, the grooves are located inside the chip, which does not increase the packaging volume, and the effect of reducing parasitic capacitance can be achieved without the need for additional external structures. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0040] Figure 1 A schematic structural diagram of a chip packaging structure according to an embodiment of the present invention;
[0041] Figure 2 A schematic diagram of a process for preparing a chip packaging structure according to an embodiment of the present invention;
[0042] Figure 3 A schematic diagram of a specific process of a method for preparing a chip packaging structure according to an embodiment of the present invention;
[0043] Figure 4 , Figure 5 , Figure 6 and Figure 7 The present invention is a schematic structural diagram of various processes of a specific method for preparing a chip packaging structure according to an embodiment of the present invention.
[0044] Description of reference numerals:
[0045] 1-chip; 11-chip layer; 12-passivation layer; 13-PAD; 2-through silicon via; 3-RDL layer; 4-groove; 5-first insulating layer; 6-second insulating layer; 7-metal bump; 8-substrate; 9-photoresist. DETAILED DESCRIPTION
[0046] In order to solve the problem that a large parasitic capacitance is generated between the TSVs when an AC signal passes through the existing TSV chip structure, thereby reducing the signal transmission performance of the chip, the present invention provides a chip packaging structure, comprising: a chip, the chip comprising a chip layer and a passivation layer, the surface of the chip layer facing away from the passivation layer being a first surface, and the surface of the passivation layer facing away from the chip layer being a second surface; a plurality of PADs of the chip are arranged in the passivation layer; a plurality of TSVs, the TSVs are perpendicular to the first surface and extend from the first surface into the passivation layer to connect the PADs; an RDL layer, covering the inner walls of the TSVs, connecting the PADs, and extending to the first surface; a groove, located between adjacent TSVs, the groove extending from the first surface to the passivation layer and penetrating the chip layer.
[0047] The present invention also provides a method for preparing a chip packaging structure, comprising the following steps: providing a chip, the chip comprising a chip layer and a passivation layer, the surface of the chip layer facing away from the passivation layer being a first surface, and the surface of the passivation layer facing away from the chip layer being a second surface; a plurality of PADs of the chip are arranged in the passivation layer; a plurality of through silicon vias are formed on the first surface; the through silicon vias are perpendicular to the first surface and extend from the first surface into the passivation layer to connect the PADs; an RDL layer is formed on the inner wall of the through silicon via and the first surface, the RDL layer connecting the PADs; a groove is formed between adjacent through silicon vias; the groove extends from the first surface to the passivation layer and passes through the chip layer.
[0048] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
[0049] Example 1
[0050] refer to Figure 1 , this embodiment provides a chip packaging structure, including:
[0051] A chip 1, comprising a chip layer 11 and a passivation layer 12, wherein a surface of the chip layer 11 facing away from the passivation layer 12 is a first surface, and a surface of the passivation layer 12 facing away from the chip layer 11 is a second surface; a plurality of PADs 13 of the chip are arranged in the passivation layer 12;
[0052] A plurality of through silicon vias 2, wherein the through silicon vias 2 are perpendicular to the first surface and extend from the first surface into the passivation layer 12 to connect the PAD 13;
[0053] The RDL layer 3 covers the inner wall of the through silicon via 2 , is connected to the PAD 13 , and extends to the first surface.
[0054] The groove 4 is located between adjacent through silicon vias 2 . The groove 4 extends from the first surface to the passivation layer 12 and penetrates the chip layer 11 .
[0055] In specific implementation, PAD13 is inside the chip layer 11. Since the net inside the chip needs to lead the chip outside for packaging, but the line width is too thin to withstand the welding pressure, it needs to be connected to a larger metal PAD13 for support. PAD13 serves as the pin of the chip. RDL layer 3 can lead the signal of PAD13 to the first surface of chip 1.
[0056] The chip packaging structure provided in this embodiment, on the one hand, can reduce the parasitic capacitance between the through silicon via structures when the chip is connected to an AC signal by etching grooves between the through silicon via structures, thereby improving the transmission performance of the chip. On the other hand, the grooves are located inside the chip, which does not increase the packaging volume, and does not require additional external structures to achieve the effect of reducing parasitic capacitance.
[0057] Furthermore, in this embodiment, the dielectric constant of the groove 4 is smaller than the dielectric constant of the chip layer 11 .
[0058] In specific implementation, capacitance is proportional to dielectric constant. The dielectric constant of groove 4 is smaller than that of chip layer 11. It can be regarded as replacing part of the chip layer with a filling material with a lower dielectric constant. The dielectric constant of the area between the through silicon vias can be reduced, thereby reducing the parasitic capacitance between the through silicon vias and improving the transmission performance of the chip.
[0059] Furthermore, in this embodiment, the groove 4 is filled with air.
[0060] In a specific implementation, since the dielectric constant of air is approximately 1, and the chip layer 11 is usually composed of silicon, and the relative dielectric constant of silicon is 11.9, the dielectric constant of the groove 4 is much smaller than the dielectric constant of the chip layer 11, which can effectively reduce the parasitic capacitance between silicon vias and improve the transmission performance of the chip.
[0061] In addition, the size of the groove is as large as possible within the feasible range of product design space and process. If the groove is as large as possible, more silicon in the chip layer can be replaced by air. The capacitance is proportional to the dielectric constant, which can more effectively reduce the parasitic capacitance between TSVs.
[0062] In one example, the groove 4 is filled with air, and according to electrical simulation results, the parasitic capacitance between through silicon vias can be reduced by about 50%.
[0063] Furthermore, in this embodiment, it also includes:
[0064] A first insulating layer 5, located between the RDL layer 3 and the chip layer 11;
[0065] The second insulating layer 6 covers the surface of the RDL layer 3 facing away from the chip layer 11 and completely fills the through silicon via 2 ; the RDL layer 3 surrounds the second insulating layer 6 filled in the through silicon via 2 .
[0066] The metal bump 7 is located on a side of the second insulating layer 6 facing away from the first surface.
[0067] In a specific implementation, the first insulating layer 5 is disposed between the RDL layer 3 and the chip layer 11, so that the RDL layer 3 and the surface of the chip layer 11 are insulated, and the RDL layer 3 and the inner sidewall of the through silicon via 2 are insulated, so that the RDL layer 3 can lead the electrical signal of the PAD 13 inside the chip layer 1 to the metal bump 7 on the first surface. The second insulating layer 6 is coated on the surface of the RDL layer 3 and completely fills the through silicon via 2, so that the chip surface can be insulated and protected; at the same time, filling the through silicon via 2 with the second insulating layer 6 can also improve the support force of the through silicon via 2.
[0068] Furthermore, in this embodiment, the chip layer 1 is silicon;
[0069] The first insulating layer 5 is an inorganic dielectric layer;
[0070] The second insulating layer 6 is a polyimide layer or other insulating medium layer.
[0071] In a specific implementation, the second insulating layer 6 may be a polyimide layer or other insulating medium layer.
[0072] In one embodiment, the first insulating layer 5 is silicon oxide.
[0073] Example 2
[0074] refer to Figure 2 The present invention also provides a method for preparing a chip packaging structure, which is used to manufacture the chip packaging structure of the above embodiment 1. The method comprises the following steps:
[0075] S201, providing a chip, wherein the chip comprises a chip layer and a passivation layer, wherein a surface of the chip layer facing away from the passivation layer is a first surface, and a surface of the passivation layer facing away from the chip layer is a second surface; and a plurality of PADs of the chip are arranged in the passivation layer.
[0076] S202, forming a plurality of through silicon vias on the first surface; the through silicon vias are perpendicular to the first surface and extend from the first surface into the passivation layer to connect the PAD.
[0077] S203 , forming an RDL layer on the inner wall of the through silicon via and the first surface, wherein the RDL layer is connected to the PAD.
[0078] S204, forming a groove between adjacent through silicon vias; the groove extends from the first surface to the passivation layer and penetrates the chip layer.
[0079] The chip packaging structure preparation method provided by the present invention can prepare the chip packaging structure provided by the present invention. On the one hand, by etching grooves between the through silicon via structures, the parasitic capacitance between the through silicon via structures can be reduced when an AC signal passes through, thereby improving the transmission performance of the chip. On the other hand, the grooves are located inside the chip, which does not increase the packaging volume, and the effect of reducing parasitic capacitance can be achieved without the need for additional external structures.
[0080] Furthermore, in some embodiments, before the step of forming a plurality of through silicon vias on the first surface, the method further includes:
[0081] A substrate is provided, and the substrate is connected and fixed to the second surface of the chip; the substrate is used to support the chip.
[0082] Furthermore, in some embodiments, before the step of forming the RDL layer on the inner wall of the through silicon via and the first surface, the method further includes:
[0083] A first insulating layer is formed on the inner wall of the through silicon via and the first surface, and the first insulating layer is located between the RDL layer and the chip layer.
[0084] Furthermore, in some embodiments, before the step of forming grooves between adjacent through silicon vias, the method further includes:
[0085] A second insulating layer is formed, wherein the second insulating layer covers a surface of the RDL layer facing away from the chip layer and completely fills the through silicon via.
[0086] Further, in some embodiments, forming a groove between adjacent through silicon vias includes:
[0087] Coating a photoresist on a side of the second insulating layer facing away from the first surface, and etching the photoresist to form openings of the grooves between the through silicon vias;
[0088] The groove is formed according to the opening of the groove by dry etching.
[0089] In one example, a specific method for preparing a chip packaging structure is as follows: Figure 3 As shown, the following steps are included:
[0090] S301, provide a chip 1, the chip comprising a chip layer 11 and a passivation layer 12, the surface of the chip layer 11 facing away from the passivation layer 12 is a first surface, and the surface of the passivation layer 12 facing away from the chip layer 11 is a second surface; a plurality of PADs 13 of the chip are arranged in the passivation layer 12.
[0091] S302 , providing a substrate 8 , and connecting and fixing the substrate 8 to the second surface of the chip 1 ; the substrate 8 is used to support the chip 1 .
[0092] In a specific implementation, the substrate 8 is glass or silicon; the size of the substrate 8 is the same as the size of the second surface.
[0093] S303, forming a plurality of through silicon vias 2 on the first surface; the through silicon vias 2 are perpendicular to the first surface and extend from the first surface 1 into the passivation layer 12 to connect the PAD 13, such as Figure 4 shown.
[0094] S304 , forming a first insulating layer 5 on the inner wall of the through silicon via 2 and the first surface, wherein the first insulating layer 5 is located between the RDL layer 3 and the chip layer 1 .
[0095] S305 , forming an RDL layer 3 on a surface of the first insulating layer 5 that is opposite to the inner wall of the through silicon via 2 and the first surface, wherein the RDL layer 3 is connected to the PAD 13 .
[0096] S306 , forming a second insulating layer 6 , wherein the second insulating layer 6 covers the surface of the RDL layer facing away from the chip layer 11 and completely fills the interior of the through silicon via 2 .
[0097] S307 , forming a groove 4 between adjacent through silicon vias 2 ; the groove 4 extends from the first surface to the passivation layer 12 and penetrates the chip layer.
[0098] When implementing it, first, Figure 5 As shown, a photoresist 9 is coated on the side of the second insulating layer 6 facing away from the first surface, and the photoresist 9 is etched to form the opening of the groove between the through silicon vias 2; secondly, as shown Figure 6 As shown, dry etching is used to form the groove 4 according to the opening of the groove, and finally the photoresist 9 is removed.
[0099] S308, forming a metal bump 7, wherein the metal bump 7 is located on a side of the second insulating layer 6 facing away from the first surface. Figure 7 shown.
[0100] S309, removing the substrate 8, such as Figure 7 shown.
[0101] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.
Claims
1. A chip packaging structure, characterized in that: include: A chip, wherein the chip comprises a chip layer and a passivation layer, wherein a surface of the chip layer facing away from the passivation layer is a first surface, and a surface of the passivation layer facing away from the chip layer is a second surface; and a plurality of PADs of the chip are arranged in the passivation layer; A plurality of through silicon vias, wherein the through silicon vias are perpendicular to the first surface and extend from the first surface into the passivation layer to connect the PAD; An RDL layer, covering the inner wall of the through silicon via, connecting the PAD, and extending to the first surface; The groove is located between adjacent through silicon vias, and the groove extends from the first surface to the passivation layer and penetrates the chip layer.
2. The chip packaging structure according to claim 1, characterized in that: The dielectric constant of the filling material inside the groove is smaller than the dielectric constant of the chip layer.
3. The chip packaging structure according to claim 2, characterized in that: The groove is filled with air.
4. The chip packaging structure according to claim 3, characterized in that: Also includes: A first insulating layer, located between the RDL layer and the chip layer; A second insulating layer covers a surface of the RDL layer facing away from the chip layer and completely fills the through silicon via; The metal bump is located on a side of the second insulating layer facing away from the first surface.
5. The chip packaging structure according to claim 4, characterized in that: The chip layer is silicon; The substrate is glass or silicon; the size of the substrate is the same as the size of the second surface; The first insulating layer is an inorganic dielectric layer; The second insulating layer is a polyimide layer.
6. A method for preparing a chip packaging structure, characterized in that: The following steps are involved: A chip is provided, the chip comprising a chip layer and a passivation layer, a surface of the chip layer facing away from the passivation layer is a first surface, and a surface of the passivation layer facing away from the chip layer is a second surface; a plurality of PADs of the chip are arranged in the passivation layer; forming a plurality of through silicon vias on the first surface; The through silicon via is perpendicular to the first surface and extends from the first surface into the passivation layer to connect the PAD; Forming an RDL layer on the inner wall of the through silicon via and the first surface, wherein the RDL layer is connected to the PAD; A groove is formed between adjacent through silicon vias; the groove extends from the first surface to the passivation layer and penetrates the chip layer.
7. The method for preparing a chip packaging structure according to claim 6, characterized in that: Before the step of forming a plurality of through silicon vias on the first surface, the method further comprises: A substrate is provided, and the substrate is connected and fixed to the second surface of the chip; the substrate is used to support the chip.
8. The method for preparing a chip packaging structure according to claim 7, characterized in that: Before the step of forming the RDL layer on the inner wall of the through silicon via and the first surface, the method further includes: A first insulating layer is formed on the inner wall of the through silicon via and the first surface, and the first insulating layer is located between the RDL layer and the chip layer.
9. The method for preparing a chip packaging structure according to claim 8, characterized in that: Before the step of forming grooves between adjacent through silicon vias, the method further includes: A second insulating layer is formed, wherein the second insulating layer covers a surface of the RDL layer facing away from the chip layer and completely fills the through silicon via.
10. The method for preparing a chip packaging structure according to claim 9, characterized in that: The forming of grooves between adjacent through silicon vias comprises: Coating a photoresist on a side of the second insulating layer facing away from the first surface, and etching the photoresist to form openings of the grooves between the through silicon vias; The groove is formed according to the opening of the groove by dry etching.