Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof, and the method for manufacturing the semiconductor element mainly comprises the steps: firstly, providing a substrate which comprises a low-voltage region and a medium-voltage region, and then forming a first metal gate in the low-voltage region and a second metal gate in the medium-voltage region, the method includes forming a first metal gate on a substrate, forming a second metal gate on the substrate, forming a first patterned mask on the second metal gate, removing a portion of the first metal gate, forming a second patterned mask on the first metal gate, removing a portion of the second metal gate, and then forming a first hard mask on the first metal gate and a second hard mask on the second metal gate.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a semiconductor element, and in particular to a method for adjusting the thickness of a hard mask directly above a gate structure in a low-voltage area and a medium-voltage area. Background Art

[0002] With the current semiconductor technology level, the industry has been able to integrate control circuits, memory, low-voltage operating circuits, and high-voltage operating circuits and components on a single chip, thereby reducing costs and improving operating performance. Among them, high-voltage components such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT) and lateral-diffusion metal-oxide-semiconductor (LDMOS) are more commonly used because of their better switching efficiency. As known to those familiar with the art, the aforementioned high-voltage components are often required to withstand a higher breakdown voltage and operate at a lower resistance.

[0003] In addition, as the size of components continues to shrink, the development of existing planar field effect transistor components has faced the limit of manufacturing process. In order to overcome the limitation of manufacturing process, it has become the current mainstream development trend to replace planar transistor components with non-planar field effect transistor components, such as fin field effect transistor (Fin FET) components. Since the three-dimensional structure of the fin field effect transistor component can increase the contact area between the gate and the fin structure, the gate can further increase the control of the carrier channel region, thereby reducing the drain induced barrier lowering (DIBL) effect faced by small-sized components and suppressing the short channel effect (SCE). Furthermore, since the fin field effect transistor component has a wider channel width at the same gate length, it can obtain double the drain drive current. Even more, the threshold voltage of the transistor component can be regulated by adjusting the work function of the gate.

[0004] However, as the size of components continues to shrink, there are still many challenges in integrating the existing high-voltage components with the fin structure, such as the control of leakage current and breakdown voltage, etc. Therefore, how to improve the existing high-voltage component architecture is an important issue today. Summary of the invention

[0005] An embodiment of the present invention discloses a method for manufacturing a semiconductor element, which mainly provides a substrate including a low-voltage area and a medium-voltage area, then forms a first metal gate in the low-voltage area and a second metal gate in the medium-voltage area, forms a first patterned mask on the second metal gate, removes a portion of the first metal gate, forms a second patterned mask on the first metal gate, removes a portion of the second metal gate, and then forms a first hard mask on the first metal gate and a second hard mask on the second metal gate.

[0006] Another embodiment of the present invention discloses a semiconductor element, which mainly includes a substrate including a low-voltage area and a medium-voltage area, a first gate structure arranged in the low-voltage area and a second gate structure arranged in the medium-voltage area, a first hard mask arranged on the first gate structure and a second hard mask arranged on the second gate structure, wherein the first hard mask and the second hard mask include different thicknesses. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 8 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0008] Fig. 9 FIG. 4 is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention.

[0009] Explanation of symbols

[0010] 12: Base

[0011] 14: Fin structure

[0012] 16: Shallow Trench Isolation

[0013] 18: Gate structure

[0014] 20: Gate structure

[0015] 22: Gate structure

[0016] 24: Gate structure

[0017] 26: Gate structure

[0018] 28: Gate structure

[0019] 30: Gate dielectric layer

[0020] 32: Gate material layer

[0021] 34: Gap wall

[0022] 36: Source / drain region

[0023] 38: Epitaxial layer

[0024] 40: Contact hole etching stop layer

[0025] 42: Interlayer dielectric layer

[0026] 46: High dielectric constant dielectric layer

[0027] 48: Work function metal layer

[0028] 50: Low impedance metal layer

[0029] 52:Metal gate

[0030] 54: Patterned mask

[0031] 56: Groove

[0032] 58: Groove

[0033] 60: Patterned mask

[0034] 62: Hard mask

[0035] 64: Contact plug

[0036] 102: Low pressure area

[0037] 104: Medium pressure area DETAILED DESCRIPTION

[0038] Please refer to Figures 1 to 8 , Figures 1 to 8 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, wherein the substrate 12 preferably has a low voltage region 102 and a medium voltage region 104, and the surface of the substrate 12 in the low voltage region 102 is preferably aligned with the surface of the substrate 12 in the medium voltage region 104. Then, a fin structure 14 can be selectively formed on the substrate 12 in the low voltage region 102, but no fin structure is formed on the substrate 12 in the medium voltage region 104. In other words, non-planar field effect transistors such as fin structure transistors can be prepared on the low voltage region 102 according to the manufacturing process requirements, while planar field effect transistors are preferably prepared on the medium voltage region 104.

[0039] According to one embodiment of the present invention, the fin structure 14 is preferably manufactured by sidewall image transfer (SIT) and other technologies, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. Subsequently, the patterned sacrificial layer is removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0040] In addition, the formation method of the fin structure 14 may include first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the fin structure 14. In addition, the formation method of the fin structure 14 may also include first forming a patterned hard mask layer (not shown) on the substrate 12, and using an epitaxial process to grow a semiconductor layer such as silicon germanium on the substrate 12 exposed from the patterned hard mask layer, and this semiconductor layer can serve as the corresponding fin structure 14. These embodiments of forming the fin structure 14 are all within the scope of the present invention.

[0041] Then, a shallow trench isolation (STI) 16 is formed to surround the fin structure 14 and separate the low voltage region 102 from the high voltage region 104. In the present embodiment, the shallow trench isolation 16 can be formed by first using a flowable chemical vapor deposition (FCVD) process to form a silicon oxide layer on the substrate 12 and completely cover the fin structure 14. Then, a chemical mechanical polishing (CMP) process is used in combination with an etching process to remove a portion of the silicon oxide layer, so that the remaining silicon oxide layer is lower than the surface of the fin structure 14 to form the shallow trench isolation 16.

[0042] Then, gate structures 18, 20, 22, 24, 26, 28 or dummy gates are formed on the substrate 12 in the low voltage region 102 and the medium voltage region 104. In the present embodiment, the gate structures 18, 20, 22, 24, 26, 28 can be fabricated by gate first fabrication process, gate last fabrication process of high-k first fabrication process, gate last fabrication process of high-k last fabrication process, etc. according to the fabrication process requirements. Taking the post-high-k dielectric layer manufacturing process of the present embodiment as an example, a gate dielectric layer 30 or a dielectric layer, a gate material layer 32 composed of polycrystalline silicon and a selective hard mask (not shown) can be sequentially formed on the substrate 12, and a pattern transfer manufacturing process is performed using a patterned photoresist (not shown) as a mask to remove part of the gate material layer 32 and part of the gate dielectric layer 30 by a single etching or successive etching steps, and then the patterned photoresist is stripped off to form gate structures 18, 20, 22, 24, 26, 28 each composed of a patterned gate dielectric layer 30 and a patterned gate material layer 32 on the fin structure 14.

[0043] It should be noted that in order to cope with the different voltages required for the operation of low-voltage components and medium-voltage components, the gate structures 18, 20, 22 in the low-voltage region 102 and the gate structures 24, 26, 28 in the medium-voltage region 104 are preferably completed in different stages, wherein the gate dielectric layer 30 of the low-voltage region 102 and the gate dielectric layer 30 of the medium-voltage region 104 preferably have different thicknesses, for example, the thickness of the gate dielectric layer 30 of the low-voltage region 102 is preferably smaller than the thickness of the gate dielectric layer 30 of the medium-voltage region 104.

[0044] Then, at least one spacer 34 is formed on the sidewalls of the gate structures 18, 20, 22, 24, 26, and 28, respectively, and then a source / drain region 36 and / or an epitaxial layer 38 are formed in the fin structure 14 and / or the substrate 12 on both sides of the spacer 34, and a metal silicide (not shown) is selectively formed on the surface of the source / drain region 36 and / or the epitaxial layer 38. It should be noted that in this embodiment, since the source / drain region 36 is only formed in the substrate 12 on both sides of the gate structure 20 in the low voltage region 102 and the gate structure 26 in the medium voltage region 104, only the gate structures 20 and 26 are active gate structures, and the remaining gate structures 18, 22, 24, and 28 are dummy gate structures.

[0045] In the present embodiment, the spacer 34 may be a single spacer or a composite spacer, for example, it may include an offset spacer and a main spacer in detail. The offset spacer and the main spacer may include the same or different materials, and both may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide. The source / drain region 36 may include different dopants according to the conductivity type of the transistor to be provided, for example, it may include P-type dopants or N-type dopants.

[0046] In a preferred embodiment of the present invention, the epitaxial layer 38 may have different materials according to different types of metal oxide semiconductor (MOS) transistors. For example, if the metal oxide semiconductor transistor is a P-type transistor (PMOS), the epitaxial layer 38 may include silicon germanium (SiGe), silicon germanium boron (SiGeB) or silicon germanium tin (SiGeSn). In another embodiment of the present invention, if the metal oxide semiconductor transistor is an N-type transistor (NMOS), the epitaxial layer 38 may include silicon carbide (SiC), silicon carbon phosphide (SiCP) or silicon phosphide (SiP). In addition, the selective epitaxial manufacturing process may be formed in a single layer or multi-layer manner, and its heterogeneous atoms (such as germanium atoms or carbon atoms) may also be changed in a gradual manner, but it is preferred to make the surface of the epitaxial layer 38 lighter or without germanium atoms to facilitate the subsequent formation of a metal silicide layer.

[0047] According to one embodiment of the present invention, the source / drain region 36 can be selectively formed on a part or all of the epitaxial layer 38. In one embodiment, the formation of the source / drain region 36 can also be performed in-situ in the selective epitaxial growth process. For example, when the metal oxide semiconductor is a PMOS, the formation of a germanium silicide epitaxial layer, a germanium boron silicide epitaxial layer or a germanium tin silicide epitaxial layer can be accompanied by the implantation of a P-type dopant; or when the metal oxide semiconductor is an NMOS, the formation of a carbon silicide epitaxial layer, a carbon phosphorus silicide epitaxial layer or a phosphorus silicide epitaxial layer can be accompanied by the implantation of an N-type dopant. This can omit the subsequent use of additional ion implantation steps to form the source / drain region 36 of the P-type / N-type transistor. In addition, in another embodiment, the dopants of the source / drain region 36 can also be formed in a gradual manner.

[0048] Next, a contact hole etch stop layer 40 is formed to cover the surfaces of the gate structures 18, 20, 22, 24, 26, 28 and the shallow trench isolation 16, and then an interlayer dielectric layer 42 is formed on the contact hole etch stop layer 40. Then, a planarization process is performed, such as using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 42 and part of the contact hole etch stop layer 40 and expose the gate material layer 32 composed of polysilicon material, so that the upper surface of the gate material layer 32 is flush with the upper surface of the interlayer dielectric layer 42.

[0049] like Figure 2 As shown, a metal gate replacement process is then performed to convert the gate structures 18, 20, 22, 24, 26, 28 of the medium voltage region 102 and the low voltage region 104 into metal gates. For example, a selective dry etching or wet etching process may be performed first, such as using ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH) or other etching solutions are used to remove the gate material layer 32 and even the gate dielectric layer 30 in the gate structures 18, 20, 22, 24, 26, and 28 to form a groove in the interlayer dielectric layer 42 (not shown).

[0050] Then, a selective dielectric layer (not shown) or gate dielectric layer, a high dielectric constant dielectric layer 46, a work function metal layer 48 and a low impedance metal layer 50 are sequentially formed in the groove, and then a planarization process is performed, such as using CMP to remove part of the low impedance metal layer 50, part of the work function metal layer 48 and part of the high dielectric constant dielectric layer 46 to form a metal gate 52. Taking the gate structure manufactured by the post high dielectric constant dielectric layer manufacturing process in this embodiment as an example, each formed metal gate 52 preferably includes a dielectric layer or gate dielectric layer 30, a U-shaped high dielectric constant dielectric layer 46, a U-shaped work function metal layer 48 and a low impedance metal layer 50.

[0051] In this embodiment, the high-k dielectric layer 46 includes a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (tantalum oxide, Ta 2 O 5 ), yttrium oxide (yttrium oxide, Y 2 O 3 ), zirconium oxide (zirconium oxide, ZrO 2 ), strontium titanate oxide (SrTiO3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 ,PZT), barium strontium titanate (Ba x Sr 1- x TiO 3 , BST), or a group consisting of their combinations.

[0052] The work function metal layer 48 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl) or TiAlC (titanium aluminum carbide), etc., but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 48 and the low resistance metal layer 50, wherein the barrier layer may be made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low resistance metal layer 50 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., or a combination thereof.

[0053] like Figure 3 As shown, a patterned mask 54 such as a patterned photoresist is then formed on the metal gate 52 and the interlayer dielectric layer 42 in the medium voltage region 104 and exposes the metal gate 52 and the surface of the interlayer dielectric layer 42 in the low voltage region 102 .

[0054] Then as Figure 4As shown, an etching process is performed using the patterned mask 54 as a mask to remove part of the metal gate 52 in the low voltage region 102 and even part of the interlayer dielectric layer 42, and then the patterned mask 54 is removed. More specifically, the etching process performed at this stage preferably removes part of the high dielectric constant dielectric layer 46, part of the work function metal layer 48, part of the low resistance metal layer 50, and even part of the interlayer dielectric layer 42 around the metal gate 52 in the low voltage region 102, so as to form a groove 56 above the remaining metal gate 52 and a groove 58 in the interlayer dielectric layer 42 next to the metal gate 52.

[0055] In this embodiment, the bottom surface of the groove 56 directly above the metal gate 52 is preferably slightly lower than the bottom surface of the groove 58 in the interlayer dielectric layer 42, and when removing part of the metal gate 52, it is preferred to remove more high-k dielectric layer 46 and work function metal layer 48 and less low-resistance metal layer 50, so that the top surface of the remaining low-resistance metal layer 50 is slightly higher than the top surfaces of the high-k dielectric layer 46 and the work function metal layer 48. According to one embodiment of the present invention, the depth of the groove 56 directly above the metal gate 52 in the low voltage region 102 is preferably about 350-400 angstroms or 380 angstroms, and the depth of the groove 58 in the interlayer dielectric layer 42 is preferably about 50-70 angstroms or 60 angstroms.

[0056] like Figure 5 As shown, another patterned mask 60 such as another patterned photoresist is subsequently formed on the metal gate 52 and the interlayer dielectric layer 42 in the low voltage region 102 to expose the metal gate 52 and the top surface of the interlayer dielectric layer 42 in the medium voltage region 104 .

[0057] Then as Figure 6 As shown, an etching process is performed using the patterned mask 60 as a mask to remove part of the metal gate 52 in the medium voltage region 104 and even part of the interlayer dielectric layer 42, and then the patterned mask 60 is removed. As in the above-mentioned removal of the metal gate 52 in the low voltage region 102, the etching process performed in this stage preferably removes part of the high dielectric constant dielectric layer 46, part of the work function metal layer 48, part of the low resistance metal layer 50 in the metal gate 52 in the medium voltage region 104, and part of the interlayer dielectric layer 42 around the metal gate 52, so as to form a groove 56 above the remaining metal gate 52 and a groove 58 in the interlayer dielectric layer 42 next to the metal gate 52.

[0058] In this embodiment, the bottom surface of the groove 56 directly above the metal gate 52 in the medium voltage region 104 is preferably slightly lower than the bottom surface of the groove 58 in the interlayer dielectric layer 42, and when removing part of the metal gate 52, it is preferred to remove more high dielectric constant dielectric layer 46 and work function metal layer 48 and less low impedance metal layer 50, so that the top surface of the remaining low impedance metal layer 50 is slightly higher than the top surfaces of the high dielectric constant dielectric layer 46 and the work function metal layer 48.

[0059] According to an embodiment of the present invention, the depth of the groove 56 directly above the metal gate 52 in the medium voltage region 104 is preferably about 150-200 angstroms or 180 angstroms in the best case, and the depth of the groove 58 in the interlayer dielectric layer 42 is preferably about 50-70 angstroms or 60 angstroms in the best case. In other words, at this stage, the depth of the groove 56 directly above the metal gate 52 in the medium voltage region 104 is preferably slightly smaller than the depth of the groove 56 directly above the metal gate 52 in the low voltage region 102, or the bottom surface of the groove 56 directly above the metal gate 52 in the medium voltage region 104 is slightly higher than the bottom surface of the groove 56 directly above the metal gate 52 in the low voltage region 102.

[0060] Then as Figure 7 As shown, a hard mask 62 is formed in the grooves 56 and 58 of the low voltage region 102 and the medium voltage region 104 and fills each groove 56 and 58, and then a planarization process is performed, such as using CMP to remove part of the hard mask 62, including part of the hard mask 62 directly above each gate structure and all the hard mask 62 in the interlayer dielectric layer 42, so that the top surface of the remaining hard mask 62 is flush with the top surface of the interlayer dielectric layer 42. It should be noted that since the depth of the groove 56 of the medium voltage region 104 is less than the depth of the groove 56 of the low voltage region 102, the thickness of the hard mask 62 of the medium voltage region 104 after filling the hard mask 62 is preferably less than the thickness of the hard mask 62 of the low voltage region 102. In this embodiment, the hard mask 62 can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon nitride carbide.

[0061] From a detailed perspective, at this stage, since approximately 150 angstroms of the hard mask 62 are removed from the low-voltage region 102 and the medium-voltage region 104 respectively through the aforementioned CMP process, the thickness of the hard mask 62 remaining directly above the metal gate 52 in the low-voltage region 102 is preferably approximately 200 to 250 angstroms or optimally 230 angstroms, and the thickness of the hard mask 62 remaining directly above the metal gate 52 in the medium-voltage region 104 is preferably approximately 10 to 60 angstroms or optimally approximately 30 angstroms.

[0062] Afterwards Figure 8As shown, a pattern transfer process may be performed, for example, a pattern mask may be used to remove a portion of the interlayer dielectric layer 42 and a portion of the contact hole etch stop layer 40 next to the gate structures 18, 20, 22, 24, 26, 28 and a portion of the hard mask 62 directly above the gate structures 20, 26 to form a plurality of contact holes (not shown) and expose the source / drain regions 36 and the top surfaces of the active gate structures 20, 26. Then, the required metal material is filled in each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from a low-resistance material such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., or a combination thereof. Then, a planarization process is performed, such as chemical mechanical polishing to remove part of the metal material to form contact plugs 64 in each contact hole to electrically connect the source / drain region 36 and the active gate structures 20 and 26. Thus, the manufacturing of the semiconductor device of the preferred embodiment of the present invention is completed.

[0063] Please continue to refer to Fig. 9 , Fig. 9 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is disclosed. Fig. 9 As shown, the semiconductor device mainly includes at least one gate structure 20 disposed in the low voltage region 102 and at least one gate structure 26 disposed in the medium voltage region 104, a hard mask 62 disposed directly above the gate structure 20 in the low voltage region 102 and another hard mask 62 disposed on the gate structure 26 in the medium voltage region 104. Compared with the surface of the substrate 12 of the low voltage region 102 in the previous embodiment being flush with the surface of the substrate 12 of the medium voltage region 104, the surface of the substrate 12 of the low voltage region 102 in this embodiment is preferably slightly higher than the surface of the substrate 12 of the medium voltage region 104.

[0064] In addition, in this embodiment, the hard mask 62 directly above the gate structure 20 in the low voltage region 102 and the hard mask 62 directly above the gate structure 26 in the medium voltage region 104 preferably have different thicknesses, but the top surfaces of the two are preferably aligned with each other. In addition, unlike the previous embodiment in which the thickness of the hard mask 62 in the pressure region 104 is less than the thickness of the hard mask 62 in the low voltage region 102, the thickness of the hard mask 62 in the pressure region 104 in this embodiment is preferably greater than the thickness of the hard mask 62 in the low voltage region 102. In detail, in this embodiment, the thickness of the hard mask 62 directly above the metal gate 52 in the low voltage region 102 is preferably between 200 and 250 angstroms or preferably 230 angstroms, while the thickness of the hard mask 62 directly above the metal gate 52 in the medium voltage region 104 is preferably between 400 and 450 angstroms or preferably 430 angstroms.

[0065] In summary, the present invention mainly discloses a method for adjusting the thickness of the hard mask directly above the gate structure of the low-voltage region and the medium-voltage region respectively by using photolithography and etching processes, thereby reducing the situation in which the medium-voltage region has a large height difference due to excessive loss of the hard mask in the general low-voltage region. According to one embodiment of the present invention, after converting the polysilicon gate into a metal gate in the low-voltage region and the medium-voltage region according to the metal gate replacement process, a patterned mask 54 is first formed to cover the medium-voltage region, a portion of the metal gate in the low-voltage region is removed to form a groove, the patterned mask 54 is removed, another patterned mask 60 is formed to cover the low-voltage region, a portion of the metal gate in the medium-voltage region is removed to form a groove, the patterned mask 60 is removed, and a hard mask is simultaneously formed in the grooves of the low-voltage region and the medium-voltage region. Since the grooves of the low-voltage region and the medium-voltage region have different depths, the hard masks finally formed in each region also preferably have different thicknesses. In addition, although the aforementioned embodiment takes the removal of the metal gate in the low voltage area first and then the metal gate in the medium voltage area as an example, it is not limited to this order. The present invention can also remove the metal gate in the medium voltage area first and then the metal gate in the low voltage area according to the manufacturing process requirements. Such variations are all within the scope of the present invention.

[0066] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: Providing a substrate including a low pressure area and a medium pressure area; forming a first metal gate in the low voltage region and a second metal gate in the medium voltage region; forming a first patterned mask on the second metal gate; removing a portion of the first metal gate; forming a second patterned mask on the first metal gate; removing a portion of the second metal gate; as well as A first hard mask is formed on the first metal gate and a second hard mask is formed on the second metal gate.

2. The method of claim 1, further comprising: forming a first gate structure in the low voltage region and a second gate structure in the medium voltage region; forming an interlayer dielectric layer surrounding the first gate structure and the second gate structure; and The first gate structure and the second gate structure are converted into the first metal gate and the second metal gate. The method of claim 1 , wherein the base surface of the low-pressure region is aligned with the base surface of the medium-pressure region. The method of claim 3 , wherein a bottom surface of the first metal gate is lower than a bottom surface of the second metal gate. The method of claim 3 , wherein the second hard mask thickness is less than the first hard mask thickness. The method of claim 1 , wherein the substrate surface of the low-pressure zone is higher than the substrate surface of the medium-pressure zone. 7 . The method of claim 6 , wherein a bottom surface of the first metal gate is higher than a bottom surface of the second metal gate. The method of claim 6 , wherein the first hard mask thickness is less than the second hard mask thickness.

9. The method of claim 1, wherein the first hard mask top surface is flush with the second hard mask top surface.

10. A semiconductor element, characterized in that: Include: The base, which includes low-pressure areas and medium-pressure areas; A first gate structure disposed in the low voltage region and a second gate structure disposed in the medium voltage region; and A first hard mask is disposed on the first gate structure and a second hard mask is disposed on the second gate structure, wherein the first hard mask and the second hard mask have different thicknesses. 11 . The semiconductor device as claimed in claim 10 , wherein the base surface of the low voltage region is flush with the base surface of the medium voltage region. 12 . The semiconductor device as claimed in claim 11 , wherein a bottom surface of the first metal gate is lower than a bottom surface of the second metal gate. 13 . The semiconductor device as claimed in claim 11 , wherein a thickness of the second hard mask is smaller than a thickness of the first hard mask. 14 . The semiconductor device as claimed in claim 10 , wherein the substrate surface of the low voltage region is higher than the substrate surface of the medium voltage region. 15 . The semiconductor device as claimed in claim 14 , wherein a bottom surface of the first metal gate is higher than a bottom surface of the second metal gate. The semiconductor device as claimed in claim 14 , wherein the first hard mask thickness is smaller than the second hard mask thickness. 17 . The semiconductor device as claimed in claim 10 , wherein a top surface of the first hard mask is flush with a top surface of the second hard mask.

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