Method for processing substrate with supporting structure and chip packaging structure

Abstract

The invention relates to the technical field of chip packaging, in particular to a processing method of a substrate with a supporting structure and a chip packaging structure. According to the chip packaging structure, the supporting structure is arranged on the substrate, the barrier film is supported through the supporting structure, the barrier film is prevented from being in contact with the chip pins due to the influence of pressure, pollution caused by an effective resonance area is avoided, meanwhile, the integrity of the cavity is guaranteed, and the performance of the chip is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a substrate processing method with a supporting structure and a chip packaging structure. Background Art

[0002] Chip packaging structure is one of the key steps in the integrated circuit (IC) manufacturing process, designed to protect the fragile silicon chip from physical damage, chemical corrosion and environmental impact, and provide a way to electrically connect to external circuit boards.

[0003] At present, the chip packaging adopts a plastic sealing layer covering the substrate to wrap the chip, and the plastic sealing layer, substrate and chip form a sealed cavity to prevent the effective resonance area of ​​the chip from being contaminated by the outside world. In order to prevent the overflowing resin from entering the cavity and contaminating the effective resonance area of ​​the chip when the resin and the substrate surface are pressed together, a barrier film is usually set between the chip and the plastic sealing layer. The edge of the barrier film is adhesively connected to the substrate. However, during the resin pressing process, the barrier film will extend downward due to the pressure, and even contact with the pins of the chip, destroying the integrity of the cavity and seriously reducing the performance of the chip. Summary of the invention

[0004] The embodiments of the present invention provide a substrate processing method with a support structure and a chip packaging structure to solve the problem in the prior art that during the resin pressing process, the barrier film will extend downward due to the pressure and even contact the pins of the chip, thereby destroying the integrity of the cavity and seriously reducing the performance of the chip.

[0005] In a first aspect, the present invention provides a chip packaging structure, comprising: a substrate, a chip, a barrier film and a plastic sealing layer, wherein the conductive pins of the chip are electrically interconnected with the substrate, the barrier film is arranged on the substrate, the barrier film and the substrate form a cavity, the chip is arranged in the cavity, the barrier film and the substrate form a plastic sealing layer, a support structure is arranged on the substrate in the cavity, and the support structure is used to support the barrier film when the plastic sealing layer is pressed.

[0006] In one embodiment, the height of the support structure is half of the height of the chip on the substrate.

[0007] In one embodiment, the support structure includes a first solder resist layer and a second solder resist layer, wherein the second solder resist layer is disposed above the first solder resist layer.

[0008] In one embodiment, the support structure is a step structure, and a width of the second solder resist layer is smaller than a width of the first solder resist layer.

[0009] In one embodiment, the support structures are respectively disposed on the front side, the back side, the left side and the right side of the chip.

[0010] In a second aspect, the present invention provides a method for processing a substrate having a support structure, the processing method comprising:

[0011] Providing a substrate with a prepared circuit pattern;

[0012] Applying ink on the substrate for the first time to obtain a substrate coated with ink for the first time;

[0013] Performing a first exposure on the substrate using an exposure device to obtain a substrate after the first exposure;

[0014] coating ink for a second time on the substrate after the first exposure to obtain a substrate coated with ink for the second time;

[0015] performing a second exposure on the substrate using the exposure device to obtain a substrate after the second exposure;

[0016] The substrate after the second exposure is developed and cleaned to obtain a substrate with a support structure.

[0017] In one embodiment, after obtaining the substrate having the support structure, the processing method further comprises:

[0018] The substrate with the support structure is cured to obtain a cured substrate.

[0019] In one embodiment, after obtaining the substrate coated with ink for the first time and before using an exposure device to expose the substrate for the first time, the processing method further includes:

[0020] Performing a first pre-curing on the substrate after the first coating of ink to obtain a first pre-cured substrate;

[0021] After obtaining the substrate coated with ink for the second time and before exposing the substrate for the second time using an exposure device, the processing method further includes:

[0022] The substrate after the second coating of ink is subjected to a second pre-curing to obtain a substrate after the second pre-curing.

[0023] In one embodiment, after obtaining the cured substrate, the processing method further comprises:

[0024] Performing surface treatment on the substrate to obtain a surface-treated substrate;

[0025] The substrate after the surface treatment is subjected to detection treatment to obtain the substrate after the detection treatment.

[0026] In one embodiment, providing a substrate with a circuit pattern prepared includes:

[0027] A substrate is provided, and the substrate is subjected to copper coating, film lamination, exposure, development and etching to prepare a circuit pattern.

[0028] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0029] The chip packaging structure of the present invention is provided with a support structure on the substrate, and the barrier film is supported by the support structure to prevent the barrier film from contacting the chip pins due to pressure, thereby avoiding contamination of the effective resonance area and ensuring the integrity of the cavity, thereby greatly improving the performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0031] Figure 1 is a schematic cross-sectional structural diagram of a chip packaging structure provided by an embodiment of the present invention;

[0032] Figure 2 is a schematic diagram of a top view of a chip packaging structure provided by an embodiment of the present invention;

[0033] Figure 3 It is a schematic flow chart of a method for processing a substrate with a support structure provided by one embodiment of the present invention;

[0034] Figure 4 It is a schematic flow chart of a method for processing a substrate with a support structure provided by one embodiment of the present invention;

[0035] Figure 5 It is a schematic flow chart of a method for processing a substrate with a support structure provided by one embodiment of the present invention;

[0036] Figure 6 It is a schematic flow chart of a method for processing a substrate with a support structure provided by one embodiment of the present invention;

[0037] Among them, 1. chip, 2. barrier film, 3. plastic sealing layer, 4. substrate, 5. supporting structure, 6. pins of chip packaging structure, 51. first solder resist layer, 52. second solder resist layer. DETAILED DESCRIPTION

[0038] In order to make the technical problems, technical solutions and beneficial effects solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0039] In the description of the present invention, it should be understood that the terms "longitudinal", "radial", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0040] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0041] In order to fully understand the present invention, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0043] like Figure 1 As shown, a schematic diagram of the cross-sectional structure of a chip 1 packaging structure is provided, such as Figure 2 As shown, a schematic diagram of a top view of a chip 1 packaging structure is provided.

[0044] In one embodiment, if Figure 1 and Figure 2As shown, it includes: a substrate 4, a chip 1, a barrier film 2 and a plastic sealing layer 3, the conductive pins of the chip 1 are electrically interconnected with the substrate 4, the barrier film 2 is arranged on the substrate 4, the barrier film 2 and the substrate 4 form a cavity, the chip 1 is arranged in the cavity, the barrier film 2 and the plastic sealing layer 3 are formed on the substrate 4, and a support structure 5 is arranged on the substrate 4 in the cavity, and the support structure 5 is used to support the barrier film 2 when the plastic sealing layer 3 is pressed.

[0045] The support structure 5 can be a support structure 5 of any material, the support structure 5 can be made of metal, the support structure 5 can also be made of ink, and the support structure 5 can also be made of plastic. The height of the support structure 5 can be set according to the actual application situation. Preferably, the height of the support structure 5 should not be greater than the height of the chip 1 on the substrate 4, and the height of the support structure 5 should be greater than the height of the pins of the chip 1 on the substrate 4.

[0046] The support structure 5 may be a separately arranged support structure 5, or a metal column may be arranged on the line, and the metal column and the line together form the support structure 5; a metal column may be arranged on the pad, and the metal column and the pad together form the support structure 5; or a solder resist ink may be arranged in the solder resist ink layer to form the support structure 5.

[0047] The support structure 5 can have only one layer or multiple layers. The number of layers of the support structure 5 can be set according to the actual application. The shape of the support structure 5 can be circular or rectangular. The shape of the support structure 5 can be any shape.

[0048] It is understandable that the pin side of the substrate 4 should be provided with pins 6 of the chip packaging structure for connecting the chip packaging structure with the outside.

[0049] The position of the support structure 5 can be set according to the actual application situation. The support structure 5 can be set only on one side of the chip 1, or on the left and right sides of the chip 1, or on the front and back sides of the chip 1, or on the front, back, left and right sides of the chip 1. The various support structures 5 can be connected together, or each metal support structure 5 can be set independently.

[0050] The chip 1 packaging structure of this embodiment is provided with a support structure 5 on a substrate 4, and the barrier film 2 is supported by the support structure 5 to prevent the barrier film 2 from contacting with the pins of the chip 1 due to pressure, thereby avoiding contamination of the effective resonance area and ensuring the integrity of the cavity, thereby greatly improving the performance of the chip 1.

[0051] In one embodiment, if Figure 1 and Figure 2As shown, based on the above embodiment, the height of the support structure 5 is half of the height of the chip 1 on the substrate 4 .

[0052] In the chip 1 packaging structure of this embodiment, the height of the support structure 5 is set to half the height of the chip 1 on the substrate 4, which can better support the barrier film 2, making the barrier film 2 more stable and improving the reliability of the chip 1 packaging structure.

[0053] In one embodiment, if Figure 1 and Figure 2 As shown, on the basis of the above embodiment, the support structure 5 includes a first solder resist layer 51 and a second solder resist layer 52 , and the second solder resist layer 52 is arranged above the first solder resist layer 51 .

[0054] In this embodiment, the support structure 5 is formed by setting two layers of solder resist layers. The first solder resist layer 51 can be the original solder resist layer on the substrate 4, or a specially set solder resist layer. Preferably, the first solder resist layer 51 is the original solder resist layer of the substrate 4. The width of the first solder resist layer 51 and the width of the second solder resist layer 52 can be set according to actual application conditions. The width of the first solder resist layer 51 and the second solder resist layer 52 can be set to be the same, or the width of the first solder resist layer 51 can be set to be different from that of the second solder resist layer 52. Preferably, the width of the second solder resist layer 52 is greater than the width of the second solder resist layer 52.

[0055] The thickness of the first solder resist layer 51 and the second solder resist layer 52 can be set according to the actual application situation. The thickness of the first solder resist layer 51 and the second solder resist layer 52 can be the same, or the thickness of the first solder resist layer 51 and the thickness of the second solder resist layer 52 can also be different. As another embodiment, the supporting structure 5 can also include a first solder resist layer 51, a second solder resist layer 52 and a third solder resist layer.

[0056] The chip 1 packaging structure of this embodiment is provided with two layers of solder resist to avoid the difficulty of preparing the support structure 5 being too high, and the original solder resist layer on the substrate 4 is used as the first solder resist layer 51, so that the second solder resist layer 52 is easier to prepare. It can also increase the height that the support structure 5 can support.

[0057] In one embodiment, if Figure 1 and Figure 2 As shown, based on the above embodiment, the support structure 5 is a step structure, and the width of the second solder resist layer 52 is smaller than the width of the first solder resist layer 51 .

[0058] In the chip 1 packaging structure of this embodiment, the support structure 5 is configured as a step-type, so that the support structure 5 can be more stable, further ensuring the stability of the chip 1 packaging structure.

[0059] In one embodiment, if Figure 1 and Figure 2 As shown, based on the above embodiment, the support structure 5 is respectively provided on the front side, the back side, the left side and the right side of the chip 1 .

[0060] Preferably, the support structures 5 on the front, rear, left and right sides of the chip 1 are rectangular, and the length of the support structures 5 on each side of the chip 1 can be set according to actual application conditions.

[0061] The chip 1 packaging structure of this embodiment has a separate support structure 5 on each side of the chip 1, which can reduce the stress of the laminated plastic sealing layer 3 and avoid damage to the connected support structures 5 due to stress during lamination, thereby affecting the support of the support structure 5 for the barrier film 2.

[0062] In one embodiment, if Figure 3 As shown, a schematic flow chart of a method for processing a substrate 4 having a metal support structure 5 is provided, and the processing method comprises:

[0063] Step S101: providing a substrate 4 with a prepared circuit pattern.

[0064] The substrate 4 is a board formed by laminating glass fiber cloth and epoxy resin. Blind holes and / or through holes are prepared on the substrate 4. A copper layer is arranged on the substrate 4 with the prepared holes. According to actual conditions, the copper layer is used to form a circuit pattern.

[0065] Step S102: coating ink on the substrate 4 for the first time to obtain the substrate 4 coated with ink for the first time.

[0066] A pattern is set on the screen printing screen according to actual application conditions, and ink is printed onto the substrate 4 through the screen.

[0067] Step S103: performing a first exposure on the substrate 4 by using an exposure device to obtain the substrate 4 after the first exposure.

[0068] The substrate 4 is exposed by an exposure machine. The ink undergoes chemical changes under the action of light. The exposed portion is more easily dissolved by the developer, and the unexposed portion is the first solder resist layer 51 .

[0069] Step S104: coating ink for a second time on the substrate 4 after the first exposure to obtain the substrate 4 coated with ink for the second time.

[0070] A pattern is set on the screen printing screen according to actual application conditions, and ink is printed onto the substrate 4 through the screen.

[0071] Step S105: using the exposure device to perform a second exposure on the substrate 4 to obtain the substrate 4 after the second exposure.

[0072] The substrate 4 is exposed by an exposure machine, and the ink undergoes chemical changes under the action of light, and the exposed portion is more easily dissolved by the developer. The unexposed portion is the second solder resist layer 52.

[0073] Step S106 : developing and cleaning the substrate 4 after the second exposure to obtain a substrate 4 with a support structure 5 .

[0074] The unhardened ink portion is washed away using a developing solution, leaving the support structure 5 formed by the first solder resist layer 51 and the second solder resist layer 52 .

[0075] In this embodiment, a solder resist process is added to the conventional manufacturing process of the substrate 4. Through two solder resist processes, the original ink layer is partially thickened, and the thickened ink layer and the original ink layer thereunder form a support structure 5. The barrier film 2 is supported by the support structure 5 to prevent the barrier film 2 from contacting the pins of the chip 1 due to pressure, thereby avoiding contamination of the effective resonance area and ensuring the integrity of the cavity, thereby greatly improving the performance of the chip 1.

[0076] In one embodiment, if Figure 4 As shown, a schematic flow chart of a method for processing a substrate 4 having a metal support structure 5 is provided. Figure 3 Based on the embodiment, after step S106, the processing method includes:

[0077] Step S201 : performing a curing treatment on the substrate 4 with the support structure 5 to obtain a cured substrate 4 .

[0078] The solder resist layer is completely hardened by heat curing, ultraviolet (UV) curing or infrared (IR) curing to form a support structure 5 .

[0079] In this embodiment, by curing the support structure 5 , the support structure 5 has good heat resistance and corrosion resistance, making the support structure 5 more stable.

[0080] In one embodiment, if Figure 5 As shown, a schematic flow chart of a method for processing a substrate 4 having a metal support structure 5 is provided. Figure 3 Based on the embodiment, after step S102 and before step S103, the processing method further includes:

[0081] Step S301: performing a first pre-curing on the substrate 4 after the first coating of ink, to obtain a substrate 4 after the first pre-curing.

[0082] After the first printing of ink, the substrate 4 is placed in an oven for pre-curing to evaporate the solvent in the ink and preliminarily fix the position of the first printing of ink.

[0083] After step S104 and before step S105, the processing method further includes:

[0084] Step S302: performing a second pre-curing on the substrate 4 after the second coating of ink, to obtain a substrate 4 after the second pre-curing.

[0085] After the second printing of ink, the substrate 4 is placed in an oven for pre-curing to evaporate the solvent in the ink and preliminarily fix the position of the second printing of ink.

[0086] In this embodiment, the substrate 4 after printing the ink is pre-cured. The pre-curing can evaporate the solvent in the ink and preliminarily fix the position of the ink to avoid displacement during subsequent processing.

[0087] In one embodiment, if Figure 6 As shown, a schematic flow chart of a method for processing a substrate 4 having a metal support structure 5 is provided. Figure 4 Based on the embodiment, after step S201, the processing method further includes:

[0088] Step S401: performing surface treatment on the substrate 4 to obtain a surface-treated substrate 4.

[0089] The surface treatment may be performed to clean the substrate 4 and remove impurities. The surface treatment may also be performed to mechanically treat the substrate 4 . The surface treatment may also be performed to chemically treat the substrate 4 .

[0090] Step S402: performing detection processing on the substrate 4 after the surface treatment to obtain the substrate 4 after the detection processing.

[0091] Inspection may include appearance inspection processing, inspection may also include functional testing, inspection may also include performance testing, and inspection may also include mechanical strength testing.

[0092] In this embodiment, after the support structure 5 is prepared, the substrate 4 is subjected to surface treatment and testing to fully verify the comprehensive quality of the substrate 4 and ensure the quality and reliability of the substrate 4 .

[0093] In one embodiment, in the above Figure 3 Based on the embodiment, step S101 includes:

[0094] A substrate 4 is provided, and copper coating, film lamination, exposure, development and etching are performed on the substrate 4 to prepare a circuit pattern.

[0095] A substrate 4 is provided, and a uniform copper foil is first covered on the substrate 4, a photosensitive dry film or liquid photoresist is coated on the surface of the copper foil, and a heat press or UV light is used to cure it, and an exposure machine is used to expose the cured substrate 4.

[0096] The unexposed dry film is removed using a developer, and the copper is etched using an etchant to remove the copper layer not protected by the dry film or photoresist, leaving only the circuit pattern.

[0097] In this embodiment, the substrate 4 is subjected to copper coating, film lamination, exposure, development, and etching to prepare a circuit pattern, which enables the circuit to be highly integrated while reducing signal interference and delay, thereby improving the signal transmission quality of the circuit.

[0098] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: A substrate, a chip, a barrier film and a plastic sealing layer, wherein the conductive pins of the chip are electrically interconnected with the substrate, the barrier film is arranged on the substrate, the barrier film and the substrate form a cavity, the chip is arranged in the cavity, the barrier film and the substrate form a plastic sealing layer, a support structure is arranged on the substrate in the cavity, and the support structure is used to support the barrier film when the plastic sealing layer is pressed.

2. The chip packaging structure according to claim 1, characterized in that: The height of the support structure is half of the height of the chip on the substrate.

3. The chip packaging structure according to claim 1 or 2, characterized in that: The support structure includes a first solder resist layer and a second solder resist layer, wherein the second solder resist layer is disposed above the first solder resist layer.

4. The chip packaging structure according to claim 3, characterized in that: The supporting structure is a step structure, and the width of the second solder resist layer is smaller than the width of the first solder resist layer.

5. The chip packaging structure according to claim 4, characterized in that: The supporting structures are respectively arranged on the front side, the back side, the left side and the right side of the chip.

6. A method for processing a substrate having a support structure, characterized in that: The processing method comprises: Providing a substrate with a prepared circuit pattern; Applying ink on the substrate for the first time to obtain a substrate coated with ink for the first time; Performing a first exposure on the substrate using an exposure device to obtain a substrate after the first exposure; coating ink for a second time on the substrate after the first exposure to obtain a substrate coated with ink for the second time; performing a second exposure on the substrate using the exposure device to obtain a substrate after the second exposure; The substrate after the second exposure is developed and cleaned to obtain a substrate with a support structure.

7. The method for processing a substrate having a support structure according to claim 6, wherein: After obtaining the substrate with the support structure, the processing method further comprises: The substrate with the support structure is cured to obtain a cured substrate.

8. The method for processing a substrate having a support structure according to claim 6, wherein: After obtaining the substrate coated with ink for the first time and before using an exposure device to expose the substrate for the first time, the processing method further includes: Performing a first pre-curing on the substrate after the first coating of ink to obtain a first pre-cured substrate; After obtaining the substrate coated with ink for the second time and before exposing the substrate for the second time using an exposure device, the processing method further includes: The substrate after the second coating of ink is subjected to a second pre-curing to obtain a substrate after the second pre-curing.

9. The method for processing a substrate having a support structure according to claim 7, wherein: After obtaining the cured substrate, the processing method further comprises: Performing surface treatment on the substrate to obtain a surface-treated substrate; The substrate after the surface treatment is subjected to detection treatment to obtain the substrate after the detection treatment.

10. The method for processing a substrate having a support structure according to claim 6, wherein: Providing a substrate with a prepared circuit pattern includes: A substrate is provided, and the substrate is subjected to copper coating, film lamination, exposure, development and etching to prepare a circuit pattern.

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