Chip packaging structure and chip packaging method

Abstract

The invention relates to a chip packaging structure and a chip packaging method. The chip packaging structure comprises an epitaxial layer; the top conductive layer is located on one side of the epitaxial layer and comprises a plurality of metal wires which are arranged at intervals in the first direction; the first packaging layer is located on the side, away from the epitaxial layer, of the top conductive layer; the second packaging layer is located on the side, away from the top conductive layer, of the first packaging layer; the second packaging layer is provided with a plurality of first protrusions at positions corresponding to the metal wires. The third packaging layer is located on the side, away from the first packaging layer, of the second packaging layer; the third packaging layer is provided with a plurality of second protrusions at positions corresponding to the first protrusions. Wherein the second packaging layer and the third packaging layer are formed by adopting the same target process; the longitudinal section contour of each first protrusion in the first direction and the longitudinal section contour of each second protrusion in the first direction are triangular. According to the invention, the problem of cracks at the weak process part in the packaging layer can be avoided, so that the process yield can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip packaging structure and a chip packaging method. Background Art

[0002] The Bipolar-CMOS-DMOS (BCD) process refers to a semiconductor process that integrates bipolar devices, complementary metal oxide semiconductors (CMOS) and double-diffused metal oxide semiconductors (DMOS) into the same chip. The BCD process is widely used in the field of power chip manufacturing. In order to meet the high current load capacity requirements of power chips, the relevant technology usually uses a thicker top metal (for example, a thickness greater than 3μm) in the manufacture of BCD chips, which will cause greater stress in the BCD chip.

[0003] However, the passivation layer of the BCD chip in the related art has the problem of being too thick. In addition, the top metal layer in the BCD chip is also thick, which often leads to cracks in the passivation layer, reduces the process yield, and thus has an adverse effect on the performance of the BCD chip. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a chip packaging structure and a chip packaging method to effectively avoid crack problems at weak points in the packaging layer, thereby facilitating improving the process yield.

[0005] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a chip packaging structure. The chip packaging structure includes an epitaxial layer, a top conductive layer, a first packaging layer, a second packaging layer and a third packaging layer; the top conductive layer is located on one side of the epitaxial layer; the top conductive layer includes a plurality of metal wires arranged at intervals along a first direction; the first packaging layer is located on the side of the top conductive layer away from the epitaxial layer; the second packaging layer is located on the side of the first packaging layer away from the top conductive layer; the second packaging layer has a plurality of first protrusions at corresponding positions of each metal wire; the third packaging layer is located on the side of the second packaging layer away from the first packaging layer; the third packaging layer has a plurality of second protrusions at corresponding positions of each first protrusion; wherein the second packaging layer and the third packaging layer are formed by the same target process; the longitudinal cross-sectional profile of each first protrusion in the first direction and the longitudinal cross-sectional profile of each second protrusion in the first direction are both triangular.

[0006] In some embodiments, the first protrusions are arranged at intervals in the first direction; and the second protrusions are arranged at intervals in the first direction.

[0007] In some embodiments, the ratio of the thickness of the top conductive layer to the sum of the thickness of the second packaging layer and the third packaging layer ranges from 10:9 to 10:11.

[0008] In some embodiments, the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer each include an oxide layer.

[0009] In some embodiments, the chip packaging structure further includes a fourth packaging layer; the fourth packaging layer is located on a side of the third packaging layer away from the second packaging layer; and the fourth packaging layer has a plurality of third protrusions at positions corresponding to the second protrusions.

[0010] In some embodiments, the third protrusions are arranged at intervals in the first direction.

[0011] In some embodiments, the thickness of the first packaging layer is less than 800A; the thickness of the fourth packaging layer is less than 5000A.

[0012] On the other hand, the present disclosure also provides a chip packaging method according to some embodiments; the chip packaging method includes: providing a chip to be packaged; the chip to be packaged includes an epitaxial layer and a top conductive layer located on one side of the epitaxial layer; the top conductive layer includes a plurality of metal wires arranged at intervals along a first direction; a first packaging layer is formed on a side of the top conductive layer away from the epitaxial layer; a second packaging layer is formed on a side of the first packaging layer away from the top conductive layer; the second packaging layer has a plurality of first protrusions at corresponding positions of each metal wire; a third packaging layer is formed on a side of the second packaging layer away from the first packaging layer; the third packaging layer has a plurality of second protrusions at corresponding positions of each first protrusion; wherein the second packaging layer and the third packaging layer are formed using the same target process; the longitudinal cross-sectional profile of each first protrusion in the first direction and the longitudinal cross-sectional profile of each second protrusion in the first direction are both triangular.

[0013] In some embodiments, the first packaging layer is formed using a first target process; the second packaging layer and the third packaging layer are both formed using a second target process; wherein the first target process includes a silicon-rich oxide layer deposition process; and the second target process includes a high-density plasma-assisted chemical vapor deposition process.

[0014] In some embodiments, after forming a third packaging layer on a side of the second packaging layer away from the first packaging layer, the chip packaging method further includes: forming a fourth packaging layer on a side of the third packaging layer away from the second packaging layer; the fourth packaging layer has a plurality of third protrusions at positions corresponding to the second protrusions; wherein the third protrusions are arranged at intervals in the first direction.

[0015] The embodiments of the present application may or at least have the following advantages:

[0016] In the embodiment of the present application, the second encapsulation layer and the third encapsulation layer are formed by adopting the same target process, so that the longitudinal cross-sectional profile of each first protrusion in the second encapsulation layer in the first direction and the longitudinal cross-sectional profile of each second protrusion in the third encapsulation layer in the first direction are both triangular, that is, the thin film interface between the first encapsulation layer and the second encapsulation layer is sharper, and the longitudinal cross-sectional area of ​​each first protrusion and each second protrusion is also reduced. In this way, the encapsulation layer (such as the passivation layer) covering the top conductive layer is formed by adopting the target process, so that the formed encapsulation layer (such as the passivation layer) has a relatively sharp and obvious top morphological feature, so as to leave space for the layer structure formed above in the subsequent process, avoid the squeezing problem caused by the close contact between adjacent protrusions that are easy to appear at the minimum feature size, thereby effectively avoiding the crack problem at the process weak point in the encapsulation layer (such as the passivation layer), which is conducive to improving the process yield and improving the performance of the semiconductor chip.

[0017] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic structural diagram of a chip packaging structure provided in some embodiments;

[0020] Figure 2 A schematic structural diagram of another chip packaging structure provided in some embodiments;

[0021] Figure 3 Figures (a) and (b) are electron microscope scans of conventional chip packaging structures. Figure 3 Figures (c) and (d) are electron microscope scanning images of chip packaging structures provided in some embodiments;

[0022] Figure 4 An electron microscope scanning image of a chip packaging structure provided in some embodiments after multiple alloy furnace tube processes;

[0023] Figure 5 A schematic flow chart of a chip packaging method provided in some embodiments;

[0024] Figure 6 A schematic flow chart of another chip packaging method provided in some embodiments;

[0025] Figure 7 is a flow chart of step S100 provided in some embodiments;

[0026] Figure 8 A schematic diagram of the structure of a chip to be packaged provided in some embodiments;

[0027] Fig. 9 A schematic structural diagram of a structure obtained after forming a first encapsulation layer provided in some embodiments;

[0028] Fig.10 It is a schematic structural diagram of a structure obtained after forming a second packaging layer provided in some embodiments.

[0029] Description of reference numerals:

[0030] 1. Epitaxial layer, 11. Metal routing layer, 12. Dielectric layer, 2. Top conductive layer, 21. Metal wire, 3. First packaging layer, 4. Second packaging layer, 41. First protrusion, 5. Third packaging layer, 51. Second protrusion, 6. Fourth packaging layer, 61. Third protrusion, C. Crack. DETAILED DESCRIPTION

[0031] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0034] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] Embodiments of the invention are described herein with reference to longitudinal cross-sectional views as schematic diagrams of ideal embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0036] The embodiments of the present application provide a chip packaging structure and a chip packaging method to effectively avoid crack problems at process weak points in the packaging layer, thereby facilitating improving process yield.

[0037] In some embodiments, see Figure 1The chip packaging structure includes an epitaxial layer 1, a top conductive layer 7, a first packaging layer 3, a second packaging layer 4 and a third packaging layer 5; the top conductive layer 7 is located on one side of the epitaxial layer 1; the top conductive layer 7 includes a plurality of metal wires 21 arranged at intervals along a first direction (e.g., X direction); the first packaging layer 3 is located on the side of the top conductive layer 7 away from the epitaxial layer 1; the second packaging layer 4 is located on the side of the first packaging layer 3 away from the top conductive layer 7; the second packaging layer 4 has a plurality of first protrusions 41 at corresponding positions of each metal wire 21; the third packaging layer 5 is located on the side of the second packaging layer 4 away from the first packaging layer 3; the third packaging layer 5 has a plurality of second protrusions 51 at corresponding positions of each first protrusion 41; wherein the second packaging layer 4 and the third packaging layer 5 are formed by the same target process; the longitudinal cross-sectional profile of each first protrusion 41 in the first direction (e.g., X direction) and the longitudinal cross-sectional profile of each second protrusion 51 in the first direction (e.g., X direction) are both triangular.

[0038] In the embodiment of the present application, the second encapsulation layer 4 and the third encapsulation layer 5 are formed by adopting the same target process, so that the longitudinal cross-sectional profile of each first protrusion 41 in the second encapsulation layer 4 in the first direction and the longitudinal cross-sectional profile of each second protrusion 51 in the third encapsulation layer 5 in the first direction are both triangular, that is, the thin film interface between the first encapsulation layer 3 and the second encapsulation layer 4 is sharper, and the longitudinal cross-sectional area of ​​each first protrusion 41 and each second protrusion 51 is also reduced. In this way, the encapsulation layer (such as the passivation layer) covering the top conductive layer 7 is formed by adopting the target process, so that the formed encapsulation layer (such as the passivation layer) has a relatively sharp and obvious top morphological feature, so as to leave space for the layer structure formed above in the subsequent process, avoid the squeezing problem caused by the close contact between adjacent protrusions that are easy to appear at the minimum feature size, thereby effectively avoiding the crack problem at the process weak point in the encapsulation layer (such as the passivation layer), which is conducive to improving the process yield and improving the performance of the semiconductor chip.

[0039] By way of example, the epitaxial layer 1 may be a redistribution layer (RDL for short).

[0040] In some examples, the epitaxial layer 1 includes a metal wiring layer 11 and a dielectric layer 12 . The dielectric layer 12 has a plurality of through holes, and the metal wiring layer 11 is embedded in each through hole of the dielectric layer 12 .

[0041] In some examples, the metal wiring layer 11 and the metal wire 21 are electrically connected.

[0042] For example, the material of the metal wiring layer 11 includes but is not limited to a conductive material; the conductive material may be, for example, a conductive metal (such as aluminum Al) or the like.

[0043] By way of example, the material of the dielectric layer 12 includes, but is not limited to, an insulating material; the insulating material may be, for example, an oxide or the like.

[0044] By way of example, the top conductive layer 7 may be a pad layer (Pad), for example.

[0045] In some embodiments, the thickness of the top conductive layer 7 is greater than 3000 nm.

[0046] For example, the thickness of the top conductive layer 7 may be 3000 nm, 3500 nm, 4000 nm, 4500 nm or 5000 nm.

[0047] It should be noted that the first packaging layer 3 conformally covers the epitaxial layer 1 and each metal wire 21 .

[0048] By way of example, the material of the metal wire 21 includes, but is not limited to, a conductive material; the conductive material may be, for example, a conductive metal (eg, aluminum Al) or the like.

[0049] For example, the size of the metal wire 21 in the first direction (eg, X direction) ranges from 1500nm to 3000nm; the size of the metal wire 21 in the first direction (eg, X direction) may be, for example, 1500nm, 2000nm, 2083nm, 2500nm, 2987nm or 3000nm.

[0050] For example, the size of the metal wire 21 in the second direction (eg, Y direction) ranges from 3000nm to 4500nm; the size of the metal wire 21 in the second direction (eg, Y direction) may be, for example, 3000nm, 3500nm, 4000nm, 4189nm or 4500nm.

[0051] In some examples, first encapsulation layer 3 , second encapsulation layer 4 , and third encapsulation layer 5 all include an oxide layer.

[0052] For example, the first encapsulation layer 3 may be a silicon rich oxide (Silicon Rich Oxide, SRO for short) layer; the first encapsulation layer 3 may be formed by using a silicon rich oxide (Silicon Rich Oxide, SRO for short) deposition process.

[0053] In some embodiments, the second encapsulation layer 4 and the third encapsulation layer 5 are both formed by a high density plasma assisted chemical vapor deposition (HDP CVD) process.

[0054] For example, the range of the ion density of the plasma used in the formation process (eg, HDP CVD process) of the second encapsulation layer 4 and the third encapsulation layer 5 includes 10 11 / cm 3 ~10 12 / cm 3 The ion density of the plasma used in the formation process of the second encapsulation layer 4 and the third encapsulation layer 5 (eg, HDP CVD process) may be, for example, 1×10 11 / cm 3 , 2×10 11 / cm 3 , 4×10 11 / cm 3 , 5×10 11 / cm 3 , 6×10 11 / cm 3 , 8×10 11 / cm 3 or 1×10 12 / cm 3 wait.

[0055] For example, the deposition temperature of the formation process of the second encapsulation layer 4 and the third encapsulation layer 5 (for example, the HDP CVD process) ranges from 550°C to 700°C; the deposition temperature of the formation process of the second encapsulation layer 4 and the third encapsulation layer 5 (for example, the HDP CVD process) can be, for example, 550°C, 600°C, 650°C or 700°C.

[0056] It should be noted that the high-density plasma assisted chemical vapor deposition (HDP CVD) process used in the embodiments of the present application can obtain higher plasma density and better film quality under the premise of using lower temperature, and defects such as cracks and voids are not easily generated in the formed layer structure.

[0057] In some examples, each first protrusion 41 protrudes from the second packaging layer 4 along the second direction (e.g., the Y direction) and covers the first packaging layer 3 on each metal wire 21; each second protrusion 51 protrudes from the third packaging layer 5 along the second direction (e.g., the Y direction) and covers each first protrusion 41.

[0058] In some embodiments, please refer to Figure 1 , the first protrusions 41 are arranged at intervals in the first direction (eg, the X direction); and the second protrusions 51 are arranged at intervals in the first direction (eg, the X direction).

[0059] In some examples, the first protrusions 41 are arranged at equal intervals in the first direction (eg, the X direction); and the second protrusions 51 are arranged at equal intervals in the first direction (eg, the X direction).

[0060] It should be noted that the second packaging layer 4 and the third packaging layer 5 formed by the HDP CVD process have high compactness, and can form first protrusions 41 and second protrusions 51 with triangular longitudinal cross-sectional profiles in the first direction (for example, the X direction), so that the second packaging layer 4 and the third packaging layer 5 can more tightly cover the metal wires 21 of the top conductive layer 7, so that there is a certain interval between each first protrusion 41 and each second protrusion 51, thereby leaving space for the layer structure formed above in the subsequent process, avoiding the problem of adjacent protrusions being close to each other that may occur at the minimum feature size.

[0061] In some embodiments, the ratio of the thickness of the top conductive layer 7 to the sum of the thickness of the second encapsulation layer 4 and the third encapsulation layer 5 ranges from 10:9 to 10:11.

[0062] For example, the ratio between the thickness of the top conductive layer 7 and the sum of the thicknesses of the second encapsulation layer 4 and the third encapsulation layer 5 may be 10:9, 1:1 or 10:11.

[0063] In some embodiments, the thickness of the first encapsulation layer 3 is less than 800 Å.

[0064] For example, the thickness of the first encapsulation layer 3 may be 300A, 400A, 500A, 600A, 700A or 800A, etc.

[0065] In some embodiments, see Figure 2 The chip packaging structure further includes a fourth packaging layer 6 ; the fourth packaging layer 6 is located on a side of the third packaging layer 5 away from the second packaging layer 4 ; and the fourth packaging layer 6 has a plurality of third protrusions 61 at positions corresponding to the second protrusions 51 .

[0066] In some embodiments, the fourth encapsulation layer 6 includes a nitride layer

[0067] By way of example, the material of the fourth encapsulation layer 6 may be silicon nitride (SiN), for example.

[0068] In some embodiments, the formation process of the fourth encapsulation layer 6 includes but is not limited to a deposition process.

[0069] In some embodiments, the thickness of the fourth encapsulation layer 6 is less than 5000 Å.

[0070] For example, the thickness of the fourth encapsulation layer 6 may be 1000 Å, 2000 Å, 3000 Å, 4000 Å or 5000 Å, etc.

[0071] It should be noted that each third protrusion 61 protrudes from the fourth encapsulation layer 6 along the second direction (eg, the Y direction) and covers each second protrusion 51 .

[0072] In some embodiments, please refer to Figure 2 The third protrusions 61 are arranged at intervals in the first direction (eg, the X direction).

[0073] For example, the third protrusions 61 are arranged at equal intervals in the first direction (eg, the X direction).

[0074] In the embodiment of the present application, since the second packaging layer 4 and the third packaging layer 5 formed by the target process (such as the HDP CVD process) have high compactness, and the morphological features of the formed first protrusions 41 and the second protrusions 51 are similar, and there is a gap between each first protrusion 41 and each second protrusion 51, this leaves sufficient formation space for the fourth packaging layer 6, so that there is also a gap between each third protrusion 61 in the fourth packaging layer 6 (that is, there will be no extrusion problem caused by adjacent protrusions being close to each other between each third protrusion 61), thereby effectively avoiding the problem of cracks in the weak points of the process in the packaging layer, which is beneficial to improving the process yield.

[0075] In summary, in order to verify the improvement effect of the chip packaging structure provided by the embodiments of the present application on the crack problem in the packaging layer. In some embodiments of the present application, the formation process of the second packaging layer 4 using the high density plasma assisted chemical vapor deposition (HDP CVD) process is taken as an example; and the chip packaging structure using the tetraethyl ortho silicate (TEOS) process and the HDP CVD process to form the third packaging layer 5 is respectively scanned by an electrical microscope to obtain the electron microscope scanning images of the above two chip packaging structures. Figure 3 shown; Figure 3 Figure (a) is a longitudinal cross-sectional schematic diagram of a conventional chip packaging structure in which the third packaging layer 5 is formed using a TEOS process. Figure 3 Figure (b) is a top view of a conventional chip packaging structure. Figure 3 FIG. (c) is a schematic longitudinal cross-sectional view of the chip packaging structure provided by the present application in which the third packaging layer 5 is formed by the HDP CVD process. Figure 3 Figure (d) is a top view schematic diagram of the chip packaging structure provided in this application.

[0076] according to Figure 3As can be seen from Figure (a) in the conventional chip packaging structure, the top morphology of the second protrusion 51 of the third packaging layer 5 formed by the TEOS process is relatively smooth, so that the top morphology of the fourth packaging layer 6 formed on the third packaging layer 5 is also relatively smooth. Figure 3 As can be understood from Figures (a) and (b) in FIG. 1 , since the tops of the third encapsulation layer 5 and the fourth encapsulation layer 6 are relatively smooth, there will be a gap between adjacent protrusions (e.g. Figure 3 The two parts (area A in the figure) are pressed against each other and squeezed, resulting in cracks C in the weak points of the packaging layer, reducing the process yield and causing adverse effects on the performance of the chip.

[0077] It should be noted that due to the bombardment of argon (Ar) ions in the HDP CVD process, the isotropic growth characteristics of the vapor deposition will be weakened, so that the interface of the formed third encapsulation layer 5 is relatively sharp. Figure 3 As can be seen from (c) in the chip packaging structure provided in the present application, the top of each second protrusion 51 of the third packaging layer 5 formed by the HDP CVD process is relatively sharp, its longitudinal section is triangular, and there is a gap between each second protrusion 51, so that the top morphology of the fourth packaging layer 6 formed on the third packaging layer 5 is also relatively sharp. Figure 3 As can be understood from Figures (c) and (d) in FIG. 1 , since the top morphology of each third protrusion 61 is relatively sharp and there is a gap between each adjacent third protrusion 61 (e.g. Figure 3 In the B area in the figure), there are also intervals between the fourth protrusions, and there is no squeezing problem between adjacent protrusions, which effectively improves the crack problem in the packaging layer.

[0078] In addition, in order to further verify the improvement effect of the chip packaging structure provided in the embodiment of the present application on the problem of cracks in the packaging layer when multiple furnace tube processes are performed, electron microscope scanning images of the chip packaging structure provided in the embodiment of the present application after three and seven alloy furnace tube processes are obtained, as shown in FIG. Figure 4 shown.

[0079] according to Figure 4 As can be seen from Figure (a) in the figure, the chip packaging structure provided in the embodiment of the present application has no crack problem after undergoing three alloy furnace tube processes; Figure 4 As can be seen from Figure (b), the chip packaging structure provided in the embodiment of the present application only has slight cracks under the extreme condition of seven alloy furnace tube processes.

[0080] From the above, the chip packaging structure provided by the embodiment of the present application avoids the extrusion problem caused by the close contact between adjacent protrusions that are prone to occur at the minimum feature size, thereby effectively improving the crack problem at the weak point of the process in the packaging layer (such as the passivation layer), thereby improving the process yield and the performance of the semiconductor chip.

[0081] On the other hand, the present application also provides a chip packaging method according to some embodiments, and the chip packaging method can be used to prepare the chip packaging structure in some of the above embodiments. The chip packaging method also has the technical advantages of the above chip packaging structure. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be described in detail below.

[0082] In some embodiments, see Figure 5 The chip packaging method includes the following steps S100~S400.

[0083] S100, providing a chip to be packaged; the chip to be packaged includes an epitaxial layer and a top conductive layer located on one side of the epitaxial layer; the top conductive layer includes a plurality of metal wires arranged at intervals along a first direction.

[0084] S200 , forming a first packaging layer on a side of the top conductive layer away from the epitaxial layer.

[0085] S300, forming a second packaging layer on a side of the first packaging layer away from the top conductive layer; the second packaging layer has a plurality of first protrusions at positions corresponding to each metal wire.

[0086] S400, forming a third encapsulation layer on a side of the second encapsulation layer away from the first encapsulation layer; the third encapsulation layer has a plurality of second protrusions at positions corresponding to the first protrusions; wherein the second encapsulation layer and the third encapsulation layer are formed using the same target process; the longitudinal cross-sectional profile of each first protrusion in the first direction and the longitudinal cross-sectional profile of each second protrusion in the first direction are both triangular.

[0087] In some embodiments, see Figure 6 , after step S400, the chip packaging method further includes the following step S500.

[0088] S500, forming a fourth encapsulation layer on a side of the third encapsulation layer away from the second encapsulation layer; the fourth encapsulation layer has a plurality of third protrusions at positions corresponding to the second protrusions; wherein the third protrusions are arranged at intervals in the first direction.

[0089] In some embodiments, see Figure 7 , step S100 includes the following steps S110~S120.

[0090] S110, forming an epitaxial layer.

[0091] S120, forming a plurality of metal wires on one side of the epitaxial layer to obtain a top conductive layer.

[0092] It should be understood that although Figure 5~Figure 7 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 5~Figure 7 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0093] In order to more clearly illustrate the chip packaging method in some of the above embodiments, the following embodiments are combined with Figure 8~Figure 10 and Figure 1~Figure 2 Understand.

[0094] In some embodiments, the chip packaging method includes steps S100 to S400.

[0095] In step S100, refer to Figure 8 , providing a chip to be packaged; the chip to be packaged includes an epitaxial layer 1 and a top conductive layer 7 located on one side of the epitaxial layer 1; the top conductive layer 7 includes a plurality of metal wires 21 arranged at intervals along a first direction.

[0096] In some examples, step S100 includes steps S110 to S120.

[0097] In step S110 , an epitaxial layer 1 is formed.

[0098] By way of example, the epitaxial layer 1 may be a redistribution layer (RDL for short).

[0099] In some examples, the epitaxial layer 1 includes a metal wiring layer 11 and a dielectric layer 12 . The dielectric layer 12 has a plurality of through holes, and the metal wiring layer 11 is embedded in each through hole of the dielectric layer 12 .

[0100] In step S120 , a plurality of metal wires 21 are formed on one side of the epitaxial layer 1 to obtain a top conductive layer 7 .

[0101] For example, the metal wire 21 is electrically connected to the metal wiring layer 11 of the epitaxial layer 1 .

[0102] In step S200, refer to Fig. 9 , a first packaging layer 3 is formed on the side of the top conductive layer 7 facing away from the epitaxial layer 1 .

[0103] In some examples, first encapsulation layer 3 includes an oxide layer.

[0104] In some embodiments, the first encapsulation layer 3 is formed by a first target process.

[0105] Among them, the first target process includes a silicon rich oxide (Silicon Rich Oxide, referred to as SRO) layer deposition process.

[0106] For example, the material of the first encapsulation layer 3 may be silicon rich oxide (Silicon Rich Oxide, SRO for short).

[0107] In step S300, refer to Fig.10 A second packaging layer 4 is formed on the side of the first packaging layer 3 away from the top conductive layer 7 ; the second packaging layer 4 has a plurality of first protrusions 41 at positions corresponding to the metal wires 21 .

[0108] Illustratively, the second encapsulation layer 4 includes an oxide layer.

[0109] In some embodiments, the first protrusions 41 are arranged at intervals in the first direction (eg, the X direction).

[0110] In some examples, each first protrusion 41 protrudes from the second packaging layer 4 along the second direction (eg, the Y direction) and covers the first packaging layer 3 on each metal wire 21 .

[0111] In step S400, refer to Figure 1 , a third encapsulation layer 5 is formed on the side of the second encapsulation layer 4 away from the first encapsulation layer 3; the third encapsulation layer 5 has a plurality of second protrusions 51 at positions corresponding to the first protrusions 41; wherein the second encapsulation layer 4 and the third encapsulation layer 5 are formed using the same target process; the longitudinal cross-sectional profile of each first protrusion 41 in the first direction and the longitudinal cross-sectional profile of each second protrusion 51 in the first direction are both triangular.

[0112] In some embodiments, the second protrusions 51 are arranged at intervals in the first direction (eg, the X direction).

[0113] In some examples, each second protrusion 51 protrudes from the third encapsulation layer 5 along the second direction (eg, the Y direction) and covers each first protrusion 41 .

[0114] Illustratively, the third encapsulation layer 5 includes an oxide layer.

[0115] In some embodiments, the second encapsulation layer 4 and the third encapsulation layer 5 are both formed by the second target process.

[0116] In some examples, the second target process includes a High Density Plasma Chemical Vapor Deposition (HDP CVD) process.

[0117] It should be noted that the second packaging layer 4 and the third packaging layer 5 formed by the HDP CVD process have high compactness, and can form first protrusions 41 and second protrusions 51 with triangular longitudinal cross-sectional profiles in the first direction (for example, the X direction), so that the second packaging layer 4 and the third packaging layer 5 can more tightly cover the metal wires 21 of the top conductive layer 7, so that there is a certain interval between each first protrusion 41 and each second protrusion 51, thereby leaving space for the layer structure formed above in the subsequent process, avoiding the problem of adjacent protrusions being close to each other that may occur at the minimum feature size.

[0118] In some embodiments, after step S400 , the chip packaging method further includes step S500 .

[0119] In step S500, refer to Figure 2 A fourth encapsulation layer 6 is formed on a side of the third encapsulation layer 5 away from the second encapsulation layer 4 ; the fourth encapsulation layer 6 has a plurality of third protrusions 61 at positions corresponding to the second protrusions 51 ; wherein the third protrusions 61 are arranged at intervals in the first direction.

[0120] By way of example, the fourth encapsulation layer 6 includes a nitride layer; the material of the fourth encapsulation layer 6 may be, for example, silicon nitride (SiN).

[0121] In some embodiments, the formation process of the fourth encapsulation layer 6 includes but is not limited to a deposition process.

[0122] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0123] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A chip packaging structure, It is characterized in that include: Epitaxial layer; A top conductive layer, located on one side of the epitaxial layer; the top conductive layer comprises a plurality of metal wires arranged at intervals along a first direction; A first packaging layer, located on a side of the top conductive layer away from the epitaxial layer; a second packaging layer, located on a side of the first packaging layer away from the top conductive layer; The second packaging layer has a plurality of first protrusions at positions corresponding to the metal wires; a third encapsulation layer, located on a side of the second encapsulation layer facing away from the first encapsulation layer; The third encapsulation layer has a plurality of second protrusions at positions corresponding to the first protrusions; The second encapsulation layer and the third encapsulation layer are formed by the same target process; the longitudinal cross-sectional profile of each of the first protrusions in the first direction and the longitudinal cross-sectional profile of each of the second protrusions in the first direction are both triangles.

2. The chip packaging structure according to claim 1, It is characterized in that The first protrusions are arranged at intervals in the first direction; and the second protrusions are arranged at intervals in the first direction.

3. The chip packaging structure according to claim 1, It is characterized in that The ratio of the thickness of the top conductive layer to the sum of the thickness of the second packaging layer and the third packaging layer is in the range of 10:9 to 10:

11.

4. The chip packaging structure according to claim 1, It is characterized in that The first encapsulation layer, the second encapsulation layer, and the third encapsulation layer each include an oxide layer.

5. The chip packaging structure according to claim 1, It is characterized in that Also includes: a fourth encapsulation layer, located on a side of the third encapsulation layer away from the second encapsulation layer; The fourth encapsulation layer has a plurality of third protrusions at positions corresponding to the second protrusions.

6. The chip packaging structure according to claim 5, It is characterized in that The third protrusions are arranged at intervals in the first direction.

7. The chip packaging structure according to claim 5, It is characterized in that The thickness of the first packaging layer is less than 800A; the thickness of the fourth packaging layer is less than 5000A.

8. A chip packaging method, It is characterized in that include: Providing a chip to be packaged; the chip to be packaged comprises an epitaxial layer and a top conductive layer located on one side of the epitaxial layer; The top conductive layer includes a plurality of metal wires arranged at intervals along a first direction; forming a first packaging layer on a side of the top conductive layer away from the epitaxial layer; A second packaging layer is formed on a side of the first packaging layer away from the top conductive layer; the second packaging layer has a plurality of first protrusions at positions corresponding to the metal wires; A third encapsulation layer is formed on a side of the second encapsulation layer away from the first encapsulation layer; the third encapsulation layer has a plurality of second protrusions at positions corresponding to the first protrusions; The second encapsulation layer and the third encapsulation layer are both formed by the same target process; the longitudinal cross-sectional profile of each of the first protrusions in the first direction and the longitudinal cross-sectional profile of each of the second protrusions in the first direction are both triangles.

9. The chip packaging method according to claim 8, It is characterized in that The first encapsulation layer is formed by a first target process; the second encapsulation layer and the third encapsulation layer are both formed by a second target process; wherein the first target process includes a silicon-rich oxide layer deposition process; and the second target process includes a high-density plasma-assisted chemical vapor deposition process.

10. The chip packaging method according to claim 8, It is characterized in that After forming the third packaging layer on the side of the second packaging layer away from the first packaging layer, the chip packaging method further includes: A fourth encapsulation layer is formed on a side of the third encapsulation layer away from the second encapsulation layer; the fourth encapsulation layer has a plurality of third protrusions at positions corresponding to the second protrusions; Wherein, the third protrusions are arranged at intervals in the first direction.

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