Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device. The array substrate is provided with an array area and a peripheral area arranged around the array area. The array substrate comprises a substrate, a driving circuit layer and a shading layer. The driving circuit layer is arranged on one side of the substrate and comprises a plurality of signal wires arranged in the array area. The shading layer is arranged between the substrate and the driving circuit layer and comprises at least two conductive layers arranged in a stacked mode and a plurality of connecting lines located in the peripheral area, and the connecting lines are connected with the signal wires respectively.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Currently, there is an urgent need to improve the performance of display panels in the application end of display products such as laptops, tablets and cars, and the application end of display products poses higher challenges to narrow bezels.

[0003] Therefore, how to achieve a narrow border on the product application side is a technical problem that needs to be solved. Summary of the invention

[0004] The present application provides an array substrate, a display panel and a display device, so as to reduce the size of a peripheral area of ​​the array substrate and further reduce the size of a frame of the display panel.

[0005] In a first aspect, the present application provides an array substrate, the array substrate having an array area and a peripheral area arranged around the array area, the array substrate comprising:

[0006] substrate;

[0007] A driving circuit layer, disposed on one side of the substrate and comprising a plurality of signal traces disposed in the array area; and

[0008] The light shielding layer is arranged between the substrate and the driving circuit layer, and includes at least two stacked conductive layers and a plurality of connecting wires located in the peripheral area, wherein the plurality of connecting wires are respectively connected to the plurality of signal wirings.

[0009] In a second aspect, the present application further provides a display panel, which includes the array substrate of any of the above embodiments.

[0010] In a third aspect, the present application further provides a display device, comprising a display panel according to any of the above embodiments.

[0011] In the array substrate, display panel and display device of some embodiments of the present application, the shading layer includes at least two stacked conductive layers, and includes a plurality of connecting lines located in the peripheral area. The plurality of connecting lines are respectively connected to a plurality of signal routing lines located in the array area. In this way, the plurality of connecting lines include at least two stacked conductive layers, the impedance of the plurality of connecting lines is small, and the speed at which the connecting lines transmit signals to the signal routing lines is fast, thereby improving the performance of the display panel. In addition, the signal routing lines can be wired using the connecting lines of the shading layer in the peripheral area, which facilitates the multi-layer wiring of the signal routing lines in the peripheral area, thereby reducing the space occupied by the signal routing lines in the peripheral area, and the display panel can achieve a narrow frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 Schematic diagram of a plan view of an array substrate of some embodiments of the present application;

[0013] Figure 2 Schematic diagrams of plan views of array substrates according to other embodiments of the present application;

[0014] Figure 3 Schematic diagrams of plan views of array substrates according to some other embodiments of the present application;

[0015] Figure 4 For along Figure 1 A schematic diagram of a cross-sectional structure taken along the A-A' tangent line;

[0016] Figure 5 For along Figure 1 A schematic diagram of a cross-sectional structure taken along the B-B' tangent line;

[0017] Figure 6 For along Figure 1 Another schematic diagram of the cross-section structure taken along the A-A' tangent line;

[0018] Figure 7 For along Figure 1 Another schematic diagram of the cross-section structure taken along the B-B' tangent line;

[0019] Figure 8 A partial plan view of an array substrate according to some embodiments of the present application;

[0020] Fig. 9 A partial plan view of an array substrate according to some other embodiments of the present application;

[0021] Fig.10 Partial plan views of array substrates according to some other embodiments of the present application;

[0022] Fig.11 Partial plan views of array substrates according to some other embodiments of the present application;

[0023] Fig.12 Partial plan views of array substrates according to some other embodiments of the present application;

[0024] Fig.13 Partial plan views of array substrates according to some other embodiments of the present application;

[0025] Fig.14 Partial plan views of array substrates according to some other embodiments of the present application;

[0026] Fig.15 Partial plan views of array substrates according to some other embodiments of the present application;

[0027] Fig.16 Schematic diagram of a display panel according to some embodiments of the present application;

[0028] Fig.17 Schematic diagram of a display device according to some embodiments of the present application.

[0029] The reference numerals are as follows:

[0030] 300, display panel; 400, backlight module; 500, display device;

[0031] 100, array substrate; 100a, array area; 100b, peripheral area;

[0032] 200, a counter substrate;

[0033] 1. Substrate;

[0034] 2. Driving circuit layer;

[0035] 21, first conductive layer; 211, scanning line;

[0036] 22, a second conductive layer;

[0037] 23, a third conductive layer;

[0038] 24, a first transparent conductive layer; 241, a pixel electrode;

[0039] 25, second transparent conductive layer; 251, common electrode block; 252, touch electrode;

[0040] 26, semiconductor layer; 261, active layer; 2611, channel portion; 2612, lightly doped portion; 2613, heavily doped portion;

[0041] 27, black matrix;

[0042] 281, first insulating layer; 282, second insulating layer; 283, third insulating layer; 284, fourth insulating layer; 285, fifth insulating layer; 286, sixth insulating layer;

[0043] 3. Shading layer;

[0044] 31, first metal layer; 32, second metal layer; 33, third metal layer; 34, fourth metal layer;

[0045] 35, connecting line; 351, first connecting line; 352, second connecting line; 36, light shielding portion; 36A, light shielding portion group; 37, light shielding connecting portion; 371, hollow portion; 3711, first hollow portion; 3712, second hollow portion;

[0046] 4, signal line; 41, data line; 42, touch line;

[0047] 5. Drive unit;

[0048] H1, first via hole; H2, second via hole; H3, third via hole;

[0049] 61, bridge connection;

[0050] x, first direction; y, second direction; w, third direction. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0052] like Figures 1 to 7 As shown, the present application provides an array substrate 100. The array substrate 100 is applied to a display panel 300, and the display panel 300 includes but is not limited to at least one of a liquid crystal display panel, an organic light emitting diode display panel, a micro light emitting diode display panel, and a sub-millimeter light emitting diode display panel. The array substrate 100 has an array area 100a and a peripheral area 100b arranged around the array area 100a. The array area 100a overlaps with the display area of ​​the display panel 300. The peripheral area 100b overlaps with the non-display area of ​​the display panel 300.

[0053] The array substrate 100 includes a substrate 1 , a driving circuit layer 2 and a light shielding layer 3 .

[0054] The substrate 1 may include a hard substrate such as a glass substrate, or a flexible substrate such as a polymer substrate.

[0055] The driving circuit layer 2 includes a plurality of driving circuits. Figures 1 to 3 , Figure 5 as well as Figure 7 The driving circuit layer 2 is disposed on one side of the substrate 1 and includes a plurality of signal traces 4 disposed in the array area 100a. The plurality of signal traces 4 are used to transmit signals.

[0056] like Figures 4 to 7 As shown, the light shielding layer 3 is disposed between the substrate 1 and the driving circuit layer 2. The light shielding layer 3 includes at least two stacked conductive layers. Thus, the light shielding layer 3 not only has a light shielding function, but also has a low impedance.

[0057] like Figures 1 to 3 , Figure 5 as well as Figure 7As shown, the light shielding layer 3 includes a plurality of connecting wires 35 located in the peripheral area 100b. The plurality of connecting wires 35 are respectively connected to the plurality of signal traces 4. In this way, the plurality of connecting wires 35 include at least two layers of conductive layers stacked together, and the connecting wires 35 with a smaller impedance transmit signals to the signal traces 4 in the array area 100a at a faster speed, thereby improving the performance of the display panel 300. In addition, in addition to using the film layer where the signal traces 4 are located to be wired in the peripheral area 100b, the signal traces 4 can also be wired in the peripheral area 100b using the connecting wires 35 of the light shielding layer 3, which facilitates the multi-layer wiring of the signal traces 4 in the peripheral area 100b, thereby reducing the space occupied by the signal traces 4 in the peripheral area 100b, and the display panel 300 can achieve a narrow frame design. In addition, since the light shielding layer 3 is located below the driving circuit layer 2, the light shielding layer 3 is not easily damaged, which reduces the risk of damage to the connecting wires 35 connected to the signal traces 4, thereby improving the performance stability of the display panel 300.

[0058] It should be noted that in the related art, in order to reduce the thickness of the light shielding layer and reduce the risk of the film layer above the light shielding layer breaking due to climbing, the light shielding layer is usually designed with a single metal layer. In some embodiments of the present application, in order to reduce the impedance of the light shielding layer when it is applied to the wiring of the peripheral area 100b, the light shielding layer 3 is adjusted to include at least two conductive layers.

[0059] In some embodiments, the plurality of connection lines 35 are also connected to the driving unit 5. Thus, the driving unit 5 and the signal trace 4 are connected via the plurality of connection lines 35.

[0060] In some embodiments, Figures 1 to 3 As shown, the plurality of signal lines 4 include at least one of a data line 41 and a touch line 42. It is understandable that the plurality of signal lines 4 may also be other signal lines.

[0061] The data lines 41 are used to transmit data signals. The plurality of data lines 41 extend along the second direction y and are arranged at intervals along the first direction x. The first direction x intersects with the second direction y.

[0062] The touch control lines 42 are used to transmit touch control signals. The touch control lines 42 are insulated from the data lines 41. The touch control lines 42 extend along the second direction y and are arranged at intervals along the first direction x.

[0063] In some embodiments, the first direction x is perpendicular to the second direction y, but the invention is not limited thereto. The angle between the first direction x and the second direction y may be an acute angle or an obtuse angle.

[0064] like Figures 1 to 3 As shown, the array substrate 100 may further include a plurality of touch electrodes 252, and one touch line 42 is connected to one touch electrode 252. Figures 1 to 3The black dot P1 in illustrative figures represents the connection position between the touch line 42 and the touch electrode 252 .

[0065] In some embodiments, the plurality of data lines 41 and the plurality of touch lines 42 may be located in one conductive layer, so that the plurality of data lines 41 and the plurality of touch lines 42 may be formed simultaneously, simplifying the preparation process of the plurality of data lines 41 and the plurality of touch lines 42 .

[0066] In some other embodiments, the data lines 41 and the touch lines 42 may be located in different conductive layers to increase the layout space of the data lines 41 and the touch lines 42 .

[0067] In some embodiments, Figure 1 As shown, the plurality of connection lines 35 are respectively connected to the plurality of data lines 41, and the connection positions between the connection lines 35 and the data lines 41 are indicated by black dots P2. The plurality of touch control lines 42 extend from the array area 100a to the peripheral area 100b and are connected to the drive unit 5. In this way, on the basis of realizing a narrow frame of the display panel 300, the impedance of the wiring for transmitting data signals is reduced, and the refresh rate of the display panel 300 is improved.

[0068] In other embodiments, Figure 2 As shown, the plurality of connection lines 35 are respectively connected to the plurality of touch lines 42, and the connection positions between the connection lines 35 and the touch lines 42 are indicated by black dots P2. The plurality of data lines 41 extend from the array area 100a to the peripheral area 100b and are connected to the drive unit 5. In this way, on the basis of realizing a narrow frame of the display panel 300, the impedance of the wiring for transmitting the touch signal is reduced, and the touch sensitivity of the display panel 300 is improved.

[0069] In some other embodiments, Figure 3 As shown, the plurality of connection lines 35 include a plurality of first connection lines 351 and a plurality of second connection lines 352 that are spaced apart from each other. The plurality of first connection lines 351 are respectively connected to the plurality of data lines 41. The plurality of second connection lines 352 are respectively connected to the plurality of touch lines 42. The connection positions between the first connection lines 351 and the data lines 41 and the connection positions between the second connection lines 352 and the touch lines 42 are both represented by black dots P2. In this way, on the basis of realizing the narrow frame of the display panel 300, the impedance of the routing lines for transmitting data signals and touch signals is reduced at the same time, thereby improving the refresh rate and touch sensitivity of the display panel 300.

[0070] In some embodiments, Figure 5 As shown, the connection line 35 of the peripheral area 100 b and the signal line 4 of the array area 100 a may be connected through the first via H1 .

[0071] In other embodiments, Figure 7As shown, the connection line 35 of the peripheral area 100b and the signal line 4 of the array area 100a can be bridged by a bridge line 61. The bridge line 61 is connected to the connection line 35 through the second via H2, and the bridge line 61 is connected to the signal line 4 through the third via H3.

[0072] like Figure 4 and Figure 5 As shown, in some embodiments, at least two stacked conductive layers include a first metal layer 31 and a second metal layer 32, the first metal layer 31 is located between the substrate 1 and the second metal layer 32, and the reflectivity of the first metal layer 31 to light is greater than the reflectivity of the second metal layer 32 to light. In this way, when the array substrate 100 is applied to a liquid crystal display device, the first metal layer 31 reflects backlight from different directions emitted by a backlight module of the liquid crystal display device, and the reflected backlight is reused after being incident on the backlight module, thereby improving the utilization rate of the backlight, improving the light output efficiency of the panel, and finally improving the display brightness of the display panel 300.

[0073] In some embodiments, the material of the first metal layer 31 is selected from at least one of aluminum, aluminum alloy, copper and copper alloy. The material of the second metal layer 32 is selected from at least one of molybdenum, molybdenum alloy, titanium and titanium alloy. In this way, while the light shielding layer 3 has low impedance, the reflectivity of the first metal layer 31 to light is greater than the reflectivity of the second metal layer 32 to light. In addition, the second metal layer 32 protects the first metal layer 31 and reduces the risk of corrosion of the first metal layer 31.

[0074] Exemplarily, the first metal layer 31 includes aluminum, and the second metal layer 32 includes molybdenum. Thus, the first metal layer 31 has high reflectivity and low impedance to light, and the second metal layer 32 protects the first metal layer 31 and is also resistant to high temperatures.

[0075] In some embodiments, the thickness of the first metal layer 31 may be greater than the thickness of the second metal layer 32. In this way, the reflection effect of the first metal layer 31 on the backlight is improved, thereby improving the utilization rate of the backlight.

[0076] In other embodiments, the thickness of the first metal layer 31 may be less than or equal to the thickness of the second metal layer 32. In this way, the utilization rate of the backlight is improved and the impedance of the light shielding layer 3 is reduced, while reducing the risk of other film layers being broken due to excessive thickness of the light shielding layer 3.

[0077] like Figure 6 and Figure 7As shown, in some embodiments, at least two stacked conductive layers include two third metal layers 33 and a fourth metal layer 34, the fourth metal layer 34 is located between the two third metal layers 33, and the conductivity of the material of the fourth metal layer 34 is greater than the conductivity of the material of the third metal layer 33. In this way, the impedance of the light shielding layer 3 is reduced.

[0078] In some embodiments, the material of the third metal layer 33 is selected from at least one of molybdenum, molybdenum alloy, titanium and titanium alloy, and the material of the fourth metal layer 34 is selected from at least one of aluminum, aluminum alloy, copper and copper alloy. In this way, the light shielding layer 3 has low impedance, and the two third metal layers 33 protect the fourth metal layer 34, reducing the risk of corrosion of the fourth metal layer 34.

[0079] For example, the light shielding layer 3 may include but is not limited to any one of three-layer laminated metals such as MoAlMo, TiAlTi, MoCuMo, and TiCuTi. In this way, the light shielding layer 3 has low impedance, and the two third metal layers 33 protect the fourth metal layer 34, reducing the risk of corrosion of the fourth metal layer 34.

[0080] In some embodiments, the thickness of the fourth metal layer 34 is greater than the thickness of the third metal layer 33 , so as to further reduce the impedance of the light shielding layer 3 .

[0081] In some embodiments, the thickness of the fourth metal layer 34 is 1500 angstroms to 5000 angstroms, and the thickness of the third metal layer 33 is 200 angstroms to 1000 angstroms.

[0082] like Figure 1 , Figure 4 and Figure 6 As shown, the driving circuit layer 2 includes a plurality of thin film transistors T arranged in an array along a first direction x and a second direction y.

[0083] In some embodiments, the thin film transistor T can be selected from any one of a metal oxide transistor, a low temperature polysilicon transistor and an amorphous silicon transistor. Exemplarily, the thin film transistor T is a low temperature polysilicon transistor, which improves the stability of the thin film transistor T under high temperature and high humidity conditions.

[0084] It should be noted that, when the thin film transistor T is a low-temperature polysilicon transistor, the light-shielding layer 3 adopts the design of the above-mentioned first metal layer 31 and the second metal layer 32 or the above-mentioned two third metal layers 33 and the fourth metal layer 34, which can improve the high temperature resistance of the light-shielding layer 3 in the process of forming the low-temperature polysilicon transistor.

[0085] In some embodiments, the thin film transistor T may include at least one of a driving transistor and a switching transistor. The current when the driving transistor is turned on can be used to drive the light emitting device to emit light. When the switching transistor is turned on, the data signal transmitted by the data line 41 can be transmitted to the driving transistor. Exemplarily, the plurality of thin film transistors T may be driving transistors.

[0086] In some embodiments, Figure 1 As shown, a column of thin film transistors T arranged along the second direction y is connected to a data line 41 .

[0087] like Figure 4 , Figure 6 as well as Figures 8 to 12 As shown, the driving circuit layer 2 further includes a semiconductor layer 26. The semiconductor layer 26 includes a plurality of active layers 261 arranged in an array along a first direction x and a second direction y, and the plurality of active layers 261 are located in the array area 100a. The plurality of thin film transistors T include a plurality of active layers 261. The active layer 261 includes a channel portion 2611.

[0088] In some embodiments, the active layer 261 may include at least one of a low temperature polysilicon active layer, an amorphous silicon active layer, and a metal oxide active layer, but is not limited thereto. Exemplarily, the active layer 261 is a low temperature polysilicon active layer. In this way, the high temperature resistance and other properties of the active layer 261 are improved.

[0089] In some embodiments, Figure 4 and Figure 6 As shown, in the case where the active layer 261 is a low temperature polysilicon active layer, the active layer 261 further includes doped portions located on both sides of the channel portion 2611, and the channel portion 2611 is connected between the two doped portions. A doped portion includes a lightly doped portion 2612 and a heavily doped portion 2613, and a lightly doped portion 2612 is connected between the channel portion 2611 and a heavily doped portion 2613.

[0090] In some embodiments, Figures 8 to 12 As shown, the active layer 261 is U-shaped, and the two parts of the active layer 261 overlapping the scan line 211 are two channel parts. In other embodiments, the active layer 261 may also be in other shapes, such as a straight line or an irregular shape.

[0091] like Figure 4 , Figure 6 , Figures 8 to 12As shown, the light shielding layer 3 also includes a plurality of light shielding portions 36 arranged in an array along the first direction x and the second direction y in the array area 100a. The plurality of orthographic projections of the plurality of channel portions 2611 on the substrate are respectively located within the orthographic projections of the plurality of light shielding portions 36 on the substrate. In this way, the plurality of light shielding portions 36 shield the incident light, thereby improving the problem of the active layer 261 generating photogenerated carriers due to the incident light entering the channel portion 2611. Moreover, on the basis that the light shielding layer 3 includes at least two conductive layers, the area of ​​the light shielding portion 36 is increased, thereby reducing the problem of the active layer 261 climbing and breaking due to the increase in the thickness of the light shielding layer 3.

[0092] like Figure 8 As shown, in some embodiments, the orthographic projection of the channel portion 2611 of an active layer 261 on the substrate 1 is located within the orthographic projection of the light shielding portion 36 on the substrate 1, and the orthographic projection of the other parts of the active layer 261 except the channel portion 2611 on the substrate 1 does not overlap with the orthographic projection of the light shielding portion 36 on the substrate 1. In this way, the light shielding portion 36 plays a role of partially shielding the active layer 261, reducing the effect of the channel portion 261 of the active layer 261 generating photogenerated carriers.

[0093] like Figures 9 to 12 As shown, in some embodiments, the orthographic projection of an active layer 261 on the substrate 1 is located within the orthographic projection of a light shielding portion 36 on the substrate 1. In this way, each light shielding portion 36 covers an active layer 261, so that the multiple light shielding portions 36 can better shield the incident light, while also reducing the risk of the active layer 261 climbing and breaking due to the increase in the thickness of the light shielding layer 3.

[0094] In some embodiments, Figures 8 to 15 As shown, the light shielding layer 3 further includes a light shielding connection portion 37, and at least two light shielding portions 36 are connected via at least one light shielding connection portion 37. In this way, when the area of ​​the light shielding portion 36 increases, the coupling effects between at least two signal lines and at least two interconnected light shielding portions 36 offset each other, thereby improving the problem of signal crosstalk.

[0095] In some embodiments, Figures 8 to 15 As shown, the light shielding layer 3 includes at least two light shielding portion groups 36A, any two light shielding portion groups 36A are insulated from each other, and one light shielding portion group 36A includes at least two light shielding portions 36 connected to each other through at least one light shielding portion connecting portion 37. In this way, the coupling effects between the at least two light shielding portions 36 connected to each other in one light shielding portion group 36A and the signal line offset each other, thereby improving the signal crosstalk problem. Any two light shielding portions 36 located in any two light shielding portion groups 36A are disconnected.

[0096] In some embodiments, Figures 8 to 12As shown, any two adjacent light shielding portions 36 in an even number of adjacent light shielding portions 36 in the first direction x are connected by a light shielding connecting portion 37. In this way, the signal crosstalk problem caused by the coupling between the light shielding portion 36 and the data line 41 transmitting opposite polarities is improved when the area of ​​the light shielding portion 36 is increased.

[0097] In some embodiments, in the first direction x, any two adjacent light shielding portions 36 among the 2n adjacent light shielding portions 36 are connected by a light shielding connection portion 37, where n is an integer greater than or equal to 2 and less than or equal to 5. In this way, the crosstalk problem caused by the coupling between the light shielding portion 36 and the data line 41 is improved, while the risk of the light shielding connection portion 37 being broken due to process reasons and thus causing the connection failure of the adjacent light shielding portions 36 is reduced, and the controllability of improving the crosstalk problem is also improved.

[0098] In some embodiments, in the first direction x, two adjacent shading portions 36 are connected by a shading connecting portion 37; and / or, any two adjacent shading portions 36 among four adjacent shading portions 36 are connected by a shading connecting portion 37; and / or, any two adjacent shading portions 36 among six adjacent shading portions 36 are connected by a shading connecting portion 37.

[0099] For example, Figures 8 to 12 As shown, in the first direction x, any two adjacent light shielding portions 36 among the four adjacent light shielding portions 36 are connected by a light shielding connecting portion 37 .

[0100] It should be noted that when the array substrate 100 is applied to a liquid crystal display panel, the liquid crystal display panel will use column inversion technology or dot inversion technology to reduce damage to liquid crystal molecules. When using column inversion technology or dot inversion technology, adjacent data lines 41 will transmit data signals with opposite polarities. Specifically, when the data voltage transmitted by one of the two adjacent data lines 41 is greater than the common voltage, the data voltage transmitted by the data line 41 is a positive polarity data voltage, and the positive polarity data voltage is represented by "+"; when the data voltage transmitted by the other of the two adjacent data lines 41 is less than the common voltage, the data voltage transmitted by the data line 41 is a negative polarity data voltage, and the negative polarity data voltage is represented by "-".

[0101] like Fig.13 and Fig.14 As shown, when the liquid crystal display panel 300 adopts the column inversion technology or the dot inversion technology, the shading portion 36 coupled to the data line 41 transmitting the positive polarity data voltage is marked with "+", and the shading portion 36 coupled to the data line 41 transmitting the negative polarity data voltage is marked with "-".

[0102] for Figures 8 to 13The design shown, that is, any two adjacent shading portions 36 among an even number of adjacent shading portions 36 in the first direction x are connected by a shading connecting portion 37, so that the coupling effects between the even number of adjacent shading portions 36 in the first direction x and the data lines 41 transmitting opposite polarities cancel each other out, thereby improving the signal crosstalk problem caused by the coupling effect between the shading portions 36 and the data lines 41.

[0103] for Fig.14 In the design shown, in the third direction w, any two adjacent light shielding portions 36 among the even number of adjacent light shielding portions 36 are connected by a light shielding connecting portion 37, and the third direction w intersects with the first direction x and the second direction y. In this way, the coupling effects between the even number of adjacent light shielding portions 36 in the third direction w and the data lines 41 transmitting opposite polarities cancel each other out, thereby improving the crosstalk problem caused by the coupling effect between the light shielding portions 36 and the data lines 41.

[0104] Exemplarily, the angle between the third direction w and one of the first direction x and the second direction y is 45 degrees, but is not limited thereto.

[0105] In some embodiments, Figures 8 to 12 As shown, the driving circuit layer 2 further includes a plurality of scanning lines 211. The plurality of scanning lines 211 are insulated from the plurality of data lines 41 and the plurality of touch control lines 42. The plurality of scanning lines 211 extend along the first direction x and are arranged at intervals along the second direction y.

[0106] In some embodiments, Fig.14 As shown, in the second direction y, at least two light shielding portions 36 are connected by at least one light shielding connecting portion 37. In this way, the signal crosstalk problem caused by the coupling between the light shielding portion 36 and the plurality of scanning lines 211 is improved when the area of ​​the light shielding portion 36 is increased.

[0107] In some embodiments, in the second direction y, any two adjacent light shielding portions 36 among the m adjacent light shielding portions 36 are connected by a light shielding connection portion 37, and m is an integer greater than or equal to 2 and less than or equal to 10. In this way, the signal crosstalk problem caused by the coupling between the light shielding portion 36 and the data line 41 is improved, while the risk of the light shielding connection portion 37 being broken due to process reasons and thus causing the connection failure of the adjacent light shielding portions 36 is reduced, and the controllability of improving the crosstalk problem is also improved. Exemplarily, m can be 2, 3, 4, 5, 6, 7, 8, 9 or 10.

[0108] In some embodiments, the orthographic projection of the light shielding connection portion 37 on the substrate is staggered from the orthographic projection of at least one of the signal wiring 4 and the scanning line 211 on the substrate. In this way, the overlapping area between the light shielding connection portion 37 and at least one of the signal wiring 4 and the scanning line 211 is reduced, the coupling capacitance generated by the overlapping area is reduced, and the risk of signal crosstalk caused by the coupling capacitance is reduced.

[0109] In an exemplary embodiment, Fig. 9 As shown, the light shielding connection portion 37 extends along the first direction x and connects two adjacent light shielding portions 36 in the first direction x, and the orthographic projection of the light shielding connection portion 37 on the substrate 1 is staggered from the orthographic projection of the scanning line 211 on the substrate 1. In this way, the light shielding connection portion 37 and the scanning line 211 do not overlap, reducing the coupling capacitance formed between the light shielding connection portion 37 and the scanning line 211, further improving the signal crosstalk problem.

[0110] In another exemplary embodiment, the light shielding connection portion 37 extends along the second direction y and connects two adjacent light shielding portions 36 in the second direction y, and the orthographic projection of the light shielding connection portion 37 on the substrate 1 is staggered from the orthographic projection of the data line 41 and the touch line 42 on the substrate 1. In this way, the light shielding connection portion 37 does not overlap with the data line 41 and the touch line 42, thereby reducing the coupling capacitance formed between the light shielding connection portion 37 and the data line 41 and the touch line 42, and further improving the signal crosstalk problem.

[0111] In some embodiments, Figure 8 and Fig. 9 As shown, the area of ​​one light shielding connection part 37 is smaller than the area of ​​one light shielding part 36. Thus, the area of ​​the light shielding connection part 37 is smaller, which improves the signal crosstalk problem caused by the coupling between the light shielding connection part 37 and other signal lines, and improves the light transmittance of the array substrate 100.

[0112] like Figures 10 to 12 As shown, the light shielding connection portion 37 includes a hollow portion 371, and the hollow portion 371 penetrates the light shielding connection portion 37 along the thickness direction of the light shielding layer 3. In this way, light can pass through the hollow portion 371, and more light can be incident on the array substrate 100, thereby improving the display brightness of the display panel.

[0113] In some embodiments, Figures 10 to 12 As shown, the plurality of hollow portions 371 are arranged at intervals. In this way, light incident on the array substrate 100 can pass through the plurality of hollow portions 371 .

[0114] In some embodiments, Fig.10 As shown, the plurality of hollow portions 371 may be identical, thus simplifying the manufacturing process of the plurality of hollow portions 371 .

[0115] In some embodiments, the shapes of the plurality of hollow portions 371 may be the same to simplify the process of forming the hollow portions 371. In other embodiments, the shapes of at least two hollow portions 371 may be different.

[0116] like Figures 10 to 12As shown, the orthographic projection of the hollow portion 371 on the substrate overlaps with the orthographic projection of at least one of the scanning line 211 and the signal wiring 4 on the substrate. In this way, on the basis of improving the transmittance of the array substrate 100 to light, the overlapping area between the light shielding connection portion 37 and at least one of the signal wiring 4 and the scanning line 211 is reduced, the coupling capacitance generated by the overlapping area is reduced, and the risk of signal crosstalk caused by the coupling capacitance is reduced.

[0117] In some embodiments, Fig.11 and Fig.12 As shown, the plurality of hollow portions 371 include a first hollow portion 3711 and a second hollow portion 3712, and the area of ​​the first hollow portion 3711 is greater than the area of ​​the second hollow portion 3712. The first hollow portion 3711 overlaps with the data line 41 and the scan line 211, and the second hollow portion 3712 overlaps with one of the data line 41 and the scan line 211. In this way, the first hollow portion 3711 with a larger area overlaps with both the data line 41 and the scan line 211, reducing the overlapping area between the light shielding connection portion 37 and the data line 41 and the scan line 211, and the second hollow portion 3712 with a smaller area overlaps with one of the data line 41 and the scan line 211.

[0118] In some embodiments, the number of the second hollow portions 3712 is greater than the number of the first hollow portions 3711. In this way, the coupling capacitance between one of the data line 41 and the scan line 211 and the light shielding connection portion 37 can be reduced more flexibly.

[0119] In some embodiments, the plurality of light shielding portions 36 may not be connected to a voltage. In other embodiments, the plurality of light shielding portions 36 may also be connected to a constant voltage.

[0120] like Fig.12 As shown, the array substrate 100 further includes a black matrix 27. The black matrix 27 has a shielding effect on light. The black matrix 27 is located on the side of the light shielding layer 3 facing away from the substrate 1. The orthographic projection of the black matrix 27 on the substrate 1 overlaps with the orthographic projection of the light shielding connecting portion 37 on the substrate. In this way, the black matrix 27 has a shielding effect on the light shielding connecting portion 37. The orthographic projection of the black matrix 27 on the substrate can also cover the orthographic projection of the scanning line 211 and the data line 41 on the substrate.

[0121] In some embodiments, Figure 4 and Figure 6 As shown, the array substrate 100 further includes a first insulating layer 281 , and the first insulating layer 281 is located between the driving circuit layer 2 and the light shielding layer 3 .

[0122] In some embodiments, Figure 4 and Figure 6 As shown, the driving circuit layer 2 includes a first conductive layer 21. The first conductive layer 21 is located on a side of the light shielding layer 3 that is away from the substrate.

[0123] like Figure 4 As shown, the first conductive layer 21 may include a scan line 211 and a gate of a thin film transistor T. Figure 7 As shown, the first conductive layer 21 may further include a signal trace 4 .

[0124] like Figure 4 and Figure 6 As shown, in some embodiments, the first conductive layer 21 may be located on the side of the semiconductor layer 26 away from the light shielding layer 3, and the corresponding thin film transistor T includes a top gate. In other embodiments, the first conductive layer 21 may be located between the semiconductor layer 26 and the light shielding layer 3, and the corresponding thin film transistor T includes a bottom gate.

[0125] In some embodiments, a second insulating layer 282 is disposed between the first conductive layer 21 and the semiconductor layer 26 .

[0126] In some embodiments, Figure 4 and Figure 6 As shown, the driving circuit layer 2 includes a second conductive layer 22. The second conductive layer 22 is located on a side of the first conductive layer 21 away from the substrate. Figure 4 and Figure 5 As shown, in some embodiments, the second conductive layer 22 may include signal wirings 4 such as data lines 41 and touch lines 42 and the source of the thin film transistor T. Figure 6 As shown, in some other embodiments, the second conductive layer 22 includes a data line 41 , a touch line 42 , and a source and a drain of the thin film transistor T.

[0127] In some embodiments, a third insulating layer 283 is disposed between the second conductive layer 22 and the first conductive layer 21 .

[0128] like Figure 4 As shown, in some embodiments, the driving circuit layer 2 further includes a third conductive layer 23. The third conductive layer 23 is located on a side of the second conductive layer 22 away from the substrate 1. The third conductive layer 23 may include a touch line 42 and a drain electrode of the thin film transistor T.

[0129] In some embodiments, a fourth insulating layer 284 is disposed between the third conductive layer 23 and the second conductive layer 22 .

[0130] In some embodiments, the array substrate 100 further includes a first transparent conductive layer 24 and a second transparent conductive layer 25. The first transparent conductive layer 24 is located on the side of the driving circuit layer 2 away from the substrate. The second transparent conductive layer 25 is located on the side of the first transparent conductive layer 24 away from the substrate.

[0131] One of the first transparent conductive layer 24 and the second transparent conductive layer 25 includes a pixel electrode 241 connected to the drain of the thin film transistor T. The other of the first transparent conductive layer 24 and the second transparent conductive layer 25 includes a plurality of common electrode blocks 251. Exemplarily, the first transparent conductive layer 24 includes the pixel electrode 241, and the second transparent conductive layer 25 includes the common electrode block 251.

[0132] In some embodiments, a plurality of common electrode blocks 251 are connected to the touch lines 42 through vias, so that the common electrode blocks 251 are reused as touch electrodes 252 .

[0133] like Figure 4 and Figure 6 As shown, in some embodiments, a fifth insulating layer 285 is disposed between the first transparent conductive layer 24 and the second conductive layer 22 or the third conductive layer 23. A sixth insulating layer 286 is disposed between the first transparent conductive layer 24 and the second transparent conductive layer 25.

[0134] In some embodiments, the first to fourth insulating layers 281 to 284 and the sixth insulating layer 286 may all be inorganic insulating layers. The inorganic insulating layer may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The fifth insulating layer 285 may be an organic insulating layer. The organic insulating layer may include at least one of polyimide and polyacrylate.

[0135] Based on the same inventive concept, Fig.16 As shown, the present application further provides a display panel 300. The display panel 300 includes the array substrate 100 described above.

[0136] In some embodiments, the display panel 300 further includes an opposing substrate 200, and the opposing substrate 200 is disposed opposite to the array substrate 100. The opposing substrate 200 can be any one of a color filter substrate and a packaging substrate.

[0137] In some embodiments, when the display panel 300 is a liquid crystal display panel, a black matrix 27 is disposed on the surface of the counter substrate 200 facing the array substrate 100. When the light shielding layer 3 of the array substrate 100 includes a light shielding connection portion 37, the orthographic projection of the black matrix 27 on the array substrate 100 covers the light shielding connection portion 37.

[0138] like Fig.17 As shown, based on the same inventive concept, the present application further provides a display device 500. The display device 500 includes the display panel 300 described above.

[0139] In some embodiments, when the display device 500 is a liquid crystal display device, the display device 500 further includes a backlight module 400 , and the backlight module 400 is located at the light incident side of the display panel 300 .

[0140] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: The array substrate has an array area and a peripheral area arranged around the array area, and the array substrate includes: substrate; A driving circuit layer, disposed on one side of the substrate and comprising a plurality of signal traces disposed in the array area; and The light shielding layer is arranged between the substrate and the driving circuit layer, and includes at least two stacked conductive layers and a plurality of connecting wires located in the peripheral area, wherein the plurality of connecting wires are respectively connected to the plurality of signal wirings.

2. The array substrate according to claim 1, characterized in that: The driving circuit layer further comprises a semiconductor layer, wherein the semiconductor layer comprises a plurality of active layers arranged at intervals, and the active layer comprises a channel portion; The light shielding layer further includes a plurality of light shielding portions, and a plurality of orthographic projections of the plurality of channel portions on the substrate are respectively located within the orthographic projections of the plurality of light shielding portions on the substrate.

3. The array substrate according to claim 2, characterized in that: An orthographic projection of the active layer on the substrate is located within an orthographic projection of the light shielding portion on the substrate.

4. The array substrate according to claim 2, characterized in that: The light-shielding layer further includes a light-shielding connecting portion, and at least two of the light-shielding portions are connected via at least one of the light-shielding connecting portions.

5. The array substrate according to claim 4, characterized in that: The driving circuit layer further includes a plurality of data lines arranged at intervals, the plurality of data lines being arranged along a first direction and extending along a second direction; In the first direction, any two adjacent shading portions among an even number of adjacent shading portions are connected by one shading connecting portion; and / or, In the third direction, any two adjacent light-shielding portions among an even number of adjacent light-shielding portions are connected via one light-shielding connecting portion, and the third direction intersects the first direction and the second direction.

6. The array substrate according to claim 4, characterized in that: The driving circuit layer further includes a plurality of scan lines arranged at intervals, the plurality of scan lines extending along the first direction and arranged along the second direction; In the second direction, at least two of the light shielding portions are connected via the light shielding connecting portion.

7. The array substrate according to claim 4, characterized in that: The signal wiring includes at least one of a data line and a touch line, and the driving circuit layer further includes a scan line; An orthographic projection of the light-shielding connection portion on the substrate is offset from an orthographic projection of at least one of the signal wiring and the scanning line on the substrate.

8. The array substrate according to claim 4, characterized in that: The light-shielding connection portion includes a hollow portion, and the hollow portion penetrates the light-shielding connection portion along a thickness direction of the light-shielding layer.

9. The array substrate according to claim 8, characterized in that: The signal wiring includes at least one of a data line and a touch line, and the driving circuit layer further includes a scan line; An orthographic projection of the hollow portion on the substrate overlaps with an orthographic projection of at least one of the scan line and the signal wiring on the substrate.

10. The array substrate according to claim 4, characterized in that: The light-shielding layer includes at least two light-shielding portion groups, any two of the light-shielding portion groups are insulated from each other, and one light-shielding portion group includes at least two light-shielding portions that are interconnected via at least one light-shielding portion connecting portion.

11. The array substrate according to any one of claims 1 to 10, characterized in that: The at least two stacked conductive layers include a first metal layer and a second metal layer, the first metal layer is located between the substrate and the second metal layer, and the reflectivity of the first metal layer to light is greater than the reflectivity of the second metal layer to light.

12. The array substrate according to claim 11, characterized in that: The material of the first metal layer is selected from at least one of aluminum, aluminum alloy, copper and copper alloy, and the material of the second metal layer is selected from at least one of molybdenum, molybdenum alloy, titanium and titanium alloy.

13. The array substrate according to any one of claims 1 to 10, characterized in that: The at least two stacked conductive layers include two third metal layers and a fourth metal layer. The fourth metal layer is located between the two third metal layers. The conductivity of the material of the fourth metal layer is greater than the conductivity of the material of the third metal layer.

14. The array substrate according to claim 13, characterized in that: The material of the third metal layer is selected from at least one of molybdenum, molybdenum alloy, titanium and titanium alloy, and the material of the fourth metal layer is selected from at least one of aluminum, aluminum alloy, copper and copper alloy; and / or the thickness of the fourth metal layer is greater than the thickness of the third metal layer.

15. The array substrate according to claim 4, characterized in that: The array substrate further includes: The black matrix is ​​located on a side of the light shielding layer away from the substrate, and the orthographic projection of the black matrix on the substrate overlaps with the orthographic projection of the light shielding connecting portion on the substrate.

16. A display panel, characterized in that: Comprising the array substrate according to any one of claims 1 to 15.

17. A display device, characterized in that: The display device comprises the display panel according to claim 16.

Images