Display panel and display device

Abstract

The invention provides a display panel and a display device. According to the display panel, a first metal layer comprises a drain electrode, a doping part penetrates through a first via hole to be connected with the drain electrode, so that the display panel can adopt the same metal layer to form an electrode and a shading pattern, the number of mask plates is reduced, a buffer layer comprises a special-shaped part, and a channel part is arranged on one plane of the special-shaped part and the side wall of the special-shaped part, so that the thickness of the buffer layer is reduced. The grid electrode is arranged corresponding to the side wall of the channel part and the top surface of the channel part, so that the length of the channel can be increased, the length of the part, opposite to the channel, of the grid electrode can be increased, the grid electrode control area is increased, the grid electrode width can be correspondingly reduced, the size of a single thin film transistor is reduced, and the pixel density is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, in order to improve the performance of display devices, top gate indium gallium zinc oxide thin film transistors (Top gate IGZO TFT) are used in existing display devices to reduce parasitic capacitance, but the number of mask plates required to form a thin film transistor with a top gate structure is greater than the number of mask plates required to form a thin film transistor with a bottom gate structure, resulting in increased costs and more processes. In order to reduce the number of mask plates required in the preparation process of a thin film transistor with a top gate structure, existing display devices use the same metal layer to form the light shielding layer and the source and drain electrode layer, thereby reducing two mask plates and reducing parasitic capacitance. However, since the light shielding layer and the source and drain electrode layer are formed using the same metal layer, the layout space is limited, resulting in a low pixel density of the display device.

[0003] Therefore, the existing display device in which the light shielding layer and the source and drain electrode layer are arranged on the same metal layer has a technical problem of low pixel density. Summary of the invention

[0004] The embodiments of the present application provide a display panel and a display device, which are used to solve the technical problem that the existing display device in which the light shielding layer and the source and drain layer are arranged on the same metal layer has a low pixel density.

[0005] An embodiment of the present application provides a display panel, the display panel comprising:

[0006] substrate;

[0007] A first metal layer, disposed on one side of the substrate, wherein the first metal layer includes a drain electrode;

[0008] a buffer layer, disposed on a side of the first metal layer away from the substrate, the buffer layer comprising a first via hole;

[0009] an active layer, arranged on a side of the buffer layer away from the first metal layer, the active layer comprising a channel portion and doped portions arranged on both sides of the channel portion, the doped portion passing through the first via hole and connected to the drain electrode;

[0010] A second metal layer is disposed on a side of the active layer away from the buffer layer, and the second metal layer includes a gate;

[0011] Wherein, the buffer layer further includes a shaped portion, the channel portion is arranged on a plane of the shaped portion and a side wall of the shaped portion, and the gate is arranged corresponding to the side wall of the channel portion and a top surface of the channel portion.

[0012] In some embodiments, the special-shaped portion includes a second via hole, the channel portion is disposed in the second via hole, and the channel portion overlaps the side wall and the bottom surface of the second via hole.

[0013] In some embodiments, the display panel also includes a gate insulating layer, which is arranged between the active layer and the gate, the channel portion includes a first channel portion overlapping the side wall of the second via and a second channel portion overlapping the bottom surface of the second via, the gate insulating layer includes a first insulating portion overlapping the first channel portion and a second insulating portion overlapping the second channel portion, the gate overlaps the first insulating portion and contacts the second insulating portion, and the gate is arranged corresponding to the first channel portion and the second channel portion.

[0014] In some embodiments, the first metal layer further includes a light shielding pattern, the light shielding pattern is arranged corresponding to the channel portion, and there is a distance between a top surface of the light shielding pattern and the second via hole.

[0015] In some embodiments, a distance between the light shielding pattern and a top surface of a portion of the buffer layer corresponding to the second via hole is one fifth to four fifths of a thickness of the buffer layer.

[0016] In some embodiments, an angle between a top surface and a side wall of a portion of the buffer layer corresponding to the second via hole ranges from 25 degrees to 80 degrees.

[0017] In some embodiments, the special-shaped portion includes a protrusion, the channel portion is disposed on the protrusion, and the channel portion overlaps the side wall of the protrusion.

[0018] In some embodiments, the display panel also includes a gate insulating layer, which is arranged between the active layer and the gate, the gate insulating layer is arranged on the top surface of the channel portion and overlaps the side wall of the channel portion, and the gate is arranged on the top surface of the gate insulating layer and overlaps the side wall of the gate insulating layer.

[0019] In some embodiments, the display panel further includes a pixel electrode layer, the pixel electrode layer includes a pixel electrode, and the pixel electrode is directly connected to another of the doped parts.

[0020] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0021] Beneficial effects: The present application provides a display panel and a display device; the display panel enables the first metal layer to include a drain electrode, and the doped portion is connected to the drain electrode through a first via hole, so that the display panel can use the same metal layer to form an electrode and a shading pattern, thereby reducing the number of mask plates, and enables the buffer layer to include a shaped portion, the channel portion is arranged on a plane of the shaped portion and on the side wall of the shaped portion, and the gate is arranged corresponding to the side wall of the channel portion and the top surface of the channel portion, thereby increasing the channel length, and increasing the length of the portion where the gate and the channel are arranged opposite to each other, thereby increasing the gate control area, thereby correspondingly reducing the gate width, reducing the size of a single thin film transistor, and improving the pixel density. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0023] Figure 1 A schematic diagram of a first comparison display panel provided in an embodiment of the present application.

[0024] Figure 2 A schematic diagram of a second comparison display panel provided in an embodiment of the present application.

[0025] Figure 3 A first schematic diagram of a display panel provided in an embodiment of the present application.

[0026] Figure 4 A second schematic diagram of a display panel provided in an embodiment of the present application.

[0027] Figure 5 A schematic diagram of the structure of a display panel corresponding to each step of a method for preparing a display panel provided in an embodiment of the present application.

[0028] Figure 6 A schematic diagram of the structure of a display panel corresponding to each step of another method for preparing a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0030] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0031] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0032] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0033] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0034] As an introduction to the embodiments of the present application, some comparative display panels are provided to illustrate the principle of the technical problem to be solved by the embodiments of the present application. Figure 1 As shown, a comparative display panel includes a substrate 101, a light shielding film 102, a buffer film 103, a semiconductor film 104, a gate insulating film 105, a gate film 106, an interlayer insulating film 107, a source-drain film 108, a first passivation film 109, a planarization film 111, a common electrode film 112, a second passivation film 113, and a second electrode film 114. Figure 1 It can be seen that the comparative display panel requires a mask plate when forming the light shielding film 102, the semiconductor film 104, the gate film 106, the source and drain film 108, the common electrode film 112, and the second electrode film 114, and forming via holes in the buffer film 103, the interlayer insulating film 107, the planarization film 111, and the second passivation film 113. Since the patterns of the film layers are different, the via holes of the film layers are set at different positions. The structures of the mask plates used when forming the film layers and forming via holes in the film layers are different, resulting in a large number of mask plates. Figure 1 The display panel requires 10 mask plates (i.e., 6 mask plates required to form the shading film 102, the semiconductor film 104, the gate film 106, the source and drain film 108, the common electrode film 112 and the second electrode film 114, and 4 mask plates required to form vias for the buffer film 103, the interlayer insulating film 107, the planarization film 111 and the second passivation film 113, a total of 10 mask plates), resulting in high cost and complex process.

[0035] In order to reduce the number of masks, such as Figure 2 As shown, another comparative display panel removes the source and drain films and the interlayer insulating film, and uses the light shielding film 102 to form a light shielding pattern and an electrode, so that Figure 2 The comparative display panel shown only needs to use 8 mask plates, but because the light shielding pattern and the electrode are located in the same layer, multiple metal patterns need to be formed in the same layer, resulting in a low pixel density of the display device. Therefore, the existing display device in which the light shielding layer and the source and drain electrode layer are arranged in the same metal layer has a technical problem of low pixel density.

[0036] In view of the above technical problems, the embodiments of the present application provide a display panel and a display device to solve the above technical problems.

[0037] Figure 3 A first schematic diagram of a display panel provided in an embodiment of the present application. Figure 4 A second schematic diagram of a display panel provided in an embodiment of the present application. Figure 5 A schematic diagram of the structure of a display panel corresponding to each step of a method for preparing a display panel provided in an embodiment of the present application. Figure 6 A schematic diagram of the structure of a display panel corresponding to each step of another method for preparing a display panel provided in an embodiment of the present application.

[0038] like Figure 3 As shown, an embodiment of the present application provides a display panel, the display panel 2 includes a substrate 21, a first metal layer 22, a buffer layer 23, an active layer 24 and a second metal layer 26, the first metal layer 22 is arranged on one side of the substrate 21, and the first metal layer 22 includes a drain 221; the buffer layer 23 is arranged on a side of the first metal layer 22 away from the substrate 21, and the buffer layer 23 includes a first via 231; the active layer 24 is arranged on a side of the buffer layer 23 away from the first metal layer 22, and the active layer 24 includes a channel portion 241 and doped portions 242 arranged on both sides of the channel portion 241, and the doped portion 242 passes through the first via 231 and is connected to the drain 221; the second metal layer 26 is arranged on a side of the active layer 24 away from the buffer layer 23, and the second metal layer 26 includes a gate 261;

[0039] The buffer layer 23 further includes a shaped portion 232 , the channel portion 241 is disposed on a plane of the shaped portion 232 and on a sidewall of the shaped portion 232 , and the gate 261 is disposed corresponding to the sidewall of the channel portion 241 and the top surface of the channel portion 241 .

[0040] An embodiment of the present application provides a display panel, which enables the first metal layer to include a drain electrode, and the doped portion to be connected to the drain electrode through a first via hole, so that the display panel can use the same metal layer to form an electrode and a shading pattern, thereby reducing the number of mask plates, and enables the buffer layer to include a shaped portion, the channel portion is arranged on a plane of the shaped portion and on the side wall of the shaped portion, and the gate is arranged corresponding to the side wall of the channel portion and the top surface of the channel portion, thereby increasing the channel length, and increasing the length of the portion where the gate and the channel are arranged opposite to each other, thereby increasing the gate control area, thereby correspondingly reducing the gate width, reducing the size of a single thin film transistor, and improving the pixel density.

[0041] Specifically, the display panel may include a thin film transistor.

[0042] Specifically, Figure 2 , Figure 3 As shown, it can be seen that in the comparative display panel, due to the horizontal setting of the surface of the buffer layer, the channel length is Figure 2 The width of the channel portion in the embodiment of the present application, and accordingly, the area directly facing the gate and the channel portion is the product of the gate length and width. In the display panel in the embodiment of the present application, since the buffer layer is provided with a special-shaped portion, the channel length is the sum of the length of the channel portion and twice the length of the portion of the channel portion overlapping the side wall of the special-shaped portion. Accordingly, the area directly facing the gate and the channel portion is the product of the gate length and the gate width and the gate thickness and the gate length, thereby increasing the channel length and the gate control area. Accordingly, in order to improve the performance of the display panel and / or increase the pixel density, the channel length and the gate control area can still be guaranteed to meet the requirements or even increase the channel length and the gate control area by reducing the width of the gate, and the pixel density can be improved.

[0043] Specifically, it is understandable that Figure 3 The first via 231 and other vias and grooves are shown in the figure, but since the vias and grooves are filled with various structures, the vias and grooves cannot be observed. It can be understood that the positions where the various structures are provided are the positions of the vias and grooves. For example, the doping portion 242 is provided in the first via 231, and the passivation layer 27 is provided in the first via 231. The shape and position of the first via 231 can be determined according to the shape and position of the portion of the doping portion 242 and the passivation layer 27 embedded in the buffer layer. Similarly, the shapes and positions of other vias and grooves can be determined.

[0044] In some embodiments, Figure 3 As shown, the irregular portion 232 includes a second via hole 233, the channel portion 241 is disposed in the second via hole 233, and the channel portion 241 overlaps the side wall and the bottom surface of the second via hole 233. By making the irregular portion include the second via hole, the channel portion can be disposed in the second via hole, and the channel length of the thin film transistor in the display panel is the sum of twice the length of the side wall of the portion of the buffer layer corresponding to the second via hole and the width of the channel portion, thereby increasing the channel length of the thin film transistor in the display panel, and correspondingly reducing the width of the gate, thereby improving the pixel density, and the thickness of the display panel may not be increased or may even be reduced.

[0045] Specifically, it can be seen that the channel portion 241 overlaps the side wall and the top surface of the portion of the buffer layer 23 corresponding to the second via hole 233 , thereby increasing the channel length of the thin film transistor of the display panel.

[0046] In some embodiments, Figure 3As shown, the display panel 2 also includes a gate insulating layer 25, and the gate insulating layer 25 is arranged between the active layer 24 and the gate 261. The channel portion 241 includes a first channel portion 241a overlapping the side wall of the second via hole 233 and a second channel portion 241b overlapping the bottom surface of the second via hole 233. The gate insulating layer 25 includes a first insulating portion 251 overlapping the first channel portion 241a and a second insulating portion 252 overlapping the second channel portion 241b. The gate 261 overlaps the first insulating portion 251 and contacts the second insulating portion 252, and the gate 261 is arranged corresponding to the first channel portion 241a and the second channel portion 241b. By making the channel portion include a first channel portion arranged on the side wall of the second via hole and a second channel portion arranged on the bottom surface of the second via hole, the gate insulating layer includes a first insulating portion arranged on the first channel portion and a second insulating portion arranged on the second channel portion, so that the gate can be arranged on the first insulating portion and in contact with the second insulating portion, and the gate can be arranged corresponding to the first channel portion and the second channel portion, the gate control area can be increased, and the width of the gate can be reduced accordingly, thereby improving the pixel density.

[0047] In some embodiments, Figure 3 As shown, the first metal layer 22 further includes a light shielding pattern 222, and the light shielding pattern 222 is arranged corresponding to the channel portion 241, and there is a distance between the top surface of the light shielding pattern 222 and the second via hole 233. By making the first metal layer include the light shielding pattern, the light shielding pattern and the drain electrode are formed by the first metal layer, so that the number of film layers of the display panel can be reduced, the number of mask plates required for the display panel can be reduced, the cost can be reduced, and the process steps can be reduced. In addition, by making the top surface of the light shielding pattern and the second via hole have a distance, it can be avoided that the light shielding pattern contacts the channel portion, resulting in failure of the channel portion, thereby improving the yield of the display panel.

[0048] In some embodiments, Figure 3 As shown, the distance L1 between the light shielding pattern 222 and the top surface of the portion of the buffer layer 23 corresponding to the second via hole 233 is one-fifth to four-fifths of the thickness L2 of the buffer layer 23. By making the distance between the light shielding pattern and the top surface of the portion of the buffer layer corresponding to the second via hole one-fifth to four-fifths of the thickness of the buffer layer, it is possible to avoid the light shielding pattern from contacting the channel portion, resulting in failure of the channel portion, thereby improving the yield of the display panel.

[0049] Specifically, Figure 3As shown, it can be understood that the first metal layer 22 includes a shading pattern 222, and the shading pattern 222 can shield the channel portion from light, but the shading pattern 222 is a conductor. In order to avoid conductor failure of the channel portion 241, a buffer layer of a certain thickness needs to be retained between the shading pattern 222 and the channel portion 241 so that the display panel can work normally.

[0050] Specifically, the above-mentioned embodiment is described by taking the example that the distance between the light-shielding pattern and the top surface of the portion of the buffer layer corresponding to the second via hole is one-fifth to four-fifths of the thickness of the buffer layer, but the embodiments of the present application are not limited to this. It is sufficient that there is a distance between the light-shielding pattern and the top surface of the portion of the buffer layer corresponding to the second via hole, and the light-shielding pattern does not affect the normal function of the channel portion. For example, the distance between the light-shielding pattern and the top surface of the portion of the buffer layer corresponding to the second via hole is one-sixth of the thickness of the buffer layer.

[0051] In some embodiments, the shading pattern is connected to the gate, or the potential on the shading pattern is the same as the potential of the gate. By connecting the shading pattern to the gate, or the potential on the shading pattern is the same as the potential of the gate, the shading pattern can be used as a part of the gate, thereby increasing the gate control area and improving the performance of the display panel.

[0052] The above embodiments are described by taking the connection between the shading pattern and the gate as an example, but the embodiments of the present application are not limited to this. For example, the shading pattern can be suspended, the shading pattern is not connected to other wirings, or the shading pattern is connected to the pixel electrode, or the shading pattern is connected to the doped part.

[0053] In some embodiments, Figure 3 As shown, the angle A between the top surface of the portion of the buffer layer 23 corresponding to the second via hole 233 and the side wall is in the range of 25 to 80 degrees. By making the angle between the top surface of the portion of the buffer layer corresponding to the second via hole and the side wall in the range of 25 to 80 degrees, the channel portion overlaps the side wall of the portion of the buffer layer corresponding to the second via hole, and the channel length of the display panel is larger, thereby reducing the gate width and improving the pixel density.

[0054] Specifically, the above-mentioned embodiment is described by taking the angle between the top surface and the side wall of the portion of the buffer layer corresponding to the second via hole as ranging from 25 degrees to 80 degrees, but the embodiments of the present application are not limited to this. It is sufficient to arrange the channel portion in the second via hole so as to increase the channel length and avoid the channel portion from breaking. For example, the angle between the top surface and the side wall of the portion of the buffer layer corresponding to the second via hole can also be 20 degrees.

[0055] In some embodiments, Figure 4As shown, the profiled portion 232 includes a protrusion 234, the channel portion 241 is disposed on the protrusion 234, and the channel portion 241 overlaps the side wall of the protrusion 234. By making the profiled portion include a protrusion, the channel portion is disposed on the protrusion, and the channel portion overlaps the side wall of the protrusion, the channel length of the display panel can be increased, and the width of the gate can be reduced accordingly, thereby improving the pixel density.

[0056] In some embodiments, Figure 5 As shown, the display panel 2 further includes a gate insulating layer 25, the gate insulating layer 25 is disposed between the active layer 24 and the gate 261, the gate insulating layer 25 is disposed on the top surface of the channel portion 241 and overlaps the side wall of the channel portion 241, and the gate 261 is disposed on the top surface of the gate insulating layer 25 and overlaps the side wall of the gate insulating layer 25. By making the gate insulating layer disposed on the top surface of the channel portion and overlaps the side wall of the channel portion, and the gate being disposed on the top surface of the gate insulating layer and overlaps the side wall of the gate insulating layer, the gate can be disposed opposite to the top surface of the channel portion and the side wall of the channel portion, thereby increasing the gate control area, and correspondingly reducing the width of the gate, thereby improving the pixel density.

[0057] In some embodiments, Figure 3 , Figure 4 As shown, the display panel 2 further includes a pixel electrode layer 29, the pixel electrode layer 29 includes a pixel electrode 291, and the pixel electrode 291 is directly connected to another doped portion 242. By directly connecting the pixel electrode to the doped portion, there is no need to set a source electrode, the number of mask plates is reduced, the number of vias is reduced, the process steps are reduced, and the yield of the display panel is improved.

[0058] Specifically, Figure 3 As shown, the display panel 2 further includes a first passivation layer 27 and a planarization layer 28 .

[0059] Specifically, the display panel may further include a second passivation layer and a common electrode layer, the second passivation layer is disposed between the planarization layer and the pixel electrode layer, and the common electrode layer is disposed between the planarization layer and the second passivation layer.

[0060] Specifically, the material of the first metal layer includes molybdenum, aluminum, copper, titanium, or alloys of the above materials, or stacks of the above materials, and the thickness of the first metal layer ranges from 1000 angstroms to 8000 angstroms.

[0061] Specifically, the material of the buffer layer includes silicon nitride, silicon oxide or a stack of the two, and the thickness of the buffer layer ranges from 6000 angstroms to 10000 angstroms.

[0062] Specifically, the material of the active layer includes indium gallium zinc oxide IGZO, the thickness of the active layer ranges from 400 to 1000 angstroms, and the active layer can be formed by physical vapor deposition and patterned by yellow light process and etching process. The material of the active layer can also be indium gallium zinc tin oxide IGZTO, indium gallium oxide IGO, indium zinc oxide IZO lanthanide IZO and other oxides.

[0063] Specifically, the material of the gate insulating layer includes silicon oxide, and the thickness of the gate insulating layer ranges from 1000 angstroms to 3000 angstroms.

[0064] Specifically, the material of the second metal layer includes a stack of molybdenum-titanium alloy / copper / molybdenum-titanium alloy, the thickness of the second metal layer ranges from 2000 angstroms to 8000 angstroms, the second metal layer can be patterned by a yellow light process, and then the gate insulating layer is etched to form a pattern by self-aligning the pattern of the second metal layer.

[0065] Specifically, the doping part is doped with nitrogen, and the ion doping concentration of the doping part is greater than the ion doping concentration of the channel part.

[0066] Specifically, the materials of the first passivation layer and the second passivation layer include silicon nitride or silicon oxide, and the thickness of the first passivation layer ranges from 1000 angstroms to 5000 angstroms.

[0067] Specifically, the material of the planarization layer includes polytetrafluoroethylene, and the thickness of the planarization layer ranges from 10000 angstroms to 30000 angstroms.

[0068] Specifically, the material of the pixel electrode layer and the common electrode layer includes indium tin oxide.

[0069] Specifically, the first metal layer may further include data lines, and the second metal layer may further include scan lines.

[0070] The above-mentioned embodiments have described the display panel in detail from the perspective of each film layer and its specific design. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the angle between the top surface and the side wall of the portion of the buffer layer corresponding to the second via hole ranges from 25 degrees to 80 degrees, and the display panel also includes a pixel electrode layer, the pixel electrode layer includes a pixel electrode, and the pixel electrode is directly connected to the doped portion.

[0071] At the same time, an embodiment of the present application provides a method for preparing a display panel, and the method for preparing a display panel prepares a display panel as described in any of the above embodiments.

[0072] In some embodiments, a method for preparing a display panel includes:

[0073] Provide a substrate; the structure of the display panel corresponding to this step is as follows Figure 5 As shown in (a);

[0074] A first metal layer and a buffer layer are sequentially formed on the substrate, and the buffer layer is etched to form a first via hole and a second via hole; the structure of the display panel corresponding to this step is as follows: Figure 5 As shown in (a);

[0075] An active layer, a gate insulating layer and a second metal layer are sequentially formed on the buffer layer; the structure of the display panel corresponding to this step is as follows Figure 5 As shown in (b);

[0076] A first passivation layer, a planarization layer and a pixel electrode layer are sequentially formed on the second metal layer. The structure of the display panel corresponding to this step is as follows: Figure 3 shown.

[0077] Specifically, when etching the buffer layer to form the first via hole and the second via hole, a semi-transparent process may be used to form the first via hole and the second via hole in one step, so that the first via hole and the second via hole have different depths.

[0078] In some embodiments, a method for preparing a display panel includes:

[0079] Provide a substrate; the structure of the display panel corresponding to this step is as follows Figure 6 As shown in (a);

[0080] A first metal layer and a buffer layer are sequentially formed on the substrate, and the buffer layer is etched to form a first via hole; the structure of the display panel corresponding to this step is as follows: Figure 6 As shown in (a);

[0081] The buffer layer is etched to form a second via hole; the structure of the display panel corresponding to this step is as follows Figure 6 As shown in (b);

[0082] An active layer, a gate insulating layer and a second metal layer are sequentially formed on the buffer layer; the structure of the display panel corresponding to this step is as follows Figure 6 As shown in (c);

[0083] A first passivation layer, a planarization layer and a pixel electrode layer are sequentially formed on the second metal layer. The structure of the display panel corresponding to this step is as follows: Figure 3 shown.

[0084] Specifically, when etching the buffer layer to form the first via hole and the second via hole, the first via hole and the second via hole can be formed in two steps, respectively, so that the first via hole and the second via hole have different depths.

[0085] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0086] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0087] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: substrate; A first metal layer, disposed on one side of the substrate, wherein the first metal layer includes a drain electrode; a buffer layer, disposed on a side of the first metal layer away from the substrate, the buffer layer comprising a first via hole; an active layer, arranged on a side of the buffer layer away from the first metal layer, the active layer comprising a channel portion and doped portions arranged on both sides of the channel portion, the doped portion passing through the first via hole and connected to the drain electrode; A second metal layer is disposed on a side of the active layer away from the buffer layer, and the second metal layer includes a gate; Wherein, the buffer layer further includes a shaped portion, the channel portion is arranged on a plane of the shaped portion and a side wall of the shaped portion, and the gate is arranged corresponding to the side wall of the channel portion and a top surface of the channel portion.

2. The display panel according to claim 1, wherein: The special-shaped portion includes a second via hole, the channel portion is arranged in the second via hole, and the channel portion overlaps the side wall and the bottom surface of the second via hole.

3. The display panel according to claim 2, wherein: The display panel also includes a gate insulating layer, which is arranged between the active layer and the gate, the channel portion includes a first channel portion overlapping the side wall of the second via hole and a second channel portion overlapping the bottom surface of the second via hole, the gate insulating layer includes a first insulating portion overlapping the first channel portion and a second insulating portion overlapping the second channel portion, the gate overlaps the first insulating portion and contacts the second insulating portion, and the gate is arranged corresponding to the first channel portion and the second channel portion.

4. The display panel according to claim 2, wherein: The first metal layer further includes a light shielding pattern, the light shielding pattern is arranged corresponding to the channel portion, and there is a distance between a top surface of the light shielding pattern and the second via hole.

5. The display panel according to claim 4, wherein: The distance between the light shielding pattern and the top surface of the portion of the buffer layer corresponding to the second via hole is one fifth to four fifths of the thickness of the buffer layer.

6. The display panel according to claim 2, wherein: The angle between the top surface and the side wall of the portion of the buffer layer corresponding to the second via hole ranges from 25 degrees to 80 degrees.

7. The display panel according to claim 1, wherein: The special-shaped portion includes a protrusion, the channel portion is arranged on the protrusion, and the channel portion overlaps the side wall of the protrusion.

8. The display panel according to claim 7, wherein: The display panel also includes a gate insulating layer, which is arranged between the active layer and the gate, the gate insulating layer is arranged on the top surface of the channel portion and overlaps the side wall of the channel portion, and the gate is arranged on the top surface of the gate insulating layer and overlaps the side wall of the gate insulating layer.

9. The display panel according to claim 1, wherein: The display panel further includes a pixel electrode layer, wherein the pixel electrode layer includes a pixel electrode, and the pixel electrode is directly connected to another of the doped parts.

10. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 9.

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