Semiconductor element arrangement structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor element arrangement structure and a manufacturing method thereof. The semiconductor element arrangement structure comprises a carrier, a first semiconductor element, a second semiconductor element, a first adhesive part and a second adhesive part. The first semiconductor element and the second semiconductor element are located on the carrier separately from each other. The first adhesive portion and the second adhesive portion are separately located on the carrier, the first adhesive portion is located between the first semiconductor element and the carrier, and the second adhesive portion is located between the second semiconductor element and the carrier. In a cross-sectional view, the first adhesive portion includes a beveled edge, and the beveled edge and the carrier are adjacent to each other and form an interior angle greater than 90 degrees.

Description

Technical Field

[0001] The present invention relates to a semiconductor element arrangement structure, and in particular to a semiconductor element arrangement structure in which semiconductor elements are adhered to a carrier board and a manufacturing method thereof. Background Art

[0002] Semiconductor components such as light-emitting diodes (LEDs) have the advantages of low power consumption, low heat generation, long service life, shock resistance, small size, fast response speed, and good photoelectric properties (such as stable light emission wavelength). Therefore, they are widely used in electronic devices such as household appliances, equipment indicator lights, and displays.

[0003] In order to manufacture different electronic devices, a large number of light-emitting diodes need to be transferred between different substrates. The steps usually include transferring multiple light-emitting diodes from the growth substrate to a temporary substrate, and fixing the multiple light-emitting diodes on it through an adhesive layer on the temporary substrate. After that, an etching process is used to remove the adhesive layer between adjacent light-emitting diodes.

[0004] However, in order to completely remove the adhesive layer between adjacent LEDs during the etching process, the etching process often takes a long time, and the heat generated by the etching process may also cause some LEDs to be skewed in the vertical direction or offset in the horizontal direction. This not only makes the manufacturing process time-consuming, but also is not conducive to the subsequent processing process. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a semiconductor device arrangement structure and a manufacturing method thereof to overcome the technical problems encountered in the prior art.

[0006] According to one embodiment of the present invention, a semiconductor element arrangement structure is provided, comprising a carrier, a first semiconductor element, a second semiconductor element, a first adhesive portion, and a second adhesive portion. The first semiconductor element and the second semiconductor element are separately located on the carrier. The first adhesive portion and the second adhesive portion are separately located on the carrier, and the first adhesive portion is located between the first semiconductor element and the carrier, and the second adhesive portion is located between the second semiconductor element and the carrier. In a cross-sectional view, the first adhesive portion comprises a hypotenuse, and the hypotenuse and the carrier are adjacent to each other and form an internal angle greater than 90 degrees.

[0007] According to one embodiment of the present invention, a method for manufacturing a semiconductor element arrangement structure is provided, comprising: providing a first supporting substrate, a first semiconductor element, and a second semiconductor element, wherein the first semiconductor element and the second semiconductor element are located on the first supporting substrate and are separated from each other; providing a patternable adhesive layer to cover the first semiconductor element, the second semiconductor element, and the space between the first semiconductor element and the second semiconductor element; removing the patternable adhesive layer located in the space by a photolithography process to form a first adhesive portion and a second adhesive portion; and providing a second supporting substrate, and making the first adhesive portion and the second adhesive portion contact the second supporting substrate. The first adhesive portion is located between the first semiconductor element and the second supporting substrate, and the second adhesive portion is located between the second semiconductor element and the second supporting substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to when reading the present invention. The specific embodiments of the present invention are explained in detail through the specific embodiments in this article and with reference to the corresponding drawings, and the working principles of the specific embodiments of the present invention are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the sizes of some features in some drawings may be deliberately enlarged or reduced.

[0009] Figure 1 is a schematic diagram of a top view and an enlarged partial area of ​​a semiconductor element arrangement structure according to an embodiment of the present invention;

[0010] Figure 2 An embodiment of the present invention is along the Figure 1 The cross-sectional schematic diagrams shown by the section lines AA' and BB';

[0011] Figure 3 An embodiment of the present invention Figure 2 Enlarged schematic diagrams of local areas of two cross-sectional schematic diagrams;

[0012] Figure 4 An embodiment of the present invention Figure 2 An enlarged schematic diagram of a local area of ​​the sectional schematic diagram along the sectional line AA';

[0013] Figure 5 A variant embodiment of the present invention is along the Figure 1 A cross-sectional view and an enlarged schematic diagram of a local area shown by the section line AA';

[0014] Figure 6 is a schematic top view of a semiconductor element arrangement structure according to some embodiments of the present invention;

[0015] Figure 7It is a schematic diagram of a top view and an enlarged cross-sectional view of a local area in which a plurality of semiconductor elements are arranged on a first supporting substrate at a certain manufacturing process stage according to an embodiment of the present invention;

[0016] Figure 8 is a cross-sectional schematic diagram of different manufacturing process stages of forming an adhesive portion on a semiconductor element according to an embodiment of the present invention;

[0017] Fig. 9 is a cross-sectional schematic diagram of different stages of a manufacturing process for transferring a plurality of semiconductor elements from a supporting substrate to a carrier according to an embodiment of the present invention;

[0018] Fig.10 Schematic cross-sectional views of different stages of a fabrication process for transferring a selected semiconductor element from a carrier to a supporting substrate according to an embodiment of the present invention.

[0019] Explanation of symbols

[0020] 100…Carrier

[0021] 102…front

[0022] 104…Back

[0023] 110…Semiconductor components

[0024] 110-1 ... first semiconductor element

[0025] 110-2 ... second semiconductor element

[0026] 110-3…third semiconductor element

[0027] 110a…front

[0028] 110b…Back

[0029] 114a…first outermost edge

[0030] 114b…second outermost edge

[0031] 120…Component body

[0032] 122…Electrode

[0033] 124…Substrate

[0034] 126…Semiconductor stack

[0035] 128…Depression area

[0036] 130a, 130b… bottom angle

[0037] 150··Space

[0038] 200…Adhesive part

[0039] 200-1…First adhesive part

[0040] 200-2…Second adhesive part

[0041] 200-3…Third adhesive part

[0042] 202…bottom

[0043] 204a, 204b… bottom corner

[0044] 206a, 206b…hypotenuses

[0045] 208a, 208b ... protrusion

[0046] 210a, 210b…vertex

[0047] 300…Gap

[0048] 300-1…First gap

[0049] 300-2…Second gap

[0050] 400…first supporting substrate

[0051] 402… Positive

[0052] 404…Back

[0053] 500…Patternable adhesive layer

[0054] 502…front

[0055] 512…front

[0056] 514…Back

[0057] 614…Adhesive layer

[0058] 700…third supporting substrate

[0059] 702…front

[0060] 704…Back

[0061] 712…Carrier

[0062] 714…Adhesion layer

[0063] 1000…Semiconductor element arrangement structure

[0064] A10…First projection area

[0065] A20…Second projection area

[0066] A22…Third projection area

[0067] A24…Fourth projection area

[0068] D11, D21…First distance

[0069] D12, D22…The second distance

[0070] L1, L2, L3…shortest distance

[0071] R1, R3, R4, R5, R6…local area

[0072] S100, S102, S104, S106, S108, S110, S112…steps

[0073] θ1, θ2…internal angle DETAILED DESCRIPTION

[0074] The present invention provides several different embodiments that can be used to implement different features of the present invention. For the sake of simplicity of description, the present invention also describes examples of specific components and arrangements. The purpose of providing these embodiments is only to illustrate, not to limit in any way. Various embodiments in the present invention may use repeated reference symbols and / or text notes. The use of these repeated reference symbols and notes is to make the description more concise and clear, rather than to indicate the relevance between different embodiments and / or configurations.

[0075] In addition, for the spatially related descriptive words mentioned in the present invention, such as "under", "low", "down", "above", "on", "top", "bottom" and similar words, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the swing direction shown in the drawings, these spatially related words are also used to describe the orientation of each element during use and operation. As the orientation of each element is different (rotated 90 degrees or other orientations), the related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0076] Although the present invention uses the terms first, second, third, etc. to describe elements, components, regions, layers, and / or blocks (Section), it should be understood that these elements, components, regions, layers, and / or blocks should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and / or block from another element, component, region, layer, and / or block, and they themselves do not imply or represent any previous ordinal number of the element, nor do they represent the order of arrangement of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or block discussed below can also be referred to as the second element, component, region, layer, or block.

[0077] The terms "about" or "substantially" mentioned in the present invention generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0078] The terms "coupling", "coupling", and "electrical connection" mentioned in the present invention include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0079] Although the invention of the present invention is described below by specific embodiments, the inventive principle of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and these omitted details belong to the knowledge scope of ordinary technicians in the relevant technical field.

[0080] Figure 1 FIG. 1 is a schematic diagram of a semiconductor device arrangement structure in a top view and an enlarged view of a local area according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device arrangement structure 1000 includes a carrier 100, a plurality of semiconductor devices 110, and a plurality of adhesive portions 200. The plurality of semiconductor devices 110 may present a specific arrangement structure and be separated from each other on the carrier 100. Each adhesive portion 200 is separated from each other and is disposed between the corresponding semiconductor device 110 and the carrier 100.

[0081] like Figure 1As shown in the left top view of the carrier 100, the semiconductor element 110 and the adhesive portion (not shown) are disposed on the front side 102 of the carrier 100. According to one embodiment of the present invention, the carrier 100 is used to support the semiconductor element 110 disposed on the front side 102 thereof, so the carrier 100 may also be referred to as a supporting substrate. According to one embodiment of the present invention, the carrier 100 may be a non-epitaxial material or a non-growth substrate, for example, a ceramic substrate, a metal substrate, a glass substrate, a thermal release tape, a UV release tape, a chemical release tape, a heat-resistant tape, a blue tape, or a tape with a dynamic release layer (DRL). According to one embodiment of the present invention, the carrier 100 may be a glass substrate, a sapphire substrate, or a quartz substrate. The carrier 100 is a substrate that allows laser penetration, so that the semiconductor element 110 can be separated from the carrier 100 by a laser lift-off (LLO) manufacturing process. According to one embodiment, when performing the laser lift-off process, the laser may be incident from the back side of the carrier 100 into the carrier 100, and penetrate from the front side 102 of the carrier 100, and irradiate the adhesive portion disposed on the front side 102, so that the adhesive portion is partially or entirely decomposed or vaporized, and is lifted off from the carrier 100. In addition, the carrier 100 is electrically insulated from the semiconductor element 110, so that electrical signals are not transmitted between the carrier 100 and the semiconductor element 110.

[0082] The semiconductor element 110 may include a transistor element or a semiconductor light-emitting element, such as a light-emitting diode element, but is not limited thereto. Adjacent semiconductor elements 110 are separated from each other, and for adjacent semiconductor elements 110 in the same column or row, the shortest distance between adjacent semiconductor elements 110 is 1 μm to 50 μm. According to one embodiment, the shortest distance between adjacent semiconductor elements 110 is less than the diagonal length of each semiconductor element 110 in a top view, for example, the distance between adjacent semiconductor elements 110 is 1 / 20 to 1 / 5 of the diagonal length of each semiconductor element 110, but is not limited thereto. A plurality of semiconductor elements 110 form a specific arrangement layout, for example, arranged in an array structure on a carrier 100, but is not limited thereto. According to one embodiment, a plurality of semiconductor elements 110 form a plurality of ring structures and are concentric with each other.

[0083] against Figure 1 The local area R1 of the left top view is shown in the enlarged schematic diagram as Figure 1 As shown in the top view on the right side of Figure 1As shown in the top view on the right side of the embodiment, in the local area R1, the semiconductor elements 110 form an array of 3 rows and 3 columns, and there are gaps 300 between adjacent rows and adjacent columns of the semiconductor elements 110, such as first gaps 300-1 and second gaps 300-2. According to one embodiment, each first gap 300-1 extends along a first direction (e.g., Y direction) so that adjacent rows of the semiconductor elements 110 are separated by the first gaps 300-1. Each second gap 300-2 extends along a second direction (e.g., X direction) different from the first direction, so that adjacent columns of the semiconductor elements 110 are separated by the second gaps 300-2. In addition, in the top view, the first gap 300-1 and the second gap 300-2 are located between adjacent adhesive portions 200 to expose the front side 102 of the carrier 100.

[0084] The semiconductor element 110 includes a first semiconductor element 110-1, a second semiconductor element 110-2, a third semiconductor element 110-3, ... and an m-th semiconductor element, where m is a positive integer greater than 3. The first semiconductor element 110-1 and the second semiconductor element 110-2 are located in the same column and are arranged along the X direction, and the first semiconductor element 110-1 and the third semiconductor element 110-3 are located in the same row and are arranged along the Y direction. According to one embodiment, each semiconductor element 110 (e.g., the first semiconductor element 110-1, the second semiconductor element 110-2, and the third semiconductor element 110-3) includes a plurality of outermost edges, such as parallel first outermost edges 114a and parallel second outermost edges 114b, and the first outermost edges 114a and the second outermost edges 114b are adjacent. According to one embodiment, each semiconductor element 110 has a projected area in the Z direction, and the projected area is 50 μm 2 Up to 5000μm 2 .

[0085] Still Figure 1 As shown in the top view on the right side of the figure, adjacent adhesive portions 200 are separated from each other and are used to fix the corresponding semiconductor element 110 to the carrier 100. According to one embodiment, from the top view, each adhesive portion 200 is completely covered (or completely overlapped) by the corresponding semiconductor element 110, so the top outermost edge of the adhesive portion 200 does not exceed the outermost edge (e.g., the first outermost edge 114a and the second outermost edge 114b) of the semiconductor element 110. According to one embodiment, each adhesive portion 200 has a projected area in the Z direction, for example, 40 μm 2 Up to 4000μm 2, which projection area is smaller than the projection area of ​​the corresponding semiconductor element 110 in the Z direction. According to one embodiment, the adhesive portion 200 includes a patterned photoresist layer, and its top view profile and bottom surface area can be defined by a photolithography process. Therefore, the distance between the top view outermost edge of the adhesive portion 200 and the outermost edge of the semiconductor element 110 can be adjusted according to different needs.

[0086] A plurality of adhesive portions 200 form a specific arrangement layout, and the arrangement layout thereof corresponds to the arrangement layout formed by a plurality of semiconductor elements 110. According to one embodiment, a plurality of adhesive portions 200 may form an array structure or a ring structure, but is not limited thereto. The adhesive portion 200 includes a first adhesive portion 200-1, a second adhesive portion 200-2, a third adhesive portion 200-3... and an mth adhesive portion, where m is a positive integer greater than 3. The first adhesive portion 200-1 and the second adhesive portion 200-2 are located in the same column and are arranged along the X direction, and the first adhesive portion 200-1 and the third adhesive portion 200-3 are located in the same row and are arranged along the Y direction.

[0087] The adhesive portion 200 may be a polymer. According to different embodiments, the adhesive portion 200 may include polyimide (PI), epoxy resin (EPO), polybenzoxazole (PBO), silicone resin (Polysiloxane), polycycloolefin (COP), or benzocyclobutane (BCB), but is not limited thereto.

[0088] Figure 2 An embodiment of the present invention is along the Figure 1Schematic cross-sectional view shown by section line AA' and section line BB'. With respect to the cross-sectional area AA', the carrier 100 has a front side 102 and a back side 104 opposite to each other. The first gap portion 300-1 is located between the first semiconductor element 110-1 and the second semiconductor element 110-2, and exposes the front side 102 of the carrier 100. The first outermost edges 114a of the first semiconductor element 110-1 and the second semiconductor element 110-2 face each other, and the shortest distance L1 between the opposite first outermost edges 114a is 1 μm to 50 μm. According to one embodiment, the first semiconductor element 110-1 and the second semiconductor element 110-2 have the same or similar structure. Each semiconductor element 110 includes an element body 120 and at least one electrode 122, such as a pair of electrodes 122. The element body 120 includes a semiconductor layer (not shown) through which electrons or holes can flow. The electrode 122 faces the front side 102 of the carrier 100, so the electrode 122 and the adhesive portion 200 are located on the same side of the device body 120, and the electrode 122 and the carrier 100 are separated by the adhesive portion 200. The electrode 122 may include a single-layer or multi-layer metal structure, and the electrode 122 includes at least one material selected from the group consisting of chromium (Cr), nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), silver (Ag), gold (Au), aluminum (Al), and copper (Cu).

[0089] The structure of each semiconductor element 110 is not limited to Figure 2 According to the structure shown in one embodiment, each semiconductor element 110 includes a redistribution layer (RDL) (not shown), which is disposed on the bottom surface of the element body 120. The redistribution layer includes conductive interconnects, vias, and conductive pads. The conductive pads may have a specific layout pattern, and in the subsequent manufacturing process, the conductive pads may be electrically connected to the external circuit. In addition, according to one embodiment, each semiconductor element 110 may include a fan-out package structure, so that the element body 120 includes at least one semiconductor chip and a molding material surrounding the chip, but is not limited thereto.

[0090] The adhesive portion 200 is located between the semiconductor element 110 and the carrier 100, for example, the first adhesive portion 200-1 is located between the first semiconductor element 110-1 and the carrier 100, and the second adhesive portion 200-2 is located between the second semiconductor element 110-2 and the carrier 100. According to one embodiment, the maximum thickness T1 of the adhesive portion 200 is 2 μm to 7 μm. When the thickness T1 of the adhesive portion 200 is less than 2 μm, the adhesion between the semiconductor element 110 and the carrier 100 may be insufficient, and when the thickness T1 of the adhesive portion 200 is greater than 7 μm, the cross-sectional profile of the adhesive portion 200 may deviate from the predetermined profile (especially for the adhesive portion 200 obtained by the photolithography process).

[0091] against Figure 2 In the cross-sectional area BB' of the carrier 100, the second gap portion 300-2 is located between the first semiconductor element 110-1 and the third semiconductor element 110-3, and exposes the front side 102 of the carrier 100. The second outermost edges 114b of the first semiconductor element 110-1 and the third semiconductor element 110-3 face each other, and the shortest distance L2 between the opposite second outermost edges 114b is 1μm to 50μm. According to one embodiment, the first semiconductor element 110-1 and the third semiconductor element 110-3 have the same or similar structure. Each semiconductor element 110 includes an element body 120 and at least one electrode 122. According to one embodiment, the electrode 122 faces the front side 102 of the carrier 100, so the electrode 122 and the adhesive portion 200 are located on the same surface of the element body 120, and the electrode 122 is separated from the carrier 100 by the adhesive portion 200.

[0092] Figure 3 An embodiment of the present invention Figure 2 A magnified schematic diagram of a local area, where Figure 3 The local area R3 of the left side cross-sectional view corresponds to Figure 2 The local area R3, Figure 3 The local area R4 of the right side cross-sectional view corresponds to Figure 2 The local area R4. Figure 3 As shown in the left side cross-sectional view of , according to one embodiment, the first semiconductor element 110-1 and the remaining semiconductor elements 110 are semiconductor light-emitting elements, and the element body 120 of the first semiconductor element 110-1 includes a substrate 124 and a semiconductor stack 126. The semiconductor stack 126 is disposed between the electrode 122 and the substrate 124, and is electrically connected to the electrode 122. According to one embodiment, the semiconductor stack 126 includes a first semiconductor layer (not shown), a light-emitting layer (not shown), and a second semiconductor layer (not shown), wherein the first semiconductor layer and the second semiconductor layer respectively include dopants of different conductive types, such as n-type dopants and p-type dopants, so that the first semiconductor layer and the second semiconductor layer can supply electrons and holes respectively.

[0093] According to one embodiment, the substrate 124 includes a plurality of recessed areas 128 away from the carrier 100. The opening diameter of each recessed area 128 is 1 μm to 4 μm, and the depth is 300 nm to 2 μm. The recessed areas 128 have a repeated shape and are distributed on the main surface of the substrate 124 (distributed along the XY plane). By providing the recessed areas 128, the luminous efficiency of the semiconductor element 110 (e.g., the first semiconductor element 110-1) can be increased or the profile of the light distribution curve can be adjusted.

[0094] According to one embodiment, the first adhesive portion 200-1 includes a hypotenuse 206a. The hypotenuse 206a and the carrier 100 are adjacent to each other, and form an internal angle (Internal Angle) θ1 greater than 90 degrees with the front surface 102. The slope of each point on the hypotenuse 206a can be approximately constant, or gradually increase along the direction away from the carrier 100 (Z direction). According to one embodiment, the first adhesive portion 200-1 further includes a bottom surface 202 contacting the carrier 100, and the bottom surface 202 is fixed to the front surface 102 of the carrier 100.

[0095] According to one embodiment, in the cross-sectional view, the first adhesive portion 200-1 further includes a bottom angle 204a, a protrusion 208a and a top angle 210a, and the protrusion 208a is located between the top angle 210a and the inner angle θ1 (or the bottom angle 204a). Since the side profile of the first adhesive portion 200-1 is not a vertical profile, the distances between the bottom angle 204a, the protrusion 208a and the top angle 210a and the bottom angle 130a of the first outermost side 114a are different from each other. For example, there is a first distance D11 between the top angle 210a of the first adhesive portion 200-1 and the bottom angle 130a of the first outermost side 114a, and there is a second distance D12 between the bottom angle 204a of the adhesive portion 200 and the bottom angle 130a of the first outermost side 114a, and the first distance D11 is less than the second distance D12.

[0096] like Figure 3 As shown in the right side cross-sectional view of , according to one embodiment, the substrate 124 includes a plurality of recessed areas 128 away from the carrier 100. The recessed areas 128 have a repeated shape and are distributed on the main surface of the substrate 124 (distributed along the XY plane). According to one embodiment, the crystal plane of the second outermost edge 114b is different from the crystal plane of the first outermost edge 114a, so the two have different slopes. According to one embodiment, the second outermost edge 114b is a vertical plane, and its slope is greater than the slope of the first outermost edge 114a.

[0097] According to one embodiment, the first adhesive portion 200-1 includes a bevel 206b. The bevel 206b is adjacent to the carrier 100 and forms an internal angle θ2 greater than 90 degrees with the front surface 102. The slope of each point on the bevel 206b may be approximately constant, or gradually increase along the direction away from the carrier 100 (Z direction).

[0098] According to one embodiment, in the cross-sectional view, the first adhesive portion 200-1 further includes a bottom angle 204b, a protrusion 208b and a top angle 210b, and the protrusion 208b is located between the top angle 210b and the inner angle θ2 (or the bottom angle 204b). Since the side profile of the adhesive portion 200 is not a vertical profile, the distances between the bottom angle 204b, the protrusion 208b and the top angle 210b and the bottom angle 130b of the second outermost side 114b are different from each other. For example, there is a first distance D21 between the top angle 210b of the first adhesive portion 200-1 and the bottom angle 130b of the second outermost side 114b, and there is a second distance D22 between the bottom angle 204b of the first adhesive portion 200-1 and the bottom angle 130b of the first outermost side 114b, and the first distance D21 is less than the second distance D22.

[0099] According to different requirements, the angle of the inner angle θ1 may be different from the angle of the inner angle θ2, and the first distance D11 and the second distance D12 may be different from the first distance D21 and the second distance D22, respectively.

[0100] Figure 4 An embodiment of the present invention Figure 2 A magnified schematic diagram of a local area, corresponding to Figure 2 The local area R5. Figure 4 As shown, in the cross-sectional view, the bottom corner 204a, the protrusion 208a and the top corner 210a of each adhesive portion 200 (for example, the first adhesive portion 200-1) are arranged opposite to each other. The bottom surface of the first semiconductor element 110-1 has a first projection area A10, the bottom surface 202 of the first adhesive portion 200-1 has a second projection area A20, the transverse cross section of the protrusion 208a of the first adhesive portion 200-1 has a third projection area A22, and the transverse cross section of the top corner 210a of the first adhesive portion 200-1 has a fourth projection area A24. According to one embodiment, in the bottom view, the second projection area A20 of the bottom surface 202 of the first adhesive portion 200-1 is smaller than the first projection area A10 of the first semiconductor element 110-1. According to one embodiment, the projection areas are, from small to large, the second projection area A20 of the first adhesive portion 200-1, the fourth projection area A24 of the first adhesive portion 200-1, the third projection area A22 of the first adhesive portion 200-1, and the first projection area A10 of the first semiconductor element 110-1, but are not limited thereto.

[0101] Also refer to Figure 3 and Figure 4 According to one embodiment, at least one of the internal angle θ1 and the internal angle θ2 of the adhesive portion 200 is greater than 90 degrees, so that the contact area between the bottom surface 202 of the adhesive portion 200 and the carrier 100 (front surface 102) is reduced. Since the contact area between the bottom surface 202 of the adhesive portion 200 and the carrier 100 (i.e., the second projection area A20) is smaller than the first projection area A10 of the semiconductor element 110, and the top-view contour of the bottom surface 202 of the adhesive portion 200 can be pre-patterned and adjusted through a photolithography process in accordance with the spot shape of the laser light, it is easy to completely peel the bottom surface 202 of the adhesive portion 200 from the carrier 100 when the laser lift-off process is subsequently performed. In addition, if Figure 3 As shown, compared with the top corners 210a, 210b and the bottom corners 204a, 204b, the protrusions 208a, 208b are respectively closer to the outermost edges (e.g., the first outermost edge 114a and the second outermost edge 114b) of the semiconductor element 110, so that the laser irradiated from the back side 104 of the carrier 100 to the semiconductor element 110 can be partially or completely absorbed by the protrusions 208a, 208b, thereby preventing the laser from directly irradiating the semiconductor element 110, thereby preventing the semiconductor element 110 from being damaged by the laser.

[0102] Figure 5 A variant embodiment of the present invention is along the Figure 1 The cross-sectional view shown by the section line A-A'. Figure 5 As shown in the left sectional view, it is similar to Figure 2 The main difference between the two is that the electrodes 122 of the first semiconductor element 110-1 and the second semiconductor element 110-2 are away from the carrier 100 instead of facing the carrier 100, the first adhesive portion 200-1 is located between the first semiconductor element 110-1 and the carrier 100, and the second adhesive portion 200-2 is located between the second semiconductor element 110-2 and the carrier 100.

[0103] against Figure 5 The partial area R6 of the left side cross-sectional view is shown in the enlarged schematic diagram as follows: Figure 5 As shown in the right side cross-sectional view. Figure 5 As shown in the cross-sectional view on the right, it is similar to Figure 3 The main difference between the two is that the recessed area 128 of the substrate 124 of the first semiconductor element 110-1 faces the carrier 100, rather than away from the carrier 100. The first adhesive portion 200-1 fills or fills each recessed area 128, so the adhesion between the first semiconductor element 110-1 and the carrier 100 can be increased without changing the material or overall thickness of the first adhesive portion 200-1.

[0104] Figure 6Schematic diagram of a top view of a semiconductor element arrangement structure in some embodiments of the present invention. Figure 6 As shown, Figure 6 The left and right top views of Figure 1 The main difference is that the top view profile of the semiconductor element 110 located on the front side 102 of the carrier 100 is not a rectangle, but a triangle or a hexagon, respectively, but not limited to this. Depending on actual needs, the top view profile of the semiconductor element 110 can present any polygon or other geometric shape. The adhesive portion 200 and the semiconductor element 110 completely overlap, and the outermost edge of the adhesive portion 200 is separated from the outermost edge of the semiconductor element 110, but not limited to this. According to one embodiment, the outermost edge of the adhesive portion 200 is flush with the outermost edge of the semiconductor element 110.

[0105] In order to enable those skilled in the art to implement the invention, the method for manufacturing the semiconductor element arrangement structure of the invention is further described in detail below.

[0106] Figure 7 FIG. 1 is a top view schematic diagram of a first supporting substrate provided with a plurality of semiconductor elements at a certain manufacturing process stage according to an embodiment of the present invention. Figure 7 As shown, in step S100, a first support substrate 400 and a plurality of semiconductor elements 110 are provided, and the semiconductor elements 110 are arranged on the front side 402 of the first support substrate 400. According to one embodiment of the present invention, the first support substrate 400 is a growth substrate, and the semiconductor elements 110 are grown on the growth substrate. The growth substrate includes epitaxial material, such as silicon (Si), germanium (Ge), lithium aluminate (LiAlO2), zinc oxide (ZnO), silicon carbide (SiC), sapphire (Sapphire), gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium phosphide (InP), but not limited thereto.

[0107] Figure 7 On the right Figure 7The enlarged cross-sectional view of area C-C' in the left top view schematic diagram shows that adjacent semiconductor elements 110 are separated from each other, and there is a space 150 between them. According to one embodiment, the shortest distance L3 between adjacent semiconductor elements 110 (including the first semiconductor element 110-1 and the second semiconductor element 110-2) is 1μm to 50μm, and the shortest distance L3 is less than the diagonal length of each semiconductor element 110 in the top view. For example, the shortest distance between adjacent semiconductor elements 110 is 1 / 20 to 1 / 5 of the diagonal length of each semiconductor element 110, but is not limited to this. A plurality of semiconductor elements 110 form a specific arrangement layout, for example, they are arranged in an array structure on the first supporting substrate 400, but are not limited to this. According to one embodiment, a plurality of semiconductor elements 110 form a plurality of ring structures and are concentric with each other.

[0108] Figure 8 The present invention Figure 7 The cross-sectional schematic diagram of different manufacturing process stages of forming an adhesive portion on a semiconductor element is shown as an example of the area CC' in the left top view schematic diagram. In step S102, a patternable adhesive layer 500 is provided to cover the semiconductor element 110 (including the first semiconductor element 110-1 and the second semiconductor element 110-2) and to cover the space 150 between the first semiconductor element 110-1 and the second semiconductor element 110-2. According to one embodiment, the semiconductor element 110 has a front side 110a and a back side 110b opposite to each other, and the front side 502 of the patternable adhesive layer 500 is higher than the front side 110a of the semiconductor element 110, so that the patternable adhesive layer 500 completely covers the front side 110a of the semiconductor element 110 and fills the space 150 between the semiconductor elements 110.

[0109] According to one embodiment, the patternable adhesive layer 500 can be made by, for example, spin coating, with a predetermined rotation speed (e.g., 1000 rpm to 4000 rpm) and rotation speed stage (e.g., 1 stage fixed rotation speed to 3 stages of different rotation speeds) to coat the patternable adhesive material on the front surface 402 of the first support substrate 400, so that it covers the semiconductor element 110 and fills the space 150 so that all the front surfaces 402 of the first support substrate 400 are not exposed. By adjusting the rotation speed and the rotation speed stage, the thickness of the patternable adhesive material can be controlled. Afterwards, soft baking is performed to remove part of the solvent in the patternable adhesive material to form a non-flowable patternable adhesive layer 500. According to one embodiment, the patternable adhesive layer 500 is an adhesive photoresist material, and its composition can include a photosensitive substance (e.g., a functional group or a monomer), an adhesive substance (e.g., a functional group or a monomer), and a polymer matrix. The components of the photosensitive material include, for example, naphthoquinone diazide, sulfonate of naphthoquinone diazide, or other derivatives, but are not limited thereto. The components of the adhesive material include, for example, epoxy resin or other crosslinking agents. The polymer matrix includes, for example, un-cured polymers, such as cycloolefin polymer (COP), polyimide (PI), epoxy resin (EPO), polybenzoxazole (PBO), silicone resin (Polysiloxane), cycloolefin (COP), or benzocyclobutane (BCB), but are not limited thereto. Since the patternable adhesive layer 500 contains not only photosensitive functional groups or monomers but also adhesive functional groups or monomers, even if the patternable adhesive layer 500 is subsequently subjected to a photolithography process, the patterned adhesive layer still has appropriate viscosity (which can be used as the adhesive portion 200), or an additional activation process can be performed to make the adhesive material in the patterned adhesive layer have appropriate viscosity, so that the patterned adhesive layer can be used to fix other components. Therefore, in the subsequent lamination process, the patterned photoresist layer with appropriate viscosity can be fixed to the components pressed thereon.

[0110] After completing step S102, step S104 is then performed to remove the patternable adhesive layer 500 located in the space 105, thereby exposing a portion of the front surface 402 of the first supporting substrate 400, and forming a patterned adhesive layer on the semiconductor element 110, such as a plurality of adhesive portions 200 (including a first adhesive portion 200-1 and a second adhesive portion 200-2). According to one embodiment, a photolithography process is used to remove the patternable adhesive layer 500 in the space 105, and the patternable adhesive layer 500 is patterned to produce a specific cross-sectional profile and a top-view profile. For example, the patternable adhesive layer 500 includes a positive photoresist, so the area of ​​the patternable adhesive layer 500 irradiated by light will be removed. In addition, due to the development characteristics of the positive photoresist, the top-view area of ​​the front surface 512 of each adhesive portion 200 will be smaller than the top-view area of ​​the back surface 514 of each adhesive portion 200.

[0111] According to one embodiment, each semiconductor element 110 includes a plurality of outermost edges, such as a first outermost edge 114a. After the patternable adhesive layer 500 in the space 105 is removed to obtain the adhesive portion 200, more than 50% of the area of ​​the outermost edge of the semiconductor element 110 will not be covered by the adhesive portion 200. In this embodiment, as shown in the figure, the outermost edge 114a of the semiconductor element 110 is not covered by the adhesive portion 200 at all. In addition, in step S104, the front side 512 of each adhesive portion 200 is higher than the front side 110a of each semiconductor element 110. Since the top view profile of the adhesive portion 200 can be determined by the photomask pattern used in the photolithography process, it is possible to avoid the adhesive portion 200 covering the outermost edge of the semiconductor element 110 and avoid the adhesive portion 200 existing between adjacent semiconductor elements 110. Therefore, it is not necessary to perform an etching process to remove the adhesive portion between adjacent semiconductor elements 110. Since the etching process is eliminated, the semiconductor element 110 may be effectively prevented from being skewed or deflected due to the heat energy of the etching process.

[0112] In step S104, an activation process may be further performed to activate the adhesive material remaining in the adhesive portion 200, so that the adhesive material generates more active free radicals in the subsequent bonding and pressing process, thereby increasing the strength of the adhesive portion 200 and the target component during bonding and pressing. In addition, in the activation process, the adhesive portion 200 still does not produce a cross-linking reaction. According to one embodiment, the activation process includes performing a heat treatment in a gas environment. The gas environment is mainly composed of nitrogen, and the oxygen concentration is low (e.g., less than 1000ppm).

[0113] Fig. 9 The present invention is Figure 7The area C-C' in the left top view is a cross-sectional view of different stages of the manufacturing process of transferring multiple semiconductor elements from the first support substrate to the carrier. In step S106, the semiconductor element 110 on the first support substrate 400 faces the carrier 100 (or the second support substrate). According to one embodiment, the carrier 100 has a front side 102 and a back side 104 opposite to each other, and the front side 110a of the semiconductor element 110 faces the front side 102 of the carrier 100.

[0114] In step S106, at least one of the first supporting substrate 400 and the carrier 100 is moved so that the carrier 100 contacts the adhesive portion 200 (including the first adhesive portion 200-1 and the second adhesive portion 200-2), for example, contacts the front surface 512 of the adhesive portion 200, and the adhesive portion 200 is fixed to the carrier 100. At this time, the first adhesive portion 200-1 is located between the first semiconductor element 110-1 and the carrier 100 (or referred to as the second supporting substrate), and the second adhesive portion 200-2 is located between the second semiconductor element 110-2 and the carrier 100. According to one embodiment, in order to fix the adhesive portion 200 to the carrier 100, a pressing process may be performed first to contact the carrier 100 with the adhesive portion 200. Then, a hard baking process is performed to cause a cross-linking reaction between the cross-linking agent in the adhesive portion 200 and the uncross-linked polymer. According to one embodiment, the process temperature of the heat treatment for generating the cross-linking reaction is higher than the process temperature of the activation process for activating the adhesive material, for example, the former is 200° C. and the latter is 100° C.

[0115] In step S108, a separation process is performed to separate the first support substrate 400 and the carrier 100, and the semiconductor element 110 is separated from the first support substrate 400 to expose the back side 110b of the semiconductor element 110. According to one embodiment, a laser lift-off process can be used to irradiate a laser from the back side 404 of the first support substrate 400 to the front side 402 to dissociate the semiconductor material, such as gallium nitride or other compound semiconductor materials, between the semiconductor element 110 and the first support substrate 400, so that the semiconductor element 110 and the first support substrate 400 generate gas and are separated. After the separation process is completed, the semiconductor element 110 can be further cleaned to remove semiconductor residues or metal residues, such as gallium-containing particles, remaining on the back side 110b of the semiconductor element 110. Therefore, unnecessary electrical connections of the semiconductor element 110 can be avoided. After completing step S108, a structure similar to Figure 1 The semiconductor device arrangement structure shown.

[0116] After the arrangement structure shown in step S108 is completed, the semiconductor elements 110 on the carrier 100 can be further transferred individually to other supporting substrates to group the semiconductor elements 110 with similar or identical electrical or optical specifications. The steps are similar to those shown in FIG. Fig.10 shown.

[0117] Fig.10 1 is a cross-sectional schematic diagram of different manufacturing process stages of transferring a semiconductor element from a carrier to a third supporting substrate according to an embodiment of the present invention. In step S110, the back side 110b of the semiconductor element 110 on the carrier 100 faces the third supporting substrate 700. According to one embodiment, the third supporting substrate 700 has a front side 702 and a back side 704 opposite to each other, the front side 702 faces the carrier 100, and the back side 704 is away from the carrier 100. The third supporting substrate 700 can be a non-epitaxial material or a non-growth substrate, for example, a ceramic substrate, a metal substrate, a glass substrate, a thermal release tape, a UV release tape, a chemical release tape, a heat-resistant tape, a blue tape, or a tape with a dynamic release layer (DRL). According to one embodiment, the third supporting substrate 700 includes a carrier 712 and an adhesive layer 714. The carrier 712 has sufficient mechanical strength to support the adhesive layer 714. The adhesive layer 714 has sufficient adhesiveness to fix the components pressed onto its surface. Next, when the front surface 102 of the carrier 100 faces the front surface 702 of the third supporting substrate 700, at least one of the carrier 100 or the third supporting substrate 700 is moved so that the semiconductor element 110 on the carrier 100 contacts the adhesive layer 714 of the third supporting substrate 700.

[0118] In step S112, a separation process is performed to transfer the selected semiconductor element 110 (e.g., the first semiconductor element 110-1) from the carrier 100 to the third supporting substrate 700, and expose the bottom surface 202 of the first adhesive portion 200-1. The remaining unselected semiconductor elements 110 (e.g., the second semiconductor element 110-2) are still disposed on the front surface 102 of the carrier 100. According to one embodiment, a laser lift-off process can be used to irradiate the selected first semiconductor element 110-1 with a laser to decompose or vaporize the first adhesive layer 200-1 between the first semiconductor element 110-1 and the carrier 100, so that the first semiconductor element 110 is separated from the carrier 100. The unselected semiconductor elements 110 are not irradiated by the laser, and thus are still disposed on the front surface 102 of the carrier 100. According to one embodiment, in a subsequent manufacturing process, other selected semiconductor elements 110 (for example, a second semiconductor element 110-2) can continue to be transferred from the carrier 100 to other supporting substrates (not shown), and the transfer manufacturing process can be repeated until all the semiconductor elements 110 located on the carrier 100 are transferred to the selected same and / or different supporting substrates.

[0119] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device arrangement structure, comprising: Carrier; The first semiconductor element and the second semiconductor element are separately located on the carrier; and A first adhesive portion and a second adhesive portion are located separately from each other on the carrier, the first adhesive portion is located between the first semiconductor element and the carrier, and the second adhesive portion is located between the second semiconductor element and the carrier; in, In the cross-sectional view, the first adhesive portion includes a bevel, and the bevel and the carrier are adjacent to each other and form an internal angle (Internal Angle) greater than 90 degrees.

2. The semiconductor device arrangement structure according to claim 1, wherein: The first semiconductor element includes a plurality of recessed areas having a repeated shape, facing the carrier and filled with the adhesive portion.

3. The semiconductor device arrangement structure according to claim 1, wherein: The first adhesive portion and the second adhesive portion include a patterned photoresist layer.

4. The semiconductor device arrangement structure according to claim 1, wherein: The first adhesive portion further includes a bottom surface contacting the carrier, and in a bottom view, a projection area of ​​the bottom surface is smaller than a projection area of ​​the first semiconductor element.

5. The semiconductor device arrangement structure according to claim 1, wherein: The first adhesive portion further includes a protrusion and a vertex, wherein the protrusion is located between the vertex and the inner corner.

6. A method for manufacturing a semiconductor device arrangement structure, comprising: Providing a first supporting substrate, a first semiconductor element, and a second semiconductor element, wherein the first semiconductor element and the second semiconductor element are located on the first supporting substrate and are separated from each other; Providing a patternable adhesive layer to cover the first semiconductor element, the second semiconductor element, and a space between the first semiconductor element and the second semiconductor element; removing the patternable adhesive layer in the space by a photolithography process to form the first adhesive portion and the second adhesive portion; and providing a second supporting substrate, and making the first adhesive portion and the second adhesive portion contact the second supporting substrate, The first adhesive portion is located between the first semiconductor element and the second supporting substrate, and the second adhesive portion is located between the second semiconductor element and the second supporting substrate.

7. The method for manufacturing a semiconductor device arrangement structure according to claim 6, wherein: The first supporting substrate includes a growth substrate, and the first semiconductor element and the second semiconductor element are grown on the growth substrate.

8. The method for manufacturing a semiconductor device arrangement structure according to claim 6, wherein: The patternable adhesive layer fills the space.

9. The method for manufacturing a semiconductor device arrangement structure according to claim 6, wherein: The first semiconductor element includes a plurality of outermost edges. After the removing step, more than 50% of the area of ​​the plurality of outermost edges is not covered by the first adhesive portion.

10. The method for manufacturing a semiconductor device arrangement structure according to claim 6, wherein: In a top view, the first adhesive portion completely overlaps the first semiconductor element.

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