SGT device and manufacturing method thereof
By forming a second shielded gate polysilicon spaced on both sides of the lateral sides of the first shielded gate polysilicon in the SGT device, and forming an insulating isolation layer through thermal oxidation process, the problem of electric field concentration at the bottom of the deep trench is solved, and the drift area is improved The voltage withstand performance solves the problem of insufficient voltage withstand in the drift zone in the prior art.
Patent Information
- Application Number
- CN202411204596.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2024-12-13
AI Technical Summary
SGT devices in related art are prone to the problem of concentrated electric fields at the bottom of deep trench, resulting in insufficient withstand voltage in the drift region, low breakdown voltage in the device and high quality factor.
The second shielded gate polysilicon with phase spaced apart on both sides of the first shielded gate polysilicon, and an insulating isolation layer is formed through a thermal oxidation process to improve the problem of electric field concentration at the bottom of the deep trench, thereby increasing the withstand voltage of the drift region.
By forming a second shielded gate polysilicon spaced on both sides of the transverse direction of the first shielded gate polysilicon, the problem of electric field concentration at the bottom of the deep trench is effectively improved, and the voltage withstand performance of the drift region is improved.
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Figure CN119133242A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to an SGT device and a manufacturing method thereof. Background Art
[0002] The SGT (Spit Gate Trench) device is a trench power MOSFET that uses the charge balance technology theory to introduce additional polysilicon field plates into the traditional power MOSFET for electric field modulation to improve the device's voltage resistance and reduce the on-resistance.
[0003] The gate of the SGT device in the related art is formed in a deep trench, including a shielding gate at the bottom and a control gate at the top. The shielding gate is located in the drift region, and its function in the drift region is equivalent to a field plate in the body region to adjust the electric field in the drift region.
[0004] However, the SGT devices in the related art are prone to the problem of electric field concentration at the bottom of the deep trench, insufficient withstand voltage in the drift region, and are prone to the problem of low device breakdown voltage and high quality factor. Summary of the invention
[0005] The present application provides an SGT device and a manufacturing method thereof, which can solve the problem of electric field concentration at the bottom of a deep trench of an SGT device in the related art.
[0006] In order to solve the technical problem in the background technology, the first aspect of the present application provides an SGT device, the SGT device comprising: a semiconductor base layer, a deep trench extending longitudinally is formed in the semiconductor base layer, and a source doping region is formed in the semiconductor base layer on both sides of the top of the deep trench;
[0007] A shielding gate structure is formed in the deep trench;
[0008] The shielding gate structure includes a trench gate polysilicon located at an upper portion and a shielding gate polysilicon located at a lower portion;
[0009] The shielding gate polysilicon comprises a first shielding gate polysilicon located in the middle in the lateral direction, and a second shielding gate polysilicon located on both sides in the lateral direction of the first shielding gate polysilicon;
[0010] An insulating isolation layer is formed between the shielding gate structure and the sidewall of the deep trench, and between the trench gate polysilicon, the first shielding gate polysilicon and the second shielding gate polysilicon;
[0011] The upper end of the first shielding gate polysilicon exceeds the upper end of the second shielding gate polysilicon, and the lower end of the first shielding gate polysilicon exceeds the lower end of the second shielding gate polysilicon.
[0012] Optionally, the distance that the upper end of the first shielding gate polysilicon extends upward beyond the upper end of the second shielding gate polysilicon is one third of the length of the first shielding gate polysilicon.
[0013] Optionally, the distance that the lower end of the first shielding gate polysilicon extends downward beyond the lower end of the second shielding gate polysilicon is one third of the length of the first shielding gate polysilicon.
[0014] Optionally, the second shielding gate polysilicon is floating.
[0015] Optionally, the first shielding gate polysilicon and the second shielding gate polysilicon are parallel to each other and extend in a longitudinal direction.
[0016] Optionally, the trench gate polysilicon extends in a lateral direction, and both ends of the trench gate polysilicon in the lateral direction are flush with lateral end surfaces of the second shield gate polysilicon.
[0017] In order to solve the technical problem in the background technology, the second aspect of the present application provides a method for manufacturing an SGT device, wherein the method for manufacturing an SGT device is used to manufacture the SGT device as described in the first aspect of the present application, and the method for manufacturing an SGT device comprises the following steps:
[0018] Providing a semiconductor base layer, in which a deep trench extending longitudinally is formed;
[0019] Depositing a first oxide layer according to the surface morphology of the semiconductor base layer, and forming a first shielding gate polysilicon in the deep trench with the first oxide layer;
[0020] Etching the first oxide layer so that the remaining first oxide layer is located at the lower part of the first shield gate polysilicon, and first spaces are respectively formed between the part of the first shield gate polysilicon that exceeds the remaining first oxide layer and the two side walls of the deep trench;
[0021] Oxidizing the silicon surface by a thermal oxidation process to form a second oxide layer, forming a second shielding gate polysilicon in the first space with the second oxide layer, wherein the upper end of the first shielding gate polysilicon exceeds the upper end of the second shielding gate polysilicon;
[0022] Depositing to form a third oxide layer, the third oxide layer covers the second shielding gate polysilicon and the first shielding gate polysilicon;
[0023] Forming trench gate polysilicon on the third oxide layer;
[0024] A source doping region is formed on both sides of the deep trench by an ion implantation process.
[0025] Optionally, the distance that the upper end of the first shielding gate polysilicon extends upward beyond the upper end of the second shielding gate polysilicon is one third of the length of the first shielding gate polysilicon.
[0026] Optionally, the distance that the lower end of the first shielding gate polysilicon extends downward beyond the lower end of the second shielding gate polysilicon is one third of the length of the first shielding gate polysilicon.
[0027] The technical solution of the present application includes at least the following advantages: the present application improves the problem of electric field concentration at the bottom of the deep trench by forming a second shielding gate polysilicon spaced apart on both lateral sides of the first shielding gate polysilicon, thereby improving the withstand voltage of the drift region. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0029] Figure 1 A schematic cross-sectional structure diagram of an SGT device provided in an embodiment of the present application is shown;
[0030] Figure 2 A flow chart showing a method for manufacturing the SGT device is shown;
[0031] Figure 3 A schematic diagram of a cross-sectional structure of the device after step S1 is completed is shown;
[0032] Figure 4 A schematic diagram of the cross-sectional structure of the device after step S2 is completed is shown;
[0033] Figure 5 A schematic diagram of the cross-sectional structure of the device after step S3 is completed is shown;
[0034] Figure 6 A schematic diagram of the cross-sectional structure of the device after step S4 is completed is shown;
[0035] Figure 7 FIG. 4 shows a schematic diagram of a cross-sectional structure of the device after step S5 is completed. DETAILED DESCRIPTION
[0036] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0037] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0038] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0039] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0040] Figure 1 The schematic diagram of the cross-sectional structure of the SGT device provided in one embodiment of the present application is shown. Figure 1 As can be seen from the figure, the SGT device includes a semiconductor substrate layer 100 , in which a deep trench 200 extending longitudinally is formed, and source doping regions 500 are formed in the semiconductor substrate layer 100 on both sides of the top of the deep trench 200 .
[0041] A shield gate structure is formed in the deep trench 200 , and the shield gate structure includes a trench gate polysilicon 310 located at an upper portion and a shield gate polysilicon 320 located at a lower portion.
[0042] The shielding gate polysilicon 320 includes a first shielding gate polysilicon 321 located in the middle in a lateral direction, and second shielding gate polysilicon 322 located on both sides of the first shielding gate polysilicon 321 in a lateral direction.
[0043] An insulating isolation layer 400 is formed between the shielding gate structure and the sidewall of the deep trench, and between the trench gate polysilicon 310 , the first shielding gate polysilicon 321 , and the second shielding gate polysilicon 322 .
[0044] The upper end of the first shielding gate polysilicon 321 exceeds the upper end of the second shielding gate polysilicon 322 , and the lower end of the first shielding gate polysilicon 321 exceeds the lower end of the second shielding gate polysilicon 322 .
[0045] In this embodiment, the second shield gate polysilicon 322 is formed at two lateral sides of the first shield gate polysilicon 321 to improve the problem of electric field concentration at the bottom of the deep trench, thereby improving the withstand voltage of the drift region.
[0046] Exemplarily, the distance that the upper end of the first shielding gate polysilicon 321 exceeds the upper end of the second shielding gate polysilicon 322 upwards is one third of the length of the first shielding gate polysilicon. The distance that the lower end of the first shielding gate polysilicon 321 exceeds the lower end of the second shielding gate polysilicon 322 downwards is one third of the length of the first shielding gate polysilicon.
[0047] The second shielding gate polysilicon 322 located on both sides of the first shielding gate polysilicon 321 are both in a floating state.
[0048] Continue to refer to Figure 1 The first shield gate polysilicon 321 and the second shield gate polysilicon 322 are parallel to each other and extend in the longitudinal direction. The trench gate polysilicon 310 extends in the lateral direction, and both ends of the trench gate polysilicon 310 in the lateral direction are flush with the lateral end surface of the second shield gate polysilicon 322.
[0049] The present application also provides a method for manufacturing an SGT device. Figure 2 A flow chart showing a method for manufacturing the SGT device is shown. Figure 2 It can be seen that the manufacturing method of the SGT device includes the following steps:
[0050] Step S1: providing a semiconductor substrate layer, in which a longitudinally extending deep trench is formed.
[0051] Figure 3 The schematic diagram of the cross-sectional structure of the device after step S1 is completed is shown. Figure 3 As can be seen from the figure, a deep trench 200 is formed in the semiconductor substrate layer 100 , and the deep trench 200 extends downward from the upper surface of the semiconductor substrate layer 100 .
[0052] Step S2: depositing a first oxide layer according to the surface morphology of the semiconductor base layer, and forming a first shielding gate polysilicon in the deep trench with the first oxide layer.
[0053] Figure 4 The schematic diagram of the cross-sectional structure of the device after step S2 is completed is shown. Figure 4 It can be seen that Figure 1 The surface of the semiconductor substrate layer 100 is shown to form a first oxide layer 410, and the first oxide layer 410 covers the bottom surface, the side surface and the upper surface of the semiconductor substrate layer 100 of the deep trench 200. Exemplarily, the thickness of the first oxide layer 410 is 1.2um. The deep trench with the first oxide layer 410 is filled and etched back to form a first shield gate polysilicon 321.
[0054] Step S3: etching the first oxide layer so that the remaining first oxide layer is located at the bottom of the first shield gate polysilicon, and first spaces are formed between the portion of the first shield gate polysilicon exceeding the remaining first oxide layer and the two side walls of the deep trench.
[0055] Figure 5 The schematic diagram of the cross-sectional structure of the device after step S3 is completed is shown. Figure 5 As can be seen in the figure, the remaining first oxide layer surrounds the lower part of the first shielding gate polysilicon 321. The upper end of the first shielding gate polysilicon 321 exceeds the remaining first oxide layer 410, and the first spaces 210 are formed between the part of the first shielding gate polysilicon 321 that exceeds the remaining first oxide layer 410 and the two side walls of the deep trench 200.
[0056] Step S4: oxidizing the silicon surface by a thermal oxidation process to form a second oxide layer, forming a second shielding gate polysilicon in the first space with the second oxide layer, and the upper end of the first shielding gate polysilicon exceeds the upper end of the second shielding gate polysilicon.
[0057] Figure 6 The schematic diagram of the cross-sectional structure of the device after step S4 is completed is shown. Figure 6 As can be seen from the figure, the second oxide layer 420 covers Figure 5 The device surface shown, that is, the second oxide layer 420 covers the surface of the first space 210 and the upper surface of the semiconductor substrate layer 100. The second shielding gate polysilicon 322 fills the first space 210 with the second oxide layer 420. And the upper end of the first shielding gate polysilicon 321 exceeds the upper end of the second shielding gate polysilicon 322.
[0058] Step S5: depositing and forming a third oxide layer, wherein the third oxide layer covers the second shielding gate polysilicon and the first shielding gate polysilicon.
[0059] Figure 7 FIG. 4 shows a schematic diagram of the cross-sectional structure of the device after step S5 is completed. Figure 7As can be seen in FIG. 4 , the third oxide layer 430 covers the first shielding gate polysilicon 321 and the second shielding gate polysilicon 322 . That is, the top of the shielding gate polysilicon 320 formed by the first shielding gate polysilicon 321 and the second shielding gate polysilicon 322 is covered by the third oxide layer 430 .
[0060] Exemplarily, the distance that the upper end of the first shielding gate polysilicon 321 exceeds the upper end of the second shielding gate polysilicon 322 upwards is one third of the length of the first shielding gate polysilicon. The distance that the lower end of the first shielding gate polysilicon 321 exceeds the lower end of the second shielding gate polysilicon 322 downwards is one third of the length of the first shielding gate polysilicon.
[0061] Step S6: forming trench gate polysilicon on the third oxide layer.
[0062] Step S7: forming source doping regions on both sides of the deep trench by an ion implantation process.
[0063] Figure 1 FIG. 4 shows a schematic diagram of the cross-sectional structure of the device after step S7 is completed. Figure 1 It can be seen that the source doping region 500 is formed on both sides of the trench gate polysilicon deep trench 200 formed on the third oxide layer. A source metal layer 600 is also formed on the front side of the semiconductor base layer 100. The source metal layer 600 is in contact with the source doping region 500, and a silicon oxide layer is separated between the source metal layer 600 and the second shield gate polysilicon 322. A drain doping region and a drain metal layer 700 are also formed on the back side of the semiconductor base layer 100.
[0064] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. An SGT device, characterized in that: The SGT device comprises: a semiconductor base layer, a deep trench extending longitudinally is formed in the semiconductor base layer, and source doping regions are formed in the semiconductor base layer on both sides of the top of the deep trench; A shielding gate structure is formed in the deep trench; The shielding gate structure includes a trench gate polysilicon located at an upper portion and a shielding gate polysilicon located at a lower portion; The shielding gate polysilicon comprises a first shielding gate polysilicon located in the middle in the lateral direction, and a second shielding gate polysilicon located on both sides in the lateral direction of the first shielding gate polysilicon; An insulating isolation layer is formed between the shielding gate structure and the sidewall of the deep trench, and between the trench gate polysilicon, the first shielding gate polysilicon and the second shielding gate polysilicon; The upper end of the first shielding gate polysilicon exceeds the upper end of the second shielding gate polysilicon, and the lower end of the first shielding gate polysilicon exceeds the lower end of the second shielding gate polysilicon.
2. The SGT device according to claim 1, characterized in that: The distance that the upper end of the first shielding gate polysilicon exceeds the upper end of the second shielding gate polysilicon upward is one third of the length of the first shielding gate polysilicon.
3. The SGT device according to claim 1, characterized in that: The distance that the lower end of the first shielding gate polysilicon extends downward beyond the lower end of the second shielding gate polysilicon is one third of the length of the first shielding gate polysilicon.
4. The SGT device according to claim 1, characterized in that: The second shielding gate polysilicon is floating.
5. The SGT device according to claim 1, characterized in that: The first shielding gate polysilicon and the second shielding gate polysilicon are parallel to each other and extend along a longitudinal direction.
6. The SGT device according to claim 1, characterized in that: The trench gate polysilicon extends in a lateral direction, and both ends of the trench gate polysilicon in the lateral direction are flush with a lateral end surface of the second shield gate polysilicon.
7. A method for manufacturing a SGT device, characterized in that: The method for manufacturing the SGT device is used to manufacture the SGT device according to any one of claims 1 to 6, and the method for manufacturing the SGT device comprises the following steps: Providing a semiconductor base layer, in which a deep trench extending longitudinally is formed; Depositing a first oxide layer according to the surface morphology of the semiconductor base layer, and forming a first shielding gate polysilicon in the deep trench with the first oxide layer; Etching the first oxide layer so that the remaining first oxide layer is located at the lower part of the first shield gate polysilicon, and first spaces are respectively formed between the part of the first shield gate polysilicon that exceeds the remaining first oxide layer and the two side walls of the deep trench; Oxidizing the silicon surface by a thermal oxidation process to form a second oxide layer, forming a second shielding gate polysilicon in the first space with the second oxide layer, wherein the upper end of the first shielding gate polysilicon exceeds the upper end of the second shielding gate polysilicon; Depositing to form a third oxide layer, the third oxide layer covers the second shielding gate polysilicon and the first shielding gate polysilicon; Forming trench gate polysilicon on the third oxide layer; A source doping region is formed on both sides of the deep trench by an ion implantation process.
8. The method for manufacturing a SGT device according to claim 7, wherein: The distance that the upper end of the first shielding gate polysilicon exceeds the upper end of the second shielding gate polysilicon upward is one third of the length of the first shielding gate polysilicon.
9. The SGT device according to claim 7, characterized in that: The distance that the lower end of the first shielding gate polysilicon extends downward beyond the lower end of the second shielding gate polysilicon is one third of the length of the first shielding gate polysilicon.