Chip preparation method for improving electrode migration prevention capability

Abstract

The invention relates to the technical field of chip preparation, in particular to a chip preparation method for improving electrode migration prevention capability, which comprises the following steps of: sequentially preparing an epitaxial wafer, an N-GaN step, a transparent conductive layer, an electrode layer, an electrode protection interface layer and a passivation insulating layer on a substrate; and the passivation insulating layer is prepared from a multi-layer composite material, so that the electromigration resistance and the corrosion resistance of the chip are effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip preparation, and in particular to a chip preparation method for improving the ability to prevent electrode migration. Background Art

[0002] Electromigration refers to the phenomenon that metal atoms migrate due to electron momentum transfer under high current density conditions, often leading to wire breakage or contact failure. In tiny LED chips, the electromigration problem is particularly serious due to the high current density, affecting the reliability and service life of the LED chip.

[0003] Especially in the field of outdoor display, tiny-sized LED chips need to withstand various harsh environments, such as high temperature, high humidity, salt spray, etc. These factors will accelerate the electromigration phenomenon. For example, in an environment such as a simulated seaside, LED chips need to resist halogen corrosion, which requires the chip to have a stronger anti-electromigration ability. The salt spray test is an important test for evaluating the corrosion resistance of electronic devices in a salty environment, which can directly reflect the reliability of LED chips in harsh outdoor environments. Publication No. CN117637962A discloses an LED chip that prevents metal migration failure. Although it has improved the ability to prevent metal migration, it does not have corrosion resistance.

[0004] Therefore, how to improve the anti-electromigration and anti-corrosion capabilities of tiny-sized LED chips has become a problem that needs to be solved urgently. Summary of the invention

[0005] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art, optimize the structure of the passivation insulating layer and the electrode layer, and provide a chip preparation method capable of improving the anti-electrode migration capability.

[0006] The technical solution adopted by the present invention to solve the technical problem is as follows: a chip preparation method for improving the anti-electrode migration capability comprises sequentially preparing an epitaxial wafer, an N-GaN step, a transparent conductive layer, an electrode layer, an electrode protection interface layer and a passivation insulating layer on a substrate;

[0007] The passivation insulating layer is prepared by using a multi-layer composite material.

[0008] The epitaxial wafer comprises an N-GaN layer, a multi-quantum well layer and a P-GaN layer which are sequentially grown on a substrate, and the epitaxial wafer is grown and prepared on the substrate by adopting MOCVD technology.

[0009] The epitaxial wafer is grown using high-purity hydrogen as carrier gas, high-purity ammonia as nitrogen source, trimethylgallium and triethylgallium as gallium sources, trimethylindium as indium source, silane as N-type dopant, trimethylaluminum as aluminum source, and bismuthocene magnesium as P-type dopant.

[0010] During the growth process, by precisely controlling the thickness and doping concentration of each layer, the thickness of the N-GaN layer ranges from 1μm to 3μm, the thickness of the P-GaN layer ranges from 200nm to 300nm, and the molar ratio of In components in the multi-quantum well layer ranges from 10% to 35%. This fine epitaxial growth process optimizes the performance of each layer and lays a solid foundation for subsequent device manufacturing.

[0011] When preparing the N-GaN steps, photolithography technology was used for pattern transfer, and then ICP etching technology was used to finely etch the material using Cl2, BCl3 and Ar as reaction gases, with an etching depth ranging from 1μm to 1.2μm, thus successfully exposing the N-GaN steps.

[0012] When preparing the transparent conductive layer, a magnetron sputtering device was used to grow a transparent conductive layer film (In2O3: 90wt%, SnO2: 10wt%), and the oxygen flow rate was maintained at 2sccm during the growth process;

[0013] The grown film is then placed in a rapid thermal annealing furnace for treatment to form a transparent conductive layer. In this embodiment, a high temperature treatment is performed for 7 minutes in a N2 gas atmosphere (flow range: 6 slm-4 sccm) to finally form a novel ITO film.

[0014] In addition, the present application utilizes yellow light exposure etching to remove the N-region film layer, and shrinks the region in step 2 by 1 μm to 3 μm to avoid overlapping sections between the transparent conductive layer and the N-region.

[0015] When preparing the electrode layer, a negative photoresist is coated on the surface of the epitaxial wafer, and the transparent conductive layer and part of the N-GaN layer are exposed through exposure and development, ready for evaporation of the electrode metal;

[0016] The epitaxial wafer is placed in an electron beam evaporation device, and Cr, Al, Ti, Pt, Cu, and Au layers are sequentially evaporated to form a PN type electrode. In order to improve the corrosion resistance, a Cu alloy layer is added.

[0017] TiW alloy evaporation is used to form an electrode protection interface layer on the PN type electrode. The present application adds an electrode protection interface layer after the electrode layer, and TiW alloy evaporation is used to increase the bonding strength with the PSV protection layer and improve the corrosion resistance. The metal in the excess area is then torn off, and the photoresist is removed in a degumming solution, leaving only the positive and negative PN electrode metal areas.

[0018] The passivation insulating layer is deposited by using PECVD technology.

[0019] The present application uses PECVD technology to deposit a passivation insulating layer on the outermost surface. The passivation insulating layer (8) uses a multilayer composite material. Specifically, the passivation insulating layer of the present application includes a combination of several materials such as SiO2, Si3N4 and Al2O3. These materials each have different advantages. By using them in combination, their comprehensive advantages can be brought into play to provide excellent electrical insulation performance and mechanical protection capabilities.

[0020] SiO2 (silicon oxide) has good thermal and chemical stability, and can effectively isolate chemicals in the external environment. It is often used in protective films and insulating layers to provide basic electrical insulation and protection. Si3N4 (silicon nitride) has high mechanical strength and hardness, and can provide excellent mechanical protection. It also has low stress and excellent electrical insulation performance. It is used to enhance the mechanical strength and durability of the insulating layer and prevent external mechanical damage. Al2O3 (aluminum oxide) has a high dielectric constant and excellent thermal conductivity, which helps to improve the electrical performance and heat dissipation performance of the device. It is used to improve the dielectric properties and thermal management capabilities of the insulating layer to ensure the stable operation of the device in high-power and high-temperature environments.

[0021] The preparation process of the passivation insulating layer in this application is as follows:

[0022] A layer of SiO2 is deposited on the outermost layer using PECVD technology with a thickness ranging from 20nm to 30nm to provide basic electrical insulation and chemical protection;

[0023] Depositing a layer of Si3N4 with a thickness ranging from 30nm to 40nm to enhance mechanical strength and provide additional electrical insulation;

[0024] A layer of Al2O3 is deposited with a thickness ranging from 30nm to 40nm to improve the dielectric constant and thermal conductivity, and optimize electrical performance and heat dissipation.

[0025] Through exposure, development and etching, holes are opened at the positions corresponding to the P-type electrode and the N-type electrode, and the thickness of the passivation insulating layer is controlled to be 80nm-100nm. The etching is done by dry method, and the etching parameters are controlled to ensure that the passivation insulating layer and the lower electrode protection interface layer are etched cleanly without excessively damaging the Au on the top of the metal layer.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] 1. The passivation insulation layer and electrode layer structure of the tiny LED chip are optimized, which effectively improves the chip's anti-electromigration and anti-corrosion capabilities. It is especially suitable for outdoor display fields, can pass the salt spray test, and prolongs the chip's service life. It has important practical value and market prospects.

[0028] 2. The present application optimizes the passivation insulating layer material: Different from the traditional preparation process that uses SiO2 or SiN single material as a barrier layer, or uses ALD (atomic layer deposition) technology to coat Al2O3, which increases the machine purchase cost. The present invention uses a multi-layer composite material structure, and selects a variety of materials with high electromigration resistance and corrosion resistance as a passivation insulating layer, such as SiN, SiO2 or Al2O3, etc., which ensures both light transmittance and insulation density, and is prepared by physical vapor deposition (PVD) process without adding other process machines;

[0029] 3. The present application optimizes the electrode layer material: The present application selects materials with high melting point, high resistivity and corrosion resistance as the electrode layer, such as tungsten (W), tantalum (Ta) or molybdenum (Mo), etc., or uses Cu alloy as the electrode material to reduce the electromigration effect and improve corrosion resistance.

[0030] 4. This application optimizes the interface design: an electrode protection interface layer is added between the electrode layer and the passivation insulating layer, for example, TiW or NiCr is used as the electrode protection interface layer to increase the interface bonding strength and reduce electromigration and corrosion at the interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of the chip structure of the present invention.

[0032] In the figure: 1. substrate; 2. N-GaN layer; 3. multi-quantum well layer; 4. P-GaN layer; 5. transparent conductive layer; 6. P-layer metal electrode; 7. electrode protection interface layer; 8. passivation insulating layer; 9. N-layer metal electrode. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0035] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] Reference Figure 1 , a chip preparation method for improving the anti-electrode migration capability comprises sequentially preparing an epitaxial wafer, an N-GaN step, a transparent conductive layer 5, an electrode layer, an electrode protection interface layer 7 and a passivation insulating layer 8 on a substrate 1;

[0037] The passivation insulating layer 8 is made of a multi-layer composite material.

[0038] The epitaxial wafer comprises an N-GaN layer 2, a multi-quantum well layer 3, and a P-GaN layer 4 which are sequentially grown on a substrate 1. The epitaxial wafer is grown and prepared on a sapphire substrate 1 by using MOCVD technology.

[0039] Epitaxial wafers are grown using high-purity hydrogen (≥99.999%) as a carrier gas, high-purity ammonia (≥99.999%) as a nitrogen source, trimethylgallium and triethylgallium as gallium sources, trimethylindium as an indium source, silane as an N-type dopant, trimethylaluminum as an aluminum source, and bismuthocene magnesium as a P-type dopant.

[0040] During the growth process, by precisely controlling the thickness and doping concentration of each layer, the thickness of the N-GaN layer 2 ranges from 1 μm to 3 μm, the thickness of the P-GaN layer 4 ranges from 200 nm to 300 nm, and the molar ratio of the In component in the multi-quantum well layer 3 ranges from 10% to 35%. This fine epitaxial growth process optimizes the performance of each layer and lays a solid foundation for subsequent device manufacturing.

[0041] When preparing the N-GaN steps, photolithography technology was used for pattern transfer, and then ICP etching technology was used to finely etch the material using Cl2, BCl3 and Ar as reaction gases, with an etching depth ranging from 1μm to 1.2μm, thus successfully exposing the N-GaN steps.

[0042] When preparing the transparent conductive layer 5, a magnetron sputtering device is used to grow a transparent conductive layer film (In2O3: 90wt%, SnO2: 10wt%), and the oxygen flow rate is maintained at 2sccm during the growth process;

[0043] The grown film is then placed in a rapid thermal annealing furnace for treatment to form a transparent conductive layer. In this embodiment, a high temperature (500°C-550°C) treatment is performed for 7 minutes in a N2 (flow range: 6slm-4sccm) gas atmosphere to finally form a new ITO film.

[0044] In addition, the present application utilizes yellow light exposure etching to remove the N-region film layer, and shrinks the region in step 2 by 1 μm to 3 μm to avoid overlapping sections between the transparent conductive layer and the N-region.

[0045] When preparing the electrode layer, a negative photoresist is coated on the surface of the epitaxial wafer, and the transparent conductive layer and part of the N-GaN layer are exposed through exposure and development, ready for evaporation of the electrode metal;

[0046] The epitaxial wafer is placed in an electron beam evaporation device, and Cr, Al, Ti, Pt, Cu, and Au layers are sequentially evaporated to form a PN type electrode. In order to improve the corrosion resistance, a Cu alloy layer is added.

[0047] The electrode protection interface layer 7 is formed on the PN type electrode by TiW alloy evaporation. The electrode protection interface layer is added after the electrode layer by TiW alloy evaporation to increase the bonding strength with the PSV protection layer and improve the corrosion resistance. Then the metal in the excess area is torn off, and the photoresist is removed in the degumming liquid, leaving only the positive and negative PN electrode metal areas.

[0048] The passivation insulating layer 8 is deposited by using PECVD technology.

[0049] The present application uses PECVD technology to deposit a passivation insulating layer on the outermost surface. The passivation insulating layer 8 is a multi-layer composite material. Specifically, the passivation insulating layer of the present application includes a combination of several materials such as SiO2, Si3N4 and Al2O3. These materials each have different advantages. By using them in combination, their comprehensive advantages can be brought into play to provide excellent electrical insulation performance and mechanical protection capabilities.

[0050] SiO2 (silicon oxide) has good thermal and chemical stability, and can effectively isolate chemicals in the external environment. It is often used in protective films and insulating layers to provide basic electrical insulation and protection. Si3N4 (silicon nitride) has high mechanical strength and hardness, and can provide excellent mechanical protection. It also has low stress and excellent electrical insulation performance. It is used to enhance the mechanical strength and durability of the insulating layer and prevent external mechanical damage. Al2O3 (aluminum oxide) has a high dielectric constant and excellent thermal conductivity, which helps to improve the electrical performance and heat dissipation performance of the device. It is used to improve the dielectric properties and thermal management capabilities of the insulating layer to ensure the stable operation of the device in high-power and high-temperature environments.

[0051] The preparation process of the passivation insulating layer 8 in this application is as follows:

[0052] A layer of SiO2 is deposited on the outermost layer using PECVD technology with a thickness ranging from 20nm to 30nm to provide basic electrical insulation and chemical protection;

[0053] Depositing a layer of Si3N4 with a thickness ranging from 30nm to 40nm to enhance mechanical strength and provide additional electrical insulation;

[0054] A layer of Al2O3 is deposited with a thickness ranging from 30nm to 40nm to improve the dielectric constant and thermal conductivity, and optimize electrical performance and heat dissipation.

[0055] Through exposure, development and etching, holes are opened at the positions corresponding to the P-type electrode and the N-type electrode, and the thickness of the passivation insulating layer 8 is controlled to be 80nm-100nm. The etching and opening are carried out by dry method, and the etching parameters are controlled. Specifically, the ICP power is 500W-600W, the Bias power is 200W-250W, and the CF4 gas flow is controlled below 200SCCM; through control, it is ensured that the passivation insulating layer 8 and the lower electrode protection interface layer 7 are etched cleanly, and the Au on the top of the metal layer is not damaged too much.

[0056] The above descriptions are only optional embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A method for preparing a chip for improving the ability to prevent electrode migration, characterized in that: An epitaxial wafer, an N-GaN step, a transparent conductive layer (5), an electrode layer, an electrode protection interface layer (7) and a passivation insulating layer (8) are sequentially prepared on a substrate (1); The passivation insulating layer (8) is prepared from a multi-layer composite material.

2. The method for preparing a chip for improving the anti-electrode migration capability according to claim 1, characterized in that: The epitaxial wafer comprises an N-GaN layer (2), a multi-quantum well layer (3), and a P-GaN layer (4) which are grown in sequence on a substrate (1); the epitaxial wafer is grown and prepared on the substrate (1) using MOCVD technology.

3. The method for preparing a chip for improving the anti-electrode migration capability according to claim 2, characterized in that: The epitaxial wafer is grown using hydrogen as a carrier gas, ammonia as a nitrogen source, trimethylgallium and triethylgallium as gallium sources, trimethylindium as an indium source, silane as an N-type dopant, trimethylaluminum as an aluminum source, and bismuthocene magnesium as a P-type dopant.

4. The method for preparing a chip for improving the anti-electrode migration capability according to claim 3, characterized in that: The thickness of the N-GaN layer (2) is in the range of 1 μm to 3 μm, the thickness of the P-GaN layer (4) is in the range of 200 nm to 300 nm, and the molar ratio of the In component in the multi-quantum well layer (3) is in the range of 10% to 35%.

5. The method for preparing a chip for improving the anti-electrode migration capability according to claim 3, characterized in that: When preparing N-GaN steps, photolithography technology is used for pattern transfer, and then ICP etching technology is used to finely etch the material using Cl2, BCl3 and Ar as reaction gases, with an etching depth ranging from 1μm to 1.2μm.

6. The method for preparing a chip for improving the anti-electrode migration capability according to claim 3, characterized in that: When preparing the transparent conductive layer (5), a magnetron sputtering device is used to grow a transparent conductive layer thin film, and an oxygen flow rate is maintained at 2 sccm during the growth process; The grown film is then placed in a rapid thermal annealing furnace for processing to form a transparent conductive layer.

7. The method for preparing a chip for improving the anti-electrode migration capability according to claim 3, characterized in that: When preparing the electrode layer, a negative photoresist is coated on the surface of the epitaxial wafer, and the transparent conductive layer and part of the N-GaN layer are exposed through exposure and development; The epitaxial wafer is placed in an electron beam evaporation device, and Cr, Al, Ti, Pt, Cu, and Au layers are evaporated in sequence to form a PN type electrode.

8. The method for preparing a chip for improving the anti-electrode migration capability according to claim 7, characterized in that: TiW alloy evaporation is used to form an electrode protection interface layer (7) on the PN type electrode, and then the metal in the redundant area is torn off, and the photoresist is removed in a degumming liquid, leaving only the positive and negative PN electrode metal areas.

9. The method for preparing a chip for improving the anti-electrode migration capability according to claim 1, characterized in that: The passivation insulating layer (8) is deposited using PECVD technology.

10. The method for preparing a chip for improving the anti-electrode migration capability according to claim 9, characterized in that: The preparation process of the passivation insulating layer (8) is as follows: Deposit a layer of SiO2 with a thickness ranging from 20nm to 30nm; Deposit a layer of Si3N4 with a thickness ranging from 30nm to 40nm; Deposit a layer of Al2O3 with a thickness ranging from 30nm to 40nm; Holes are opened at positions corresponding to the P-type electrode and the N-type electrode respectively by exposure, development and etching, and the thickness of the passivation insulating layer (8) is controlled to be 80nm-100nm.

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