Circuit structure for realizing full duty ratio control processing aiming at peak current mode DCDC

Abstract

The invention relates to a circuit structure for realizing full duty ratio control processing aiming at a peak current mode DCDC, and the circuit structure comprises a minimum turn-off time logic unit which is used for generating a low-level pulse signal by detecting a rising edge of a clock signal; the minimum conduction time logic unit is used for acquiring the minimum conduction time of the circuit structure; the full duty ratio detection logic unit is used for sampling the PWM signal according to the falling edge of the low-level pulse signal; and the cross-cycle control logic unit is used for performing cross-cycle control processing on the input signal meeting the maximum duty ratio state according to the detection state of the full duty ratio detection logic unit. By adopting the circuit structure for realizing full duty ratio control processing aiming at the peak current mode DCDC, full duty ratio work is realized through full duty ratio detection and cross-cycle logic, direct switching between the maximum duty ratio and the 100% duty ratio is avoided, and the problem of intermediate fault occurring from the maximum duty ratio to the 100% duty ratio is eliminated.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, in particular to the field of peak current mode DCDC, and specifically refers to a circuit structure for implementing full duty cycle control processing for peak current mode DCDC. Background Art

[0002] Peak current mode DCDC has the advantages of simple compensation, fixed frequency, small EMI radiation and small voltage ripple, and is widely used. It consists of an oscillator, a reference, a resistor divider circuit, an error amplifier, a current sampling circuit, a PWM comparator, a control logic and an output switch circuit. Figure 1 As shown in the figure, the whole DCDC working principle is as follows: the oscillator generates a fixed frequency clock, the reference generates a fixed voltage, the output voltage is divided by a resistor and the reference is differentially amplified by the error amplifier, and the output is provided to the PWM comparator and compared with the current sampling signal, and then the pulse width modulation signal is obtained through the control logic to control the switch circuit. When each clock rising edge comes, the output switch is turned on, and when the PWM comparator output flips, the output switch tube is turned off. Through the feedback loop, a corresponding pulse width modulation signal (duty cycle switch signal) is obtained to adjust the output voltage to the target voltage.

[0003] In battery-powered applications, as the battery wears out, the input voltage of the DCDC will become lower and slowly approach the output voltage. In order to extend the battery life as much as possible, it is hoped that the DCDC can work normally even when the input drops to the output voltage. For a step-down DCDC, the relationship between the input voltage and the output voltage satisfies VIN=D*VOUT, where D is the duty cycle of the switch. To satisfy VIN=VOUT, the duty cycle D needs to be equal to 100%, which is the full duty cycle. However, for conventional peak current mode DCDC, due to the limitations of fixed switching frequency and minimum off time, full duty cycle operation cannot be achieved.

[0004] In response to this situation, there is currently such a method, which determines that if the output voltage is still lower than the preset voltage under the maximum duty cycle, the chip directly switches to the full duty cycle mode. The disadvantages of this technology are as follows: there is no continuous transition between the maximum duty cycle and the full duty cycle, which will cause a significant sudden change in the output voltage during the switching, thus seriously affecting the output voltage ripple index. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art, and provide a circuit structure that can realize full duty cycle operation of peak current mode DCDC, and realize smooth transition from maximum duty cycle to full duty cycle, avoid discontinuity in the switching process, and reduce the ripple of the output voltage in the switching process to realize full duty cycle control processing for peak current mode DCDC.

[0006] In order to achieve the above object, the circuit structure of the present invention for implementing full duty cycle control processing for peak current mode DCDC is as follows:

[0007] The circuit structure for implementing full duty cycle control processing for peak current mode DCDC has the following main features:

[0008] A minimum off-time logic unit is used to detect the rising edge of a clock signal and generate a low-level pulse signal accordingly;

[0009] A minimum on-time logic unit, connected to the minimum off-time logic unit, for obtaining the minimum on-time of the circuit structure;

[0010] A full duty cycle detection logic unit is connected to the minimum off time logic unit and is used to sample the PWM signal according to the falling edge of the low level pulse signal to detect whether the current circuit structure reaches the maximum duty cycle state; and

[0011] The cross-cycle control logic unit is connected to the minimum off-time logic unit, the minimum on-time logic unit and the full duty cycle detection logic unit, and is used to perform cross-cycle control processing on the input signal that meets the maximum duty cycle state according to the detection state of the full duty cycle detection logic unit.

[0012] Preferably, the minimum off-time logic unit includes: an inverter I21, an inverter I22, an inverter I23, a NAND gate I24 and an AND gate I26 connected in sequence, a capacitor C21 is also provided between the inverter I21 and the inverter I22, wherein the NAND gate I24 and the AND gate I26 are connected via a D flip-flop I25, the D terminal of the D flip-flop I25 is connected to VDD, the CLK terminal is connected to the CLK_MINOFF signal output by the NAND gate I24, the R terminal is connected to the PWM_PULSE signal, the output Q terminal is used to output a PWM signal, and the PWM signal is connected to the input terminal of the AND gate I26, thereby realizing pulse width modulation logic.

[0013] Preferably, the minimum on-time logic unit includes a D flip-flop I27, an inverter I34 and a delay unit, the inverter I34 is connected to the XQ end of the D flip-flop I27, and the delay unit is connected to the Q end of the D flip-flop I27, wherein the delay unit includes an inverter I28, an inverter I29 and an inverter I30 connected in sequence, and a capacitor C22 is arranged between the inverter I28 and the inverter I29.

[0014] Preferably, the D terminal of the D flip-flop I27 is connected to VDD, and the CLK terminal is connected to the output terminal of the AND gate I26. When the output of the AND gate I26 jumps high, the Q terminal of the D flip-flop I27 jumps high, and the XQ terminal jumps low, and outputs a high level after being processed by the inverter I34; when the output of the AND gate I26 jumps low, the XQ terminal of the D flip-flop I27 maintains a low level, and the XQ terminal is set to 1 through the delay unit, thereby obtaining the minimum on-time.

[0015] Preferably, the full duty cycle detection logic unit is composed of an inverter I31 and a D flip-flop I32, wherein the inverter I31 is connected to the CLK_MINOFF signal, and the output end is connected to the CLK end of the D flip-flop I32, and the D end of the D flip-flop I32 is connected to the Q end of the D flip-flop I25.

[0016] Preferably, the full duty cycle detection logic unit specifically performs the following processing:

[0017] When the CLK_MINOFF signal is in the falling edge cycle, the PWM signal is sampled and processed. If the sampling value is 0, the maximum duty cycle state has not been reached at present, and the output signal MAXDUTY_FLG of the D flip-flop I32 is set to 0; if the sampling value is 1, the maximum duty cycle state has been reached at present, and the output signal MAXDUTY_FLG is set to 1 and continues until the falling edge of the CLK_MINOFF signal of the next cycle arrives, thereby completing the full duty cycle detection.

[0018] Preferably, the cross-cycle control logic unit is implemented by an OR gate I33, wherein the input end of the OR gate I33 is respectively connected to the inverter I34, the AND gate I26 and the Q end of the D flip-flop I32, and the output end of the OR gate I33 serves as the switching signal DRV1 of the power switch tube.

[0019] Preferably, the cross-cycle control logic unit specifically performs the following processing:

[0020] When the system does not reach the maximum duty cycle state, MAXDUTY_FLG=0, and the switch signal DRV1 is equal to the duty cycle control signal DRV through the OR gate I33; when the system reaches the maximum duty cycle state, the output signal MAXDUTY_FLG=1, and it lasts until the falling edge of the next cycle CLK_MINOFF signal;

[0021] Through the OR gate I33, MAXDUTY_FLG=1, and the switch signal DRV1 is forcibly set to 1, and continues until the falling edge of the next cycle CLK_MINOFF, thereby achieving cross-cycle operation; when MAXDUTY_FLG is set to 0, the switch signal DRV1 shows the minimum off time again, jumps out of the cross-cycle mode, and thus resumes normal fixed-cycle operation.

[0022] The circuit structure of the present invention for realizing full duty cycle control processing for peak current mode DCDC is adopted. A new method for generating minimum on-time and minimum off-time is used. When the chip is detected to be in the maximum duty cycle state, it does not directly switch to BYPASS direct mode, but increases the time of the current working cycle by crossing the cycle, so that the DCDC can work to any value between the maximum duty cycle and 100% duty cycle, ensuring the continuity of the duty cycle value. This not only avoids the occurrence of burrs with too small off time in the switching signal, but also can smoothly transition to full duty cycle operation. At the same time, because the switching signal works across cycles, the subharmonic components generated are multiples of the cycle, reducing the influence of clutter EMI. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a current mode DCDC structure diagram used in the prior art.

[0024] Figure 2 This is a schematic diagram of the conventional current mode DCDC control logic structure.

[0025] Figure 3 It is a schematic diagram of the current mode DCDC control logic structure of the present invention.

[0026] Figure 4 It is the waveform diagram of each signal in the control logic of the present invention.

[0027] Figure 5 (a) to (c) are input and output voltage comparison curves of the present invention. DETAILED DESCRIPTION

[0028] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0029] Before describing in detail embodiments according to the present invention, it should be noted that, hereinafter, the terms "comprises", "includes" or any other variations are intended to cover non-exclusive inclusion, whereby a process, method, article or apparatus comprising a series of elements includes not only these elements, but also other elements not explicitly listed or inherent to such process, method, article or apparatus.

[0030] like Figure 2 As shown, it is a conventional peak current mode DCDC control logic circuit, wherein the inverters I11, I12, I13, the NOR gate I14, and the capacitor C11 are the falling edge trigger pulse generation circuits, and a high level pulse signal is generated every time the falling edge of CLK is detected. I15 and I16 are RS triggers, and whenever the rising edge of CLK comes, the DRV0 signal will jump low and turn off the upper tube. When the high level of CLK ends and the falling edge jumps, I14 outputs a high level pulse, I15 outputs a low level, and I16 outputs DRV0 jumps high to charge the external inductor. When the external inductor is charged to the preset peak current, PWM_PULSE will output a high level pulse, so that the RS trigger output is cleared to 0, the DRV signal jumps low, the upper tube is turned off, the lower tube is turned on, and the external inductor is discharged until the next CLK falling edge comes, and it repeats over and over again, and finally generates a fixed frequency duty cycle control signal DRV to periodically switch the power tube switch and adjust the output voltage to stabilize at the set value.

[0031] The current practice is to design CLK as a clock signal with a small duty cycle, which can ensure the minimum off time and avoid the subsequent drive errors caused by glitches due to the DRV low level time being too short. However, this brings another defect: when the input is getting closer to the output, the duty cycle will have an upper limit, that is: Dmax = 1-tmin_off / Tclk, where tmin_off is the high level time of CLK, and Tclk is the working cycle of the system clock CLK; therefore, the original logic cannot achieve full duty cycle operation.

[0032] In view of the above-mentioned defects, this technical solution proposes a new control method:

[0033] First, change the original minimum off-time control method to avoid the high level of CLK directly turning off the upper tube (DRV is set to 0). At the same time, design a full duty cycle detection logic to determine when the chip reaches the maximum duty cycle state.

[0034] The judgment basis is as follows: As the input gets closer to the output, the duty cycle gets larger. If the inductor current detection signal does not trigger the PWM_PULSE signal to jump high from the beginning of a cycle to the end of the cycle, it means that the chip is in the maximum duty cycle state.

[0035] In order to avoid subsequent driving errors caused by glitches due to too short a DRV low level time, when it is detected that the DCDC is working in the maximum duty cycle state, instead of further increasing the maximum duty cycle setting value, the cross-cycle mode is turned on, that is, the upper tube remains on at the beginning of the next cycle. The upper tube is turned off at the beginning of the next cycle until PWM_PULSE jumps high. After the upper tube is turned off, the lower tube is turned on and maintained for the minimum on time before turning off. The upper tube is turned on again and enters normal cycle operation.

[0036] Since the inter-cycle mode can span any cycle, in principle, any value between the maximum duty cycle and 100% duty cycle can be achieved. If PWM_PULSE does not jump high after entering the inter-cycle mode, it means that the input is infinitely close to the output, the inductor current rising slope is 0, and the upper tube remains on, that is, it enters the BYPASS direct mode.

[0037] See also Figure 3 As shown, the circuit structure for implementing full duty cycle control processing for peak current mode DCDC, wherein the circuit structure includes:

[0038] A minimum off-time logic unit is used to detect the rising edge of a clock signal and generate a low-level pulse signal accordingly;

[0039] A minimum on-time logic unit, connected to the minimum off-time logic unit, for obtaining the minimum on-time of the circuit structure;

[0040] A full duty cycle detection logic unit is connected to the minimum off time logic unit and is used to sample the PWM signal according to the falling edge of the low level pulse signal to detect whether the current circuit structure reaches the maximum duty cycle state; and

[0041] The cross-cycle control logic unit is connected to the minimum off-time logic unit, the minimum on-time logic unit and the full duty cycle detection logic unit, and is used to perform cross-cycle control processing on the input signal that meets the maximum duty cycle state according to the detection state of the full duty cycle detection logic unit.

[0042] As a preferred embodiment of the present invention, the minimum off-time logic unit includes: an inverter I21, an inverter I22, an inverter I23, a NAND gate I24 and an AND gate I26 connected in sequence, a capacitor C21 is also arranged between the inverter I21 and the inverter I22, wherein the NAND gate I24 and the AND gate I26 are connected through a D flip-flop I25, the D terminal of the D flip-flop I25 is connected to VDD, the CLK terminal is connected to the CLK_MINOFF signal output by the NAND gate I24, the R terminal is connected to the PWM_PULSE signal, the output Q terminal is used to output a PWM signal, and the PWM signal is connected to the input terminal of the AND gate I26, thereby realizing pulse width modulation logic.

[0043] As a preferred embodiment of the present invention, the minimum on-time logic unit includes a D flip-flop I27, an inverter I34 and a delay unit, the inverter I34 is connected to the XQ end of the D flip-flop I27, and the delay unit is connected to the Q end of the D flip-flop I27, wherein the delay unit includes an inverter I28, an inverter I29 and an inverter I30 connected in sequence, and a capacitor C22 is arranged between the inverter I28 and the inverter I29.

[0044] As a preferred embodiment of the present invention, the D terminal of the D flip-flop I27 is connected to VDD, and the CLK terminal is connected to the output terminal of the AND gate I26. When the output of the AND gate I26 jumps high, the Q terminal of the D flip-flop I27 jumps high, and the XQ terminal jumps low, and outputs a high level after being processed by the inverter I34; when the output of the AND gate I26 jumps low, the XQ terminal of the D flip-flop I27 maintains a low level, and the XQ terminal is set to 1 through the delay unit, thereby obtaining the minimum conduction time.

[0045] As a preferred embodiment of the present invention, the full duty cycle detection logic unit is composed of an inverter I31 and a D flip-flop I32, wherein the inverter I31 is connected to the CLK_MINOFF signal, and the output end is connected to the CLK end of the D flip-flop I32, and the D end of the D flip-flop I32 is connected to the Q end of the D flip-flop I25.

[0046] As a preferred embodiment of the present invention, the full duty cycle detection logic unit specifically performs the following processing:

[0047] When the CLK_MINOFF signal is in the falling edge cycle, the PWM signal is sampled and processed. If the sampling value is 0, the maximum duty cycle state has not been reached at present, and the output signal MAXDUTY_FLG of the D flip-flop I32 is set to 0; if the sampling value is 1, the maximum duty cycle state has been reached at present, and the output signal MAXDUTY_FLG is set to 1 and continues until the falling edge of the CLK_MINOFF signal of the next cycle arrives, thereby completing the full duty cycle detection.

[0048] As a preferred embodiment of the present invention, the cross-cycle control logic unit is implemented by an OR gate I33, wherein the input end of the OR gate I33 is respectively connected to the inverter I34, the AND gate I26 and the Q end of the D flip-flop I32, and the output end of the OR gate I33 serves as the switching signal DRV1 of the power switch tube.

[0049] As a preferred embodiment of the present invention, the cross-cycle control logic unit specifically performs the following processing:

[0050] When the system does not reach the maximum duty cycle state, MAXDUTY_FLG=0, and the switch signal DRV1 is equal to the duty cycle control signal DRV through the OR gate I33; when the system reaches the maximum duty cycle state, the output signal MAXDUTY_FLG=1, and it lasts until the falling edge of the next cycle CLK_MINOFF signal;

[0051] Through the OR gate I33, MAXDUTY_FLG=1, and the switch signal DRV1 is forcibly set to 1, and continues until the falling edge of the next cycle CLK_MINOFF, thereby achieving cross-cycle operation; when MAXDUTY_FLG is set to 0, the switch signal DRV1 shows the minimum off time again, jumps out of the cross-cycle mode, and thus resumes normal fixed-cycle operation.

[0052] The control method of the present technical solution will be further described below in conjunction with specific implementation methods. The control logic circuit includes minimum off-time logic, minimum on-time logic, pulse width modulation logic, full duty cycle detection logic and cross-cycle control logic, as follows:

[0053] Inverters I21, I22, I23, NAND gate I24, capacitors C21 and I26 constitute a minimum off-time logic; each time a rising edge of CLK is detected, a low-level pulse CLK_MINOFF signal is generated.

[0054] The D terminal of D flip-flop I25 is connected to VDD, the CLK terminal is connected to the CLK_MINOFF signal, the R terminal is connected to the PWM_PULSE signal, and the output Q terminal is a PWM signal to implement pulse width modulation logic. When the CLK_MINOFF signal jumps high, the Q terminal of D flip-flop I25 outputs a high level, which not only avoids the CLK rising edge directly turning off the upper tube, but also reserves the minimum off time, which is convenient for later cross-cycle operation.

[0055] Inverters I28, I29, I30, I34, and D flip-flop I27 form the minimum on-time logic. When the output of I26 jumps high, the Q end of the D flip-flop I27 jumps high, and the XQ end jumps low, and outputs a high level after passing through the inverter I34. When the output of I26 jumps low, the XQ end of the D flip-flop I27 maintains a low level, and waits for the Q end to pass through the delay unit composed of I28, I29, I30, and C22 before setting the XQ end to 1, thereby obtaining a minimum on-time to avoid the subsequent drive errors caused by glitches due to the DRV high level time being too short;

[0056] I31 and I32 form a full duty cycle detection logic, where the input of the inverter I31 is connected to the CLK_MINOFF signal, and the output is connected to the CLK terminal of the D flip-flop I32; the D terminal of the D flip-flop I32 is connected to the Q terminal of I25;

[0057] The working principle of the full duty cycle detection logic is as follows: use the falling edge of CLK_MINOFF to sample the PWM signal. If the sampled value is 0, it means that the maximum duty cycle state has not been reached, and MAXDUTY_FLG is set to 0; if the sampled value is 1, it means that the maximum duty cycle state has been reached, and MAXDUTY_FLG is set to 1, and it continues until the falling edge of CLK_MINOFF in the next cycle.

[0058] The OR gate I33 implements the cross-cycle control logic, the input end of the OR gate I33 is connected to the Q end of the D flip-flop I32, the other input end of the OR gate I33 is connected to the output end of I26, and the output end of the OR gate I33 serves as the switching signal DRV1 of the power switch tube.

[0059] The working principle of the cross-cycle logic is as follows: when the system does not reach the maximum duty cycle state, MAXDUTY_FLG = 0, through the OR gate I33, the DRV1 signal is equal to the DRV signal; when the system reaches the maximum duty cycle state, MAXDUTY_FLG = 1, and it will continue until the falling edge of the next cycle CLK_MINOFF. Through the OR gate I33, MAXDUTY_FLG = 1 will force DRV1 to 1, and the DRV1 signal will skip the minimum off-time pulse and continue until the falling edge of the next cycle CLK_MINOFF, thus achieving a skip cycle. When MAXDUTY_FLG is set to 0, DRV1 will have the minimum off-time again, jump out of the cross-cycle mode, and resume normal fixed-cycle operation.

[0060] In practical applications, Figure 4 The following are examples of the waveform diagrams of various signals in the control logic:

[0061] In the first three cycles, PWM_PULSE has a high level pulse in each cycle, and DRV1, like DRV, outputs a duty cycle signal with a fixed frequency;

[0062] In the fourth cycle, there is no high-level pulse in PWM_PULSE. Then, at the rising edge of CLK_MINIOFF in the fifth cycle, MAXDUTY_FLG jumps to 1, and the DRV1 output maintains a high level, spanning the minimum off time of the next (fifth) cycle.

[0063] In the fifth cycle, PWM_PULSE has a high-level pulse, and DRV1 has a minimum off time in the next (sixth) cycle and then jumps high again;

[0064] In the 6th and 7th CLK cycles, there is no high-level pulse in PWM_PULSE. Then, at the rising edge of CLK_MINIOFF in the 7th cycle, MAXDUTY_FLG jumps to 1, and the DRV1 output maintains a high level, spanning the 7th and 8th minimum off times.

[0065] In the 8th CLK cycle, PWM_PULSE has a high-level pulse, and DRV1 has a minimum off time in the next (9th) cycle and then jumps high again;

[0066] In the 9th, 10th, 11th, and 12th CLK cycles, there is no high-level pulse in PWM_PULSE. Then, at the rising edge of the 10th CLK_MINIOFF, MAXDUTY_FLG jumps to 1, and the DRV1 output maintains a high level thereafter.

[0067] From the above waveform, we can see that when the duty cycle is getting larger and larger and exceeds the maximum duty cycle, it will enter the cross-cycle mode. In the cross-cycle mode, with the different appearance time of PWM_PULSE, an arbitrary duty cycle value greater than the maximum duty cycle can be obtained. After entering the cross-cycle mode, if PWM_PULSE has not jumped high, it means that the input is infinitely close to the output, and the upper tube has been kept in the open state, it will enter the BYPASS direct mode.

[0068] Figure 5 This is the input-output voltage comparison curve. It can be seen that as the input voltage decreases and slowly approaches VOUT:

[0069] Figure 5 (a) shows the effect diagram of the input-output voltage curve before the present technical solution is adopted. After the input drops to a certain level close to VOUT, VOUT will slowly decrease because it is limited by the maximum duty cycle.

[0070] Figure 5 (b) shows the effect of the input-output voltage curve after switching in direct-pass mode. When the input is close to VOUT to a certain extent, it is detected that it is at the maximum duty cycle, and it directly outputs 100% duty cycle and enters direct-pass mode. The input is equal to the output, and the output voltage shows a large jump during the switching process.

[0071] Figure 5 (c) shows the curve change of input and output voltage after adopting this technical solution. When the input is close to VOUT to a certain extent, it is detected that it is at the maximum duty cycle, and it enters the skip cycle mode to stabilize the output voltage. Only when the input is equal to VOUT, VOUT will decrease with VIN and enter the direct pass state. When the input increases and exceeds the VOUT set voltage, VOUT remains unchanged and exits the direct pass state.

[0072] Based on the above description, this technical solution realizes full duty cycle operation through full duty cycle detection and cross-cycle logic, and avoids direct switching between maximum duty cycle and 100% duty cycle, eliminating the problem of intermediate fault between maximum duty cycle and 100% duty cycle. As the input voltage and output voltage gradually approach, the duty cycle can smoothly transition to 100%. In summary, this technical solution realizes continuous and smooth conversion from duty cycle to 100% by improving the logic control circuit, reduces the ripple of output voltage during switching, and has a simple circuit design, which can be easily extended to any current mode control DCDC system.

[0073] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0074] It should be understood that each part of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution device.

[0075] A person of ordinary skill in the art may understand that all or part of the steps of the method for implementing the above-mentioned embodiment may be completed by instructing the relevant hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one of the steps of the method embodiment or a combination thereof.

[0076] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0077] In the description of this specification, the description with reference to the terms "an embodiment", "some embodiments", "example", "specific example", or "embodiment" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0078] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

[0079] The circuit structure of the present invention for realizing full duty cycle control processing for peak current mode DCDC is adopted. A new method for generating minimum on-time and minimum off-time is used. When the chip is detected to be in the maximum duty cycle state, it does not directly switch to BYPASS direct mode, but increases the time of the current working cycle by crossing the cycle, so that the DCDC can work to any value between the maximum duty cycle and 100% duty cycle, ensuring the continuity of the duty cycle value. This not only avoids the occurrence of burrs with too small off time in the switching signal, but also can smoothly transition to full duty cycle operation. At the same time, because the switching signal works across cycles, the subharmonic components generated are multiples of the cycle, reducing the influence of clutter EMI.

[0080] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A circuit structure for implementing full duty cycle control processing for peak current mode DCDC, It is characterized in that The circuit structure comprises: A minimum off-time logic unit is used to detect the rising edge of a clock signal and generate a low-level pulse signal accordingly; A minimum on-time logic unit, connected to the minimum off-time logic unit, for obtaining the minimum on-time of the circuit structure; A full duty cycle detection logic unit is connected to the minimum off time logic unit and is used to sample the PWM signal according to the falling edge of the low level pulse signal to detect whether the current circuit structure reaches the maximum duty cycle state; and The cross-cycle control logic unit is connected to the minimum off-time logic unit, the minimum on-time logic unit and the full duty cycle detection logic unit, and is used to perform cross-cycle control processing on the input signal that meets the maximum duty cycle state according to the detection state of the full duty cycle detection logic unit.

2. The circuit structure for implementing full duty cycle control processing for peak current mode DCDC according to claim 1, It is characterized in that The minimum off-time logic unit includes: an inverter I21, an inverter I22, an inverter I23, a NAND gate I24 and an AND gate I26 connected in sequence, a capacitor C21 is also arranged between the inverter I21 and the inverter I22, wherein the NAND gate I24 and the AND gate I26 are connected through a D flip-flop I25, the D terminal of the D flip-flop I25 is connected to VDD, the CLK terminal is connected to the CLK_MINOFF signal output by the NAND gate I24, the R terminal is connected to the PWM_PULSE signal, the output Q terminal is used to output a PWM signal, and the PWM signal is connected to the input terminal of the AND gate I26, thereby realizing pulse width modulation logic.

3. The circuit structure for implementing full duty cycle control processing for peak current mode DCDC according to claim 2, It is characterized in that The minimum on-time logic unit includes a D flip-flop I27, an inverter I34 and a delay unit, wherein the inverter I34 is connected to the XQ end of the D flip-flop I27, and the delay unit is connected to the Q end of the D flip-flop I27, wherein the delay unit includes an inverter I28, an inverter I29 and an inverter I30 connected in sequence, and a capacitor C22 is arranged between the inverter I28 and the inverter I29.

4. The circuit structure for implementing full duty cycle control processing for peak current mode DCDC according to claim 3, It is characterized in that The D terminal of the D flip-flop I27 is connected to VDD, and the CLK terminal is connected to the output terminal of the AND gate I26. When the output of the AND gate I26 jumps high, the Q terminal of the D flip-flop I27 jumps high, and the XQ terminal jumps low, and outputs a high level after being processed by the inverter I34; when the output of the AND gate I26 jumps low, the XQ terminal of the D flip-flop I27 maintains a low level, and the XQ terminal is set to 1 through the delay unit, thereby obtaining the minimum conduction time.

5. The circuit structure for implementing full duty cycle control processing for peak current mode DCDC according to claim 3, It is characterized in that The full duty cycle detection logic unit is composed of an inverter I31 and a D flip-flop I32, wherein the inverter I31 is connected to the CLK_MINOFF signal, and the output end is connected to the CLK end of the D flip-flop I32, and the D end of the D flip-flop I32 is connected to the Q end of the D flip-flop I25.

6. The circuit structure for implementing full duty cycle control processing for peak current mode DCDC according to claim 5, It is characterized in that The full duty cycle detection logic unit specifically performs the following processing: When the CLK_MINOFF signal is in the falling edge cycle, the PWM signal is sampled and processed. If the sampling value is 0, the maximum duty cycle state has not been reached at present, and the output signal MAXDUTY_FLG of the D flip-flop I32 is set to 0; if the sampling value is 1, the maximum duty cycle state has been reached at present, and the output signal MAXDUTY_FLG is set to 1 and continues until the falling edge of the CLK_MINOFF signal of the next cycle arrives, thereby completing the full duty cycle detection.

7. The circuit structure for implementing full duty cycle control processing for peak current mode DCDC according to claim 5, It is characterized in that The cross-cycle control logic unit is implemented by an OR gate I33, wherein the input end of the OR gate I33 is respectively connected to the inverter I34, the AND gate I26 and the Q end of the D flip-flop I32, and the output end of the OR gate I33 serves as the switching signal DRV1 of the power switch tube.

8. The circuit structure for implementing full duty cycle control processing for peak current mode DCDC according to claim 7, It is characterized in that The cross-cycle control logic unit specifically performs the following processing: When the system does not reach the maximum duty cycle state, MAXDUTY_FLG=0, and the switch signal DRV1 is equal to the duty cycle control signal DRV through the OR gate I33; when the system reaches the maximum duty cycle state, the output signal MAXDUTY_FLG=1, and it lasts until the falling edge of the next cycle CLK_MINOFF signal; Through the OR gate I33, MAXDUTY_FLG=1, and the switch signal DRV1 is forcibly set to 1, and continues until the falling edge of the next cycle CLK_MINOFF, thereby achieving cross-cycle operation; when MAXDUTY_FLG is set to 0, the switch signal DRV1 shows the minimum off time again, jumps out of the cross-cycle mode, and thus resumes normal fixed-cycle operation.

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