Frequency dividing circuit and method, frequency divider and electronic equipment

Abstract

The invention relates to the technical field of signal frequency division, and further relates to a frequency division circuit and method, a frequency divider and electronic equipment. The circuit comprises a start-stop control circuit which is configured to control the opening or closing of a frequency dividing circuit based on an enable signal; a frequency division coefficient selection circuit configured to select a frequency division coefficient based on an external input signal when the frequency division circuit is turned on; the frequency division output circuit is configured to perform frequency division processing on the external input signal based on the frequency division coefficient and obtain a first output signal; the phase marking circuit is configured to perform phase marking processing on the first output signal based on the frequency division coefficient and the external input signal and output a phase marking signal, and the phase marking signal is used for reflecting the phase relation between the external input signal and the first output signal. The circuit improves the accuracy of transmission synchronization of signals from high frequency to low frequency or from low frequency to high frequency.

Description

Technical Field

[0001] The present application relates to the technical field of signal frequency division, and further to a frequency division circuit, method, frequency divider and electronic equipment. Background Art

[0002] In traditional designs, the frequency division circuit lacks enable control and cannot be started or stopped at will, which limits its flexibility in practical applications. In addition, these circuits only support basic integer frequency division and cannot provide any indication of the phase relationship of the clock before and after the frequency division, which in turn affects the accuracy of the transmission synchronization of the signal from high frequency to low frequency or from low frequency to high frequency. Summary of the invention

[0003] In order to solve the above technical problems, the present application provides a frequency division circuit, method, frequency divider and electronic device, which improve the accuracy of transmission synchronization of signals from high frequency to low frequency or from low frequency to high frequency.

[0004] In a first aspect, the present application provides a frequency division circuit, comprising: a start-stop control circuit, configured to control the opening or closing of the frequency division circuit based on an enable signal; a frequency division coefficient selection circuit, configured to select a frequency division coefficient based on an external input signal when the frequency division circuit is turned on; a frequency division output circuit, configured to perform frequency division processing on the external input signal based on the frequency division coefficient, and obtain a first output signal; a phase mark circuit, configured to perform phase mark processing on the first output signal based on the frequency division coefficient and the external input signal, and output a phase mark signal, wherein the phase mark signal is used to reflect the phase relationship between the external input signal and the first output signal.

[0005] The above frequency division circuit can randomly start or stop the frequency division circuit by setting a start-stop control circuit, thereby improving the flexibility of the frequency division circuit. In addition, the frequency division signal is subjected to phase marking processing by the phase marking circuit to obtain a phase marking signal, and the phase marking signal is used to indicate the phase relationship between the external input signal and the first output signal, thereby improving the accuracy of the transmission synchronization of the signal from high frequency to low frequency or from low frequency to high frequency.

[0006] In one implementation, when the frequency division coefficient is a first preset value, the phase mark signal is at a high level; when the frequency division coefficient is not the first preset value, the phase mark signal maintains a high level for a preset time before each rising edge of the first output signal.

[0007] In one implementation, the phase mark circuit includes: a judgment circuit configured to judge whether the frequency division coefficient is a first preset value; and a combination circuit configured to output the phase mark signal based on the judgment result and the external input signal.

[0008] The above frequency division circuit checks whether the frequency division coefficient is the first preset value through the judgment circuit. If it is, the phase mark signal will maintain a high level state; if not, the phase mark signal will output a high level pulse before the rising edge of each first output signal to indicate the phase of the signal after frequency division. Different phase mark signals are generated according to different frequency division coefficients, which further improves the flexibility of the frequency division circuit and the accuracy of signal transmission synchronization.

[0009] In one implementation, it also includes: a first clock gating circuit, wherein the input end of the first clock gating circuit is connected to the frequency division coefficient selection circuit, and the output end of the first clock gating circuit is connected to an AND-OR gate.

[0010] In one implementation, the frequency division coefficient selection circuit includes: a frequency division coefficient control circuit, configured to decrement the frequency division coefficient based on preset conditions and output the decrement result; a selection circuit, configured to select the corresponding frequency division coefficient based on the decrement result and the frequency of the external input signal.

[0011] In one implementation, the frequency division coefficient control circuit is configured to control the first clock gating circuit to output an undivided signal when the frequency division coefficient is a first preset value, and use the undivided signal as the first output signal.

[0012] The design of the first clock gating circuit in the above frequency division circuit realizes dynamic frequency control of the external input signal by working in coordination with the frequency division coefficient control circuit. The frequency division coefficient control circuit decreases the frequency division coefficient according to the preset conditions, and the selection circuit selects the most appropriate frequency division coefficient based on the decrease result and the input signal frequency. Not only the flexibility of the frequency division circuit is improved, but also the synchronization of signal transmission and the response efficiency of the frequency division circuit are ensured through the precise selection of the frequency division coefficient. In addition, the output end of the first clock gating circuit is connected to the OR gate, which further ensures that at any given moment, the frequency division circuit can output the correct clock signal, whether it is the original signal without frequency division or the signal after precise frequency division, thereby improving the reliability and performance of the entire frequency division circuit.

[0013] In one implementation, it includes: a second clock gating circuit configured to control the on or off of the clock of the frequency dividing circuit based on the enable signal.

[0014] In the above frequency division circuit, the second clock gating circuit dynamically controls the opening or closing of the frequency division circuit clock through the enable signal, thereby realizing effective management of power consumption. When the enable signal is at a high level, the second clock gating circuit allows the external input signal to pass through, ensuring the normal operation of the frequency division circuit; and when the enable signal is at a low level, the second clock gating circuit is closed, prohibiting the external input signal from entering the frequency division circuit, reducing the power consumption of the frequency division circuit, and at the same time reducing the burrs generated during the opening or closing of the frequency division circuit.

[0015] In a second aspect, the present application further provides a frequency division method, comprising: when the frequency division circuit is turned on, according to the external input signal, controlling the frequency division coefficient selection circuit to select the frequency division coefficient; according to the frequency division coefficient, controlling the frequency division output circuit to perform frequency division processing on the external input signal and obtain a first output signal. According to the frequency division coefficient and the external input signal, controlling the phase mark circuit to perform phase mark processing on the first output signal and output a phase mark signal, wherein the phase mark signal is used to reflect the phase relationship between the external input signal and the first output signal.

[0016] The above frequency division method can randomly start or stop the frequency division circuit by setting a start-stop control circuit, thereby improving the flexibility of the frequency division circuit. In addition, the frequency division signal is subjected to phase marking processing by the phase marking circuit to obtain a phase marking signal, and the phase marking signal is used to indicate the phase relationship between the external input signal and the first output signal, thereby improving the accuracy of the transmission synchronization of the signal from high frequency to low frequency or from low frequency to high frequency.

[0017] In a third aspect, the present application also provides a frequency divider, comprising any of the frequency dividing circuits described above.

[0018] In a fourth aspect, the present application also provides an electronic device, comprising any of the frequency division circuits described above.

[0019] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0020] 1. By setting a start-stop control circuit, the frequency division circuit can be started or stopped randomly, thereby improving the flexibility of the frequency division circuit. In addition, the frequency division signal is subjected to phase marking processing by the phase marking circuit to obtain a phase marking signal, which is used to indicate the phase relationship between the external input signal and the first output signal, thereby improving the accuracy of the transmission synchronization of the signal from high frequency to low frequency or from low frequency to high frequency.

[0021] 2. Check whether the frequency division coefficient is the first preset value through the judgment circuit. If it is, the phase mark signal will remain in a high level state; if not, the phase mark signal will output a high level pulse before the rising edge of each first output signal to indicate the phase of the signal after frequency division. Different phase mark signals are generated according to different frequency division coefficients, which further improves the flexibility of the frequency division circuit and the accuracy of signal transmission synchronization.

[0022] 3. The design of the first clock gating circuit realizes dynamic frequency control of the external input signal by working in conjunction with the frequency division coefficient control circuit. The frequency division coefficient control circuit decreases the frequency division coefficient according to the preset conditions, and the selection circuit selects the most appropriate frequency division coefficient based on the decrease result and the input signal frequency. Not only the flexibility of the frequency division circuit is improved, but also the synchronization of signal transmission and the response efficiency of the frequency division circuit are ensured through accurate frequency division coefficient selection. In addition, the output end of the first clock gating circuit is connected to the OR gate, which further ensures that at any given moment, the frequency division circuit can output the correct clock signal, whether it is the original signal without frequency division or the signal after accurate frequency division, thereby improving the reliability and performance of the entire frequency division circuit.

[0023] 4. The second clock gating circuit dynamically controls the opening or closing of the frequency division circuit clock through the enable signal to achieve effective management of power consumption. When the enable signal is at a high level, the second clock gating circuit allows the external input signal to pass through to ensure the normal operation of the frequency division circuit; when the enable signal is at a low level, the second clock gating circuit is closed, prohibiting the external input signal from entering the frequency division circuit, reducing the power consumption of the frequency division circuit, and at the same time reducing the burrs generated during the opening or closing of the frequency division circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The preferred implementation modes will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present invention.

[0025] Figure 1 A frame diagram of a frequency division circuit provided in an embodiment of the present application is shown;

[0026] Figure 2 A schematic diagram of a frequency division circuit provided in an embodiment of the present application is shown;

[0027] Figure 3 A timing diagram of a signal provided by an embodiment of the present application is shown;

[0028] Figure 4 A flow chart of a frequency division method provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0030] In order to simplify the drawings, only the parts related to the invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0031] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0032] In this document, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0034] It should be noted that the above embodiments can be freely combined as needed. The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.

[0035] The main function of the frequency division circuit is to convert a high-frequency signal into a signal with a lower frequency. In digital circuits and communication systems, frequency division circuits are widely used in key areas such as clock management, signal synchronization, and data transmission. They mainly realize the frequency division of signals through the decrement and comparison mechanism of the counter. It usually adopts two ways to realize frequency division: even frequency division and odd frequency division. In even frequency division, the counter will be decremented to half of the frequency division coefficient, and then the control register will be flipped to realize frequency division. In odd frequency division, the counter of the falling edge clock is used to decrement and compare. However, there are some limitations in the frequency division circuit, such as no enable control, and the frequency division process cannot be started or stopped at will; and the phase relationship between the two clocks before and after the frequency division cannot be indicated. Therefore, the present application realizes the opening or closing of the frequency division circuit by setting a start-stop control circuit on the frequency division circuit, and reflects the phase relationship between the input signal and the output signal through the phase mark signal. At least one of the following beneficial effects can be achieved: the accuracy of the transmission synchronization of the signal from high frequency to low frequency or from low frequency to high frequency and the flexibility of the frequency division circuit are improved; or, the power consumption of the frequency division circuit is reduced.

[0036] The following is explained with reference to the accompanying drawings:

[0037] Reference Figure 1 , which shows a framework diagram of a frequency division circuit provided by an embodiment of the present application. Figure 1 As shown, it includes: a start-stop control circuit 100, a frequency division coefficient selection circuit 200, a frequency division output circuit 300 and a phase mark circuit 400. The start-stop control circuit 100 is configured to control the start or stop of the frequency division circuit based on an enable signal; the frequency division coefficient selection circuit 200 is configured to select the frequency division coefficient based on an external input signal when the frequency division circuit is turned on; the frequency division output circuit 300 is configured to perform frequency division processing on the external input signal based on the frequency division coefficient and obtain a first output signal; the phase mark circuit 400 is configured to perform phase mark processing on the first output signal based on the frequency division coefficient and the external input signal, and output a phase mark signal, and the phase mark signal is used to reflect the phase relationship between the external input signal and the first output signal.

[0038] The external input signal may be a clock signal, a data signal, an analog signal, a test signal, a signal processing signal, or other periodic signals.

[0039] Taking the external input signal as a clock signal as an example, the start-stop control circuit 100 is used to control the opening or closing of the frequency division circuit according to the enable signal (for example, the enable signal can be Div_en). For example, when the enable signal is at a low level (Div_en=0), the start-stop control circuit 100 controls the frequency division circuit to be closed; when the enable signal is at a high level (Div_en=1), the start-stop control circuit 100 controls the frequency division circuit to be opened. Among them, there is also a flag signal (for example, the flag signal can be Stop) for whether the frequency division circuit works normally. When the flag signal is at a high level (Stop=1), it indicates that the frequency division circuit is closed; when the flag signal is at a low level (Stop=0), it indicates that the frequency division circuit is working.

[0040] After the start-stop control circuit 100 controls the frequency division circuit to work normally, the frequency division coefficient selection circuit 200 selects the corresponding frequency division coefficient from the preset frequency division coefficient range according to the frequency of the external input signal. The frequency division output circuit 300 performs frequency division processing on the external input signal according to the frequency division coefficient to obtain a frequency division signal, which is the first output signal. Among them, if the selected frequency division coefficient is a first preset value (for example, the first preset value can be 0), the external input signal is not subjected to frequency division processing, and the first output signal is essentially the external input signal. Then, the phase mark circuit 400 performs phase mark processing on the first output signal according to the frequency division coefficient and the external input signal to obtain a phase mark signal.

[0041] The embodiment of the present application can randomly start or stop the frequency division circuit by setting a start-stop control circuit, thereby improving the flexibility of the frequency division circuit. In addition, the frequency division signal is processed by the phase mark circuit to obtain a phase mark signal, and the phase mark signal is used to indicate the phase relationship between the external input signal and the first output signal, thereby improving the accuracy of the transmission synchronization of the signal from high frequency to low frequency or from low frequency to high frequency.

[0042] Reference Figure 2 , which shows a schematic diagram of a frequency division circuit provided by an embodiment of the present application. Figure 2 As shown, the phase mark circuit 400 includes: a judgment circuit 410 and a combination circuit 420. The judgment circuit 410 is configured to judge whether the frequency division coefficient is a first preset value; the combination circuit 420 is configured to output a phase mark signal based on the judgment result and an external input signal.

[0043] Before frequency division processing is performed on the external input signal, the range of the frequency division coefficient Ndiv[3:0] is first set, and the range of the frequency division coefficient Ndiv[3:0] can be set according to the requirements, for example, it can be 0 to 15. When the frequency division coefficient Ndiv[3:0] is a first preset value, the frequency phase of the external input signal Clk_in and the first output signal Clkout is the same, that is, the external input signal Clk_in=the first output signal Clkout.

[0044] Similarly, after the start-stop control circuit 100 controls the frequency division circuit to work normally, the frequency division coefficient selection circuit 200 selects a corresponding value from the range of the frequency division coefficient Ndiv[3:0], and then the frequency division output circuit 300 performs frequency division processing on the external input signal according to the frequency division coefficient Ndiv[3:0] to obtain the corresponding first output signal Clkout. The judgment circuit 410 judges whether the value of the frequency division coefficient Ndiv[3:0] selected by the frequency division coefficient selection circuit 200 is the first preset value. When the value of the frequency division coefficient Ndiv[3:0] is the first preset value, the external input signal Clk_in = the first output signal Clkout, and the phase mark signal Clksync output by the combination circuit 420 is maintained at a high level (refer to the attached Figure 3 , that is, the phase mark signal Clksync=1); when the value of the frequency division coefficient Ndiv[3:0] is not the first preset value, the first output signal Clkout is the frequency division signal R_divclk after the frequency division output circuit 300 is processed by the frequency division, and the phase mark signal Clksync output by the combination circuit 420 is maintained for a preset time (for example, refer to the attached figure) before the rising edge of each first output signal Clkout. Figure 3 The preset time may be a high level pulse of one cycle of the external input signal Clk_in).

[0045] In the embodiment of the present application, the judgment circuit checks whether the frequency division coefficient is a first preset value. If so, the phase mark signal will remain in a high level state; if not, the phase mark signal will output a high level pulse before the rising edge of each first output signal to indicate the phase of the signal after frequency division. Different phase mark signals are generated according to different frequency division coefficients, further improving the flexibility of the frequency division circuit and the accuracy of signal transmission synchronization.

[0046] In some embodiments of the present application, refer to the attached Figure 2, further comprising: a first clock gating circuit 500, the input end of the first clock gating circuit 500 is connected to the frequency division coefficient selection circuit 200, and the output end of the first clock gating circuit 500 is connected to the AND gate OR. The frequency division coefficient selection circuit 200 further comprises: a frequency division coefficient control circuit 210, configured to decrement the frequency division coefficient based on a preset condition and output the decrement result; a selection circuit 220, configured to select the corresponding frequency division coefficient based on the decrement result and the frequency of the external input signal.

[0047] The frequency division coefficient control circuit 210 decrements the frequency division coefficient Ndiv[3:0] according to the preset conditions, and then determines whether to not perform frequency division processing on the external input signal Clk_in. For example, when the decrement result is the first preset value, the selection circuit 220 selects the value of the frequency division coefficient Ndiv[3:0] as the first preset value according to the decrement result. At this time, the frequency division output circuit 300 does not perform frequency division processing on the external input signal Clk_in, and the frequency division coefficient control circuit 210 controls the first clock gating circuit 500 to be turned on, so that the first clock gating circuit outputs the undivided signal Byp_clk based on the external input signal Clk_in. The undivided signal Byp_clk is obtained by the OR gate to obtain the first output signal Clkout, that is, the undivided signal Byp_clk = the external input signal Clk_in = the first output signal Clkout, and the frequency division signal R_divclk = 0. At this time, the phase mark signal Clksync output by the corresponding combination circuit 420 is maintained at a high level.

[0048] When the decrement result is not the first preset value, the selection circuit 220 selects the value of the corresponding frequency division coefficient Ndiv[3:0] according to the decrement result. At this time, the frequency division circuit 200 performs frequency division processing on the external input signal Clk_in based on the frequency division coefficient selected by the selection circuit 220 to obtain the frequency division signal R_divclk. The frequency division signal R_divclk is obtained by the AND gate OR to obtain the first output signal Clkout, that is, the first output signal Clkout = frequency division signal R_divclk = Clk_in / (Ndiv[3:0]+1), and the undivided signal Byp_clk = 0. At this time, the phase mark signal Clksync output by the corresponding combination circuit 420 maintains a high level pulse for a preset time before the rising edge of each first output signal Clkout.

[0049] In the embodiment of the present application, the design of the first clock gating circuit realizes dynamic frequency control of the external input signal by working in coordination with the frequency division coefficient control circuit. The frequency division coefficient control circuit decreases the frequency division coefficient according to the preset conditions, and the selection circuit selects the most appropriate frequency division coefficient based on the decrease result and the input signal frequency. Not only the flexibility of the frequency division circuit is improved, but also the synchronization of signal transmission and the response efficiency of the frequency division circuit are ensured by accurate frequency division coefficient selection. In addition, the output end of the first clock gating circuit is connected to the OR gate OR, which further ensures that at any given moment, the frequency division circuit can output the correct clock signal, whether it is the original signal without frequency division or the signal after accurate frequency division, thereby improving the reliability and performance of the entire frequency division circuit.

[0050] In some embodiments of the present application, refer to the attached Figure 2 , further comprising: a second clock gating circuit 600, configured to control the on or off of the clock of the frequency division circuit based on an enable signal. The frequency division output circuit 300 further comprises a frequency division control circuit 310, a register 320 and a latch 330. The latch 330 is connected to the second clock gating circuit 600 through a diode, and the register 320 is frequency-dividedly connected to the OR gate OR and the frequency division control circuit 310. The frequency division control circuit 310, the register 320 and the latch 330 cooperate with each other to complete the frequency division processing of the external input signal Clk_in.

[0051] In the embodiment of the present application, the second clock gating circuit dynamically controls the opening or closing of the frequency division circuit clock through the enable signal, thereby realizing effective management of power consumption. When the enable signal is at a high level, the second clock gating circuit allows the external input signal to pass through, ensuring the normal operation of the frequency division circuit; and when the enable signal is at a low level, the second clock gating circuit is closed, prohibiting the external input signal from entering the frequency division circuit, reducing the power consumption of the frequency division circuit, and at the same time reducing the burrs generated during the opening or closing of the frequency division circuit.

[0052] Reference Figure 4 , which shows a flow chart of a frequency division method provided by an embodiment of the present application. Figure 4 As shown, including:

[0053] S400, when the frequency division circuit is turned on, the frequency division coefficient selection circuit is controlled to select the frequency division coefficient according to the external input signal.

[0054] S410, controlling the frequency division output circuit to perform frequency division processing on the external input signal according to the frequency division coefficient, and obtaining a first output signal.

[0055] S420, according to the frequency division coefficient and the external input signal, control the phase mark circuit to perform phase mark processing on the first output signal, and output a phase mark signal, where the phase mark signal is used to reflect the phase relationship between the external input signal and the first output signal.

[0056] The start-stop control circuit is used to control the opening or closing of the frequency division circuit according to the enable signal (for example, the enable signal can be Div_en). For example, when the enable signal is at a low level (Div_en=0), the start-stop control circuit controls the frequency division circuit to be closed; when the enable signal is at a high level (Div_en=1), the start-stop control circuit controls the frequency division circuit to be opened. There is also a flag signal (for example, the flag signal can be Stop) to determine whether the frequency division circuit is working normally. When the flag signal is at a high level (Stop=1), it indicates that the frequency division circuit is closed; when the flag signal is at a low level (Stop=0), it indicates that the frequency division circuit is working.

[0057] After the start-stop control circuit controls the frequency division circuit to work normally, the frequency division coefficient selection circuit selects the corresponding frequency division coefficient from the preset frequency division coefficient range according to the frequency of the external input signal. The frequency division output circuit performs frequency division processing on the external input signal according to the frequency division coefficient to obtain a frequency division signal, which is the first output signal. Among them, if the selected frequency division coefficient is a first preset value (for example, the first preset value can be 0), the external input signal is not subjected to frequency division processing, and the first output signal is essentially the external input signal. Then, the phase mark circuit performs phase mark processing on the first output signal according to the frequency division coefficient and the external input signal to obtain a phase mark signal.

[0058] The embodiment of the present application can randomly start or stop the frequency division circuit by setting a start-stop control circuit, thereby improving the flexibility of the frequency division circuit. In addition, the frequency division signal is processed by the phase mark circuit to obtain a phase mark signal, and the phase mark signal is used to indicate the phase relationship between the external input signal and the first output signal, thereby improving the accuracy of the transmission synchronization of the signal from high frequency to low frequency or from low frequency to high frequency.

[0059] An embodiment of the present application further provides a frequency divider, comprising the frequency dividing circuit described in any of the above embodiments.

[0060] An embodiment of the present application further provides an electronic device, comprising the frequency division circuit described in any of the above embodiments.

[0061] It should be noted that the above embodiments can be freely combined as needed. The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A frequency division circuit, It is characterized in that include: A start-stop control circuit, configured to control the start or stop of the frequency division circuit based on an enable signal; A frequency division coefficient selection circuit configured to select a frequency division coefficient based on an external input signal when the frequency division circuit is turned on; A frequency division output circuit is configured to perform frequency division processing on the external input signal based on the frequency division coefficient and obtain a first output signal; The phase mark circuit is configured to perform phase mark processing on the first output signal based on the frequency division coefficient and the external input signal, and output a phase mark signal, wherein the phase mark signal is used to reflect the phase relationship between the external input signal and the first output signal.

2. The frequency division circuit according to claim 1, It is characterized in that When the frequency division coefficient is a first preset value, the phase mark signal is at a high level; when the frequency division coefficient is not the first preset value, the phase mark signal maintains a high level for a preset time before each rising edge of the first output signal.

3. The frequency division circuit according to claim 2, It is characterized in that The phase marking circuit comprises: A judging circuit configured to judge whether the frequency division coefficient is a first preset value; The combination circuit is configured to output the phase mark signal based on the determination result and the external input signal.

4. The frequency division circuit according to claim 1, It is characterized in that Also includes: A first clock gating circuit, wherein an input end of the first clock gating circuit is connected to the frequency division coefficient selection circuit, and an output end of the first clock gating circuit is connected to an AND-OR gate.

5. The frequency division circuit according to claim 4, It is characterized in that The frequency division coefficient selection circuit comprises: A frequency division coefficient control circuit, configured to decrement the frequency division coefficient based on a preset condition and output a decrement result; The selection circuit is configured to select the corresponding frequency division coefficient based on the decrement result and the frequency of the external input signal.

6. The frequency division circuit according to claim 5, It is characterized in that The frequency division coefficient control circuit is configured to control the first clock gating circuit to output an undivided signal when the frequency division coefficient is a first preset value, and use the undivided signal as the first output signal.

7. The frequency division circuit according to claim 1, It is characterized in that include: The second clock gating circuit is configured to control the on or off of the clock of the frequency dividing circuit based on the enable signal.

8. A frequency division method, It is characterized in that The frequency division circuit according to any one of claims 1 to 7 comprises: When the frequency division circuit is turned on, according to the external input signal, controlling the frequency division coefficient selection circuit to select the frequency division coefficient; According to the frequency division coefficient, controlling the frequency division output circuit to perform frequency division processing on the external input signal and obtain a first output signal; According to the frequency division coefficient and the external input signal, the phase mark circuit is controlled to perform phase mark processing on the first output signal and output a phase mark signal, wherein the phase mark signal is used to reflect the phase relationship between the external input signal and the first output signal.

9. A frequency divider, It is characterized in that The frequency dividing circuit comprises the frequency dividing circuit as described in any one of claims 1 to 7.

10. An electronic device, It is characterized in that The frequency dividing circuit comprises the frequency dividing circuit as described in any one of claims 1 to 7.

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