Semiconductor drive circuit

Abstract

The invention provides a semiconductor driving circuit which can realize soft turn-off with a simple structure. A semiconductor drive circuit (100) is a semiconductor drive circuit (100) for driving a semiconductor element. A semiconductor drive circuit (100) includes a control circuit (110) that inputs an input signal and generates a set signal and a reset signal from the input signal. Further, the semiconductor drive circuit (100) has a drive signal circuit (120) that turns on a drive signal of the semiconductor element in response to a rising edge of the set signal, and turns off the drive signal in response to a rising edge of the reset signal. Furthermore, the semiconductor drive circuit (100) has a soft shut-off circuit (130) that, when the set signal and the reset signal are turned on simultaneously, softly shuts off the drive signal of the semiconductor element more slowly in response to rising edges of the set signal and the reset signal than when the drive signal is turned off by the drive signal circuit (120).

Description

Technical Field

[0001] The present invention relates to a semiconductor driving circuit. Background Art

[0002] In the past, in devices that use power semiconductor elements to control loads such as motors, there is a technology related to a power module that assembles power semiconductor elements and integrated circuit chips that control them into a single package. The following technology is proposed: when an abnormality such as overcurrent or short circuit occurs at the output terminal of the power module, an abnormality detection signal is transmitted to the inside of the power module, and the output element is turned off, thereby protecting the power module, etc. Patent document 1 discloses a semiconductor device drive circuit. The semiconductor device drive circuit disclosed in patent document 1 slowly reduces the gate voltage of the semiconductor switch element when an error occurs, thereby slowly turning off the semiconductor switch element and performing short circuit protection.

[0003] Patent Document 1: International Publication No. 2017 / 098624

[0004] In the semiconductor device driving circuit disclosed in Patent Document 1, it is necessary to temporarily level-shift the error signal detected by the unsaturated voltage detection circuit to a high potential error signal in the second level shift main circuit. However, the level shift circuit shown in the second level shift main circuit generally requires a large number of semiconductor elements, thereby increasing the circuit scale. Summary of the invention

[0005] The present invention has been made in view of the above problems in the prior art. Another object of the present invention is to provide a semiconductor drive circuit that can achieve soft shutdown with a simple structure.

[0006] The semiconductor driving circuit of the present invention is used to drive a semiconductor element, and the semiconductor driving circuit comprises: a control circuit, which inputs an input signal and generates a set signal and a reset signal according to the input signal; a drive signal circuit, which turns on the drive signal of the semiconductor element in response to the rising edge of the set signal, and turns off the drive signal in response to the rising edge of the reset signal; and a soft cut-off circuit, which, when the set signal and the reset signal are turned on at the same time, responds to the rising edges of the set signal and the reset signal to softly cut off the drive signal of the semiconductor element more slowly than when the drive signal is turned off by the drive signal circuit.

[0007] According to the present invention, it is possible to provide a semiconductor driving circuit capable of realizing soft turn-off with a simple structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a diagram showing the structure of the semiconductor driving circuit according to the first embodiment.

[0009] Figure 2 This is a timing chart for explaining the operation of the semiconductor driving circuit according to the first embodiment.

[0010] Figure 3 This is a circuit diagram schematically showing a control circuit provided in the semiconductor drive circuit according to the first embodiment.

[0011] Figure 4 This is a timing chart for explaining the operation of the control circuit provided in the semiconductor drive circuit according to the first embodiment.

[0012] Figure 5 It is a diagram showing the structure of a semiconductor driving circuit according to a second embodiment.

[0013] Figure 6 This is a circuit diagram schematically showing a control circuit provided in the semiconductor drive circuit according to the second embodiment.

[0014] Figure 7 This is a timing chart for explaining the operation of the control circuit provided in the semiconductor drive circuit according to the second embodiment.

[0015] Description of Reference Numerals

[0016] 100: semiconductor drive circuit; 110: control circuit; 111: pulse generating unit; 112a, 112e: set signal generating circuit; 112b, 112d: reset signal generating circuit; 112c: logic OR circuit; 113: filter circuit; 114a: first pulse conversion circuit; 114b: second pulse conversion circuit; 114c: third pulse conversion circuit; 115: TFF circuit; 116a: first DFF circuit; 116b: second DFF circuit; 120: drive signal circuit; 130: soft cut-off circuit; 141: low-side control circuit; 142: low-side drive circuit; 143: semiconductor element; 144: comparator; 200: control IC; 300: three-phase motor; 400: power supply. DETAILED DESCRIPTION

[0017] Hereinafter, the semiconductor driving circuit 100 according to several embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts in the drawings of the driving circuits of the respective embodiments are denoted by the same reference numerals and their description will be omitted.

[0018] (First embodiment)

[0019] Figure 1 1 is a diagram showing the structure of a semiconductor drive circuit 100 according to a first embodiment. The semiconductor drive circuit 100 according to this embodiment is a device for driving a load (a three-phase motor 300). Figure 1In the example shown, the structure of the semiconductor drive circuit 100 for controlling the power supplied from the power source 400 to the U terminal of the three-phase motor 300 is shown. In addition, since the semiconductor drive circuit 100 for supplying power to the V terminal and the W terminal is Figure 1 The circuits shown have the same structure, so illustration and description are omitted here.

[0020] The semiconductor driving circuit 100 has a high-side semiconductor element QH, a low-side semiconductor element QL, a high-side driver IC chip HSDIC, and a low-side driver IC chip LSDIC. The semiconductor driving circuit 100 operates according to a control signal from the control IC 200. In the present embodiment, the high-side semiconductor element QH and the low-side semiconductor element QL are power semiconductor elements, and the gate terminals are connected to the high-side driver IC chip HSDIC and the low-side driver IC chip LSDIC, respectively. The power semiconductor element is, for example, an IGBT (Insulated Gate Bipolar Transistor). In addition, in the present embodiment, the high-side semiconductor element QH is equivalent to a semiconductor element.

[0021] The control IC 200 is a circuit for controlling the semiconductor drive circuit 100, and transmits control signals to the high-side drive IC chip HSDIC and the low-side drive IC chip LSDIC. In addition, the control IC 200 obtains information related to abnormalities transmitted from the low-side drive IC chip LSDIC and transmits it to the high-side drive IC chip HSDIC. In addition, in the first embodiment, the transmission of abnormal information to the high-side drive IC chip HSDIC is performed by the alarm signal Alert. The high-side drive IC chip HSDIC and the low-side drive IC chip LSDIC are driven by the power supplied to the power supply terminals VCCHU and VCCL, respectively.

[0022] The semiconductor driving circuit 100 sends driving signals from the high-side driving IC chip HSDIC and the low-side driving IC chip LSDIC to the gates of the high-side semiconductor element QH and the low-side semiconductor element QL, thereby controlling the three-phase motor 300 .

[0023] The high-side driver IC chip HSDIC has a control circuit 110 in the low voltage area LA, and has a level shifter, a drive signal circuit 120, and a soft cut-off circuit 130 in the high voltage area HA. ​​In addition, the high-side driver IC chip HSDIC and the low-side driver IC chip LSDIC may be accommodated in one chip, or may be configured as separate chips on the high side and the low side.

[0024] like Figure 1As shown, the low-side driver IC chip LSDIC has a low-side control circuit 141 and a low-side driver circuit 142 for driving the low-side semiconductor element QL. In addition, the low-side driver IC chip LSDIC has a semiconductor element 143 and a comparator 144, which are used to transmit information related to the abnormality detected in the current detection terminal sense to the control IC 200.

[0025] The control circuit 110 inputs an input signal HIN, and generates a set signal Set and a reset signal Reset according to the input signal HIN. In addition, the control circuit 110 inputs an alarm signal Alert from the control IC 200, and when the alarm signal Alert is turned on, the set signal Set and the reset signal Reset are turned on at the same time. In addition, in the present embodiment, the simultaneous turning on of the set signal Set and the reset signal Reset is not limited to the timing of the turning on being completely consistent in time. For example, as long as the timing of the simultaneous turning on is detected in the drive signal circuit 120 and the soft cut-off circuit 130 described later, a slight time deviation in the timing of the simultaneous turning on of the set signal Set and the reset signal Reset may also be included.

[0026] The drive signal circuit 120 turns on the drive signal HO of the high-side semiconductor element QH in response to the rising edge of the set signal Set, and turns off the drive signal HO in response to the rising edge of the reset signal Reset. In addition, when the set signal Set and the reset signal Reset are turned on at the same time, the drive signal circuit 120 turns off the drive signal HO. In addition, in this specification, in order to distinguish it from the soft cut-off described later, the cut-off of the drive signal HO performed by the drive signal circuit 120 is sometimes referred to as "normal cut-off".

[0027] The soft cut-off circuit 130 generates a drive signal HO for softly turning off the high-side semiconductor element QH in response to the rising edges of the set signal Set and the reset signal Reset. Specifically, when the set signal Set and the reset signal Reset are turned on at the same time, the soft cut-off circuit 130 generates a drive signal HO for softly turning off the high-side semiconductor element QH. That is, when the set signal Set and the reset signal Reset are turned on at the same time, the soft cut-off circuit 130 softly cuts off the drive signal HO in response to the rising edges of the set signal Set and the reset signal Reset. The soft cut-off of the soft cut-off circuit 130 turns off the drive signal HO more slowly than when the drive signal circuit 120 turns off the drive signal HO.

[0028] In the present embodiment, the time required for soft cutoff is at least three times the time required for disconnecting the drive signal HO by the drive signal circuit 120. In addition, in the present embodiment, the manner in which the time required for soft cutoff is at least three times the time required for disconnection by the drive signal circuit 120 does not limit the structure of the present embodiment. For example, the structure in which the time required for soft cutoff is about 3 to 10 times the time required for disconnection by the drive signal circuit 120 may be adopted.

[0029] Furthermore, when the set signal Set and the reset signal Reset are turned on at the same time, as described above, the drive signal HO is subjected to normal cutoff by the drive signal circuit 120 and soft cutoff by the soft cutoff circuit 130. In this case, the soft cutoff requires at least three times the time of the normal cutoff operation, and therefore, in fact, the gate voltage of the high-side semiconductor element QH is cut off at the timing when the soft cutoff is completed.

[0030] Figure 2 This is a timing chart for explaining the operation of the semiconductor driving circuit 100 according to the first embodiment.

[0031] first, Figure 2 During the normal on-action shown in the period T1 (time t1 to time t3), in response to the rising edge of the high-side input signal HIN, a set signal Set is generated in the control circuit 110 (time t2). The set signal Set generated in the control circuit 110 is level-shifted and transmitted to the drive signal circuit 120 and the soft cut-off circuit 130. The drive signal circuit 120 causes the gate drive signal of the high-side semiconductor element QH, i.e., the drive signal HO, to migrate from "L" (disconnected) to "H" (connected) (time t2 to time t3) according to the transmitted set signal Set. In addition, at time t2, the reset signal Reset is disconnected, so the soft cut-off circuit 130 does not perform the soft cut-off processing at this timing.

[0032] also, Figure 2 During the normal cut-off operation shown in the period T2 (time t4 to time t6), in response to the falling edge of the input signal HIN, a reset signal Reset is generated in the control circuit 110 (time t5). The reset signal Reset generated in the control circuit 110 is level-shifted and transmitted to the drive signal circuit 120. The drive signal circuit 120 causes the gate drive signal of the high-side semiconductor element QH, that is, the drive signal HO, to migrate from "H" (on) to "L" (off) (time t5 to time t6) according to the transmitted reset signal Reset. In addition, at time t2, the set signal Set is disconnected, so the soft cut-off circuit 130 does not perform the soft cut-off processing at this timing.

[0033] Then, something happened Figure 2 The operation of the semiconductor drive circuit 100 in the abnormal case shown in the period T3 (time t10 to time t14) is described. When an abnormality such as an overcurrent occurs in the output element of the semiconductor drive circuit 100, that is, the high-side semiconductor element QH or the low-side semiconductor element QL, the overcurrent is detected by the current detection terminal sense of the low-side semiconductor element QL.

[0034] The abnormality is transmitted from the current detection terminal sense to the low-side drive IC chip LSDIC, and information indicating the abnormality is transmitted from the abnormality detection output terminal FO of the low-side drive IC chip LSDIC to the control IC 200 .

[0035] Then, the control IC 200 transmits an abnormality detection signal in the form of the abnormality detection signal terminal (alert signal Alert) of the high-side drive IC chip HSDIC transitioning from “L” to “H” according to the information transmitted from the abnormality detection output terminal FO.

[0036] The control circuit 110 generates signal pulses for both the set signal Set and the reset signal Reset simultaneously in response to the rising edge of the alarm signal Alert. The set signal Set and the reset signal Reset are both level-shifted and transmitted to the drive signal circuit 120 and the soft cutoff circuit 130.

[0037] The soft cut-off circuit 130 transitions from "H" (on) to "L" (off) at a gentle decline (time t13 to time t14) such as cutting off more slowly than usual according to the set signal Set and the reset signal Reset. In addition, the drive signal circuit 120 transitions the drive signal HO of the high-side semiconductor element QH from "H" (on) to "L" (off) at normal timing according to the reset signal Reset. Here, the drive signal HO transitions to "L" (off) through the drive signal circuit 120 and the soft cut-off circuit 130, but slowly transitions from "H" (on) to "L" (off) through the soft cut-off circuit 130.

[0038] Thus, when an abnormality occurs, the semiconductor driving circuit 100 can reduce a surge voltage generated in the output terminal during the shutdown by softly cutting off the driving signal HO of the high-side semiconductor element QH and softly turning off the high-side semiconductor element QH.

[0039] Figure 3 1 is a circuit diagram schematically showing a control circuit 110 provided in the semiconductor drive circuit 100 according to the first embodiment. Figure 3 As shown, the control circuit 110 is configured to include a pulse generating unit 111, a set signal generating circuit 112a, and a reset signal generating circuit 112b.

[0040] The pulse generating unit 111 generates a pulse set signal P_Set, a pulse alarm signal P_Alert, and a pulse reset signal P_Reset according to the input signal HIN and the alarm signal Alert.

[0041] The set signal generating circuit 112a generates a set signal Set according to the pulse set signal P_Set or the pulse alarm signal P_Alert. Figure 3 As shown, the set signal generating circuit 112a is composed of a logical OR circuit, and generates the set signal Set by performing a logical OR of the pulse set signal P_Set and the pulse alarm signal P_Alert.

[0042] The reset signal generating circuit 112b generates a reset signal Reset according to the pulse reset signal P_Reset or the pulse alarm signal P_Alert. Figure 3 As shown, the reset signal generating circuit 112 b is composed of a logic OR circuit, and generates the reset signal Reset by the logic OR of the pulse reset signal P_Reset and the pulse alarm signal P_Alert.

[0043] Figure 4 This is a timing chart for explaining the operation of the control circuit 110 provided in the semiconductor driving circuit 100 according to the first embodiment.

[0044] The pulse generating unit 111 responds to Figure 4 The set signal generating circuit 112a generates a pulse set signal P_Set at the rising edge of the input signal HIN at time t1. In addition, the set signal generating circuit 112a outputs a set signal Set in response to the pulse set signal P_Set.

[0045] The pulse generating unit 111 responds to Figure 4 The reset signal generating circuit 112b generates a pulse reset signal P_Reset at the falling edge of the input signal HIN at time t2. In addition, the reset signal generating circuit 112b outputs a reset signal Reset in response to the pulse reset signal P_Reset.

[0046] based on Figure 4 The rising action of the input signal HIN at time t3 is the same as the action at time t1 described above, and therefore, the description thereof is omitted here.

[0047] The pulse generating unit 111 responds to Figure 4 In response to the rising edge of the alarm signal Alert at time t4, the pulse alarm signal P_Alert is generated. In addition, the set signal generating circuit 112a and the reset signal generating circuit 112b output the set signal Set and the reset signal Reset in response to the pulse alarm signal P_Alert.

[0048] As described above, the semiconductor driving circuit 100 of the first embodiment is a semiconductor driving circuit 100 for driving a semiconductor element. The semiconductor driving circuit 100 has a control circuit 110, which inputs an input signal HIN and generates a set signal and a reset signal according to the input signal HIN. In addition, the semiconductor driving circuit 100 has a drive signal circuit 120, which turns on the drive signal of the semiconductor element in response to the rising edge of the set signal, and turns off the drive signal in response to the rising edge of the reset signal. In addition, the semiconductor driving circuit 100 has a soft cut-off circuit 130, which, when the set signal and the reset signal are turned on at the same time, slowly and softly cuts off the drive signal of the semiconductor element in response to the rising edges of the set signal and the reset signal. In addition, the soft cut-off circuit 130 slowly and softly cuts off the drive signal of the semiconductor element compared to turning off the drive signal by the drive signal circuit 120.

[0049] Thus, the semiconductor driving circuit 100 does not need to provide a level shifter for shifting the voltage level of the abnormality detection signal to a high voltage, and can achieve a small circuit scale. That is, the semiconductor driving circuit 100 of the first embodiment can achieve soft shutdown with a simple structure.

[0050] Furthermore, the time required for the soft cutoff performed by the soft cutoff circuit 130 of the semiconductor driving circuit 100 may be at least three times the time required to cut off the driving signal by the driving signal circuit 120. Thus, the semiconductor driving circuit 100 can slowly cut off the semiconductor element and reduce the surge voltage generated in the output terminal during the cutoff.

[0051] In addition, the control circuit 110 of the semiconductor driving circuit 100 can also input the alarm signal Alert, and when the alarm signal Alert is turned on, the set signal Set and the reset signal Reset are turned on at the same time. As a result, the semiconductor driving circuit 100 does not need to set a path for the alarm signal from the control circuit 110 to the drive signal circuit 120 and the soft cut-off circuit 130. In other words, the semiconductor driving circuit 100 does not need to set a level shifter that shifts the voltage level of the alarm signal to a high voltage, and the circuit can be miniaturized.

[0052] Furthermore, the control circuit 110 may include a pulse generating unit 111, which generates a pulse set signal P_Set, a pulse alarm signal P_Alert, and a pulse reset signal P_Reset according to the input signal HIN and the alarm signal Alert. In addition, the control circuit 110 may also include a set signal generating circuit 112a, which generates a set signal Set according to the pulse set signal P_Set or the pulse alarm signal P_Alert. Furthermore, the control circuit 110 may also include a reset signal generating circuit 112b, which generates a reset signal Reset according to the pulse reset signal P_Reset or the pulse alarm signal P_Alert. Thus, the semiconductor driving circuit 100 can form a circuit that simultaneously turns on the set signal Set and the reset signal Reset in response to the rising edge of the alarm signal Alert with a simple structure, thereby achieving small scale.

[0053] (Second embodiment)

[0054] For example, in the above embodiment, the set signal Set and the reset signal Reset are both raised simultaneously according to the alarm signal Alert input from the control IC 200.

[0055] Here, the semiconductor driving circuit 100 of the second embodiment which applies a pulse wave that changes between on, off, and on at intervals shorter than the filter time constant of the filter circuit 113 to the input signal HIN when an abnormality is detected will be described in detail with respect to a structure different from that of the first embodiment.

[0056] Figure 5 1 is a diagram showing a configuration of a semiconductor drive circuit 100 according to a second embodiment. The semiconductor drive circuit 100 according to the second embodiment is different from the semiconductor drive circuit 100 in that there is no alarm signal Alert transmitted from the control IC 200 to the semiconductor drive circuit 100. Figure 1 The semiconductor driving circuit 100 of the first embodiment shown has a different structure.

[0057] Figure 6 1 is a schematic circuit diagram showing a control circuit 110 provided in the semiconductor drive circuit 100 according to the second embodiment. Figure 6As shown, the control circuit 110 of the second embodiment includes a filter circuit 113, a first pulse conversion circuit 114a, a second pulse conversion circuit 114b, a third pulse conversion circuit 114c, and a logical OR circuit 112c. In addition, the control circuit 110 of the second embodiment includes a TFF circuit 115, a first DFF circuit 116a, a second DFF circuit 116b, a set signal generation circuit 112e, and a reset signal generation circuit 112d.

[0058] The filter circuit 113 performs filtering processing on the input signal HIN at a predetermined time. Generally speaking, in order to eliminate the influence of noise, the drive signal sent to the power module such as the high-side semiconductor element QH is filtered, and after delay, the set signal Set and the reset signal Reset are output. Therefore, when the signal input to the filter circuit 113 changes from "H" to "L" to "H" at a time shorter than the time constant of the filter circuit 113, the pulse waveform after filtering is not generated, thereby preventing erroneous operation caused by noise waveform.

[0059] Regarding the processing in the filter circuit 113, use Figure 7 The timing diagram is specifically described below. Figure 7 is a timing chart for explaining the operation of the semiconductor driving circuit 100 according to the second embodiment. Figure 7 In response to the rising edge of the input signal HIN at time t1, the second pulse set signal P2_Set is generated at time t2 via the filter circuit 113 and the second pulse conversion circuit 114b described later. Figure 7 At the falling edge of the input signal HIN at time t3, the second pulse reset signal P2_Reset is generated at the timing of time t4 via the filter circuit 113 and the second pulse conversion circuit 114b described later.

[0060] like Figure 7 As shown, the second pulse set signal P2_Set and the second pulse reset signal P2_Reset generated via the filter circuit 113 and the second pulse conversion circuit 114b are generated with a delay of a predetermined time.

[0061] On the other hand, Figure 7 As shown in the figure, from time t8 to time t9, when the input signal HIN input to the filter circuit 113 changes from "H" to "L" to "H" during a period shorter than the filter time constant (period (i) in the figure), the same processing as the noise removal is performed. That is, in response to the change of the input signal HIN from time t8 to time t9, as in Figure 7 As indicated by “×”, the second pulse set signal P2_Set and the second pulse reset signal P2_Reset are not generated.

[0062] In addition, in the control circuit 110 of the semiconductor drive circuit 100 of the second embodiment, the input signal HIN is also used as a signal after pulse conversion by the first pulse conversion circuit 114a without passing through the filter circuit 113. As a result, the semiconductor drive circuit 100 of the second embodiment enables the semiconductor drive circuit 100 to recognize the pulse waveform input of the input signal HIN of such an extremely short time as a signal when an abnormality is detected. That is, the semiconductor drive circuit 100 of the second embodiment does not use a dedicated signal (terminal) when an abnormality is detected, thereby miniaturizing the circuit. In addition, in a high-voltage power module, there is a problem of ensuring an insulation distance, which sometimes limits the number of terminals that can be set in the power module. In such a situation, there is a situation where a terminal for transmitting the detection of an abnormality cannot be set, and the structure of the semiconductor drive circuit 100 of the second embodiment can be effectively utilized.

[0063] The first pulse conversion circuit 114 a outputs a first pulse set signal P1_Set in response to a rising edge of the input signal HIN, and outputs a first pulse reset signal P1_Reset in response to a falling edge of the input signal HIN.

[0064] The second pulse conversion circuit 114 b outputs a second pulse set signal P2_Set in response to a rising edge of the output signal of the filter circuit 113 , and outputs a second pulse reset signal P2_Reset in response to a falling edge of the output signal of the filter circuit 113 .

[0065] The logical OR circuit 112 c outputs a logical OR signal C of the first pulse reset signal P1_Reset and the second pulse reset signal P2_Reset.

[0066] The TFF circuit 115 (TFF: Toggle Flip-Flop) in response to the rising edge of the logical OR signal C inverts the on / off state of the TFF output signal TO.

[0067] The first DFF circuit 116 a (DFF: Delay Flip-Flop) delays the TFF output signal TO in response to the rising edge of the first pulse set signal P1_Set, and outputs a first delay signal DO1 .

[0068] In response to the rising edge of the first pulse reset signal P1_Reset, the second DFF circuit 116 b delays the first delay signal DO1 and outputs a second delay signal DO2 .

[0069] The third pulse conversion circuit 114 c generates a pulse alarm signal P_Alert in response to the rising edge of the second delay signal DO2 .

[0070] The reset signal generating circuit 112d generates a reset signal Reset according to the second pulse reset signal P2_Reset or the pulse alarm signal P_Alert. That is, the reset signal generating circuit 112d is composed of a logic OR circuit in the same manner as the reset signal generating circuit 112b of the semiconductor driving circuit 100 of the first embodiment. That is, the reset signal generating circuit 112d generates the reset signal Reset by the logic OR of the second pulse reset signal P2_Reset and the pulse alarm signal P_Alert.

[0071] The set signal generating circuit 112e generates the set signal Set according to the second pulse set signal P2_Set or the pulse alarm signal P_Alert. That is, the set signal generating circuit 112e is composed of a logic OR circuit in the same manner as the set signal generating circuit 112a of the semiconductor driving circuit 100 of the first embodiment. That is, the set signal generating circuit 112e generates the set signal Set by the logic OR of the second pulse set signal P2_Set and the pulse alarm signal P_Alert.

[0072] In addition, as described above, in the second embodiment, the input signal HIN is a signal to which a pulse wave (pulse signal) is applied when an abnormality in the semiconductor drive circuit 100 is detected, and the pulse wave (pulse signal) changes between on, off, and on in a time shorter than the time constant of the filter circuit 113.

[0073] That is, in the second embodiment, the control IC 200 applies a pulse signal of a shorter time than the time constant of the filter circuit 113 to the input signal HIN based on the information transmitted via the abnormality detection output terminal FO, thereby transmitting information on the abnormal state.

[0074] Figure 7 This is a timing chart for explaining the operation of the semiconductor driving circuit 100 according to the second embodiment.

[0075] exist Figure 7 At time t1, in response to the rising edge of the input signal HIN, the first pulse conversion circuit 114a generates the first pulse set signal P1_Set. In addition, at time t2, the second pulse set signal P2_Set is generated via the filter circuit 113 and the second pulse conversion circuit 114b. Figure 7 As shown at time t1 and time t2, the second pulse set signal P2_Set is generated by delaying the first pulse set signal P1_Set by the delay amount in the filter circuit 113. Figure 7 In the example shown, the delay time in the filter circuit 113 is schematically shown by a rectangle with a diagonal line pattern.

[0076] Furthermore, at time t2, in response to the second pulse set signal P2_Set, the set signal generation circuit 112e generates the set signal Set, and the drive signal HO is turned on.

[0077] exist Figure 7 At time t3, in response to the falling of the input signal HIN, the first pulse reset signal P1_Reset (time t3) and the second pulse reset signal P2_Reset (time t4) are generated. In addition, similar to the second pulse set signal P2_Set, the second pulse reset signal P2_Reset is generated by delaying the first pulse reset signal P1_Reset by the delay amount in the filter circuit 113.

[0078] Furthermore, at time t4, in response to the second pulse reset signal P2_Reset, the reset signal generating circuit 112d generates the reset signal Reset, and the drive signal HO is normally cut off.

[0079] exist Figure 7 At time t5 and time t6, the connection process is performed. This connection process is the same as the connection process at time t1 and time t2 described above, so the description is omitted here.

[0080] exist Figure 7 An abnormality is detected at time t7, and at time t8 and time t9, a pulse signal (pulse wave) of period (i) is applied to the input signal HIN of the control IC 200. As described above, the period (i) is a period shorter than the time constant of the filter circuit 113. As a result, no pulse signal is generated in the second pulse conversion circuit 114b (refer to "×" in the figure). That is, at time t8 and time t9, only the first pulse reset signal P1_Reset and the first pulse set signal P1_Set are generated by the first pulse conversion circuit 114a, respectively.

[0081] At time t8, the OR circuit 112c generates an OR signal C, and the TFF output signal TO turns on in the TFF circuit 115. At time t9, in the first DFF circuit 116a, the TFF output signal TO is delayed by the first pulse set signal P1_Set and output as the first delay signal DO1.

[0082] At time t10, in the second DFF circuit 116b, the first delay signal DO1 is delayed by the first pulse reset signal P1_Reset, and the second delay signal DO2 is turned on. In response to the rise of the second delay signal DO2, the third pulse conversion circuit 114c generates a pulse alarm signal P_Alert, which is input to the set signal generation circuit 112e and the reset signal generation circuit 112d.

[0083] At time t10 , the set signal Set and the reset signal Reset are turned on simultaneously, so that the soft cutoff circuit 130 can perform soft cutoff during the period from time t11 to time t12 , similarly to the semiconductor driving circuit 100 of the first embodiment.

[0084] As described above, in the semiconductor driving circuit 100 of the second embodiment, the control circuit 110 may also include a filter circuit 113, which performs filtering processing on the input signal HIN at a predetermined time. In addition, the control circuit 110 may also include a first pulse conversion circuit 114a, which outputs a first pulse set signal P1_Set in response to the rising edge of the input signal HIN, and outputs a first pulse reset signal P1_Reset in response to the falling edge of the input signal HIN. In addition, the control circuit 110 may also include a second pulse conversion circuit 114b. The second pulse conversion circuit 114b outputs a second pulse set signal P2_Set in response to the rising edge of the output signal of the filter circuit 113, and outputs a second pulse reset signal P2_Reset in response to the falling edge of the output signal of the filter circuit 113. In addition, the control circuit 110 may also include a logic OR circuit 112c, which outputs a logic OR signal C of the first pulse reset signal P1_Reset and the second pulse reset signal P2_Reset. In addition, the control circuit 110 may also include a TFF circuit 115, which inverts the on / off state of the TFF output signal TO in response to the rising edge of the logic OR signal C. In addition, the control circuit 110 may also include a first DFF circuit 116a, which delays the TFF output signal TO and outputs a first delay signal DO1 in response to the rising edge of the first pulse set signal P1_Set. In addition, the control circuit 110 may also include a second DFF circuit 116b, which delays the first delay signal DO1 and outputs a second delay signal DO2 in response to the rising edge of the first pulse reset signal P1_Reset. In addition, the control circuit 110 may also have a third pulse conversion circuit 114c, which generates a pulse alarm signal P_Alert in response to the rising edge of the second delay signal DO2. In addition, the control circuit 110 may also have a reset signal generation circuit 112d, which generates a reset signal Reset based on the second pulse reset signal P2_Reset or the pulse alarm signal P_Alert. In addition, the control circuit 110 may also have a set signal generation circuit 112e, which generates a set signal Set based on the second pulse set signal P2_Set or the pulse alarm signal P_Alert. In addition, the input signal HIN of the control circuit 110 may also be a signal to which a pulse wave is applied when an abnormality of the semiconductor drive circuit 100 is detected, and the pulse wave changes according to on, off, and on in a time shorter than the time constant of the filter circuit 113.

[0085] Therefore, the semiconductor drive circuit 100 of the second embodiment does not need to be provided with a dedicated terminal for inputting the alarm signal Alert, and the circuit can be miniaturized. In addition, in a high-voltage power module, there is a problem of ensuring the insulation distance, which sometimes limits the number of terminals that can be provided in the power module. In such a situation, there is a situation where a terminal for transmitting the detected abnormality cannot be provided, and the structure of the semiconductor drive circuit 100 of the second embodiment can be effectively utilized.

[0086] (Other embodiments)

[0087] The embodiments are described in detail with reference to the accompanying drawings, but the embodiments are not limited by the contents described in the above embodiments. In addition, the structural elements described in the above include structural elements that are easily thought of and substantially the same by those skilled in the art. Moreover, the structures described in the above can be appropriately combined. In addition, various omissions, substitutions or changes of the structure can be made within the scope of the gist of the embodiments.

[0088] In the above-described embodiment, a semiconductor driving device including the semiconductor driving circuit 100 and the control IC 200 is also included in the scope of this embodiment.

[0089] The features of the semiconductor driving circuit 100 are described below.

[0090] The semiconductor driving circuit 100 of the first embodiment is a semiconductor driving circuit 100 for driving a semiconductor element. The semiconductor driving circuit 100 has a control circuit 110, which receives an input signal HIN and generates a set signal and a reset signal according to the input signal HIN. In addition, the semiconductor driving circuit 100 has a drive signal circuit 120, which turns on the drive signal of the semiconductor element in response to the rising edge of the set signal, and turns off the drive signal in response to the rising edge of the reset signal. In addition, the semiconductor driving circuit 100 has a soft cut-off circuit 130, which, when the set signal and the reset signal are turned on at the same time, slowly and softly cuts off the drive signal of the semiconductor element in response to the rising edges of the set signal and the reset signal. In addition, the soft cut-off circuit 130 slowly and softly cuts off the drive signal of the semiconductor element compared to turning off the drive signal by the drive signal circuit 120.

[0091] According to this configuration, the semiconductor driving circuit 100 does not need to provide a level shifter for shifting the voltage level of the abnormality detection signal to a high voltage, and can achieve a small circuit scale. That is, the semiconductor driving circuit 100 of the first embodiment can achieve soft shutdown with a simple configuration.

[0092] The time required for the soft cutoff performed by the soft cutoff circuit 130 of the semiconductor driving circuit 100 of the second embodiment may be at least three times the time required for the driving signal circuit 120 to turn off the driving signal.

[0093] According to this configuration, the semiconductor driving circuit 100 can gradually cut off the semiconductor element, and can reduce a surge voltage generated at the output terminal during the cutoff.

[0094] The control circuit 110 of the semiconductor driving circuit 100 of the third embodiment may receive an alarm signal Alert as an input, and when the alarm signal Alert is turned on, the set signal Set and the reset signal Reset may be turned on simultaneously.

[0095] According to this structure, the semiconductor driving circuit 100 does not need to provide a path for the alarm signal from the control circuit 110 to the drive signal circuit 120 and the soft cutoff circuit 130. In other words, the semiconductor driving circuit 100 does not need to provide a level shifter for shifting the voltage level of the alarm signal to a high voltage, and the circuit can be reduced in size.

[0096] The control circuit 110 of the semiconductor drive circuit 100 of the fourth embodiment may also include a pulse generating unit 111. The pulse generating unit 111 may also generate a pulse set signal P_Set, a pulse alarm signal P_Alert, and a pulse reset signal P_Reset based on the input signal HIN and the alarm signal Alert. In addition, the control circuit 110 may also include a set signal generating circuit 112a, which generates a set signal Set based on the pulse set signal P_Set or the pulse alarm signal P_Alert. Furthermore, the control circuit 110 may also include a reset signal generating circuit 112b, which generates a reset signal Reset based on the pulse reset signal P_Reset or the pulse alarm signal P_Alert.

[0097] According to this configuration, the semiconductor driving circuit 100 can be configured with a simple configuration as a circuit that simultaneously turns on the set signal Set and the reset signal Reset in response to the rising edge of the alarm signal Alert, thereby achieving miniaturization.

[0098] The control circuit 110 of the semiconductor drive circuit 100 of the fifth embodiment may also include a filter circuit 113, which performs a filter process on the input signal HIN at a predetermined time. In addition, the control circuit 110 may also include a first pulse conversion circuit 114a, which outputs a first pulse set signal P1_Set in response to the rising edge of the input signal HIN, and outputs a first pulse reset signal P1_Reset in response to the falling edge of the input signal HIN. In addition, the control circuit 110 may also include a second pulse conversion circuit 114b. The second pulse conversion circuit 114b outputs a second pulse set signal P2_Set in response to the rising edge of the output signal of the filter circuit 113, and outputs a second pulse reset signal P2_Reset in response to the falling edge of the output signal of the filter circuit 113. In addition, the control circuit 110 may also include a logic OR circuit 112c, which outputs a logic OR signal C of the first pulse reset signal P1_Reset and the second pulse reset signal P2_Reset. In addition, the control circuit 110 may also include a TFF circuit 115, which inverts the on / off state of the TFF output signal TO in response to the rising edge of the logic OR signal C. In addition, the control circuit 110 may also include a first DFF circuit 116a, which delays the TFF output signal TO and outputs a first delay signal DO1 in response to the rising edge of the first pulse set signal P1_Set. In addition, the control circuit 110 may also include a second DFF circuit 116b, which delays the first delay signal DO1 and outputs a second delay signal DO2 in response to the rising edge of the first pulse reset signal P1_Reset. In addition, the control circuit 110 may also include a third pulse conversion circuit 114c, which generates a pulse alarm signal P_Alert in response to the rising edge of the second delay signal DO2. In addition, the control circuit 110 may also include a reset signal generating circuit 112d, which generates a reset signal Reset based on the second pulse reset signal P2_Reset or the pulse alarm signal P_Alert. In addition, the control circuit 110 may also include a set signal generating circuit 112e, which generates a set signal Set based on the second pulse set signal P2_Set or the pulse alarm signal P_Alert. In addition, the input signal HIN of the control circuit 110 may also be a signal to which a pulse wave is applied when an abnormality of the semiconductor drive circuit 100 is detected, and the pulse wave changes according to on, off, and on in a time shorter than the time constant of the filter circuit 113.

[0099] According to this structure, the semiconductor drive circuit 100 does not need to be provided with a dedicated terminal for inputting the alarm signal Alert, and the circuit can be miniaturized. In addition, in a high-voltage power module, there is a problem of ensuring the insulation distance, which sometimes limits the number of terminals that can be provided in the power module. In such a situation, there is a situation where a terminal for transmitting the detected abnormality cannot be provided, and the structure of the semiconductor drive circuit 100 can be effectively utilized through this embodiment.

Claims

1. A semiconductor driving circuit for driving a semiconductor element, the semiconductor driving circuit comprising: A control circuit receives an input signal and generates a set signal and a reset signal according to the input signal; a drive signal circuit, which turns on the drive signal of the semiconductor element in response to the rising edge of the set signal, and turns off the drive signal in response to the rising edge of the reset signal; as well as A soft cut-off circuit, when the set signal and the reset signal are turned on at the same time, responds to the rising edge of the set signal and the reset signal, and softly cuts off the drive signal of the semiconductor element more slowly than when the drive signal is disconnected by the drive signal circuit.

2. The semiconductor driving circuit according to claim 1, wherein: The time required for the soft cutoff performed by the soft cutoff circuit is at least three times the time required for the drive signal circuit to cut off the drive signal.

3. The semiconductor driving circuit according to claim 1 or 2, wherein: The control circuit receives an alarm signal as input, and turns on the set signal and the reset signal simultaneously when the alarm signal is turned on.

4. The semiconductor driving circuit according to claim 3, wherein: The control circuit has: a pulse generating unit, which generates a pulse setting signal, a pulse alarm signal and a pulse reset signal according to the input signal and the alarm signal; a set signal generating circuit, which generates the set signal according to the pulse set signal or the pulse alarm signal; as well as A reset signal generating circuit generates the reset signal according to the pulse reset signal or the pulse alarm signal.

5. The semiconductor driving circuit according to claim 1 or 2, wherein: The control circuit has: A filter circuit, which performs filtering processing on the input signal at a specified time; a first pulse conversion circuit, which outputs a first pulse set signal in response to a rising edge of the input signal, and outputs a first pulse reset signal in response to a falling edge of the input signal; a second pulse conversion circuit, which outputs a second pulse set signal in response to a rising edge of the output signal of the filter circuit, and outputs a second pulse reset signal in response to a falling edge of the output signal of the filter circuit; A logic OR circuit, which outputs a logic OR signal of the first pulse reset signal and the second pulse reset signal; A TFF circuit, which inverts the on / off state of a TFF output signal in response to a rising edge of the logic OR signal; a first DFF circuit, which delays the TFF output signal and outputs a first delayed signal in response to a rising edge of the first pulse set signal; a second DFF circuit, which delays the first delay signal and outputs a second delay signal in response to a rising edge of the first pulse reset signal; a third pulse conversion circuit, which generates a pulse alarm signal in response to a rising edge of the second delay signal; a reset signal generating circuit, which generates the reset signal according to the second pulse reset signal or the pulse alarm signal; as well as a set signal generating circuit, which generates the set signal according to the second pulse set signal or the pulse alarm signal, The input signal is a signal to which a pulse wave is applied when an abnormality of the semiconductor drive circuit is detected, and the pulse wave changes in the order of on, off, and on in a time shorter than the time constant of the filter circuit.

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