Interpolated digital-to-analog converter (DAC)

Abstract

The application relates to an interpolated digital-to-analog converter (DAC). A segmented digital-to-analog converter (DAC) (100) includes an interpolated resistance (DAC) RDAC (108) and a buffer amplifier (110). The interpolation RDAC (108) comprises a dual resistor R-2R DAC (192) and a ladder resistor (194). An R-2R DAC (192) receives the first sub-word (126M) and generates an analog output signal (136H-136L) having a voltage representative of the first sub-word (126M). The first sub-word (126M) has an integer number M bits that include most significant bits (MSB) of the digital input signal (122). A ladder resistor (194) receives the analog output signal (136H-136L) and the second sub-word (126I), and generates an analog interpolated signal (146). The second sub-word (126I) has an integer I-bit that includes a middle significant bit ISB of the input signal (122). A buffer amplifier (110) receives the analog interpolated signal (146) and generates an output signal (124) for the segmented DAC (100).

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with application date of December 21, 2017, application number 201780097189.2, and invention name “Interpolation Digital / Analog Converter (DAC)”. Technical Field

[0003] The present application relates to a digital / analog converter (DAC), and in particular to an interpolation digital / analog converter (DAC). Background Art

[0004] A digital-to-analog converter (DAC) is an electrical circuit that converts a digital signal into an analog signal. DAC circuits are typically used in conjunction with (or integrated into) a microcontroller or microprocessor circuit to convert digital values ​​into analog signals for use in a variety of applications. In many applications (such as medical devices, optical devices, industrial control products, display drivers, etc.), high DAC accuracy is required. Higher-precision DACs typically take up significant circuit area, and increasing bit accuracy typically results in a significant increase in the number of switches and resistor elements. In addition, DAC circuits that provide high bit accuracy require more calibration memory and calibration time. Summary of the invention

[0005] According to at least one embodiment of the present disclosure, a segmented DAC circuit includes an interpolation resistor DAC (RDAC) and a buffer amplifier. The interpolation RDAC includes a resistor dual resistor (R-2R) DAC and a ladder resistor. The R-2R DAC is configured to receive a first sub-word and generate an analog output signal having a voltage representing the first sub-word. The first sub-word has an integer M bits, and the integer M bits include the most significant bit (MSB) of a digital input signal. The ladder resistor is configured to receive the analog output signal and a second sub-word and generate an analog interpolation signal. The second sub-word has an integer I bit, and the integer I bit includes an intermediate significant bit (ISB) of the digital input signal. The buffer amplifier is configured to receive the analog interpolation signal and generate an output signal for the segmented DAC.

[0006] Another exemplary embodiment is an interpolation RDAC, the interpolation RDAC comprising an R-2R DAC and a ladder resistor. The R-2R DAC is configured to receive a first sub-word and generate an analog output signal having a voltage representing the first sub-word. The first sub-word has an integer M bits, the integer M bits including the most significant bit MSB of a digital input signal. The ladder resistor is configured to receive the analog output signal and a second sub-word and generate an analog interpolation signal. The second sub-word has an integer I bit, the integer I bit including an intermediate significant bit ISB of the digital input signal. The buffer amplifier is configured to receive the analog interpolation signal and generate an output signal for the segmented DAC.

[0007] Yet another exemplary embodiment is a method of converting a digital input signal into a corresponding analog output signal. The method includes receiving a first sub-word of the digital input signal. The first sub-word includes an integer M bits, the integer M bits including the MSB of the digital input signal. The method also includes generating an analog output signal having a voltage representing the first sub-word by an R-2R DAC. The method also includes generating an analog interpolated signal based on the analog output signal and a second sub-word by a ladder resistor. The second sub-word includes an integer I bit, the integer I bit including the ISB of the digital input signal. The method also includes generating the analog output signal based on the analog interpolated signal by a buffer amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various examples will now be described in detail with reference to the accompanying drawings, in which:

[0009] Figure 1 shows a block diagram of an illustrative segmented DAC circuit according to various examples;

[0010] Figure 2 shows an exemplary digital input signal received by a segmented DAC circuit according to various examples;

[0011] Figure 3 An illustrative circuit diagram of a 9-bit MSB R-2R DAC of an interpolating RDAC for a segmented DAC circuit according to various examples is shown;

[0012] Figure 4A 4 to 5 show exemplary circuit diagrams of chopper switch circuits according to various examples;

[0013] Figure 5A B to B show illustrative circuit diagrams of a 3-bit ISB resistor ladder for an interpolating RDAC having a 9-bit MSB R-2R DAC with 3 thermocouple bits according to various examples;

[0014] Fig. 6AFIGS. 4 to 5 show illustrative circuit diagrams of a 3-bit ISB resistor ladder for an interpolating RDAC having a 9-bit MSB R-2R DAC with 3 thermocouple bits according to various examples;

[0015] Figure 7 An illustrative circuit diagram of an 8-bit MSB R-2R DAC for an interpolating RDAC of a segmented DAC circuit according to various examples is shown;

[0016] Fig. 8A B to B show illustrative circuit diagrams of a 4-bit ISB resistor ladder for an interpolating RDAC having an 8-bit MSB R-2R DAC with 2 thermocouple bits according to various examples;

[0017] Fig. 9A B to B show illustrative circuit diagrams of a 4-bit ISB resistor ladder for an interpolating RDAC having an 8-bit MSB R-2R DAC with 3 thermocouple bits according to various examples;

[0018] Fig. 10A shows an exemplary chopping function in a segmented DAC circuit according to various examples;

[0019] Fig. 10B shows an exemplary chopping function in a segmented DAC circuit according to various examples;

[0020] Fig. 10C shows an exemplary chopping function in a segmented DAC circuit according to various examples;

[0021] Fig.11 An illustrative flow chart showing a method for calibrating a segmented DAC according to various examples; and

[0022] Fig.12 An illustrative flow chart of a method of converting a digital input signal into a corresponding analog output signal is shown.

[0023] Annotations and naming

[0024] Certain terms are used throughout the following description and claims to refer to specific system components. As will be appreciated by those skilled in the art, companies may refer to components by different names. This document is not intended to distinguish between components that have different names but the same function. In the following discussion and claims, the terms "including" and "comprising" are used in an open-ended manner and should therefore be interpreted to mean "including but not limited to...". Moreover, the terms "couple" or "couples" are intended to mean an indirect or direct connection. Thus, if a first device is coupled to a second device, the connection may be through a direct connection or through an indirect connection via other devices and connections. The expression "based on" is intended to mean "based at least in part on". Thus, if X is based on Y, then X can be based on Y and any number of other factors. DETAILED DESCRIPTION

[0025] The following discussion relates to various embodiments of the present disclosure. Although one or more of these embodiments may be preferred, the disclosed embodiments should not be interpreted or otherwise used to limit the scope of the present disclosure, including the claims. In addition, it will be understood by those skilled in the art that the following description has a wide range of applications, and the discussion of any embodiment is intended only as an example of that embodiment, and is not intended to imply that the scope of the present disclosure, including the claims, will be limited to that embodiment.

[0026] DAC circuits convert digital signals into analog signals. In many applications (such as medical devices, optical devices, industrial control products, display drivers, etc.), high DAC accuracy (e.g., 16-bit resolution) is required. Higher-precision DACs usually occupy significant circuit area, and increasing bit accuracy usually results in a significant increase in the number of switches and resistor elements. In addition, DAC circuits that provide high bit accuracy require more calibration memory and calibration time.

[0027] Conventional DAC circuits for microcontrollers provide 12-bit or lower resolution, or have high die cost, long calibration paths, and / or high complexity. For example, some conventional DAC circuits require a relatively large number of switches for MSB interpolation. In addition, some conventional DAC circuits include interpolation amplifiers, thereby increasing the complexity of the circuit. Therefore, it is desirable to have a DAC circuit that can provide high-precision (e.g., 16-bit resolution), low-cost, low-complexity digital-to-analog conversion.

[0028] According to various examples, a segmented DAC circuit is provided, which generates an analog output signal from a digital input signal using an interpolation RDAC and a universal buffer amplifier. The interpolation RDAC includes an MSB R-2R DAC for providing a rough interpolation of the input signal and an ISB ladder resistor for generating the final interpolation of the input signal. The buffer amplifier receives the resulting interpolation signal and provides a unit voltage gain to the interpolation signal using a current gain. The resulting analog output signal is highly accurate (e.g., 16 bits) and has relatively low complexity (due to the use of ISB ladder resistors as an alternative and buffer capacitors instead of interpolation amplifiers) and cost. Such DACs can be used in a variety of applications. In other words, a wide range of topologies of such circuits can be used for different functional circuits. For example, such DACs can be used for digitally controlled oscillators, dot matrix LCD drivers, etc.

[0029] Figure 1A block diagram of an illustrative segmented DAC circuit 100 is shown according to various examples. The segmented DAC 100 is configured to receive a K-bit binary-coded digital input signal (CODE) 122 (e.g., a 16-bit digital signal) and convert the CODE 122 into an analog output signal (VOUT) 124 representing the value of the CODE 122. The CODE 122 may be received from any suitable digital signal source (e.g., a microcontroller). In an embodiment, the segmented DAC circuit 100 includes an input decoder 102, a calibration circuit 104, a calibration and dynamic element matching (DEM) circuit 106, an interpolating RDAC 108, a buffer amplifier 110, an ordered element matching (OEM) memory 112, and multiplexers 114-116. The decoder 102 is configured to receive the CODE 122, buffer, and parse the CODE 122 into three signals, MSB 126M, ISB 126I, and LSB 126L without modification. For example, CODE 122 includes an M-bit first sub-word (MSB), an I-bit second sub-word (ISB), and an L-bit third sub-word (LSB), where M, I, and L are all greater than 1, and K=M+I+L. The first sub-word is referred to herein as an "MSB sub-word" having M bits, which include the most significant bit of CODE 122. The second sub-word is referred to herein as an "ISB" sub-word having I bits, which include the middle significant bit of CODE 122. The third sub-word is referred to herein as an "LSB sub-word" having L bits, which include the least significant bit of CODE 122. The decoder 102 buffers and parses CODE 122 to output the M-bit first sub-word MSB 126M to the address input of the calibration circuit 104. The decoder 122 also outputs the I-bit second sub-word ISB 126I to the address input of the calibration circuit 104 and the L-bit third sub-word LSB 126L. In an embodiment, for a 16-bit CODE 122, decoder 102 outputs 9-bit MSB 126M, 3-bit ISB 126I, and 4-bit LSB 126L. In some embodiments, decoder 102 performs additional other digital signal operations on CODE 122. Furthermore, in some embodiments, decoder 102 is omitted.

[0030] In an embodiment, the calibration circuit 104 is configured to store calibration data indexed according to the first sub-word MSB 126M received from the decoder 102 at the first address input or according to the second sub-word ISB 126I received from the decoder 102 at the second address input. For example, the calibration circuit 104 may store a first group of K×M bits of calibration data for calibrating the first sub-word MSB 126M and a second group of K×M bits of calibration data for calibrating the second sub-word ISB 126I. In some embodiments, the calibration circuit 104 provides a calibration code CAL CODE from the calibration data based on CODE 122.

[0031] In an embodiment, in addition to the calibration circuit 104 receiving the first sub-word MSB 126M, the multiplexer 114 is also configured to receive the first sub-word MSB 126M as a first input. The second input of the multiplexer 114 is the M-bit OEM signal 130 received from the OEM memory 112. Therefore, in an embodiment, the OEM signal 130 has the same number of bits as the first sub-word MSB 126M. The multiplexer 114 also receives an enable or select signal OEM_EN 128, which provides a signal for the multiplexer 114 to output the OEM signal 130 or the first sub-word MSB 126M, which is labeled as an output signal 132.

[0032] The calibration and DEM circuit 106 is configured to receive a calibration code from the calibration circuit 104. In some embodiments, the calibration and DEM circuit 106 also receives the second sub-word ISB 126I and the third sub-word LSB 126L from the decoder 102. In an embodiment, the calibration and DEM circuit 106 includes a delta-sigma modulator (SDM) 196 as a first-order modulator; however, in other embodiments, a second-order or higher-order modulator may also be used. The calibration and DEM circuit 106 generates a modulator code SDCODE for the SDM 196 based on the calibration code received from the calibration circuit 104, the second sub-word ISB 126I, and the third sub-word LSB 126L. In an embodiment, the SDM 196 modulates the modulator code SDCODE to generate an N-bit digital interpolated code signal ICODE 138, which represents the value of the second sub-word ISB 126I and the third sub-word LSB 126L, where N is less than I+L.

[0033] In an embodiment, the multiplexer 116 is configured to receive the third sub-word LSB 126L as a first input and to receive the ICODE 138 as a second input. The multiplexer 116 also receives an enable or select signal RES_SEL 140, which provides a signal to the multiplexer 116 to output the third sub-word LSB 126L or the ICODE 138, which is labeled as an output signal 142. For example, in one state of RES_SEL 140, the multiplexer 116 provides the N-bit ICODE 138 to the interpolation RDAC 108 to obtain a (M+I+L)-bit resolution (e.g., 16-bit resolution for a 16-bit CODE 122). In another state of RES_SEL 140, the multiplexer 116 provides the third sub-word LSB 126L to the interpolation RDAC 108 to obtain a lower resolution.

[0034] In an embodiment, the interpolation RDAC 108 is configured to receive the output signal 132 from the multiplexer 114 and the output signal 142 from the multiplexer 116. The interpolation RDAC 108 includes an M-bit MSB R-2R DAC 192 and a 1-bit ISB ladder resistor 194. In an embodiment, the MSB R-2R DAC 192 receives the output signal 132 from the multiplexer 114. In some embodiments, the MSB R-2R DAC 192 includes a resistor circuit and a switch circuit that operates according to the M-bit input from the output signal 132. The MSB R-2R DAC 192 operates according to a reference voltage and an analog voltage divider to output a first analog output signal. For example, the MSB R-2R DAC 192 is configured to receive a reference voltage VrefH 134H and VrefL 134L. A voltage divider circuit is formed by the resistors in the MSB R-2R DAC 192 to provide a first analog output signal at or between the levels of the reference voltages VrefH 134H and VrefL 134L according to the M-bit input from the multiplexer 114. In operation, when the multiplexer 114 transmits the first sub-word MSB 126M, the first analog output signal represents the value of the first sub-word MSB 126M. Figure 1 In the example shown in , the MSB R-2R DAC 192 generates a differential first analog output signal VH 136H, VL 136L. In other embodiments, the MSB R-2R DAC 192 generates a single-ended first analog output signal. In some embodiments, the MSB R-2R DAC 192 includes a resistive chopping circuit that operates according to a single-bit or multi-bit chopping switch control signal (Chop) 144.

[0035] ISB resistor ladder 194 is configured to receive first analog output signal VH 136H, VL 136L from MSB R-2R DAC 192. In an embodiment, ISB resistor ladder 194 is a resistor ladder that generates analog interpolated signal 146. Analog interpolated signal 146 is an analog version of CODE 122.

[0036] The buffer amplifier 110 is configured to receive the analog interpolation signal 146 from the interpolation RDAC 108. In some embodiments, the buffer amplifier 110 is a unity gain buffer amplifier that applies negative feedback to the operational amplifier to generate VOUT 124. Therefore, in an embodiment, the voltage gain of the analog interpolation signal 146 is one (i.e., 0 dB). However, in some embodiments, the buffer amplifier 110 generates a current gain greater than one. For example, in an embodiment, the input impedance of the buffer amplifier 110 is relatively high (e.g., greater than 1 MΩ), while the output impedance is relatively low. Therefore, the buffer amplifier 110 generates VOUT 124 as if it were a voltage source. In some embodiments, the buffer amplifier 110 includes a resistive chopping circuit that operates according to a single-bit or multi-bit chopping switch control signal (chopping) 144. In addition, in some embodiments, if any offset is introduced in the DAC circuit 100, offset cancellation is applied within the universal buffer 110.

[0037] Figure 2 An exemplary digital input signal CODE 122 received by the DAC circuit 100 is shown according to various examples. Figure 2 In the example shown in , CODE 122 is 16 bits (K=16). The 16-bit example code 122 includes a 9-bit first subword MSB 126M (M=9), a 3-bit second subword ISB 126I (I=3), and a 4-bit third subword LSB 126L (L=4).

[0038] The first sub-word MSB 126M includes bits dac<15:7> (dacm<8:0>). The second sub-word ISB 126I includes bits dac<6:4>.

[0039] The third sub-word LSB 126L includes bits dac<3:0>.

[0040] Figure 3 An illustrative circuit diagram of a 9-bit MSB R-2RDAC 192 for the interpolating RDAC 108 of the segmented DAC circuit 100 is shown according to various examples. Figure 3In the example shown in , the MSB R-2R DAC 192 also includes a chopping circuit and a DEM circuit system, which are not required for all possible implementations. As described above, in an embodiment, the MSB R-2R DAC 192 is configured to generate a first analog output signal VH 136H, VL 136L using VrefH 134H and VrefL 134L as reference voltage signals.

[0041] In an embodiment, the 9-bit MSB R-2R DAC 192 includes a resistor circuit 302. The resistor circuit 302 includes an R-2R circuit 304 and a first switch circuit 314. The resistors in the resistor circuit 302 are formed as resistor elements having resistance values ​​of 1R (unit resistor) and 2R (2×unit resistor and / or 2 unit resistors in series). In other words, in an embodiment, the resistors in the resistor circuit 302 are based on the value of the unit resistor. The resistor circuit 302 is configured as a series of segments, each of which includes a tap node (e.g., tap node 352).

[0042] In an embodiment, the R-2R circuit 304 includes M or less segments. For example, for the first subword 9-bit MSB 126M, the R-2R circuit 304 includes 9 or less segments. Each segment includes two R-2R parts, and the two parts are respectively associated with a corresponding one in the differential output 136. Each of the parts includes a resistor element with a resistance value of 1R connected in series with the 1R element of the other segments, and a resistor element with a resistance of 2R connected to the switch circuit 314 at a corresponding tap node (e.g., tap node 352). The example shown is a differential R-2R circuit. However, as described above, a single-ended implementation is possible using a single output line 136, and each R-2R segment includes a single 1R resistor element and a single 2R resistor element. Each resistor element (1R and / or 2R) can be a single resistor component, or can be a plurality of resistor components connected in any suitable series and / or parallel configuration to provide a corresponding 1R or 2R resistance.

[0043] In an embodiment, the first switch circuit 314 includes a plurality of switches (e.g., switch 354) connected between a corresponding one of the tap nodes (e.g., tap node 352) and the input reference voltages VrefH 134H and VrefL 134L, respectively. In the differential example shown, the switch circuit 314 includes a first and a second switch for each R-2R segment. Each switch is connected between a segment tap node and a corresponding one of the input reference voltages VrefH 134H and VrefL 134L. The switches of the switch circuit 314 operate in a complementary manner according to a corresponding one of the first sub-word bits dacm<8:0> (dac<15:7>) to connect the corresponding tap node to the input VrefH 134H or VrefL 134L.

[0044] exist Figure 3 In the example of FIG. 3 , the resistor circuit 304 includes 6 segments that are switched according to the first 6 MSB bits dacm<5:0>, and the remaining 3 MSB bits dacm<8:6> (eg, the 3 most significant bits of the MSB bits) are provided as inputs to the thermocouple decoder 322. Figure 3 In the example of , the MSB R-2R DAC 192 is a 3-bit hot decoding and 6-bit binary decoding circuit. In an embodiment, the thermocouple decoder 322 includes an output 324 that provides a thermocouple encoded switch control signal T<6:0> to operate the OEM switch circuit 318. Figure 3 In the example shown in , the resistive OEM circuit 308 implements ordered element matching using 7 sets of OEM resistor elements. In an embodiment, the resistor elements of the OEM circuit 308 have a resistance of 2R. The 2R resistor elements of each set of OEM resistor elements are connected between an OEM tap node (e.g., OEM tap node 356) and a corresponding one of the outputs VH 136H, VL 136L. Figure 3 In the example shown in FIG. 1 , OEM switch circuit 318 includes seven sets of two OEM switches (e.g., OEM switch 358) to selectively connect a corresponding one of the OEM resistor elements between input VrefH 134H, VrefL 134L and output VH 136H, VL 136L based on an OEM code set by switch control signal T<6:0> from thermocouple decoder 322. The OEM switches of OEM switch circuit 318 operate in a complementary manner according to a corresponding one of control signals T<6:0> to connect a corresponding OEM tap node (e.g., OEM tap node 356) to input VrefH 134H or VrefL 134L.

[0045] In some embodiments, the number of thermocouple bits decoded in the 9-bit MSB R-2R DAC 192 and whether there is a 0.5LSB shift determines the total resistance in the resistor ladder 194. The following table shows the total resistance utilized by the resistor ladder 194 for 3-bit interpolation:

[0046]

[0047]

[0048] Figure 3 The MSB R-2R DAC 192 in the embodiment also includes a resistive chopping circuit 306 having a plurality of chopping resistors having a resistance value of 2R and a chopping switch circuit 316. In an embodiment, the chopping switch circuit 316 includes a plurality of chopping switches (e.g., a chopping switch 362) to selectively and simultaneously connect a corresponding one of the chopping resistors to the inputs VrefH 134H, VrefL 134L. In addition, the chopping switch circuit 316 is configured to receive a chopping code “Chop” 144. In some embodiments, the chopping circuit system (e.g., the resistive chopping circuit 306 and the chopping switch circuit 316) can be omitted, wherein the R-2R circuit system (e.g., the R-2R circuit 304, the first switch circuit 314, the OEM circuit 308, the OEM switch circuit 318, and / or the thermocouple decoder 322) provides component segmentation for all MSB bits dacm<9:0>.

[0049] Figure 3 The MSB R-2R DAC 192 in the embodiment of the present invention operates according to the MSB bits <5:0>. The switches of the first switch circuit 314 switch between V=0 (logical 0) and V=Vref (logical 1), where in the differential example shown, Vref=VrefH 134H-VrefL 134L. The R-2R network weights the MSB digital bits in their contribution to the outputs VH 136H, VL 136L, and therefore the voltage VOUT 124. Depending on which bits are set to 1 and which bits are set to 0, the output VOUT 124 has a corresponding step value between 0 and the value of Vref minus the minimum step size, which corresponds to bit 0 (dacm <0> ). The actual value of Vref (and the voltage of a logical 0) will depend on the type of technology used to generate the digital signal. The R-2R DAC is a binary weighted voltage divider. The 2R branches in parallel with each series 1R resistor produce the binary weighting, and only one bit of the first sub-word MSB 126M is required for each bit of resolution. The switch is grounded or connected to a reference voltage. In addition, the equivalent impedance of the ladder resistor is generally lower than that of a conventional string DAC, and therefore, the MSB R-2R DAC 192 has lower noise.

[0050] Figure 4A 1 to 2 show exemplary circuit diagrams of the chopper switch circuit 316 according to various examples. Figure 4A and 4B , the chopper switch circuit 316 is configured such that switches 402 and 404 are connected to VrefH 134H, while switches 362 and 406 are connected to VrefL 134L. Figure 4A An example configuration of the switches is shown when chop 144 is low (equal to zero). In such a configuration, switches 402 and 404 are open, while switches 362 and 406 are closed. Figure 4B An example configuration of the switches is shown when chop 144 is high (equal to 1). In such a configuration, switches 402 and 404 are closed, while switches 362 and 406 are open.

[0051] exist Figure 4C and 4D , the chopper switch circuit 316 is configured such that switches 402 and 406 are connected to VrefH 134H, while switches 362 and 404 are connected to VrefL 134L. Figure 4C An example configuration of the switches is shown when chop 144 is low (equal to zero). In such a configuration, switches 402 and 406 are open, while switches 362 and 404 are closed. Figure 4D An example configuration of the switches is shown when chop 144 is high (equal to 1). In such a configuration, switches 402 and 406 are closed, while switches 362 and 404 are open.

[0052] Figure 5A B to B show various examples for use with a thermocouple having three positions (such as Figure 3 1 (shown in FIG. 1 ) is an exemplary circuit diagram of a 3-bit ISB resistor ladder 194 of an interpolation RDAC 108 of a 9-bit MSBR-2R DAC 192. As described above, in an embodiment, the ISB resistor ladder 194 is configured to generate the analog interpolation signal 146 using the first analog output signal VH 136H, VL 136L. Figure 5A In the example shown in FIG. 1B , a 0.5 LSB shift is provided in the analog interpolated signal 146 .

[0053] In an embodiment, Figure 5A The ISB resistor ladder 194 from 1 to 194B includes a resistor circuit 502 and a switch circuit 504. The resistors in the resistor circuit 502 are formed as resistor elements with a resistance value of 1 / 2R (half of a unit resistor and / or two unit resistors in parallel). In other words, in an embodiment, the resistors in the resistor circuit 502 are based on the value of a unit resistor. In an embodiment, the resistor circuit 502 is composed of a series of resistor elements (in Figure 5AIn the example of FIG. 5B , there are 7 resistor elements separated by tap nodes (e.g., tap node 552) to B so as to generate 8 voltage levels for a 0.5 LSB shift. For example, the resistor elements can be connected in series with each other to define a plurality of tap nodes between adjacent resistor elements of the resistor elements. In an embodiment, the switch circuit 504 includes a plurality of switches (e.g., switch 554) respectively connected between a corresponding one of the tap nodes (e.g., tap node 552) and the output of the ISB ladder resistor 194.

[0054] exist Figure 5A In the example of FIG. 1 to B, the three ISB bits dac<6:4> are provided as inputs to the binary decoder 506. The binary decoder 506 provides a switch control signal c<7:0> to operate the switch circuit 504 by activating one of the eight output bits for each input value from 0 to 7. The switches of the switch circuit 504 are operated in a complementary manner according to a corresponding one of the control signals c<7:0> from the binary decoder 506 to connect the corresponding tap node (e.g., tap node 552) to the output of the ISB ladder resistor 194 to generate the analog interpolated signal 146. Figure 5A The example shown in is for a circuit where chop 144 is low, while Figure 5B The example shown in is for a circuit where chop 144 is high.

[0055] The following table shows that Figure 5A An example of a decoded and idealized analog interpolated signal 146 generated by the resistor ladder 194 is shown in FIG.

[0056]

[0057]

[0058] Chopping 144 swaps the decoder outputs c<0:7> so that the output voltages are the same for the same dacm<6:4>.

[0059] Fig. 6A C to C show various examples for use with a thermocouple having three positions (such as Figure 3 104 is an illustrative circuit diagram of a 3-bit ISB resistor ladder 194 of an interpolated RDAC 108 of a 9-bit MSBR-2R DAC 192 of FIG. 104 . Fig. 6A The example ISB resistor ladder 194 shown in C is Figure 5A The ISB resistor ladder 194 shown in FIG. 1 operates in a similar manner to the ISB resistor ladder 194 shown in FIG. Fig. 6A The example ISB resistor ladder 194 in FIG. 1 to C includes only 6 resistor elements. For example, in an embodiment, Fig. 6A and 6BThe decoder generates 7 voltage levels to utilize Figures 4A to 4B The chopper switch circuit 316 generates 1-7LSB values ​​and then uses Figure 4C The chopping switch circuit 316 to D generates a 0LSB or 8LSB value to generate a 0-7LSB or 1-8LSB analog interpolation signal 146. Fig. 6A In the examples of FIG. 1 to B, each of the resistance elements has a resistance of 1 / 4R (a quarter of a unit resistance and / or 4 unit resistances in parallel). Therefore, Fig. 6A The output of the example ISB resistor ladder 194 shown in FIG. 1B does not provide an LSB shift used to generate the analog interpolated signal 146 . Fig. 6A The example shown in is for a circuit where chop 144 is low, while Figure 6B The example shown in is for a circuit where chop 144 is high.

[0060] In some embodiments, Fig. 6A and 6B The decoder is not a universal decoder (e.g., a 3-8 decoder). The following table shows the decoder that can be used by Fig. 6A An example of a decoded and ideal analog interpolated signal 146 from 0 to 4095 generated by the ladder resistor 194 shown in FIG.

[0061]

[0062]

[0063] Figure 6C Generate and Fig. 6A Same output, but utilizing fewer actual resistors. As mentioned above, Fig. 6A The resistor ladder 194 from R to C includes 6R resistors. Fig. 6A To B, 24 unit resistors can be used to generate a 6R resistor. Figure 6C In the example, 8 unit resistors can be used to generate a 6R resistor and generate the same analog interpolation signal 146.

[0064] Figure 7 An exemplary circuit diagram of an 8-bit MSB R-2RDAC 192 for use with the interpolating RDAC 108 of the segmented DAC circuit 100 is shown in accordance with various examples. The exemplary 8-bit R-2R DAC 192 is used with Figure 3 The 9-bit R-2R DAC 192 shown in FIG. 1 works in a similar manner. However, in an embodiment, the 8-bit R-2R DAC utilizes 8 bits for the MSB 126M and 2-bit hot decoding. In other words, Figure 7The 8-bit R-2R DAC 192 shown in FIG. 1 is 2-bit hot decoding with 6-bit binary decoding. In other embodiments, more or fewer bits may be used for hot decoding.

[0065] In some embodiments, the number of thermocouple bits decoded in the 8-bit MSB R-2R DAC 192 corresponds to and / or determines the total resistance in the resistor ladder 194. The following table shows the total resistance utilized by the resistor ladder 194 in conjunction with the 8-bit MSB R-2R DAC 192 for 4-bit interpolation:

[0066]

[0067] Fig. 8A B to B show various examples of a method for using a thermocouple having two thermocouple positions (such as Figure 7 104 is an illustrative circuit diagram of a 4-bit ISB resistor ladder 194 of an interpolated RDAC 108 of an 8-bit MSBR-2R DAC 192 of FIG. 104 . Fig. 8A The example ISB resistor ladder 194 shown in FIG. Figure 5A The ISB resistor ladder 194 shown in FIG. 1 operates in a similar manner to the ISB resistor ladder 194 shown in FIG. Fig. 8A The example ISB resistor ladder 194 in FIG. 1 to B includes 15 taps. Fig. 8A In the examples of B to B, each of the resistance elements has a resistance of 1 / 2R (half of a unit resistance and / or 2 unit resistances in parallel). Therefore, Fig. 8A The output of the example ISB resistor ladder 194 shown in FIG. 1B does not provide an LSB shift used to generate the analog interpolated signal 146 . Fig. 8A The example shown in is for a circuit where chop 144 is low, while Figure 8B The example shown in is for a circuit where chop 144 is high.

[0068] In some embodiments, Fig. 8A and 8B The decoder of is not a universal decoder (e.g., a universal 4-16 decoder). The following table shows the decoder that can be used by Fig. 8A An example of a decoded and idealized analog interpolated signal 146 generated by the resistor ladder 194 is shown in FIG.

[0069]

[0070]

[0071] Fig. 9A 4 to B show illustrative circuit diagrams of a 4-bit ISB resistor ladder 194 for an interpolating RDAC 108 having an 8-bit MSB R-2R DAC 192 with 3 thermocouple bits, according to various examples. Fig. 9A The example ISB resistor ladder 194 shown in FIG. Figure 5A operates in a similar manner to the ISB resistor ladder 194 shown in B. However, in Fig. 9A In the example of , each of the resistance elements has a resistance of 1 / 4R (a quarter of a unit resistance and / or 4 unit resistances in parallel). Therefore, Fig. 9A The output of the example ISB resistor ladder 194 shown in FIG. 1 does not provide an LSB shift used to generate the analog interpolated signal 146 . Fig. 9A The example shown in is for a circuit where chop 144 is low.

[0072] Fig. 9B Generate and Fig. 9A Same output, but utilizing fewer actual resistors. As mentioned above, Fig. 9A The resistor ladder 194 from A to B includes 3.5R resistors. Fig. 9A In , 56 unit resistors can be used to generate a 3.5R resistor. Fig. 9B , 24 unit resistors can be used to generate a 3.5R resistor and generate the same analog interpolation signal 146.

[0073] The interpolation RDAC 108 advantageously employs an MSB R-2R DAC 192 to convert the first sub-word MSB 126M into a first analog output signal VH 136H, VL 136L using far fewer switches than a conventional ladder resistor MSB DAC. The interpolation RDAC 108 also provides interpolation through the ISB ladder resistor 194, which reduces the need for an interpolation amplifier. Thus, the need for calibration memory is reduced, and the complexity of the conventional system introduced by the interpolation amplifier is also reduced. The SDM 196 can be selectively employed to achieve additional resolution of the segmented DAC circuit 100, and 16-bit resolution can be achieved without the need for an additional calibration DAC. The reduction in switch and memory capacity and the reduction in complexity compared to conventional DACs reduce circuit area and power consumption while increasing speed.

[0074] Fig. 10A 4 to 5 C show an exemplary chopping function in the segmented DAC circuit 100 according to various examples. Fig. 10A A chopping signal 144 is shown applied to the interpolating RDAC 108. The chopping signal 144 causes the interconnection of the first analog output signal 136 to be swapped between the output of the MSB R-2R DAC 192 and the ISB resistor ladder 194. More specifically, in an embodiment, the chopping signal 144 is provided to the input of the MSB R-2R DAC 192 to switch the VH 136H and VL 136L provided to the input of the ISB resistor ladder 194.

[0075] Fig. 10B The chopped signal 144 is shown applied to the interpolating RDAC 108 and the buffer amplifier 110. Fig. 10A As in the example, Fig. 10B In the example of FIG. 1 , in an embodiment, the chopped signal 144 is provided to the input of the MSB R-2R DAC 192 to switch the VH 136H and VL 136L provided to the input of the ISB resistor ladder 194. In addition, the buffer amplifier 110 includes a chopper amplifier 1002 to decompose the analog interpolated signal 146 received from the interpolating RDAC 108 for processing as an AC signal. Once processed, the signal will be integrated back to a DC signal at the output to generate VOUT 124.

[0076] Fig. 10C 1 shows the application of the chopped signal 144 to the buffer amplifier 110. Fig. 10B As in the example, Fig. 10C In the example of FIG. 1 , the buffer amplifier 110 includes a chopper amplifier 1004 to decompose the analog interpolated signal 146 received from the interpolating RDAC 108 for processing as an AC signal. Once processed, the signal is integrated back to a DC signal at the output to generate VOUT 124 .

[0077] The segmented DAC circuit 100 is implemented by using an interpolating RDAC 108 (comprising Figure 3 and 7 The MSB R-2R DAC 192 and Figures 4A to 6C and Figures 8A to 9B The ISB resistor ladder 194) also helps reduce the need for calibration memory and shortens factory calibration time. In some examples, high performance can be achieved in terms of low integral nonlinearity error (INL) and differential nonlinearity error (DNL). For example, for the 16-bit case, within the calibration range of + / -32LSB, an INL and DNL of less than + / -1LSB can be achieved using a calibration step size of + / -1 / 4. In a 16-bit example using a 12-bit MSB DAC 120, the calibration memory only requires 12×8-bit memory 108 for MSB calibration with chopping function, 12×8-bit memory for MSB calibration without chopping function, and 16×6-bit memory for LSB calibration. In this example, no additional calibration DAC is used.

[0078] Fig.11An illustrative flow chart of a method 1100 for calibrating a DAC according to various examples is shown. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. In addition, some embodiments may only perform some of the actions shown. In some embodiments, at least some of the operations of method 1100 and other operations described herein are performed by segmented DAC circuit 100. More specifically, at least some of the operations of method 1100 and other operations described herein are performed by decoder 102, calibration circuit 104, calibration and DEM circuit (including SDM 196), interpolation DAC 108 (including MSB R-2R DAC 192 and / or ISB ladder resistor 194), buffer amplifier 110, OEM memory 112 and / or multiplexer 114, 116, and are implemented in a logical manner.

[0079] Method 1100 provides calibration for a DAC circuit that converts a K-bit digital input signal (e.g., CODE 122 above), the digital input signal including an M-bit first sub-word MSB, an I-bit second sub-word ISB, and an L-bit third sub-word LSB, the M-bit first sub-word MSB including the most significant bit of the digital input signal, the L-bit third sub-word LSB including the least significant bit of the digital input signal. The method 1100 in an embodiment is implemented during the manufacture of the segmented DAC circuit 100. In addition, compared to conventional calibration processes, the calibration method 1100 provides significant advantages in calibration memory utilization and calibration time. Relative to conventional calibration processes, the method 1100 does not require trimming of the calibration DAC and can be implemented using much less calibration memory than conventional techniques.

[0080] The method 1100 begins in block 1102, where a DAC output voltage including an output voltage of an R-2R DAC is measured for a corresponding set of values ​​of a first sub-word, an output voltage of a ladder resistor is measured for a corresponding set of values ​​of a second sub-word, and an output voltage of an SDM is measured for a corresponding set of third sub-word values. At 1110, the method includes calculating an output voltage value of a segmented DAC based on the measured output voltage. At 1120, the method provides a calibration code for calculating the R-2R DAC, the ladder resistor, and the SDM, and calculates and stores a K-bit calibration code for the DAC circuit based on the calibration code. Thereafter, at 1130, the method includes calculating a calibrated DAC INL and DNL. The method 1100 is described in the context of a 16-bit segmented DAC circuit 100 as described above, including M=9-bit first sub-word MSB, I=3-bit second sub-word ISB, and L=4-bit third sub-word LSB, but the method 1100 can be used in conjunction with calibration of other segmented DAC systems having other values ​​of M, I, and / or L.

[0081] In an embodiment, the output voltage measurement at 1102 includes blocks 1104 to 1108. In block 1104, the method 700 begins measuring M+1 output voltages VH, VL, such as VH 136H and VL 136L, of an M-bit MSB R-2R DAC (such as the MSB R-2R DAC 192) for a corresponding set of M+1 values ​​of the first sub-word MSB. In the example shown, the set of M+1 values ​​of the first sub-word MSB includes a first set in which all bits are set to 0 and only one bit of the M values ​​is set to 1. Because M+1 output voltages VH, VL are measured, 10 values ​​of the first sub-word MSB are evaluated for measurement at 1104. This significantly saves measurement time compared to a conventional ladder resistor DAC of a segmented DAC system. The method 1100 continues in block 1106, in which a corresponding set of 2 values ​​of the second sub-word ISB is measured. I A unique value is measured for a 1-bit ISB ladder resistor (such as ISB ladder resistor 194) of 2 I (eg, 8) output voltages, such as the analog interpolated signal 146. For example, in block 1108, the method 1100 continues with a corresponding set of 2 for the third sub-word LSB. L unique value, measuring 2 of an L-bit SDM (such as SDM 196) L (eg 16) output voltages, such as ICODE 138.

[0082] In an embodiment, the calculation at 1110 includes blocks 1112 to 1114. In block 1112, the method 1100 continues to calculate a K-bit output voltage value DAC VOUT, such as VOUT 124, based on the measured output voltages VH, VL, the analog interpolated signal, and ICODE. In block 1114, the method 1100 continues to calculate INL and DNL based on the K-bit output voltage value DAC VOUT calculated at 1112.

[0083] In an embodiment, processing at 1120 includes blocks 1122 to 1128. In block 1122, the method 1100 continues to calculate a calibration code CAL_MSB for the MSB R-2R DAC. In an embodiment, for ISB=VREF / 512, calculating the calibration code CAL_MSB includes calculating a 9-bit MSB calibration code code_9_bits_MSB according to the following formula: code_9_bits_MSB=(VH-VL_ideal) / (0.25*LSB). The method 1100 continues in block 1124, where a calibration code CAL_ISB for the ISB ladder resistor is calculated. In an embodiment, calculating the calibration code CAL_ISB includes calculating a 3-bit ISB calibration code "code_3_bits_ISB" according to the following formula: code_3_bits_ISB=(analog interpolated signal-ideal analog interpolated signal) / (0.25*LSB). In block 1126, the method 1100 continues to calculate the calibration code CAL_LSB for the SDM. The method 1100 continues in block 1128, where a K-bit calibration code for the segmented DAC circuit 100 is calculated based on the calibration codes CAL_MSB, CAL_ISB, CAL_LSB, and the K-bit calibration code is stored in a calibration memory, such as the calibration memory 104. The calibrated 16-bit DAC INL and DNL values ​​may then be calculated at 1130.

[0084] Fig.12 An illustrative flow chart of a method 1200 for converting a digital input signal into a corresponding analog output signal according to various examples is shown. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. In addition, some embodiments may only perform some of the actions shown. In some embodiments, at least some of the operations of method 1200 and other operations described herein are performed by segmented DAC circuit 100. More specifically, at least some of the operations of method 1200 and other operations described herein are performed by decoder 102, calibration circuit 104, calibration and DEM circuit (including SDM 196), interpolation DAC 108 (including MSB R-2R DAC 192 and / or ISB ladder resistor 194), buffer amplifier 110, OEM memory 112 and / or multiplexer 114, 116, and are implemented in a logical manner.

[0085] The method 1200 begins in block 1202, where a first sub-word of a digital input signal is received. The first sub-word includes an integer number of M bits, the integer number of M bits including the MSB of the digital input signal. For example, the M-bit MSB R-2R DAC 192 may receive the first sub-word MSB 126M from a decoder that receives the original digital signal (e.g., CODE 122). As described above, in some embodiments, the first sub-word is 9 bits. In block 1204, the method 1200 continues, where an analog output signal having a voltage representing the first sub-word is generated by the R-2R DAC. For example, the MSB R-2R DAC 192 may generate VH 136H and VL 136L as differential signals representing the first sub-word MSB 126M.

[0086] The method 1200 continues in block 1206, where an analog signal is generated by a ladder resistor based on the second sub-word of the analog output signal and the digital input signal. The second sub-word includes an integer 1 bit, and the integer 1 bit includes the ISB of the digital input signal. For example, the 1-bit ISB ladder resistor 194 can receive VH 136H, VL 136L, and the second sub-word ISB 126I. As described above, in some embodiments, the second sub-word is 3 bits. By utilizing VH 136H, VL 136L, and the second sub-word ISB 126I, the ISB ladder resistor can generate an analog interpolation signal 146. In block 1208, the method 1200 continues, where an analog output signal is generated by a buffer amplifier based on the analog interpolation signal. For example, the buffer amplifier 110 can receive the analog interpolation signal 146 and generate VOUT 124, which in some embodiments is a unity voltage gain of the analog interpolation signal 146 with a higher current version.

[0087] The above discussion is intended to illustrate the principles and various embodiments of the present disclosure. Once the above disclosure is fully understood, many changes and modifications will become apparent to those skilled in the art. The following claims are also intended to be interpreted as encompassing all such changes and modifications.

Claims

1. An integrated circuit IC device, comprising: A digital / analog converter DAC circuit, comprising: A resistor DAC comprising: a resistor dual resistor R-2R DAC configured to receive a first sub-word including a most significant bit (MSB) of a digital input signal and output an analog output signal representing the first sub-word; and a ladder resistor configured to receive the analog output signal and a second sub-word including an intermediate significant bit ISB of the digital input signal and generate an analog interpolation signal, wherein the ladder resistor comprises: a plurality of resistance elements connected in series with each other to define a plurality of tap nodes, wherein a respective tap node is arranged between every two adjacent resistance elements of the resistance elements; and A switching circuit has a plurality of switches, wherein each switch is configured to selectively connect a corresponding one of the tap nodes to an output of the resistor ladder to generate the analog interpolation signal.

2. The IC device according to claim 1, wherein: The first sub-word comprises M bits of the digital input signal; and The second sub-word includes 1 bit of the digital input signal.

3. The IC device of claim 2, wherein M and I are both integers, and wherein M is greater than I.

4. The IC device of claim 3, wherein M is equal to 9 and I is equal to 3.

5. The IC device of claim 1, wherein the DAC circuit comprises a buffer amplifier configured to receive the analog interpolated signal and generate an output signal for the DAC circuit.

6. The IC device of claim 1, wherein the IC device is a microcontroller.

7. An integrated circuit IC device, comprising: A digital / analog converter DAC circuit, comprising: A resistor DAC comprising: a resistor dual resistor R-2R DAC configured to receive a first sub-word including a most significant bit (MSB) of a digital input signal and output an analog output signal representing the first sub-word; and a ladder resistor configured to receive the analog output signal and a second sub-word including an intermediate significant bit ISB of the digital input signal and generate an analog interpolation signal; and A calibration circuit is configured to generate a calibration code and a modulator code, wherein the modulator code is generated based on the calibration code, the second sub-word, and a third sub-word including the least significant bits (LSBs) of the digital input signal.

8. The IC device of claim 7, wherein the digital input signal is K bits, the first sub-word contains M bits of the digital input signal, the second sub-word contains I bit of the digital input signal, and the third sub-word contains L bits of the digital input signal, wherein K, M, I, and L are all integers.

9. The IC device of claim 8, wherein no bit in the first sub-word is part of the second sub-word or the third sub-word, and wherein no bit in the second sub-word is part of the third sub-word. 10 . The IC device of claim 8 , wherein K is equal to 16, M is equal to 9, I is equal to 3, and L is equal to 4.

11. The IC device of claim 8, wherein the calibration code is generated using calibration data based on the digital input signal.

12. The IC device of claim 11, wherein the calibration circuit is configured to store a first set of KxM bits of calibration data for the second sub-word and a second set of KxM bits of calibration data for the third sub-word.

13. The IC device of claim 7, wherein the resistance DAC comprises a buffer amplifier configured to receive the analog interpolation signal and generate an output signal for the DAC circuit.

14. An integrated circuit IC device, comprising: A digital / analog converter DAC circuit, comprising: A resistor DAC comprising: a resistor dual resistor R-2R DAC configured to receive a first sub-word comprising a first portion of a digital input signal and to output an analog output signal representative of the first sub-word; and a resistor ladder configured to receive the analog output signal and a second sub-word comprising a second portion of the digital input signal and generate an analog interpolated signal; and a buffer amplifier configured to receive the analog interpolated signal and generate an output signal for the DAC circuit, the buffer amplifier comprising: A chopper circuit is configured to decompose the analog interpolated signal for processing as an AC signal and integrate the AC signal back to a DC signal at the output of the buffer amplifier to generate the output signal for the DAC circuit.

15. The IC device of claim 14, wherein the digital input signal comprises K bits, and wherein the first portion of the digital input signal comprises M bits of the K bits, the M bits comprising most significant bits (MSBs) of the digital input signal.

16. The IC device of claim 15, wherein the second portion of the digital input signal comprises 1 bit of the K bits, the 1 bit comprising an intermediate significant bit (ISB) of the digital input signal.

17. The IC device of claim 16, wherein any of the I bits are not included in the M bits.

18. The IC device of claim 17, wherein K is equal to 16, M is equal to 9, and I is equal to 3.

19. A circuit device comprising: an input configured to receive a digital input specifying a set of most significant bits, a set of middle significant bits, and a set of least significant bits; A first digital-to-analog converter comprising: A first reference voltage input; A second reference voltage input; A first voltage output; A second voltage output; a first set of switches coupled to the first reference voltage input and coupled to switches based on the set of most significant bits; a second set of switches coupled to the second reference voltage input and coupled to switches based on the set of most significant bits; a first set of resistors, each of the first set of resistors having a first terminal coupled to a corresponding switch of the first set of switches and a corresponding switch of the second set of switches and having a second terminal; a second set of resistors coupled in series such that each of the second set of resistors is coupled between the second terminals of a corresponding pair of the first set of resistors and such that the second set of resistors couples the first set of resistors to the first voltage output; a third set of resistors, each of the third set of resistors having a first terminal coupled to a corresponding switch of the first set of switches and a corresponding switch of the second set of switches and having a second terminal; and a fourth set of resistors coupled in series such that each of the fourth set of resistors is coupled between the second terminals of a corresponding pair of the third set of resistors and such that the fourth set of resistors couples the third set of resistors to the second voltage output; and A second digital-to-analog converter comprising: a first voltage input coupled to the first voltage output of the first digital-to-analog converter; a second voltage input coupled to the second voltage output of the first digital-to-analog converter; and An output configured to provide an analog voltage based on: the first voltage output and the second voltage output of the first digital-to-analog converter, and at least one of the set of intermediate significant bits or the set of least significant bits.

20. The circuit arrangement according to claim 19, wherein: The resistance of each of the first set of resistors is twice the resistance of each of the second set of resistors; and The resistance of each of the third set of resistors is twice the resistance of each of the fourth set of resistors.

21. The circuit device of claim 19, wherein the second digital-to-analog converter comprises a ladder resistor circuit.

22. The circuit device of claim 21, wherein the resistor ladder circuit comprises: a fifth set of resistors coupled in series, wherein a plurality of tap nodes are arranged between adjacent pairs of resistors of the fifth set of resistors; and A third set of switches, each of which is coupled between a corresponding tap node of the plurality of tap nodes and the output of the second digital-to-analog converter and is coupled to a switch based on the at least one of the set of middle significant bits or the set of least significant bits.

23. The circuit device of claim 19, wherein the first digital-to-analog converter comprises: a thermocouple decoder comprising a set of inputs coupled to receive a subset of the set of most significant bits and a set of outputs configured to provide a set of control signals based on the subset of the set of most significant bits; a third set of switches, each of the third set of switches coupled to the first reference voltage input and coupled to a switch based on the set of control signals; a fourth set of switches, each of the fourth set of switches coupled to the second reference voltage input and coupled to a switch based on the set of control signals; a fifth set of resistors, each of the fifth set of resistors having a first terminal coupled to a respective switch of the third set of switches and a respective switch of the fourth set of switches and having a second terminal directly coupled to the first voltage output; and A sixth set of resistors, each of the sixth set of resistors having a first terminal coupled to a corresponding switch of the third set of switches and a corresponding switch of the fourth set of switches and having a second terminal directly coupled to the second voltage output.

24. The circuit device of claim 19, wherein the first digital-to-analog converter comprises: a first set of chopping switches, each of the first set of chopping switches coupled to the first reference voltage input and coupled to a switch based on a chopping signal; a second set of chopping switches, each of the second set of chopping switches coupled to the second reference voltage input and coupled to a switch based on the chopping signal; a first chopper resistor having a first terminal coupled to a corresponding switch of the first set of chopper switches and a corresponding switch of the second set of chopper switches and having a second terminal coupled to the first voltage output through the second set of resistors; and A second chopper resistor has a first terminal coupled to a corresponding switch of the first set of chopper switches and a corresponding switch of the second set of chopper switches and has a second terminal coupled to the second voltage output through the fourth set of resistors.

25. The circuit arrangement of claim 24, further comprising a buffer, the buffer comprising: a first input coupled to the output of the second digital-to-analog converter to receive the analog voltage; a second input coupled to receive the chopped signal; and An output is configured to provide an output voltage based on the analog voltage of the second digital-to-analog converter and the chopped signal.

26. The circuit device of claim 19, further comprising a multiplexer coupled to receive the set of least significant bits and an interpolated signal based on the set of intermediate significant bits and the set of least significant bits, wherein the multiplexer includes an output configured to provide a signal selected between the set of least significant bits and the interpolated signal.

27. A circuit device comprising: an input configured to receive a digital input specifying a set of most significant bits, a set of middle significant bits, and a set of least significant bits; A first digital-to-analog converter is configured to: receiving the set of most significant bits; and providing a differential output voltage based on the set of most significant bits; and a second digital-to-analog converter coupled to the first digital-to-analog converter, the second digital-to-analog converter comprising a ladder resistor circuit configured to: receiving the differential output voltage; and providing an analog voltage based on: the differential output voltage and at least one of the set of middle significant bits or the set of least significant bits; The first digital-to-analog converter comprises: A first reference voltage input; A second reference voltage input; a first output and a second output for providing the differential output voltage; a first set of switches coupled to the first reference voltage input; a second set of switches coupled to the second reference voltage input; a first set of resistors, each of the first set of resistors having a first terminal coupled to a corresponding switch of the first set of switches and a corresponding switch of the second set of switches and having a second terminal; a second set of resistors coupled such that each of the second set of resistors is coupled between the second terminals of a corresponding pair of the first set of resistors and such that the second set of resistors couples the first set of resistors to the first output of the first digital-to-analog converter; a third set of resistors, each of the third set of resistors having a first terminal coupled to a corresponding switch of the first set of switches and a corresponding switch of the second set of switches and having a second terminal; and A fourth set of resistors coupled such that each of the fourth set of resistors is coupled between the second terminals of a corresponding pair of the third set of resistors and such that the fourth set of resistors couples the third set of resistors to the second output of the first digital-to-analog converter.

28. The circuit arrangement of claim 27, wherein: The resistance of each of the first set of resistors is twice the resistance of each of the second set of resistors; and The resistance of each of the third set of resistors is twice the resistance of each of the fourth set of resistors.

29. The circuit device of claim 27, wherein the first digital-to-analog converter comprises: a thermocouple decoder comprising a set of inputs coupled to receive a subset of the set of most significant bits and a set of outputs configured to provide a set of control signals based on the subset of the set of most significant bits; a third set of switches, each of the third set of switches coupled to the first reference voltage input and coupled to a switch based on the set of control signals; a fourth set of switches, each of the fourth set of switches coupled to the second reference voltage input and coupled to a switch based on the set of control signals; a fifth set of resistors, each of the fifth set of resistors having a first terminal coupled to a corresponding switch of the third set of switches and a corresponding switch of the fourth set of switches and having a second terminal directly coupled to the first output of the first digital-to-analog converter; and A sixth set of resistors, each of the sixth set of resistors having a first terminal coupled to a corresponding switch of the third set of switches and a corresponding switch of the fourth set of switches and having a second terminal directly coupled to the second output of the first digital-to-analog converter.

30. The circuit device of claim 27, wherein the first digital-to-analog converter comprises: a first set of chopping switches, each of the first set of chopping switches coupled to the first reference voltage input and coupled to a switch based on a chopping signal; a second set of chopping switches, each of the second set of chopping switches coupled to the second reference voltage input and coupled to a switch based on the chopping signal; a first chopper resistor having a first terminal coupled to a corresponding switch of the first set of chopper switches and a corresponding switch of the second set of chopper switches and having a second terminal coupled to the first output of the first digital-to-analog converter through the second set of resistors; and A second chopping resistor has a first terminal coupled to a corresponding switch of the first set of chopping switches and a corresponding switch of the second set of chopping switches and has a second terminal coupled to the second output of the first digital-to-analog converter through the fourth set of resistors.

31. The circuit arrangement of claim 30, further comprising a buffer, the buffer comprising: a first input coupled to the second digital-to-analog converter to receive the analog voltage; a second input coupled to receive the chopped signal; and An output is configured to provide an output voltage based on the analog voltage of the second digital-to-analog converter and the chopped signal.

32. The circuit device of claim 27, wherein the resistor ladder circuit comprises: a set of resistors coupled in series, wherein a plurality of tap nodes are arranged between adjacent pairs of resistors of the set of resistors; and A set of switches, each of which is coupled between a corresponding tap node of the plurality of tap nodes and an output of the second digital-to-analog converter and is coupled to a switch based on the at least one of the set of middle significant bits or the set of least significant bits.

33. A circuit device comprising: an input configured to receive a digital input specifying a set of most significant bits, a set of middle significant bits, and a set of least significant bits; A first digital-to-analog converter comprising: A first reference voltage input; A second reference voltage input; a voltage output configured to provide a first analog voltage based on the set of most significant bits; a first set of switches coupled to the first reference voltage input and coupled to switches based on the set of most significant bits; a second set of switches coupled to the second reference voltage input and coupled to switches based on the set of most significant bits; a first set of resistors, each of the first set of resistors having a first terminal coupled to a corresponding switch of the first set of switches and a corresponding switch of the second set of switches and having a second terminal; a second set of resistors coupled in series such that each of the second set of resistors is coupled between the second terminals of a corresponding pair of the first set of resistors and such that the second set of resistors couples the first set of resistors to the voltage output; and A second digital-to-analog converter comprising: a voltage input coupled to the voltage output of the first digital-to-analog converter; and A resistor ladder circuit is coupled to provide a second analog voltage based on the first analog voltage and at least one of the set of mid-significant bits or the set of least-significant bits.

34. The circuit arrangement of claim 33, wherein: The voltage output of the first digital-to-analog converter is a first voltage output; and The first digital / analog converter comprises: a second voltage output configured to provide the first analog voltage as a differential voltage in combination with the first voltage output; a third set of resistors, each of the third set of resistors having a first terminal coupled to a corresponding switch of the first set of switches and a corresponding switch of the second set of switches and having a second terminal; and A fourth set of resistors are coupled in series such that each of the fourth set of resistors is coupled between the second terminals of a corresponding pair of the third set of resistors and such that the fourth set of resistors couples the third set of resistors to the second voltage output.

35. The circuit device of claim 33, wherein a resistance of each of the first set of resistors is twice a resistance of each of the second set of resistors.

36. The circuit device of claim 33, wherein the first digital-to-analog converter comprises: a first set of chopping switches, each of the first set of chopping switches coupled to the first reference voltage input and coupled to a switch based on a chopping signal; a second set of chopping switches, each of the second set of chopping switches coupled to the second reference voltage input and coupled to a switch based on the chopping signal; and A chopper resistor has a first terminal coupled to a corresponding switch of the first set of chopper switches and a corresponding switch of the second set of chopper switches and has a second terminal coupled to the voltage output through the second set of resistors.

37. The circuit device of claim 33, wherein the first digital-to-analog converter comprises: a thermocouple decoder comprising a set of inputs coupled to receive a subset of the set of most significant bits and a set of outputs configured to provide a set of control signals based on the subset of the set of most significant bits; a third set of switches, each of the third set of switches coupled to the first reference voltage input and coupled to a switch based on the set of control signals; a fourth set of switches, each of the fourth set of switches coupled to the second reference voltage input and coupled to a switch based on the set of control signals; and A third set of resistors, each of the third set of resistors having a first terminal coupled to a corresponding switch of the third set of switches and a corresponding switch of the fourth set of switches, and having a second terminal directly coupled to the voltage output.

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