Optical receiving circuit and optical coupling device

Abstract

The invention provides an optical receiving circuit and an optical coupling device, and an optical sensing device in the optical receiving circuit comprises a single photon avalanche diode which is used for controlling the voltage of a first node according to a received optical signal. When the single-photon avalanche diode triggers avalanche, the voltage difference between the two ends of the single-photon avalanche diode is smaller than the breakdown voltage through the quenching recovery module. An output signal with the frequency equal to the switching frequency of a light emitting device in the light emitting circuit is generated through the pulse processing module according to the signal envelope of the first node, and the output signal is output to the output end of the light receiving circuit. A light sensing device in the light receiving circuit comprises a single photon avalanche diode, and the light receiving circuit comprises a quenching recovery module and a pulse processing module, so that the intensity of a light signal received by the light receiving circuit can be reduced, and meanwhile, the design requirement of an output signal is met.

Description

Technical Field

[0001] The present invention relates to the field of optical coupling, and in particular to an optical receiving circuit and an optical coupling device. Background Art

[0002] The performance of the optical coupling device is related to the current flowing through the light emitting device in the light emitting circuit. The current flowing through the light emitting device in the light emitting circuit needs to be set large enough to make the voltage signal generated by the current of the light emitting device in the light receiving circuit greater than the reference voltage. Then, after the voltage signal generated by the current of the light emitting device in the light receiving circuit is compared with the reference voltage by a comparator, the light receiving circuit output signal is controlled. However, the increase in current will cause an increase in power consumption. Summary of the invention

[0003] The embodiments of the present invention provide an optical receiving circuit and an optical coupling device, which can reduce the power consumption of an optical transmitting circuit.

[0004] The present invention provides an optical receiving circuit, comprising an optical sensing device, a quenching recovery module and a pulse processing module. The optical sensing device comprises a single-photon avalanche diode electrically connected between one of a first voltage terminal and a second voltage terminal and a first node, and the single-photon avalanche diode is configured to control the voltage of the first node according to the received optical signal. Wherein, the optical signal comprises a first optical signal corresponding to when the light-emitting device in the optical transmitting circuit emits light. The quenching recovery module is electrically connected between the other of the first voltage terminal and the second voltage terminal and the first node, and the quenching recovery module is configured to control the voltage difference between the cathode and the anode of the single-photon avalanche diode to be less than the breakdown voltage of the single-photon avalanche diode when the single-photon avalanche diode triggers an avalanche. The pulse processing module is electrically connected to the first node, and the pulse processing module is configured to generate an output signal according to the signal envelope of the first node to output to the output end of the optical receiving circuit. Wherein, the frequency of the output signal is equal to the switching frequency of the light-emitting device in the optical transmitting circuit.

[0005] An embodiment of the present invention provides an optical coupling device, comprising any of the above-mentioned optical receiving circuits and the optical transmitting circuit. The optical transmitting circuit provides the optical signal to the optical sensing device of the optical receiving circuit, and the optical transmitting circuit includes the light emitting device.

[0006] The present invention provides an optical receiving circuit and an optical coupling device. The optical sensing device in the optical receiving circuit includes a single-photon avalanche diode to control the voltage of the first node according to the received optical signal. A quenching recovery module is set to make the voltage difference between the two ends of the single-photon avalanche diode less than the breakdown voltage to adjust the voltage of the first node. A pulse processing module is set to generate an output signal with a frequency equal to the switching frequency of the light-emitting device in the optical transmitting circuit according to the signal envelope of the first node, and the output signal is output to the output end of the optical receiving circuit. By utilizing the characteristics of the single-photon avalanche diode with fast response speed, high quantum efficiency, and detection under weak optical signals, the intensity of the optical signal received by the optical receiving circuit can be reduced, and then the current driving the light-emitting device in the optical transmitting circuit can be reduced, so that the power consumption of the optical transmitting circuit can be reduced. By setting a quenching recovery module and a pulse processing module, the frequency of the output signal is equal to the switching frequency of the light-emitting device in the optical transmitting circuit to meet the design requirements of the output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0008] Figure 1 is a principle block diagram of an optical receiving circuit provided by an embodiment of the present invention;

[0009] Figure 2 is a timing diagram of an output signal provided by an embodiment of the present invention;

[0010] Figure 3A to Figure 3B is a schematic diagram of the connection between the optical sensing device and the quenching recovery module provided by an embodiment of the present invention;

[0011] Figure 4A to Figure 4B is a schematic structural diagram of an envelope detection circuit provided by an embodiment of the present invention;

[0012] Figure 5 is a schematic diagram of the structure of a pulse width delay circuit provided by an embodiment of the present invention;

[0013] Figure 6 is a structural schematic diagram of a non-overlapping clock signal generating circuit provided by an embodiment of the present invention;

[0014] Figure 7A to Figure 7C is a simplified system block diagram of an optical coupling device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0016] Figure 1 is a principle block diagram of an optical receiving circuit provided by an embodiment of the present invention, Figure 2 : is a timing diagram of an output signal provided by an embodiment of the present invention. An embodiment of the present invention provides an optical receiving circuit, which includes an optical sensing device, a quenching recovery module QC and a pulse processing module PM.

[0017] The optical sensing device includes a single photon avalanche diode SPAD electrically connected between one of a first voltage terminal VDD and a second voltage terminal GND and a first node No1, and the single photon avalanche diode SPAD is configured to control the voltage of the first node No1 according to a received optical signal hv. The optical signal hv includes a first optical signal corresponding to when the light emitting device in the optical emitting circuit emits light.

[0018] The quenching recovery module QC is electrically connected between the other of the first voltage terminal VDD and the second voltage terminal GND and the first node No1. The quenching recovery module QC is configured to control the voltage difference between the cathode and the anode of the single-photon avalanche diode SPAD to be less than the breakdown voltage of the single-photon avalanche diode SPAD when the single-photon avalanche diode SPAD triggers an avalanche.

[0019] The pulse processing module PM is electrically connected to the first node No1, and the pulse processing module PM is configured to generate an output signal OC_OUT according to the signal envelope of the first node No1, so as to output the output signal to the output terminal VO of the optical receiving circuit. The frequency of the output signal OC_OUT is equal to the switching frequency of the light emitting device in the optical transmitting circuit. The switching frequency of the light emitting device corresponds to the switching frequency of the light emitting device between emitting light and not emitting light. The switching frequency of the light emitting device between emitting light and not emitting light can be based on Figure 2 The signal LED_Pulse shown in the figure is controlled. That is, when the signal LED_Pulse is at a high level, the light-emitting device emits light. When the signal LED_Pulse is at a low level, the light-emitting device does not emit light.

[0020] Because the single photon avalanche diode SPAD has the characteristics of fast response speed, high quantum efficiency, and can also detect weak light signals hv. Therefore, if the light sensing device in the light receiving circuit includes a single photon avalanche diode SPAD, the intensity of the light signal hv received by the light receiving circuit can be reduced, and the current driving the light emitting device in the light emitting circuit can be reduced to reduce the power consumption of the light emitting circuit and reduce the light power performance requirements of the light emitting device.

[0021] To prevent the single-photon avalanche diode SPAD from being in an avalanche state after being triggered to avalanche, and from being unable to detect single photons. In addition, to improve the device loss caused by excessive avalanche current, a quenching recovery module QC is set to control the voltage difference between the cathode and anode of the single-photon avalanche diode SPAD to be less than the breakdown voltage of the single-photon avalanche diode SPAD after the single-photon avalanche diode SPAD is triggered to avalanche, thereby controlling the avalanche process of the single-photon avalanche diode SPAD to be quenched.

[0022] When the light-emitting device in the light-emitting circuit emits light, the single-photon avalanche diode SPAD can detect a single photon, which then triggers an avalanche effect, causing the current flowing through the single-photon avalanche diode SPAD to increase sharply. Afterwards, the avalanche process of the single-photon avalanche diode SPAD is quenched by the quenching recovery module QC, so that the current flowing through the single-photon avalanche diode SPAD is reduced, and the voltage of the first node No1 changes with the working state of the single-photon avalanche diode SPAD. In the process of light-emitting device emitting light, the single-photon avalanche diode SPAD cycles between being in an avalanche state and the avalanche process being quenched. When the light-emitting device in the light-emitting circuit does not emit light, the single-photon avalanche diode SPAD loses the source of the light signal hv, and the single-photon avalanche diode SPAD cannot control the voltage of the first node No1 according to the received light signal hv, and the voltage of the first node No1 remains constant. Therefore, the voltage of the first node No1 shows different changes in the light-emitting state and the non-light-emitting state of the corresponding light-emitting device. By setting up a pulse processing module PM to generate an output signal OC_OUT according to the signal envelope of the first node No1, the frequency of the output signal OC_OUT can be made equal to the switching frequency of the light-emitting device in the light-emitting circuit according to the change form of the light-emitting state and the non-light-emitting state of the light-emitting device corresponding to the voltage of the first node No1, so that the output signal OC_OUT meets the design requirements.

[0023] Optionally, the quenching recovery module QC includes a passive quenching recovery circuit, an active quenching recovery circuit or a gated quenching recovery circuit.

[0024] like Figure 3A to Figure 3BSchematic diagram of the connection between the optical sensing device and the quenching recovery module provided by the embodiment of the present invention. Taking the quenching recovery module QC as a passive quenching recovery circuit as an example, the quenching recovery module QC is described.

[0025] The quenching recovery module QC includes a first resistor R1 , and a first voltage supplied by a first voltage terminal VDD is greater than a second voltage supplied by a second voltage terminal GND.

[0026] The first resistor R1 is connected in series between the second voltage terminal GND and the first node No1, the cathode of the single photon avalanche diode SPAD is electrically connected to the first voltage terminal VDD, and the anode of the single photon avalanche diode SPAD is electrically connected to the first node No1. Figure 3A shown.

[0027] Alternatively, the first resistor R1 is connected in series between the first voltage terminal VDD and the first node No1, the anode of the single photon avalanche diode SPAD is electrically connected to the second voltage terminal GND, and the cathode of the single photon avalanche diode SPAD is electrically connected to the first node No1, such as Figure 3B shown.

[0028] Optionally, the second voltage terminal GND is a ground terminal.

[0029] Optionally, the resistance value of the first resistor R1 can be set to XKΩ, where X is less than or equal to 1000, such as X is equal to 10, 50, 100, 200 or 500.

[0030] Because the first resistor R1 and the single-photon avalanche diode SPAD are connected in series between the first voltage terminal VDD and the second voltage terminal GND, and the first resistor R1 and the single-photon avalanche diode SPAD are connected to the first node No1. Therefore, when the single-photon avalanche diode SPAD is triggered to avalanche, the avalanche current flowing through the first resistor R1 will generate a large voltage drop on the first resistor R1, so that the bias voltage at both ends of the single-photon avalanche diode SPAD is lower than the breakdown voltage, causing the electric field strength in the depletion region of the single-photon avalanche diode SPAD to be insufficient for the carriers to continue to induce collision ionization, so that the avalanche process is quenched. After the avalanche is quenched, the parasitic capacitance of the PN junction depletion region of the single-photon avalanche diode SPAD will be slowly charged through the first resistor R1, so that the bias voltage at both ends of the single-photon avalanche diode SPAD is restored to the initial bias voltage, and the single-photon avalanche diode SPAD has the ability to perform single photon detection again.

[0031] For the passive quenching recovery circuit, the recovery time for the bias voltage across the single photon avalanche diode SPAD to recover to the initial bias voltage is determined by the product of the resistance value of the first resistor R1 and the parasitic junction capacitance of the depletion region of the single photon avalanche diode SPAD.

[0032] Optionally, when the light receiving circuit is used in a pixel circuit, the first resistor R1 in the passive quenching recovery circuit may also be replaced by a transistor design.

[0033] During the duration of the quenching and recovery process of the single-photon avalanche diode (SPAD), the single-photon avalanche diode (SPAD) does not have the ability to detect photons. In order to reduce the dead time and speed up the recovery process of the single-photon avalanche diode (SPAD), an active quenching recovery circuit can be used. The active quenching recovery circuit consists of a passive branch composed of transistors and an active branch controlled by an enable signal.

[0034] When using passive quenching recovery circuits and active quenching recovery circuits, single photon avalanche diodes (SPADs) may be triggered to avalanche when they are not in dead time. Therefore, in order to make the detection of photons by single photon avalanche diodes (SPADs) controllable, a gated quenching recovery circuit is used to apply a control signal to periodically enable or disable the single photon avalanche diodes (SPADs), which can reduce power consumption while avoiding unnecessary detection.

[0035] Please continue reading Figure 1 The pulse processing module PM includes an envelope detection circuit ED, a pulse shaping circuit PS and a post-stage driving circuit ND.

[0036] The envelope detection circuit ED is electrically connected to the first node No1 , and the envelope detection circuit ED is configured to generate a first electrical signal ED_OUT according to the signal envelope of the first node No1 .

[0037] The pulse shaping circuit PS is electrically connected to the envelope detection circuit ED. The pulse shaping circuit PS is configured to filter and delay the first electrical signal ED_OUT and generate a gate control signal.

[0038] The subsequent driving circuit ND is electrically connected to the pulse shaping circuit PS. The subsequent driving circuit ND is configured to generate an output signal OC_OUT according to the gate control signal to output to the output terminal VO of the optical receiving circuit.

[0039] In order to make the frequency of the output signal OC_OUT equal to the switching frequency of the light-emitting device in the light-emitting circuit according to the change form of the light-emitting state and the non-light-emitting state of the light-emitting device corresponding to the voltage of the first node No1, the pulse processing module PM includes an envelope detection circuit ED to obtain the amplitude of the signal of the first node No1 changing with time.

[0040] Optionally, the envelope detection circuit ED includes a design form such as a diode envelope detection.

[0041] like Figure 4A to Figure 4B1 is a schematic diagram of the structure of the envelope detection circuit provided by the embodiment of the present invention. First, the envelope detection circuit ED including the diode envelope detection is used as an example for description. Figure 4A As shown, the envelope detection circuit ED includes a first device Sw, a second resistor R2 and a first capacitor C1.

[0042] The first device Sw is electrically connected between the first node No1 and the second node No2, and is configured to control signal transmission between the first node No1 and the second node No2. The second resistor R2 is connected in series between the second node No2 and the second voltage terminal GND, and the first capacitor C1 is connected in parallel with the second resistor R2.

[0043] The first device Sw includes a diode, an anode of the diode is electrically connected to the first node No1, a cathode of the diode is electrically connected to the second node No2, and the first electrical signal ED_OUT is the voltage difference between the second node No2 and the second voltage terminal GND.

[0044] It can be understood that when the second voltage terminal GND is the ground terminal, the first electrical signal ED_OUT is the signal of the second node No2, and the voltage difference between the first node No1 and the second voltage terminal GND is the signal SPAD_OUT of the first node No1.

[0045] Optionally, the resistance value of the second resistor R2 is 5 kΩ to 10 kΩ, such as 5 kΩ, 5.2 kΩ, 5.5 kΩ, 6 kΩ, 6.5 kΩ, 7 kΩ, 7.5 kΩ, 8 kΩ, 8.5 kΩ, 9 kΩ, 9.5 kΩ, 9.9 kΩ or 10 kΩ.

[0046] When the diode is turned on, the forward resistance of the diode is small, the first capacitor C1 charges faster, and the waveform of the first electrical signal ED_OUT increases at a rate of increase close to the voltage difference between the first node No1 and the second voltage terminal GND. When the diode is turned off, because the resistance value of the second resistor R2 is much larger than the internal resistance of the diode, the first capacitor discharges slowly, the amplitude of the first electrical signal ED_OUT decreases slightly, and the amplitude of the first electrical signal ED_OUT can be basically close to the amplitude of the voltage difference between the first node No1 and the second voltage terminal GND.

[0047] If the voltage difference between the first node No1 and the second voltage terminal GND forms a high-frequency constant-amplitude wave, the first electrical signal ED_OUT is a DC voltage with a fixed voltage value after ignoring a small amount of high-frequency components. At this time, the envelope detection circuit ED corresponds to a rectifier circuit with a filter capacitor.

[0048] When the voltage difference between the first node No1 and the second voltage terminal GND increases or decreases, the first electrical signal ED_OUT will also increase or decrease approximately proportionally. When the voltage difference between the first node No1 and the second voltage terminal GND forms an amplitude modulated wave, the first electrical signal ED_OUT changes along the envelope of the amplitude modulated wave. At this time, since the magnitude of the first electrical signal ED_OUT is close to the peak value of the voltage difference between the first node No1 and the second voltage terminal GND, the envelope detection circuit ED corresponds to a peak envelope detector.

[0049] In the envelope detection circuit ED, the first device can also be implemented in the form of a transistor. Figure 4B As shown, the first device Sw includes a transistor, the control terminal and the first source-drain terminal of the transistor are electrically connected to the first node No1, and the second source-drain terminal of the transistor is electrically connected to the second node No2. Figure 4B The working principle of the envelope detection circuit ED shown is similar to Figure 4A The working principle of the envelope detection circuit ED shown is similar and will not be described in detail here.

[0050] Alternatively, if Figure 4B In the envelope detection circuit ED shown, the transistor is an N-type transistor or a P-type transistor.

[0051] In order to balance the overall timing relationship of the signals of the optical receiving circuit and reduce the noise of the first electrical signal ED_OUT, a pulse shaping circuit PS is provided. The pulse shaping circuit PS includes a pulse width delay circuit PWD, which is electrically connected to the envelope detection circuit ED, and the pulse width delay circuit PWD is configured to filter and delay the first electrical signal ED_OUT to generate a second electrical signal.

[0052] like Figure 5 : is a schematic diagram of the structure of a pulse width delay circuit provided in an embodiment of the present invention. The pulse width delay circuit PWD includes a first transistor T1 to an eighth transistor T8, a third resistor R3 to a sixth resistor R6, a third capacitor C3, a Schmitt trigger SMIT and an inverter INV.

[0053] The first transistor T1 includes a control terminal receiving a first electrical signal ED_OUT, a first source-drain terminal electrically connected to the third voltage terminal Nsupply, and a second source-drain terminal.

[0054] The third transistor T3 includes a control terminal receiving the first electrical signal ED_OUT, a first source-drain terminal electrically connected to the fourth voltage terminal VSS, and a second source-drain terminal.

[0055] The second transistor T2 includes a control terminal electrically connected to the second source-drain terminal of the third transistor T3 , a first source-drain terminal electrically connected to the third voltage terminal Nsupply, and a second source-drain terminal.

[0056] The fourth transistor T4 includes a control terminal electrically connected to the second source-drain terminal of the third transistor T3 , a first source-drain terminal electrically connected to the fourth voltage terminal VSS, and a second source-drain terminal.

[0057] The fifth transistor T5 includes a control terminal, a first source-drain terminal electrically connected to the third voltage terminal Nsupply, and a second source-drain terminal.

[0058] The sixth transistor T6 includes a control terminal electrically connected to the second source-drain terminal of the third transistor T3 , a first source-drain terminal electrically connected to the second source-drain terminal of the fifth transistor T5 , and a second source-drain terminal.

[0059] The seventh transistor T7 includes a control terminal electrically connected to the second source-drain terminal of the third transistor T3 , a first source-drain terminal electrically connected to the second source-drain terminal of the sixth transistor T6 , and a second source-drain terminal.

[0060] The eighth transistor T8 includes a control terminal electrically connected to the control terminal of the fifth transistor T5 , a first source-drain terminal electrically connected to the second source-drain terminal of the seventh transistor T7 , and a second source-drain terminal electrically connected to the fourth voltage terminal VSS.

[0061] The third resistor R3 is connected in series between the second source-drain terminal of the first transistor T1 and the second source-drain terminal of the third transistor T3 .

[0062] The fourth resistor R4 and the fifth resistor R5 are connected in series between the second source-drain terminal of the second transistor T2 and the second source-drain terminal of the fourth transistor T4 .

[0063] The sixth resistor R6 is connected in series between the second source-drain terminal of the fourth transistor T4 and the input terminal of the Schmitt trigger SMIT.

[0064] The third capacitor C3 is connected in series between the input terminal of the Schmitt trigger SMIT and the fourth voltage terminal VSS.

[0065] The output end of the Schmitt trigger SMIT is electrically connected to the input end of the first inverter, and the output end of the first inverter is electrically connected to the control end of the fifth transistor T5. The output end of the first inverter is electrically connected to the input end of the second inverter, and the output end of the second inverter is electrically connected to the output end PWD_O of the pulse width delay circuit PWD.

[0066] Optionally, any one of the first transistor T1 to the eighth transistor T8 may be an N-type transistor or a P-type transistor.

[0067] Optionally, the voltage supplied by the third voltage terminal Nsupply is a DC voltage, and the voltage supplied by the third voltage terminal Nsupply is greater than the voltage supplied by the fourth voltage terminal VSS. Optionally, the voltage supplied by the third voltage terminal Nsupply may be equal to the voltage supplied by the first voltage terminal VDD, and the voltage supplied by the fourth voltage terminal VSS may be equal to the voltage supplied by the second voltage terminal GND.

[0068] Because the first electrical signal ED_OUT is a pulse signal, when the first electrical signal ED_OUT is at a high level, the third transistor T3 is turned on, and the voltage of the second source-drain terminal of the third transistor T3 is pulled down, so that the second transistor T2 and the sixth transistor T6 start to work. After the second transistor T2 is turned on, under the action of the third voltage terminal Nsupply, the current flows to the RC filter circuit composed of the fourth resistor R4 to the sixth resistor R6 and the third capacitor C3, and the third capacitor C3 is charged with the current. When the first electrical signal ED_OUT is at a low level, the first transistor T1 is turned on, and the voltage of the second source-drain terminal of the third transistor T3 is raised, so that the fourth transistor T4 and the seventh transistor T7 are turned on, and the third capacitor C3 discharges the fourth transistor T4 and the seventh transistor T7, thereby completing the overall timing adjustment.

[0069] By changing the charging and discharging time of the third capacitor C3 , the delay of the first electrical signal ED_OUT can be changed.

[0070] Since the subsequent-stage driving circuit ND can be implemented in the design form of a P-type transistor combined with an N-type transistor, in order to provide a gate control signal to the subsequent-stage driving circuit ND and prevent the P-type transistor and the N-type transistor in the subsequent-stage driving circuit ND from being turned on at the same time, the pulse shaping circuit PS can include a non-overlapping clock signal generating circuit.

[0071] like Figure 6 1 is a schematic diagram of the structure of the non-overlapping clock signal generating circuit provided by an embodiment of the present invention. In which, INV1-INV11 represent NOT gates, NAND1 and NAND2 represent NAND gates, NOR represents OR gates, Pdriver represents a first gate control signal, Ndriver represents a second gate control signal, UVLO represents an undervoltage control signal, and Vin may correspond to a second electrical signal.

[0072] When the first gate control signal Pdriver is at a low level and the second gate control signal Ndriver is at a low level, if the signal output by the first NAND gate NAND1 changes from a high level to a low level according to the received undervoltage control signal UVLO and the second electrical signal Vin, then the first gate control signal Pdriver will first change from a low level to a high level. Afterwards, the signal output by the fifth invertor INV5 is sent to the OR gate OR, and after the sixth invertor INV6 acts, the second gate control signal Ndriver is controlled to change from a low level to a high level. When the first gate control signal Pdriver is at a high level and the second gate control signal Ndriver is at a high level, if the signal output by the first NAND gate NAND1 changes from a low level to a high level according to the received undervoltage control signal UVLO and the second electrical signal Vin, then the second gate control signal Ndriver will first change from a high level to a low level. Afterwards, the signal output by the eleventh NOT gate INV11 is sent to the second NAND gate NAND2. After the action of the first NOT gate INV1 and the second NOT gate INV2, the first gate control signal Pdriver is controlled to change from a high level to a low level, so that the effective level of the first gate control signal Pdriver and the effective level of the second gate control signal Ndriver do not overlap.

[0073] Optionally, in some embodiments, a logic and dead time control circuit may be used to control the effective level of the first gate control signal Pdriver and the effective level of the second gate control signal Ndriver to not overlap. Figure 3A to Figure 3B The gate control signal for controlling the subsequent driving circuit ND includes a first gate control signal Pdriver and a second gate control signal Ndriver. The subsequent driving circuit ND includes a first switch transistor Ts1 and a second switch transistor Ts2.

[0074] The first switch transistor Ts1 includes a control terminal for receiving a first gate control signal Pdriver, a first source-drain terminal electrically connected to the first voltage terminal VDD, and a second source-drain terminal electrically connected to the output terminal VO of the light receiving circuit.

[0075] The second switch transistor Ts2 includes a control terminal for receiving a second gate control signal Ndriver, a first source-drain terminal electrically connected to the second voltage terminal GND, and a second source-drain terminal electrically connected to the output terminal VO of the light receiving circuit.

[0076] By electrically connecting the non-overlapping clock signal generating circuit to the pulse width delay circuit, the first switch transistor Ts1 and the second switch transistor Ts2 are controlled to be turned on in a time-sharing manner according to the first gate control signal Pdriver and the second gate control signal Ndriver, so that the timing of the output signal OC_OUT is as follows: Figure 2shown.

[0077] Optionally, the first switch transistor Ts1 is a P-type transistor, and the second switch transistor Ts2 is an N-type transistor.

[0078] In the optical receiving circuit using PN or PIN photodiodes as photoelectric sensing devices, the device response speed can be improved by thinning the thickness of the epitaxial layer or substrate, or increasing the bias voltage. However, increasing the bias voltage will increase the leakage current of the photodetector, and thinning the thickness of the epitaxial layer or substrate will reduce the quantum efficiency. Increasing the light receiving area of ​​the photoelectric sensing device can improve the quantum efficiency, but it will increase the parasitic capacitance and affect the transmission rate of the optical coupler. Increasing the bias voltage or increasing the thickness of the epitaxial layer can improve the quantum efficiency of the photoelectric sensing device from the perspective of photoelectric conversion and collection of photogenerated current, but increasing the bias voltage will still lead to the problem of increased leakage current, and increasing the thickness of the epitaxial layer will cause the response speed of the photoelectric sensing device in the near-infrared band to decrease. Therefore, in the optical receiving circuit using PN or PIN photodiodes as photoelectric sensing devices, it is difficult to simultaneously improve the quantum efficiency and response speed of the photoelectric sensing device.

[0079] In the optical receiving circuit provided in the present application, a single-photon avalanche diode SPAD is used as a light sensing device. The characteristics of the single-photon avalanche diode SPAD, such as fast response speed, high quantum efficiency, and the ability to detect weak light signals, can be utilized to improve the problem that it is difficult to simultaneously improve the quantum efficiency and response speed of the photoelectric sensing device in the optical receiving circuit.

[0080] In addition, in the optical receiving circuit using PN or PIN type photodiodes, a complex adjustment system for calibrating the photocurrent signal is generally required. When the light-emitting device in the optical transmitting circuit ages, the photocurrent signal generated in the optical receiving circuit using PN or PIN type photodiodes will be affected, which in turn affects the output signal OC_OUT output by the optical receiving circuit, which may cause the output signal OC_OUT to have no valid pulse. That is, when the light-emitting device in the optical transmitting circuit ages, the luminous efficiency of the light-emitting device decreases, and the photocurrent signal generated according to the light signal hv in the optical receiving circuit decreases, which correspondingly causes the amplitude of the voltage signal in the optical transmitting circuit to decrease. After the signal after the amplitude decreases is compared with the reference signal by the comparator, the period of time when the corresponding output signal OC_OUT should originally output a high level will be output as a low level because the amplitude of the signal after the amplitude decreases changes to be less than the reference signal, resulting in the output signal OC_OUT outputting a low level during the period of time corresponding to the high level.

[0081] In this application, because the single photon avalanche diode SPAD can also detect weak light signals, the effect of aging of the light emitting device in the light emitting circuit on the light receiving circuit is reduced. Therefore, this application does not need to set up a complex adjustment system for calibrating the photocurrent signal, which is conducive to saving a lot of power consumption and chip area.

[0082] In the optical receiving circuit using PN or PIN type photodiode, because the rising time of the rising edge of the photocurrent signal is less than the falling time of the falling edge, the rising time of the rising edge of the output signal OC_OUT is less than the falling time of the falling edge. The asymmetry between the rising time of the rising edge and the falling time of the falling edge of the output signal OC_OUT is called the pulse width distortion problem. In the present application, because the avalanche pulse height of the single photon avalanche diode SPAD is relatively fixed, the time of the falling edge of each avalanche pulse is fixed. After the falling time of the falling edge of each avalanche pulse is known, the envelope detection circuit ED can be controlled to have a fixed discharge time, thereby reducing the difference between the falling time of the falling edge and the rising time of the rising edge of the output signal OC_OUT. After that, the pulse shaping circuit PS can be used in conjunction with the post-stage driving circuit ND to eliminate the problem of pulse width distortion.

[0083] Please continue reading Figure 1 The optical receiving circuit can be powered by a power management module, which includes a charge pump circuit, a bandgap reference module and a bias current module. The electrostatic charge can be discharged by an electrostatic protection module.

[0084] In addition, an overvoltage protection and undervoltage lockout module may be provided, and the overvoltage protection and undervoltage lockout module is used to prevent the optical receiving circuit from being damaged and affected by overshoot voltage or undervoltage.

[0085] Figure 7A to Figure 7C is a simplified system block diagram of an optical coupling device provided by an embodiment of the present invention. An embodiment of the present invention further provides an optical coupling device, including any of the above-mentioned optical receiving circuits 100 and optical transmitting circuits 200 .

[0086] The light emitting circuit 200 is configured to provide a light signal hv to the light sensing device of the light receiving circuit 100 , and the light emitting circuit 200 includes a light emitting device LED.

[0087] Optionally, the optical coupling device may further include a feedback module 300, so that during the application of the optical coupling device, the working state of the optical coupling device becomes controllable according to the feedback signal, such as Figure 7BThe feedback module 300 is electrically connected to the optical receiving circuit 100 and the optical transmitting circuit 200, and the feedback module 300 is configured to receive the state control signal VE generated by the external control module and output the feedback signal FAULT to control the light-emitting state of the light-emitting device in the optical transmitting circuit 100. The external control module receives the output signal OC_OUT.

[0088] Please continue reading Figure 7B The feedback module 300 may include a signal processing circuit DESAT, a first light emitting diode LED1, a first photoelectric sensing device SE and a first transistor TR. The signal processing circuit DESAT is used to invert the state control signal VE. The first light emitting diode LED1 is electrically connected to the signal processing circuit DESAT. The first photoelectric sensing device SE receives the light signal hv emitted by the first light emitting diode LED1 to generate a feedback signal FAULT, so as to control the light emitting state of the light emitting device LED in the light emitting circuit 200 according to the feedback signal FAULT.

[0089] For example, the external control module receives the output signal OC_OUT for controlling the operation of the motor, but when undervoltage or overvoltage occurs, causing the operation of the motor to malfunction, the state control signal VE generated by the external control module is output to the optical coupling device. The state control signal VE is acted upon by the signal processing circuit DESAT (such as an inverter) in the feedback module 300, so that the first light-emitting diode LED1 emits light, and then the first photoelectric sensing device SE cooperates with the first transistor TR to generate a feedback signal FAULT according to the light signal hv emitted by the first light-emitting diode DESAT, and controls the light-emitting device LED in the light-emitting circuit 200 to stop emitting light according to the feedback signal FAULT, so that the output signal OC_OUT transmitted by the light-receiving circuit 100 to the external control module has no valid pulse.

[0090] Optionally, the feedback module 300 may be connected to a required voltage signal (such as VCC, VLED, etc.).

[0091] In some embodiments, in order to provide multiple optoelectronic coupling channels and save costs, the optical coupling device includes multiple optical transmitting circuits 200 and multiple optical receiving circuits 100, and each optical transmitting circuit 200 provides an optical signal hv to a corresponding optical sensing device of an optical receiving circuit 100. The multiple optical receiving circuits 100 are isolated from each other, and the multiple optical transmitting circuits 200 are isolated from each other, so that each optical transmitting circuit 200 cooperates with an optical receiving circuit 100 to form an optoelectronic coupling channel. Figure 7CAs shown, the optical coupling device includes two optical transmitting circuits 200 and two optical receiving circuits 100. Each optical transmitting circuit 200 provides an optical signal hv to a photosensitive device of an optical receiving circuit 100. The output terminal VO of the first optical receiving circuit corresponds to the first output terminal VO1 of the optical coupling device, and the output terminal VO of the second optical receiving circuit corresponds to the second output terminal VO2 of the optical coupling device.

[0092] The optical signals hv emitted by the multiple optical transmitting circuits 100 are independent of each other, and the output signals OC_OUT output by the multiple optical receiving circuits 200 are independent of each other. Figure 7C When the optocoupler device shown is used in equipment such as automobiles, multiple devices can be controlled to work independently at the same time based on the same optocoupler device to save costs.

[0093] Optionally, the optical coupling device can be packaged into a chip. Fig. 7A In the package, pin 1 may correspond to the anode Ano of the light emitting device LED in the light emitting circuit 200, pin 2 may correspond to the cathode Cath of the light emitting device LED in the light emitting circuit 200, pin 3 may correspond to the first voltage terminal VDD, pin 4 may correspond to the output terminal VO in the light receiving circuit 100, and pin 5 may correspond to the second voltage terminal GND. Figure 7B In the package, pin 1 can correspond to the anode Ano of the light emitting device LED in the light emitting circuit, pin 2 can correspond to the cathode Cath of the light emitting device LED in the light emitting circuit, pin 3 can correspond to the receiving voltage signal VCC, pin 4 can correspond to the feedback signal FAULT output by the feedback module, pin 5 and pin 8 can correspond to the second voltage terminal GND, pin 6 can correspond to the first voltage terminal VDD, pin 7 can correspond to the output terminal VO in the light receiving circuit, pin 9 can correspond to the receiving state control signal VE, and pin 10 can correspond to the receiving voltage signal VLED. Figure 7C In the package, pin 1 can correspond to the anode Ano of the light-emitting device LED in the first light-emitting circuit, pin 2 can correspond to the cathode Cath of the light-emitting device LED in the first light-emitting circuit, pin 3 can correspond to the anode Ano of the light-emitting device LED in the second light-emitting circuit, pin 4 can correspond to the cathode Cath of the light-emitting device LED in the second light-emitting circuit, pin 5 can correspond to the first voltage terminal VDD, pin 6 can correspond to the output terminal VO1 in the first light-receiving circuit, pin 7 can correspond to the output terminal VO2 in the second light-receiving circuit, and pin 8 can correspond to the second voltage terminal GND.

[0094] The description of the above embodiments is only used to help understand the method of the present invention and its core concept. For those skilled in the art, according to the concept of the present invention, there may be changes in the specific implementation method and application scope, and the content of this specification should not be understood as limiting the present invention.

Claims

1. An optical receiving circuit, characterized in that: include: A light sensing device, comprising a single photon avalanche diode electrically connected between one of a first voltage terminal and a second voltage terminal and a first node, and configured to control a voltage of the first node according to a received light signal; wherein the light signal comprises a first light signal corresponding to when a light emitting device in a light emitting circuit emits light; a quenching recovery module, electrically connected between the other of the first voltage terminal and the second voltage terminal and the first node, and configured to control the voltage difference between the cathode and the anode of the single photon avalanche diode to be less than the breakdown voltage of the single photon avalanche diode when the single photon avalanche diode triggers an avalanche; A pulse processing module is electrically connected to the first node and is configured to generate an output signal according to the signal envelope of the first node to output to the output end of the optical receiving circuit; wherein the frequency of the output signal is equal to the switching frequency of the light emitting device in the optical transmitting circuit.

2. The optical receiving circuit according to claim 1, characterized in that: The voltage supplied by the first voltage terminal is greater than the voltage supplied by the second voltage terminal; the quenching recovery module includes a first resistor; wherein the cathode of the single-photon avalanche diode is electrically connected to the first voltage terminal, the anode of the single-photon avalanche diode is electrically connected to the first node, and the first resistor is connected in series between the second voltage terminal and the first node; or, The anode of the single-photon avalanche diode is electrically connected to the second voltage terminal, the cathode of the single-photon avalanche diode is electrically connected to the first node, and the first resistor is connected in series between the first voltage terminal and the first node.

3. The optical receiving circuit according to claim 1, characterized in that: The pulse processing module comprises: an envelope detection circuit, electrically connected to the first node, and configured to generate a first electrical signal according to a signal envelope of the first node; a pulse shaping circuit, electrically connected to the envelope detection circuit, configured to filter and delay the first electrical signal and generate a gate control signal; and The post-stage driving circuit is electrically connected to the pulse shaping circuit and is configured to generate the output signal according to the gate control signal so as to output the output signal to the output end of the light receiving circuit.

4. The optical receiving circuit according to claim 3, characterized in that: The envelope detection circuit comprises: A first device, electrically connected between the first node and the second node, configured to control signal transmission between the first node and the second node; a second resistor connected in series between the second node and the second voltage terminal; and A first capacitor is connected in parallel with the second resistor.

5. The optical receiving circuit according to claim 4, characterized in that: The first device includes a diode, an anode of the diode is electrically connected to the first node, and a cathode of the diode is electrically connected to the second node; or, The first device includes a transistor, a control terminal and a first source-drain terminal of the transistor are electrically connected to the first node, and a second source-drain terminal of the transistor is electrically connected to the second node.

6. The optical receiving circuit according to claim 4, characterized in that: The gate control signal includes a first gate control signal and a second gate control signal; the subsequent drive circuit includes: a first switch transistor, comprising a control terminal for receiving the first gate control signal, a first source-drain terminal electrically connected to the first voltage terminal, and a second source-drain terminal electrically connected to the output terminal of the light receiving circuit; and The second switch transistor includes a control terminal for receiving the second gate control signal, a first source-drain terminal electrically connected to the second voltage terminal, and a second source-drain terminal electrically connected to the output terminal of the light receiving circuit.

7. The optical receiving circuit according to claim 6, characterized in that: The pulse shaping circuit comprises: a pulse width delay circuit, electrically connected to the envelope detection circuit, and configured to filter and delay the first electrical signal to generate a second electrical signal; and The non-overlapping clock signal generating circuit is electrically connected to the pulse width delay circuit and is configured to generate the gate control signal according to the second electrical signal to control the first transistor and the second transistor to be turned on in a time-sharing manner.

8. An optical coupling device, characterized in that: include: The optical receiving circuit as claimed in any one of claims 1 to 7; as well as The light emitting circuit provides the light signal to the light sensing device of the light receiving circuit, the light emitting circuit including the light emitting device.

9. The optical coupling device according to claim 8, characterized in that: The optical coupling device includes a plurality of the optical transmitting circuits and a plurality of the optical receiving circuits, and each of the optical transmitting circuits provides the optical signal to the optical sensing device of a corresponding optical receiving circuit.

10. The optical coupling device according to claim 9, characterized in that: include: A feedback module, electrically connected to the light receiving circuit and the light emitting circuit, configured to receive a state control signal generated by an external control module and output a feedback signal to control the light emitting state of the light emitting device in the light emitting circuit; Wherein, the external control module receives the output signal.

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