Feedback resistance adjustment circuit in CTLE

Abstract

The present invention discloses a feedback resistor adjustment circuit in a CTLE. In order to improve the DC gain adjustment accuracy, the feedback resistor adjustment circuit in the CTLE of the present invention includes: a decoder for receiving a decoded input signal and outputting at least n-channel control information, wherein n is a positive integer greater than 1; a feedback resistor array module, including a resistor R0, wherein the resistor R0 is connected between a first input terminal and a second input terminal, wherein the first input terminal and the second input terminal are two nodes in the CTLE; the feedback resistor array module also includes n resistors, wherein the n-channel control information controls the n resistors to establish a parallel connection or disconnect a parallel connection with the resistor R0 in a one-to-one correspondence; the DC gain of the CTLE is divided into a plurality of groups at equal intervals, and within any group, as the DC gain of the CTLE increases, a resistor is added to the n resistors to establish a parallel connection with the resistor R0. While improving the accuracy, the present invention reduces the demand for the area occupied by the feedback resistors.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a feedback resistance adjustment circuit in a CTLE. Background Art

[0002] As data centers continue to grow their bandwidth demands and hardware physical bandwidth requirements, the importance of compensating for channel high-frequency attenuation in receiver analog front-end equalization modules has become increasingly prominent. The reduction in the ratio of data signal wavelength to transmission line leads to incomplete impedance matching, which makes the attenuation, reflection, delay, and crosstalk effects of signals generated during wired channel transmission more significant. Therefore, appropriate equalization measures are needed to overcome these defects in order to achieve higher-speed data transmission. Methods for increasing data transmission rates include increasing the amount of information carried by a single symbol data, such as four-level pulse amplitude modulation (Pulse Amplitude Modulation-4, PAM-4) encoding, and compensating the signal in the time domain or frequency domain, such as feedforward equalizers, continuous time linear equalizers (Continuous Time Liner Equalization, CTLE), decision feedback equalizers, etc.

[0003] As a key equalization method, CTLE has been widely used in various double data rate (DDR) synchronous dynamic random access memory and serializer and deserializer (SerDes) systems. CTLE is essentially an active high-pass filter, which usually supports a variety of parameter combinations of feedback resistors and feedback capacitors to achieve different equalization effects and adapt to different channel attenuation. Among them, the change of feedback resistance will affect the DC gain of CTLE. CTLE is usually located at the analog front end of the received signal, and its performance has an important impact on the performance of the entire receiver.

[0004] At present, the industry mainly adopts the following methods to solve the problem of CTLE gain linearity adjustment: by accurately calculating the feedback resistor value required to achieve different CTLE gains, each gear corresponds to the same resistor value, and the gain adjustment is achieved through thermometer coding. This method is not as cost-effective as the resistor access array with binary gradient access when the CTLE load resistance is large; and when the load resistance is small, it will cause the CTLE gain change linearity to weaken rapidly. At the same time, this method will also introduce larger parasitic parameters and longer signal paths, reducing the overall performance.

[0005] In the application field of CTLE, there are clear agreements on the range of linearity of gain adjustment. However, as the data rate increases, the load resistance of the CTLE will decrease to improve the overall bandwidth of the circuit. Since the gain of the CTLE is closely related to the ratio of the load resistance to the feedback resistance, continuing to meet this proportional relationship may cause the resistance area to grow exponentially, which is not good for both signal quality and chip cost. In addition, the traditional binary coding method to adjust the CTLE gain will become inaccurate as the load resistance decreases, because as the load resistance decreases, the correlation between the gain and the ratio of the load resistance to the feedback resistance will be weakened.

[0006] The present invention effectively improves the multiplexing efficiency inside the resistor array by changing the resistor adjustment scheme, so that the CTLE in the high data rate scenario meets the gain linearity requirement without significantly increasing the layout area. Summary of the invention

[0007] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

[0008] A feedback resistor adjustment circuit in a CTLE includes: a decoder for receiving a decoded input signal and outputting at least n-channel control information, wherein n is a positive integer greater than 1; a feedback resistor array module, including a resistor R0, wherein the resistor R0 is connected between a first input terminal and a second input terminal, wherein the first input terminal and the second input terminal are two nodes in the CTLE; and the feedback resistor array module also includes n resistors, wherein the n-channel control information controls the n resistors to establish a parallel connection with the resistor R0 or disconnect the parallel connection in a one-to-one correspondence; and further, the DC gain of the CTLE is divided into a plurality of groups at equal intervals, and within any group, as the DC gain of the CTLE increases, a resistor is added to the n resistors to establish a parallel connection with the resistor R0.

[0009] Furthermore, different decoding input signals correspond to different DC gains of the CTLEs one by one.

[0010] Furthermore, in any group, as the DC gain of the CTLE increases, the n-channel control information controls more resistors among the n resistors to establish parallel connections with the resistor R0.

[0011] Furthermore, the DC gain of the CTLE is divided into two groups at equal intervals.

[0012] Furthermore, the n-channel control information controls the n resistors to establish or disconnect the parallel connection with the resistor R0 in a one-to-one correspondence, specifically by controlling the conduction or disconnection of the transmission gate to establish or disconnect the parallel connection with the resistor R0.

[0013] Furthermore, the decoder is used to realize the conversion of the decoded input signal into n-channel control information; the decoder includes a plurality of NAND gates and a plurality of NOT gates.

[0014] Furthermore, the decoder is used to receive a decoded input signal and also output n-channel inverted control information; the n-channel inverted control information is information that corresponds one-to-one to the n-channel control information and is inverted to each other.

[0015] Furthermore, the n resistors are all realized by connecting block resistors in series.

[0016] Furthermore, in any group, as the DC gain of the CTLE increases, the resistors that have been connected in parallel with the resistor R0 are reused, and a new resistor that is connected in parallel with the resistor R0 is added.

[0017] Furthermore, the CTLE includes a differential input pair of tubes and a current source; the first input terminal and the second input terminal are nodes between the source of the differential input pair of tubes and the current source.

[0018] The technical solution of the present invention has one or more of the following beneficial technical effects:

[0019] (1) The resistor segment multiplexing method adopted by the present invention is a digital control scheme similar to a thermometer code, which can increase the DC gain adjustment accuracy of the CTLE. Compared with the traditional thermometer coding method and the binary adjustment scheme, the present invention can achieve more accurate gain adjustment under the premise of using the same number of block resistors.

[0020] (2) The present invention adopts a thermometer code scheme with segmented resistor reuse. Compared with the traditional non-segmented thermometer coding method or binary coding control scheme, the present invention can reduce the area occupied by the feedback resistor of the CTLE, which not only reduces the cost but also avoids the introduction of larger parasitic resistance and parasitic capacitance, which hinders the application of high data rate scenarios.

[0021] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a common CTLE circuit diagram in the prior art;

[0023] Figure 2 It is a feedback resistance adjustment circuit in the CTLE of the present invention;

[0024] Figure 3 It is the decoder circuit diagram;

[0025] Figure 4 is an exemplary feedback resistor array module circuit diagram. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0028] Figure 1 It is a common CTLE circuit diagram in the prior art, including two load resistors with the same resistance value, a pair of N-channel Metal Oxide Semiconductor (NMOS) tubes of the same size, and a differential input pair tube, an adjustable feedback resistor and an adjustable capacitor array, and two current sources of the same size. Among them, the load resistor is connected to the device operating voltage (Voltage Drain-to-Drain, VDD), and the current source is connected to the common ground terminal voltage (Voltage Source-to-Source, VSS). The gates of the two NMOS tubes are connected to the positive input terminal In_P and the negative input terminal In_n respectively, and the drains of the two NMOS tubes and the connection points of the two load resistors are used as the positive output terminal Out_p and the negative output terminal Out_n respectively.

[0029] Figure 1 The DC gain G of the CTLE circuit shown d =g m R L / (1+g m R S ), where g m is the small signal transconductance of the differential input pair, R L is the resistance of the load resistor, R S is the resistance of the feedback resistor. S When is reduced, the DC gain of the CTLE circuit will increase.

[0030] The present invention mainly optimizes the implementation scheme of the feedback resistor in the CTLE circuit. Figure 2 The invention discloses a feedback resistor adjustment circuit in a CTLE, which includes a decoder and a feedback resistor array module.

[0031] The decoder receives a decoded input signal Sel<2:0>. As an example, the decoded input signal Sel<2:0> includes 3 bits of information: Sel <2> 、Sel <1> and Sel <0> The 3-bit decoding input is only an example, and the present invention is not limited thereto.

[0032] The decoder outputs n control information en <n-1:0>, where n is a positive integer greater than 1. Optionally, the decoder can also output n channels of inverted control information enb at the same time. <n-1:0>In an example of the present invention, n=6. The n-channel inverted control information is information that corresponds one-to-one to the n-channel control information and is inverted to each other.

[0033] n-way control information en <n-1:0>And n-way reverse control information enb <n-1:0>Both can be used to control the connection or disconnection of resistors in the feedback resistor array module.

[0034] The feedback resistor array module is connected to a first input terminal and a second input terminal, wherein the first input terminal and the second input terminal may be, for example, from Figure 1 The node between the source and current source of the differential input pair tube.

[0035] Figure 3 : is a decoder circuit diagram. In this exemplary decoder circuit diagram, the decoded input signal Sel<2:0> is the input signal of the decoder, and the 6-way control information en<5:0>: en <0> 、en <1> 、en <2> 、en <3> 、en <4> 、en <5> And 6-way inversion control information enb<5:0>: enb <0> 、enb <1> 、enb <2> 、enb <3> 、enb <4> 、enb <5> , are used as the output signals of the decoder.

[0036] The decoder includes a plurality of NOT gates and a plurality of NAND gates. Table 2 is a table of access resistor combinations for achieving different DC gains. As an important feature of the present invention, the present invention optimizes the chip area by multiplexing resistors.

[0037] From the DC gain calculation formula of the CTLE circuit, we can know that if g m R S When the product of is not much greater than 1, the DC gain of the CTLE circuit increases with R S The gain of the feedback resistor increases and decreases, and is not linearly related. Therefore, if you want to obtain a linear gain change characteristic, you need to accurately control the resistance of the feedback resistor. If a precise resistor is used to implement each DC gain level, a large amount of silicon cost will inevitably be consumed. The present invention avoids the above defects from the perspective of resistor reuse.

[0038] For example, when the goal is to obtain a low gain, a resistor can be directly connected. If the gain is increased, an additional resistor can be connected in parallel instead of reconnecting a resistor, thereby reusing the previous resistor.

[0039] Furthermore, if the step length of the DC gain is small, the DC gain can be divided into multiple groups, such as 2 groups. For example, if the DC gain can be divided into 6 levels, namely -4dB, -2dB, 0dB, 2dB, 4dB and 6dB, then -2dB, 2dB and 6dB can be divided into the first group, and -4dB, 0dB and 4dB can be divided into the second group. In this way, the gain step length can be increased, the number of resistors connected in parallel can be reduced, and the silicon cost can be further reduced.

[0040] For example, if four gears of 2R, 1.7R, 1.5R and 1.4R are required in practical applications, where R is the unit resistance value. If the traditional thermometer coding is used, a total of 2+14+12+21=49 block resistors are required to achieve it. However, if the solution of the present invention is adopted, 2R is used as a common resistor, 1.7R and 1.4R are divided into 1 group, and 1.5R is divided into 1 group, then a total of 2+14+6+7=29 block resistors are required. Compared with the former, the number of block resistors is reduced to 60%. Moreover, as the number of DC gain gears increases, or the step length of the gain decreases, this advantage of the present invention will be more prominent.

[0041] Table 1: Decoder truth table

[0042]

[0043] Table 1 is the truth table of the decoder. Different decoding input signals Sel<2:0> correspond to different DC gains. When the decoding input signal Sel<2:0> is "101" and "100", it is a reserved spare code and can be used to increase the DC gain level later.

[0044] As mentioned above, in order to further reduce silicon cost, the present invention divides the DC gain in Table 1 into two groups. For the first group, as the gain increases, the resistors {R0, R2}, {R0, R2, R4} are reused successively; for the second group, as the gain increases, the resistors {R0, R1}, {R0, R1, R3} are reused successively. Table 2 is a table of access resistor combinations for achieving different DC gains, and "||" represents the meaning of resistors in parallel.

[0045] Table 2: Table of resistor combinations for achieving different DC gains

[0046]

[0047] For example, when the target is 0 dB DC gain, resistors R0, R1 and R3 are connected to the first input terminal and the second input terminal. When the target is 6 dB DC gain, resistors R0, R2, R4 and R6 are connected to the first input terminal and the second input terminal.

[0048] Furthermore, the feedback resistor array module includes n resistors, and the n-channel control information controls the n resistors to establish parallel connection with the resistor R0 or disconnect the parallel connection one by one. In addition, the DC gain of the CTLE is divided into a plurality of groups at equal intervals, and in any group, as the DC gain of the CTLE increases, a resistor is added to the n resistors to establish parallel connection with the resistor R0.

[0049] Figure 4 : is an exemplary feedback resistor array module circuit diagram. When the aforementioned resistors R1, R2, R3, R4, R5, and R6 are specifically implemented, for example, they can be respectively implemented by two resistors with a resistance value of R1' connected in series, two resistors with a resistance value of R2' connected in series, two resistors with a resistance value of R3' connected in series, two resistors with a resistance value of R4' connected in series, two resistors with a resistance value of R5' connected in series, and two resistors with a resistance value of R6' connected in series. In other words, two resistors with a resistance value of R1' connected in series are constructed into resistor R1, and the others are similar.

[0050] For example, in order to connect two resistors with resistance values ​​of R1' and R0 in parallel, the control information en <0> and inverting control information enb <0> To control the transmission gate connected in series between the two resistors with a resistance value of R1'. When the transmission gate is turned on, the two resistors with a resistance value of R1' and the resistor R0 are connected in parallel. Similarly, by controlling the information en <1> and inverting control information enb <1> , control information <2> and inverting control information enb <2> , control information <3> and inverting control information enb <3> , control information <4> and inverting control information enb <4> , control information <5> and inverting control information enb <5> , and control information <6> and inverting control information enb <6> , respectively, to control the corresponding other transmission gates to respectively connect two resistors with resistance values ​​of R2' in series, two resistors with resistance values ​​of R3' in series, two resistors with resistance values ​​of R4' in series, two resistors with resistance values ​​of R5' in series, and two resistors with resistance values ​​of R6' in series in parallel with the resistor R0.

[0051] Furthermore, the resistors R1, R2, R3, R4, R5, and R6 may be realized by connecting different or the same number of block resistors in series.

[0052] When the decode input signal Sel<2:0> is "000" combination, en <0> is 1, enb <0> is 0, at this time, the resistors R0 and R1 are connected to the first input terminal and the second input terminal, the transmission gates of other paths are closed, and the DC gain is -4dB.

[0053] When the decoded input signal Sel<2:0> is a combination of "001", resistors R0 and R2 are connected to the first input terminal and the second input terminal, the transmission gates of other paths are closed, and the DC gain is -2dB.

[0054] When the decoded input signal Sel<2:0> is a combination of "010", the resistors R0, R1 and R3 are connected to the first input terminal and the second input terminal, the transmission gates of other paths are closed, and the DC gain is 0dB.

[0055] When the decoded input signal Sel<2:0> is a combination of "011", resistors R0, R2 and R4 are connected to the first input terminal and the second input terminal, and the transmission gates of other paths are closed, and the DC gain is 2dB.

[0056] When the decoded input signal Sel<2:0> is a combination of "110", resistors R0, R1, R3 and R5 are connected to the first input terminal and the second input terminal, and the transmission gates of other paths are closed, and the DC gain is 4dB.

[0057] When the decoding input signal Sel<2:0> is a combination of "111", the resistors R0, R2, R4 and R6 are connected to the first input terminal and the second input terminal, the transmission gates of other paths are closed, and the DC gain is 6dB.

[0058] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0059] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A feedback resistance adjustment circuit in a CTLE, characterized in that: include: A decoder, for receiving a decoded input signal and outputting at least n-channel control information, where n is a positive integer greater than 1; A feedback resistor array module includes a resistor R0, wherein the resistor R0 is connected between a first input terminal and a second input terminal, wherein the first input terminal and the second input terminal are two nodes in the CTLE; and The feedback resistor array module further includes n resistors, and the n-channel control information controls the n resistors to establish parallel connection with the resistor R0 or disconnect the parallel connection one by one; in addition, The DC gain of the CTLE is divided into a plurality of groups at equal intervals, and within any group, as the DC gain of the CTLE increases, a resistor connected in parallel with the resistor R0 is added to the n resistors; In any one group, as the DC gain of the CTLE increases, the n-channel control information controls more resistors among the n resistors to establish parallel connection with the resistor R0; In any group, as the DC gain of the CTLE increases, the resistors that have been connected in parallel with the resistor R0 are reused, and a new resistor is added that is connected in parallel with the resistor R0.

2. The feedback resistance adjustment circuit in CTLE according to claim 1, characterized in that: Different decoding input signals correspond to different DC gains of CTLE.

3. The feedback resistance adjustment circuit in CTLE according to claim 2, characterized in that: The DC gain of the CTLE is divided into two groups at equal intervals.

4. The feedback resistance adjustment circuit in CTLE according to claim 3, characterized in that: The n-channel control information controls the n resistors to establish or disconnect the parallel connection with the resistor R0 in a one-to-one correspondence, specifically, establishing or disconnecting the parallel connection with the resistor R0 is achieved by controlling the conduction or disconnection of the transmission gate.

5. The feedback resistance adjustment circuit in CTLE according to claim 4, characterized in that: The decoder is used to realize the conversion of the decoded input signal into n-channel control information; The decoder includes a plurality of NAND gates and a plurality of NOT gates.

6. The feedback resistance adjustment circuit in CTLE according to claim 5, characterized in that: A decoder, for receiving a decoded input signal and also outputting n-channel inverted control information; The n-channel inverted control information is information corresponding to the n-channel control information in one-to-one correspondence and inverted to each other.

7. The feedback resistance adjustment circuit in CTLE according to claim 6, characterized in that: The n resistors are all realized by connecting block resistors in series.

8. The feedback resistance adjustment circuit in CTLE according to claim 7, characterized in that: The CTLE includes a differential input pair tube and a current source; The first input terminal and the second input terminal are nodes between the source of the differential input pair tube and the current source.

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