Manufacturing method of multilayer silicon capacitor structure and multilayer silicon capacitor structure

Abstract

The invention discloses a manufacturing method of a multi-layer silicon capacitor structure and the multi-layer silicon capacitor structure, and the method comprises the steps: carrying out the patterning processing of a dielectric layer or an electrode layer when the dielectric layer and the electrode layer are formed layer by layer, so as to enable the odd electrode layer and the even electrode layer to be partially not overlapped in the stacking direction, therefore, interconnection and electric export between the odd electrode layers and interconnection and electric export between the even electrode layers can be realized only by one-step etching. Or patterning processing is carried out on the dielectric layer or the electrode layer, so that the odd electrode layers and the even electrode layers are respectively exposed at different sides, end part electrodes can be subsequently and directly prepared at the end parts of the two sides, interconnection and electric export between the odd electrode layers and interconnection and electric export between the even electrode layers are realized, and the reliability of the device is improved. The process is simple; and the overlay precision requirement is low.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-layer electrode connection structures and methods, and in particular to a manufacturing method of a multi-layer silicon capacitor structure and a multi-layer silicon capacitor structure. Background Art

[0002] Silicon capacitors are emerging products on the market. They can be made using mature semiconductor technology and have many advantages, such as long life, good high temperature resistance, small equivalent series resistance, good high frequency performance, and small size. However, silicon capacitors also have the defect of small capacitance. In order to solve this problem, the method used in the prior art is to increase the number of layers of internal electrodes. However, the increase in the number of layers of internal electrodes causes certain problems in the lead-out of the electrodes.

[0003] At present, vias can be formed by drilling holes layer by layer on the electrode layer and the dielectric layer, and then the vias are filled with tungsten plugs or other conductive metals to connect the electrodes. However, this process is complicated, the overlay accuracy required for drilling holes layer by layer to form vias is high, and the etching end stop position is very high, resulting in a low yield rate.

[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a method for manufacturing a multi-layer silicon capacitor structure and a multi-layer silicon capacitor structure, which can solve the problems in the prior art.

[0006] To achieve the above-mentioned purpose, an embodiment of the present invention provides a method for manufacturing a multilayer silicon capacitor structure, comprising: providing a substrate, the substrate having a first surface and a second surface arranged opposite to each other, and a third surface and a fourth surface connected to the first surface and the second surface and arranged opposite to each other; forming a first odd-numbered dielectric layer on the first surface, the second surface and the fourth surface of the substrate, forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer on the first surface of the substrate, the first odd-numbered electrode layer having a first preset distance from a plane where the third surface of the substrate is located, and the first odd-numbered electrode layer is exposed to a plane where the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate is located; forming a first even-numbered dielectric layer on the first odd-numbered electrode layer and the first odd-numbered dielectric layer on the first surface of the substrate; forming a first even-numbered dielectric layer on the first even-numbered dielectric layer, the first even-numbered electrode layer being exposed to a plane where the third surface of the substrate is located, and the first even-numbered electrode layer having a second preset distance from a plane where the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate is located; forming a surface passivation layer.

[0007] In one or more embodiments of the present invention, forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer on the first surface of the substrate includes: etching the first odd-numbered dielectric layer on the first surface of the substrate to form a first groove structure in the first odd-numbered dielectric layer; forming a first odd-numbered electrode layer in the first groove structure.

[0008] In one or more embodiments of the present invention, forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer on the first surface of the substrate includes: forming a metal electrode layer on the first odd-numbered dielectric layer on the first surface of the substrate; and patterning the metal electrode layer to form the first odd-numbered electrode layer.

[0009] In one or more embodiments of the present invention, forming a first even-numbered electrode layer on the first even-numbered dielectric layer includes: etching the first even-numbered dielectric layer to form a second groove structure in the first even-numbered dielectric layer; and forming a first even-numbered electrode layer in the second groove structure.

[0010] In one or more embodiments of the present invention, forming a first even-numbered electrode layer on the first even-numbered dielectric layer includes: forming a metal electrode layer on the first even-numbered dielectric layer; and patterning the metal electrode layer to form the first even-numbered electrode layer.

[0011] In one or more embodiments of the present invention, before the step of forming a surface passivation layer, it also includes: forming a second odd-numbered dielectric layer on the first even-numbered electrode layer and the first even-numbered dielectric layer; forming a second odd-numbered electrode layer on the second odd-numbered dielectric layer, the second odd-numbered electrode layer has a first preset distance from the plane where the third surface of the substrate is located, and the second odd-numbered electrode layer is exposed to the plane where the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate is located.

[0012] In one or more embodiments of the present invention, forming a second odd-numbered electrode layer on the second odd-numbered dielectric layer includes: etching the second odd-numbered dielectric layer to form a third groove structure in the second odd-numbered dielectric layer; forming a second odd-numbered electrode layer in the third groove structure;

[0013] In one or more embodiments of the present invention, forming a second odd-numbered electrode layer on the second odd-numbered dielectric layer includes: forming a metal electrode layer on the second odd-numbered dielectric layer; and patterning the metal electrode layer to form the second odd-numbered electrode layer.

[0014] In one or more embodiments of the present invention, the first preset distance and the second preset distance are equal.

[0015] In one or more embodiments of the present invention, the first preset distance and the second preset distance are constants greater than zero.

[0016] In one or more embodiments of the present invention, the first preset distance H1 ranges from 0.1 μm to 5 μm.

[0017] An embodiment of the present invention provides a multilayer silicon capacitor structure, including a substrate, an electrode layer group, a dielectric layer and a passivation layer. The substrate has a first surface and a second surface arranged opposite to each other, and a third surface and a fourth surface connected to the first surface and the second surface and arranged opposite to each other; the electrode layer group is arranged on the first surface of the substrate, and the electrode layer group includes an odd electrode layer and an even electrode layer arranged alternately; the dielectric layer is arranged on the first surface, the second surface and the fourth surface of the substrate and filled between the odd electrode layer and the even electrode layer; the passivation layer is formed on the surface of the electrode layer group; wherein the odd electrode layer has a first preset distance from the plane where the third surface of the substrate is located, the odd electrode layer is exposed to the plane where the outer side of the dielectric layer on the fourth surface of the substrate is located, the even electrode layer is exposed to the plane where the third surface of the substrate is located, and the even electrode layer has a second preset distance from the plane where the outer side of the dielectric layer on the fourth surface of the substrate is located.

[0018] In one or more embodiments of the present invention, the first preset distance is equal to the second preset distance.

[0019] In one or more embodiments of the present invention, the first preset distance and the second preset distance are constants greater than zero.

[0020] In one or more embodiments of the present invention, the first preset distance H1 ranges from 0.1 μm to 5 μm.

[0021] An embodiment of the present invention provides a method for manufacturing a multilayer silicon capacitor structure, comprising: providing a substrate, the substrate having a first surface and a third surface and a fourth surface connected to the first surface and arranged opposite to each other; forming a first odd-numbered dielectric layer on the first surface of the substrate; forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer, the first odd-numbered electrode layer having a first preset distance from a plane where the third surface of the substrate is located, and the first odd-numbered electrode layer having a third preset distance from a plane where the fourth surface of the substrate is located; forming a first even-numbered dielectric layer on the first odd-numbered electrode layer and the first odd-numbered dielectric layer; forming a first even-numbered electrode layer on the first even-numbered dielectric layer, the first even-numbered electrode layer having a second preset distance from a plane where the fourth surface of the substrate is located that is greater than the third preset distance, and the first even-numbered electrode layer having a fourth preset distance from a plane where the third surface of the substrate is located that is less than the first preset distance; and forming a surface passivation layer.

[0022] In one or more embodiments of the present invention, forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer comprises: etching the first odd-numbered dielectric layer to form a first groove structure in the first odd-numbered dielectric layer; forming a first odd-numbered electrode layer in the first groove structure;

[0023] In one or more embodiments of the present invention, forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer includes: forming a metal electrode layer on the first odd-numbered dielectric layer; patterning the metal electrode layer to form the first odd-numbered electrode layer;

[0024] In one or more embodiments of the present invention, forming a first even-numbered electrode layer on the first even-numbered dielectric layer includes: etching the first even-numbered dielectric layer to form a second groove structure in the first even-numbered dielectric layer; forming the first even-numbered electrode layer in the second groove structure;

[0025] In one or more embodiments of the present invention, a first even-numbered electrode layer is formed on the first even-numbered dielectric layer, and a metal electrode layer is formed on the first even-numbered dielectric layer; and the metal electrode layer is patterned to form the first even-numbered electrode layer.

[0026] In one or more embodiments of the present invention, before the step of forming a surface passivation layer, it also includes: forming a second odd-numbered dielectric layer on the first even-numbered electrode layer and the first even-numbered dielectric layer; forming a second odd-numbered electrode layer on the second odd-numbered dielectric layer, the second odd-numbered electrode layer having a first preset distance from the plane where the third surface of the substrate is located, and the second odd-numbered electrode layer having a third preset distance from the plane where the fourth surface of the substrate is located.

[0027] In one or more embodiments of the present invention, forming a second odd-numbered electrode layer on the second odd-numbered dielectric layer comprises: etching the second odd-numbered dielectric layer to form a third groove structure in the second odd-numbered dielectric layer; forming the second odd-numbered electrode layer in the third groove structure;

[0028] In one or more embodiments of the present invention, forming a second odd-numbered electrode layer on the second odd-numbered dielectric layer includes: forming a metal electrode layer on the second odd-numbered dielectric layer; and patterning the metal electrode layer to form the second odd-numbered electrode layer.

[0029] In one or more embodiments of the present invention, the third preset distance is equal to the fourth preset distance.

[0030] In one or more embodiments of the present invention, the first preset distance is equal to the second preset distance.

[0031] In one or more embodiments of the present invention, the third preset distance is 0.

[0032] In one or more embodiments of the present invention, the fourth preset distance is 0.

[0033] An embodiment of the present invention provides a multilayer silicon capacitor structure, comprising a substrate, an electrode layer group, a dielectric layer and a passivation layer. The substrate has a first surface, and a third surface and a fourth surface connected to the first surface and arranged opposite to each other; the electrode layer group is arranged on the first surface of the substrate, the electrode layer group includes an odd electrode layer and an even electrode layer arranged alternately, the odd electrode layer has a first preset distance from the plane where the third surface of the substrate is located, the odd electrode layer has a third preset distance from the plane where the fourth surface of the substrate is located, the even electrode layer has a second preset distance from the plane where the fourth surface of the substrate is located that is greater than the third preset distance, and the even electrode layer has a fourth preset distance from the plane where the third surface of the substrate is located that is less than the first preset distance; the dielectric layer is arranged between the electrode layer group and the substrate, between the odd electrode layer and the even electrode layer, and in the space formed by the first preset distance, the third preset distance, the fourth preset distance and the second preset distance; the passivation layer is formed on the surface of the electrode layer group.

[0034] In one or more embodiments of the present invention, the third preset distance is equal to the fourth preset distance.

[0035] In one or more embodiments of the present invention, the first preset distance is equal to the second preset distance.

[0036] In one or more embodiments of the present invention, the third preset distance is 0.

[0037] In one or more embodiments of the present invention, the fourth preset distance is 0.

[0038] An embodiment of the present invention provides a method for manufacturing a multi-layer silicon capacitor structure, comprising:

[0039] Providing a substrate having a first surface and a second surface disposed opposite to each other, and a third surface and a fourth surface connected to the first surface and the second surface and disposed opposite to each other;

[0040] forming a first odd-numbered dielectric layer on the first surface, the second surface, and the fourth surface of the substrate;

[0041] forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer on the first surface of the substrate, wherein the first odd-numbered electrode layer has a first preset distance from a plane where the third surface of the substrate is located, the first preset distance is a constant greater than zero, and the first odd-numbered electrode layer is exposed to a plane where the outer side of the first odd-numbered dielectric layer is located on the fourth surface of the substrate;

[0042] forming a first even-numbered dielectric layer on the first odd-numbered electrode layer and the first odd-numbered dielectric layer on the first surface of the substrate;

[0043] forming a first even-numbered electrode layer on the first even-numbered dielectric layer, wherein the first even-numbered electrode layer is exposed to the plane where the third surface of the substrate is located, and a second preset distance is formed between the first even-numbered electrode layer and the plane where the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate is located, and the second preset distance is equal to the first preset distance;

[0044] forming a second odd-numbered dielectric layer on the first even-numbered electrode layer and the first even-numbered dielectric layer;

[0045] forming a second odd-numbered electrode layer on the second odd-numbered dielectric layer, wherein the second odd-numbered electrode layer has a first preset distance from a plane where the third surface of the substrate is located, and the second odd-numbered electrode layer is exposed to a plane where the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate is located;

[0046] Forming a surface passivation layer;

[0047] preparing a first end electrode on one side of the third surface of the substrate, so that the first end electrode is connected to the first even-numbered electrode layer and the exposed end of the substrate;

[0048] A second end electrode is prepared on the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate, so that the second end electrode is connected to the exposed ends of the first odd-numbered electrode layer and the second odd-numbered electrode layer.

[0049] An embodiment of the present invention provides a method for manufacturing a multi-layer silicon capacitor structure, comprising:

[0050] Providing a substrate having a first surface and a third surface and a fourth surface connected to the first surface and disposed opposite to each other;

[0051] forming a first odd-numbered dielectric layer on the first surface of the substrate;

[0052] forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer, wherein the first odd-numbered electrode layer has a first preset distance from a plane where the third surface of the substrate is located, and the first odd-numbered electrode layer has a third preset distance from a plane where the fourth surface of the substrate is located, and the first preset distance is greater than the third preset distance;

[0053] forming a first even-numbered dielectric layer on the first odd-numbered electrode layer and the first odd-numbered dielectric layer;

[0054] A first even-numbered electrode layer is formed on the first even-numbered dielectric layer, wherein the first even-numbered electrode layer and the plane where the fourth surface of the substrate is located have a second preset distance greater than the third preset distance, and the first even-numbered electrode layer and the plane where the third surface of the substrate is located have a fourth preset distance less than the first preset distance, the first preset distance and the second preset distance are equal, the first preset distance and the second preset distance are constants greater than zero, and the third preset distance and the fourth preset distance are equal;

[0055] forming a second odd-numbered dielectric layer on the first even-numbered electrode layer and the first even-numbered dielectric layer;

[0056] forming a second odd-numbered electrode layer on the second odd-numbered dielectric layer, wherein the second odd-numbered electrode layer has a first preset distance from a plane where the third surface of the substrate is located, and the second odd-numbered electrode layer has a third preset distance from a plane where the fourth surface of the substrate is located;

[0057] Forming a surface passivation layer;

[0058] A via hole is formed by etching in the area to which the first preset distance belongs, which passes through the first even-numbered electrode layer, exposes the substrate and has a diameter or side length smaller than the first preset distance, and a conductive material is filled in the via hole to form a first extraction electrode, wherein the first extraction electrode is connected to the first even-numbered electrode layer and the substrate;

[0059] A via hole is formed by etching in the area to which the second preset distance belongs, which passes through the second odd-numbered electrode layer, exposes the first odd-numbered electrode layer and has a diameter or side length smaller than the second preset distance, and a conductive material is filled in the via hole to form a second lead-out electrode, and the second lead-out electrode is connected to the first odd-numbered electrode layer and the second odd-numbered electrode layer.

[0060] Compared with the prior art, the method for manufacturing a multilayer silicon capacitor structure and the multilayer silicon capacitor structure according to the embodiment of the present invention perform patterning pretreatment on the dielectric layer or the electrode layer when preparing the dielectric layer and the electrode layer layer by layer to form odd-numbered electrode layers and even-numbered electrode layers that are alternately stacked, so that interconnection and electrical conduction between internal electrode layers can be finally achieved by etching in one step, and the process is simple and the overlay accuracy requirement is low.

[0061] According to the manufacturing method of the multilayer silicon capacitor structure and the multilayer silicon capacitor structure of the embodiment of the present invention, when preparing the dielectric layer and the electrode layer layer by layer, the dielectric layer or the electrode layer is patterned and pre-treated to form odd-numbered electrode layers and even-numbered electrode layers that are alternately stacked and exposed to different sides, respectively, so that the end electrodes are directly prepared on both sides, the process is simple and the overlay accuracy requirement is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 is a process flow chart of a method for manufacturing a multilayer silicon capacitor structure according to a first embodiment of the present invention;

[0063] Figure 2a-2j is a schematic diagram of the process steps of a method for manufacturing a multilayer silicon capacitor structure according to a first embodiment of the present invention;

[0064] Figure 3a-3j is another schematic diagram of process steps of the method for manufacturing the multilayer silicon capacitor structure according to the first embodiment of the present invention;

[0065] Figure 4 is a schematic diagram of a multilayer silicon capacitor structure according to a first embodiment of the present invention;

[0066] Figure 5 is a process flow chart of a method for manufacturing a multilayer silicon capacitor structure according to a second embodiment of the present invention;

[0067] Figure 6a-6d is a schematic diagram of the process steps of a method for manufacturing a multilayer silicon capacitor structure according to a second embodiment of the present invention;

[0068] Figure 7 FIG. 4 is a schematic diagram of a multilayer silicon capacitor structure according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0069] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific implementation modes.

[0070] Unless explicitly stated otherwise, throughout the specification and claims, the term “comprise” or variations such as “include” or “comprising”, etc., will be understood to include the stated elements or components but not to exclude other elements or components.

[0071] As mentioned in the background technology, in order to solve the problem of small capacitance of existing silicon capacitors, the method of increasing the number of layers of internal electrodes is adopted. However, the increase in the number of layers of internal electrodes has caused certain troubles for the lead-out of the electrodes. The current process is to form vias (Via) by opening holes layer by layer on the electrode layer and the dielectric layer, and then fill the vias with tungsten plugs or other conductive metals to connect the electrodes. However, this process method has complicated steps, high requirements for the overlay accuracy required for opening holes layer by layer to form vias, and very high requirements for the end point stop position of etching, resulting in a low yield rate.

[0072] In order to solve the above technical problems, the present application provides a method for manufacturing a multilayer silicon capacitor structure and a multilayer silicon capacitor structure. When forming dielectric layers and electrode layers layer by layer, the dielectric layers or electrode layers are patterned so that the odd-numbered electrode layers and the even-numbered electrode layers are partially non-overlapping in the stacking direction, so that only one step of etching is required to realize the interconnection and electrical lead-out between the odd-numbered electrode layers, and the interconnection and electrical lead-out between the even-numbered electrode layers. Alternatively, the dielectric layers or electrode layers are patterned so that the odd-numbered electrode layers and the even-numbered electrode layers are exposed on different sides, respectively, so that the end electrodes can be directly prepared at the ends of both sides in the future, so as to realize the interconnection and electrical lead-out between the odd-numbered electrode layers, and the interconnection and electrical lead-out between the even-numbered electrode layers. The process is simple and the overlay accuracy requirement is low.

[0073] The following describes in detail a method for manufacturing a multi-layer silicon capacitor structure according to a plurality of specific embodiments in combination with the accompanying drawings.

[0074] like Figure 1As shown, the first embodiment of the present invention provides a method for manufacturing a multilayer silicon capacitor structure, including: s1, providing a substrate, the substrate having a first surface and a second surface arranged opposite to each other, and a third surface and a fourth surface connected to the first surface and the second surface and arranged opposite to each other; s2, forming a first odd-numbered dielectric layer on the first surface, the second surface and the fourth surface of the substrate; s3, forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer on the first surface of the substrate, the first odd-numbered electrode layer and the plane where the third surface of the substrate is located have a first preset distance, and the first odd-numbered electrode layer is exposed to the plane where the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate is located; s4, forming a first even-numbered dielectric layer on the first odd-numbered electrode layer and the first odd-numbered dielectric layer on the first surface of the substrate; s5, forming a first even-numbered dielectric layer on the first even-numbered dielectric layer, the first even-numbered electrode layer is exposed to the plane where the third surface of the substrate is located, and the first even-numbered electrode layer and the plane where the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate is located have a second preset distance; s6, forming a surface passivation layer.

[0075] Wherein, before step s6, it may also include the steps of forming a second odd dielectric layer on the first even electrode layer and the first even dielectric layer, forming a second odd electrode layer on the second odd dielectric layer, the second odd electrode layer having a first preset distance from the plane where the third surface of the substrate is located, and the second odd electrode layer is exposed to the plane where the outer side of the first odd dielectric layer is located on the fourth surface of the substrate. It is understandable that after this step, the second even dielectric layer and the second even electrode layer may continue to be formed, and the structure, position and formation method of the second even electrode layer are consistent with those of the first even electrode layer. Of course, more odd dielectric layers, odd electrode layers, even dielectric layers and even electrode layers may also be formed as needed, and the surface passivation layer is formed on the surface of the uppermost dielectric layer and electrode layer.

[0076] Figures 2a to 2j A process diagram of the process steps for manufacturing a multi-layer silicon capacitor structure according to the first embodiment of the present application is shown.

[0077] like Figure 2aAs shown, a substrate 10 is provided, and the substrate 10 has a first surface 10a and a second surface 10b arranged opposite to each other, and a third surface 10c and a fourth surface 10d connected to the first surface 10a and the second surface 10b and arranged opposite to each other. A first odd-numbered dielectric layer 210 is formed on the first surface 10a, the second surface 10b and the fourth surface 10d of the substrate 10. The substrate 10 is preferably a silicon substrate. The first odd-numbered dielectric layer 210 is preferably a SiN film layer. It can be understood that the first odd-numbered dielectric layer 210 can also be other dielectric film layers, such as a SiO2 film layer. Exemplarily, the silicon substrate is placed in an LPCVD (low pressure chemical vapor deposition) furnace tube, and the surface is coated, and then the silicon substrate is semi-enclosed in the dielectric layer by overall cutting or partial etching. The dielectric layer can also be obtained by thermal oxidation growth, ALD (atomic layer deposition), etc.

[0078] like Figure 2b As shown, the first odd-numbered dielectric layer 210a on the first surface 10a of the substrate 10 is etched to form a first groove structure 21 in the first odd-numbered dielectric layer 210a on the first surface 10a. The first groove structure 21 is preferably a square structure. There is a first preset distance H1 between one end of the first groove structure 21 close to the third surface 10c of the substrate 10 and the plane X1 where the third surface 10c is located; one end of the first groove structure 21 away from the third surface 10c of the substrate 10 is exposed to the plane X2 where the outer side of the first odd-numbered dielectric layer 210d on the fourth surface 10d of the substrate 10 is located. The first preset distance H1 is a constant greater than zero. Preferably, the first preset distance H1 ranges from 0.1μm to 5μm.

[0079] like Figure 2c As shown, a first odd-numbered electrode layer 310 is formed in the first groove structure 21. The first odd-numbered electrode layer 310 is formed in the first groove structure 21 by deposition, filling or evaporation. The material of the first odd-numbered electrode layer 310 can be polysilicon or conductive metal.

[0080] like Figure 2d As shown, a first even-numbered dielectric layer 410 is formed on the first odd-numbered electrode layer 310 and the first odd-numbered dielectric layer 210a on the first surface 10a of the substrate 10. The first even-numbered dielectric layer 410 is preferably a SiN thin film layer. It is understood that the first even-numbered dielectric layer 410 may also be other dielectric film layers, such as a SiO2 thin film layer. Exemplarily, the deposition of the first even-numbered dielectric layer 410 is performed by LPCVD (low pressure chemical vapor deposition).

[0081] like Figure 2eAs shown, the first even-numbered dielectric layer 410 is etched to form a second groove structure 41 in the first even-numbered dielectric layer 410. The second groove structure 41 is preferably a square structure. A second preset distance H2 is provided between one end of the second groove structure 41 close to the fourth surface 10d of the substrate 10 and the plane X2 where the outer side of the first odd-numbered dielectric layer 210d on the fourth surface 10d is located; one end of the second groove structure 41 away from the fourth surface 10d of the substrate 10 is exposed to the third surface 10c of the substrate 10. The second preset distance H2 is a constant greater than zero, and the second preset distance H2 may be equal to the first preset distance H1.

[0082] like Figure 2f As shown, a first even-numbered electrode layer 510 is formed in the second groove structure 41. The first even-numbered electrode layer 510 is formed in the second groove structure 41 by deposition, filling or evaporation. The material of the first even-numbered electrode layer 510 can be polysilicon or conductive metal.

[0083] like Figure 2g As shown, a second odd-numbered dielectric layer 220 is formed on the first even-numbered electrode layer 510 and the first even-numbered dielectric layer 410. The second odd-numbered dielectric layer 220 is preferably a SiN thin film layer. It is understood that the second odd-numbered dielectric layer 220 may also be other dielectric film layers, such as a SiO2 thin film layer, etc. Exemplarily, the second odd-numbered dielectric layer 220 is deposited by LPCVD (low pressure chemical vapor deposition).

[0084] like Figure 2h As shown, the second odd-numbered dielectric layer 220 is etched to form a third groove structure 22 in the second odd-numbered dielectric layer 220. The third groove structure 22 is preferably a square structure. There is a first preset distance H1 between one end of the third groove structure 22 close to the third surface 10c of the substrate 10 and the plane X1 where the third surface 10c is located; one end of the first groove structure 21 away from the third surface 10c of the substrate 10 is exposed to the plane X2 where the outer side of the first odd-numbered dielectric layer 210d on the fourth surface 10d of the substrate 10 is located. The first preset distance H1 is a constant greater than zero.

[0085] like Figure 2i As shown, a second odd-numbered electrode layer 320 is formed in the third groove structure 22. The second odd-numbered electrode layer 320 is formed in the third groove structure 22 by deposition, filling or evaporation. The material of the second odd-numbered electrode layer 320 can be polysilicon or conductive metal.

[0086] like Figure 2jAs shown, a surface passivation layer 60 is formed on the surface of the second odd-numbered electrode layer 320 and the second odd-numbered dielectric layer 220. The material of the surface passivation layer 60 is preferably a SiN film layer. It is understandable that the surface passivation layer 60 can also be other dielectric film layers, such as a SiO2 film layer. Exemplarily, the surface passivation layer 60 is deposited by LPCVD (low pressure chemical vapor deposition).

[0087] In the above technical solution, the substrate 10 is used as an even-numbered electrode layer. When the end electrodes are subsequently prepared, the first end electrode is directly connected to the first even-numbered electrode layer 510 and the substrate 10; the second end electrode is directly connected to the first odd-numbered electrode layer 310 and the second odd-numbered electrode layer 320. Exemplarily, the first end electrode is prepared directly on the side of the third surface 10c of the substrate 10, so that the first end electrode is connected to the exposed end of the first even-numbered electrode layer 510 and the substrate 10. The first odd-numbered electrode layer 310 and the second odd-numbered electrode layer 320 are electrically isolated from the first end electrode due to the first preset distance H1 between the side of the third surface 10c of the substrate 10 and the dielectric layer. The second end electrode is prepared directly on the outer side of the first odd-numbered dielectric layer 210d on the fourth surface 10d of the substrate 10, so that the second end electrode is connected to the exposed end of the first odd-numbered electrode layer 310 and the second odd-numbered electrode layer 320. The first even-numbered electrode layer 510 and the substrate 10 are electrically isolated from the second end electrode because they are at a second preset distance H2 from the outer side of the first odd-numbered dielectric layer 210d on the fourth surface 10d of the substrate 10 and a dielectric layer is provided.

[0088] Understandably, this may not be necessary. Figure 2g and Figure 2h The second odd-numbered dielectric layer 220 and the second odd-numbered electrode layer 320 are fabricated by directly forming a passivation layer 60 on the first even-numbered electrode layer 510 and the first even-numbered dielectric layer 410. In this solution, the substrate 10 is not used as an electrode layer. Then, when the end electrodes are subsequently fabricated, the first end electrodes are directly connected to the first even-numbered electrode layer 510; and the second end electrodes are directly connected to the first odd-numbered electrode layer 310. Of course, in Figure 2i Before the steps shown, you can also follow the Figure 2a to Figure 2f The process steps are used to manufacture multiple odd-numbered electrode layers and even-numbered electrode layers. This application will not be elaborated in detail here.

[0089] Figures 3a to 3j A process diagram of another process step for manufacturing a multi-layer silicon capacitor structure according to the first embodiment of the present application is shown.

[0090] like Figure 3aAs shown, a substrate 10 is provided, and the substrate 10 has a first surface 10a and a second surface 10b arranged opposite to each other, and a third surface 10c and a fourth surface 10d connected to the first surface 10a and the second surface 10b and arranged opposite to each other. A first odd-numbered dielectric layer 210 is formed on the first surface 10a, the second surface 10b and the fourth surface 10d of the substrate 10. The substrate 10 is preferably a silicon substrate. The first odd-numbered dielectric layer 210 is preferably a SiN film layer. It can be understood that the first odd-numbered dielectric layer 210 can also be other dielectric film layers, such as a SiO2 film layer. Exemplarily, the silicon substrate is placed in an LPCVD (low pressure chemical vapor deposition) furnace tube, and the surface is coated, and then the silicon substrate is semi-enclosed in the dielectric layer by overall cutting or partial etching. The dielectric layer can also be obtained by thermal oxidation growth, ALD (atomic layer deposition), etc.

[0091] like Figure 3b As shown, a metal electrode layer A is formed on the first odd-numbered dielectric layer 210 a on the first surface 10 a of the substrate 10 .

[0092] like Figure 3c As shown, the metal electrode layer A is patterned to obtain a first odd-numbered electrode layer 310. A first preset distance H1 exists between one end of the first odd-numbered electrode layer 310 close to the third surface 10c of the substrate 10 and the plane X1 where the third surface 10c is located; one end of the first odd-numbered electrode layer 310 away from the third surface 10c of the substrate 10 is exposed to the plane X2 where the outer side of the first odd-numbered dielectric layer 210d on the fourth surface 10d of the substrate 10 is located. The first preset distance H1 is a constant greater than zero, and preferably, the first preset distance H1 ranges from 0.1 μm to 5 μm.

[0093] like Figure 3d As shown, a first even-numbered dielectric layer 410 is formed on the first odd-numbered electrode layer 310 and the first odd-numbered dielectric layer 210a on the first surface 10a of the substrate 10. The first even-numbered dielectric layer 410 is preferably a SiN thin film layer. It is understood that the first even-numbered dielectric layer 410 may also be other dielectric film layers, such as a SiO2 thin film layer. Exemplarily, the deposition of the first even-numbered dielectric layer 410 is performed by LPCVD (low pressure chemical vapor deposition).

[0094] like Figure 3e As shown, a metal electrode layer A is formed on the first even-numbered dielectric layer 410 .

[0095] like Figure 3fAs shown, the metal electrode layer A is patterned to obtain a first even electrode layer 510. A second preset distance H2 is provided between one end of the first even electrode layer 510 close to the fourth surface 10d of the substrate 10 and the plane X2 where the outer side of the first odd dielectric layer 210d on the fourth surface 10d is located; one end of the first even electrode layer 510 far from the fourth surface 10d of the substrate 10 is exposed to the third surface 10c of the substrate 10. The second preset distance H2 is a constant greater than zero, and the second preset distance H2 may be equal to the first preset distance H1.

[0096] like Figure 3g As shown, a second odd-numbered dielectric layer 220 is formed on the first even-numbered electrode layer 510 and the first even-numbered dielectric layer 410. The second odd-numbered dielectric layer 220 is preferably a SiN thin film layer. It is understood that the second odd-numbered dielectric layer 220 may also be other dielectric film layers, such as a SiO2 thin film layer, etc. Exemplarily, the second odd-numbered dielectric layer 220 is deposited by LPCVD (low pressure chemical vapor deposition).

[0097] like Figure 3h As shown, a metal electrode layer A is formed on the second odd-numbered dielectric layer 220 .

[0098] like Figure 3i As shown, the metal electrode layer A is patterned to obtain a second odd-numbered electrode layer 320. A first preset distance H1 exists between one end of the second odd-numbered electrode layer 320 close to the third surface 10c of the substrate 10 and the plane X1 where the third surface 10c is located; one end of the second odd-numbered electrode layer 320 away from the third surface 10c of the substrate 10 is exposed to the plane X2 where the outer side of the first odd-numbered dielectric layer 210d on the fourth surface 10d of the substrate 10 is located. The first preset distance H1 is a constant greater than zero.

[0099] like Figure 3j As shown, a surface passivation layer 60 is formed on the surface of the second odd-numbered electrode layer 320 and the second odd-numbered dielectric layer 220. The material of the surface passivation layer 60 is preferably a SiN film layer. It is understandable that the surface passivation layer 60 can also be other dielectric film layers, such as a SiO2 film layer. Exemplarily, the surface passivation layer 60 is deposited by LPCVD (low pressure chemical vapor deposition).

[0100] In the above technical solution, the substrate 10 is used as an even-numbered electrode layer. When the end electrodes are subsequently prepared, the first end electrode is directly connected to the first even-numbered electrode layer 510 and the substrate 10; the second end electrode is directly connected to the first odd-numbered electrode layer 310 and the second odd-numbered electrode layer 320. Exemplarily, the first end electrode is prepared directly on the side of the third surface 10c of the substrate 10, so that the first end electrode is connected to the exposed end of the first even-numbered electrode layer 510 and the substrate 10. The first odd-numbered electrode layer 310 and the second odd-numbered electrode layer 320 are electrically isolated from the first end electrode due to the first preset distance H1 between the side of the third surface 10c of the substrate 10 and the dielectric layer. The second end electrode is prepared directly on the outer side of the first odd-numbered dielectric layer 210d on the fourth surface 10d of the substrate 10, so that the second end electrode is connected to the exposed end of the first odd-numbered electrode layer 310 and the second odd-numbered electrode layer 320. The first even-numbered electrode layer 510 and the substrate 10 are electrically isolated from the second end electrode because they are at a second preset distance H2 from the outer side of the first odd-numbered dielectric layer 210d on the fourth surface 10d of the substrate 10 and a dielectric layer is provided.

[0101] Understandably, this may not be necessary. Figure 3g and Figure 3h The second odd-numbered dielectric layer 220 and the second odd-numbered electrode layer 320 are fabricated by directly forming a passivation layer 60 on the first even-numbered electrode layer 510 and the first even-numbered dielectric layer 410. In this solution, the substrate 10 is not used as an electrode layer. Then, when the end electrodes are subsequently fabricated, the first end electrodes are directly connected to the first even-numbered electrode layer 510; and the second end electrodes are directly connected to the first odd-numbered electrode layer 310. Of course, in Figure 3i Before the steps shown, you can also follow the Figures 3a to 3f The process steps are used to manufacture multiple odd-numbered electrode layers and even-numbered electrode layers. This application will not be elaborated in detail here.

[0102] like Figure 4 As shown, the first embodiment of the present invention also provides a multilayer silicon capacitor structure made by the above method, including a substrate 10, an electrode layer group, a dielectric layer and a passivation layer 60. The substrate 10 has a first surface 10a and a second surface 10b arranged opposite to each other, and a third surface 10c and a fourth surface 10d connected to the first surface 10a and the second surface 10b and arranged opposite to each other. The electrode layer group is arranged on the first surface 10a of the substrate 10, and the electrode layer group includes an odd electrode layer O and an even electrode layer P arranged alternately. The dielectric layer is arranged on the first surface 10a, the second surface 10b and the fourth surface 10d of the substrate 10 and filled between the odd electrode layer O and the even electrode layer P. The passivation layer 60 is formed on the surface of the electrode layer group.

[0103] Among them, the odd-numbered electrode layer O has a first preset distance H1 from the plane X1 where the third surface 10c of the substrate 10 is located, the odd-numbered electrode layer O is exposed to the plane X2 where the outer side of the dielectric layer on the fourth surface 10d of the substrate 10 is located, the even-numbered electrode layer P is exposed to the plane X1 where the third surface 10c of the substrate 10 is located, and the even-numbered electrode layer P has a second preset distance H2 from the plane X2 where the outer side of the dielectric layer on the fourth surface 10d of the substrate 10 is located. The first preset distance H1 and the second preset distance H2 are constants greater than zero, and preferably, the first preset distance H1 and the second preset distance H2 are both in the range of 0.1μm-5μm.

[0104] In a specific embodiment, the first preset distance H1 is equal to the second preset distance H2.

[0105] like Figure 5 As shown, the second embodiment of the present invention provides a method for manufacturing a multilayer silicon capacitor structure, including: s1, providing a substrate, the substrate having a first surface and a third surface and a fourth surface connected to the first surface and arranged opposite to each other; s2, forming a first odd-numbered dielectric layer on the first surface of the substrate; s3, forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer, the first odd-numbered electrode layer and the plane where the third surface of the substrate is located have a first preset distance, and the first odd-numbered electrode layer and the plane where the fourth surface of the substrate is located have a third preset distance; s4, forming a first even-numbered dielectric layer on the first odd-numbered electrode layer and the first odd-numbered dielectric layer; s5, forming a first even-numbered electrode layer on the first even-numbered dielectric layer, the first even-numbered electrode layer and the plane where the fourth surface of the substrate is located have a second preset distance greater than the third preset distance, and the first even-numbered electrode layer and the plane where the third surface of the substrate is located have a fourth preset distance less than the first preset distance; s6, forming a surface passivation layer.

[0106] Wherein, before step s6, it can also include the steps of forming a second odd-numbered dielectric layer on the first even-numbered electrode layer and the first even-numbered dielectric layer, forming a second odd-numbered electrode layer on the second odd-numbered dielectric layer, the second odd-numbered electrode layer having a first preset distance from the plane where the third surface of the substrate is located, and the second odd-numbered electrode layer having a third preset distance from the plane where the fourth surface of the substrate is located. It can be understood that after this step, the second even-numbered dielectric layer and the second even-numbered electrode layer can continue to be formed, and the structure, position and formation method of the second even-numbered electrode layer are consistent with those of the first even-numbered electrode layer. Of course, more odd-numbered dielectric layers, odd-numbered electrode layers, even-numbered dielectric layers and even-numbered electrode layers can also be formed as needed, and the surface passivation layer is formed on the surface of the uppermost dielectric layer and electrode layer.

[0107] Figures 6a to 6d A process diagram of the process steps for manufacturing a multi-layer silicon capacitor structure according to the second embodiment of the present application is shown.

[0108] like Figure 6a As shown, a substrate 10 is provided, and the substrate 10 has a first surface 10a arranged opposite to each other, and a third surface 10c and a fourth surface 10d connected to the first surface 10a and arranged opposite to each other. A first odd-numbered dielectric layer 210 is formed on the first surface 10a of the substrate 10. The substrate 10 is preferably a silicon substrate. The first odd-numbered dielectric layer 210 is preferably a SiN film layer. It is understandable that the first odd-numbered dielectric layer 210 can also be other dielectric film layers, such as a SiO2 film layer. Exemplarily, the silicon substrate is placed in an LPCVD (low pressure chemical vapor deposition) furnace tube, and the surface is coated, and then the silicon substrate is semi-enclosed in the dielectric layer by overall cutting or partial etching. The dielectric layer can also be obtained by thermal oxidation growth, ALD (atomic layer deposition), etc.

[0109] A first odd-numbered electrode layer 310 is formed on the first odd-numbered dielectric layer 210 .

[0110] Exemplarily, the first odd-numbered dielectric layer 210 can be etched to form a first groove structure in the first odd-numbered dielectric layer 210. The first groove structure is preferably a square structure. A first preset distance H1 is provided between an end of the first groove structure close to the third surface 10c of the substrate 10 and a plane X1 where the third surface 10c is located; a third preset distance H3 is provided between an end of the first groove structure close to the fourth surface 10d of the substrate 10 and a plane X3 where the fourth surface 10d is located. Preferably, the first preset distance H1 is greater than the third preset distance H3. The first odd-numbered electrode layer 310 is formed in the first groove structure by deposition, filling or evaporation. The material of the first odd-numbered electrode layer 310 can be polysilicon or a conductive metal.

[0111] Exemplarily, a metal electrode layer may also be formed directly on the first odd-numbered dielectric layer 210. The metal electrode layer is patterned to obtain a first odd-numbered electrode layer 310. A first preset distance H1 is provided between an end of the first odd-numbered electrode layer 310 close to the third surface 10c of the substrate 10 and a plane X1 where the third surface 10c is located; a third preset distance H3 is provided between an end of the first odd-numbered electrode layer 310 close to the fourth surface 10d of the substrate 10 and a plane X3 where the fourth surface 10d is located. Preferably, the first preset distance H1 is greater than the third preset distance H3.

[0112] like Figure 6b As shown, a first even-numbered dielectric layer 410 is formed on the first odd-numbered electrode layer 310 and the first odd-numbered dielectric layer 210. The first even-numbered dielectric layer 410 is preferably a SiN thin film layer. It is understood that the first even-numbered dielectric layer 410 may also be other dielectric film layers, such as a SiO2 thin film layer, etc. Exemplarily, the first even-numbered dielectric layer 410 is deposited by LPCVD (low pressure chemical vapor deposition).

[0113] A first even-numbered electrode layer 510 is formed on the first even-numbered dielectric layer 410 .

[0114] Exemplarily, the first even-numbered dielectric layer 410 may be etched to form a second groove structure in the first even-numbered dielectric layer 410. The second groove structure is preferably a square structure. A second preset distance H2 greater than the third preset distance H3 exists between one end of the second groove structure close to the fourth surface 10d of the substrate 10 and the plane X3 where the fourth surface 10d is located; a fourth preset distance H4 less than the first preset distance H1 exists between one end of the second groove structure close to the third surface 10c of the substrate 10 and the plane X1 where the third surface 10c is located. Among them, the first preset distance H1 and the second preset distance H2 are constants greater than zero. In one embodiment, the third preset distance H3 and the fourth preset distance H4 are equal. In another embodiment, the first preset distance H1 and the second preset distance H2 are equal. In another embodiment, one or more of the third preset distance H3 and the fourth preset distance H4 are zero.

[0115] Exemplarily, a metal electrode layer can also be formed directly on the first even-numbered dielectric layer 410. The metal electrode layer is patterned to obtain the first even-numbered electrode layer 510. A second preset distance H2 greater than the third preset distance H3 is provided between one end of the first even-numbered electrode layer 510 close to the fourth surface 10d of the substrate 10 and the plane X3 where the fourth surface 10d is located; a fourth preset distance H4 less than the first preset distance H1 is provided between one end of the first odd-numbered electrode layer 310 close to the third surface 10c of the substrate 10 and the plane X1 where the third surface 10c is located. The first preset distance H1 and the second preset distance H2 are constants greater than zero. In one embodiment, the third preset distance H3 and the fourth preset distance H4 are equal. In another embodiment, the first preset distance H1 and the second preset distance H2 are equal. In another embodiment, one or more of the third preset distance H3 and the fourth preset distance H4 are zero.

[0116] like Figure 6c As shown, a second odd-numbered dielectric layer 220 is formed on the first even-numbered electrode layer 510 and the first even-numbered dielectric layer 410. The second odd-numbered dielectric layer 220 is preferably a SiN thin film layer. It is understood that the second odd-numbered dielectric layer 220 may also be other dielectric film layers, such as a SiO2 thin film layer, etc. Exemplarily, the second odd-numbered dielectric layer 220 is deposited by LPCVD (low pressure chemical vapor deposition).

[0117] The second odd-numbered electrode layer 320 is formed on the second odd-numbered dielectric layer 220 .

[0118] Exemplarily, the second odd-numbered dielectric layer 220 can be etched to form a third groove structure in the second odd-numbered dielectric layer 220. The third groove structure is preferably a square structure. A first preset distance H1 is provided between an end of the third groove structure close to the third surface 10c of the substrate 10 and a plane X1 where the third surface 10c is located; a third preset distance H3 is provided between an end of the third groove structure close to the fourth surface 10d of the substrate 10 and a plane X3 where the fourth surface 10d is located. Preferably, the first preset distance H1 is greater than the third preset distance H3. A second odd-numbered electrode layer 320 is formed in the third groove structure by deposition, filling or evaporation. The material of the second odd-numbered electrode layer 320 can be polysilicon or a conductive metal.

[0119] Exemplarily, a metal electrode layer may also be directly formed on the second odd-numbered dielectric layer 220. The metal electrode layer is patterned to obtain a second odd-numbered electrode layer 320. A first preset distance H1 is provided between an end of the second odd-numbered electrode layer 320 close to the third surface 10c of the substrate 10 and a plane X1 where the third surface 10c is located; a third preset distance H3 is provided between an end of the first odd-numbered electrode layer 310 close to the fourth surface 10d of the substrate 10 and a plane X3 where the fourth surface 10d is located.

[0120] like Figure 6d As shown, a surface passivation layer 60 is formed on the surface of the second odd-numbered electrode layer 320 and the second odd-numbered dielectric layer 220. The material of the surface passivation layer 60 is preferably a SiN film layer. It is understandable that the surface passivation layer 60 can also be other dielectric film layers, such as a SiO2 film layer. Exemplarily, the surface passivation layer 60 is deposited by LPCVD (low pressure chemical vapor deposition).

[0121] In the above technical solution, the substrate 10 is used as the even electrode layer. When the lead-out electrode is subsequently prepared, a via hole is etched in the area corresponding to the first preset distance H1, which passes through the first even electrode layer 510, exposes the substrate 10 and has a diameter or side length less than H1, and a conductive material is filled in the via hole to form a first lead-out electrode, which is directly connected to the first even electrode layer 510 and the substrate 10; and the first odd electrode layer 310 and the second odd electrode layer 320 are electrically isolated from the first lead-out electrode due to the space of the first preset distance H1 between them and the side of the third surface 10c of the substrate 10 and the provision of a dielectric layer. A via hole is etched in the area corresponding to the second preset distance H2, which passes through the second odd-numbered electrode layer, exposes the first odd-numbered electrode layer and has a diameter or side length less than H2, and a conductive material is filled in the via hole to form a second lead-out electrode, so as to directly connect the first odd-numbered electrode layer 310 and the second odd-numbered electrode layer 320; and the first even-numbered electrode layer 510 and the substrate 10 are electrically isolated from the second lead-out electrode due to the space of the second preset distance H2 between them and the fourth surface 10d of the substrate 10 and the provision of a dielectric layer.

[0122] Understandably, this may not be necessary. Figure 6c The second odd-numbered dielectric layer 220 and the second odd-numbered electrode layer 320 are fabricated by directly forming a passivation layer 60 on the first even-numbered electrode layer 510 and the first even-numbered dielectric layer 410. In this solution, the substrate 10 is not used as an electrode layer. Then, when the extraction electrode is subsequently prepared, the first extraction electrode is directly connected to the first even-numbered electrode layer 510; the second extraction electrode is directly connected to the first odd-numbered electrode layer 310. Of course, in Figure 6d Before the steps shown, you can also follow the Figures 6a to 6c The process steps are used to manufacture multiple odd-numbered electrode layers and even-numbered electrode layers. This application will not be elaborated in detail here.

[0123] like Figure 7 As shown, the second embodiment of the present invention also provides a multilayer silicon capacitor structure made by the above method, including a substrate 10, an electrode layer group, a dielectric layer and a passivation layer 60. The substrate 10 has a first surface 10a and a third surface 10c and a fourth surface 10d connected to the first surface 10a and arranged opposite to each other. The electrode layer group is arranged on the first surface 10a of the substrate 10, and the electrode layer group includes odd electrode layers O and even electrode layers P arranged alternately. The dielectric layer is arranged between the electrode layer group and the first surface 10a of the substrate 10 and filled between the odd electrode layers O and the even electrode layers P, including filling in the space belonging to the first preset distance, the third preset distance, the fourth preset distance and the second preset distance. The passivation layer 60 is formed on the surface of the electrode layer group.

[0124] Among them, the odd-numbered electrode layer O and the plane X1 where the third surface 10c of the substrate 10 is located have a first preset distance H1, the odd-numbered electrode layer O and the plane X3 where the fourth surface 10d of the substrate 10 is located have a third preset distance H3, the even-numbered electrode layer P and the plane X3 where the fourth surface 10d of the substrate 10 is located have a second preset distance H2 greater than the third preset distance H3, and the even-numbered electrode layer P and the plane X1 where the third surface 10c of the substrate 10 is located have a fourth preset distance H4 less than the first preset distance H1. The first preset distance H1 and the second preset distance H2 are constants greater than zero.

[0125] In one specific embodiment, the first preset distance H1 is equal to the second preset distance H2. In another specific embodiment, the third preset distance H3 is equal to the fourth preset distance H4. In another specific embodiment, one or more of the third preset distance H3 and the fourth preset distance H4 is zero.

[0126] Compared with the prior art, the method for manufacturing a multilayer silicon capacitor structure and the multilayer silicon capacitor structure according to the embodiment of the present invention perform patterning pretreatment on the dielectric layer or the electrode layer when preparing the dielectric layer and the electrode layer layer by layer to form odd-numbered electrode layers and even-numbered electrode layers that are alternately stacked, so that interconnection and electrical conduction between internal electrode layers can be finally achieved by etching in one step, and the process is simple and the overlay accuracy requirement is low.

[0127] According to the manufacturing method of the multilayer silicon capacitor structure and the multilayer silicon capacitor structure of the embodiment of the present invention, when preparing the dielectric layer and the electrode layer layer by layer, the dielectric layer or the electrode layer is patterned and pre-treated to form odd-numbered electrode layers and even-numbered electrode layers that are alternately stacked and exposed to different sides, respectively, so that the end electrodes are directly prepared on both sides, the process is simple and the overlay accuracy requirement is low.

[0128] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.

Claims

1. A method for manufacturing a multilayer silicon capacitor structure, It is characterized in that include: Providing a substrate having a first surface and a second surface disposed opposite to each other, and a third surface and a fourth surface connected to the first surface and the second surface and disposed opposite to each other; forming a first odd-numbered dielectric layer on the first surface, the second surface, and the fourth surface of the substrate; forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer on the first surface of the substrate, wherein the first odd-numbered electrode layer has a first preset distance from a plane where the third surface of the substrate is located, and the first odd-numbered electrode layer is exposed to a plane where the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate is located; forming a first even-numbered dielectric layer on the first odd-numbered electrode layer and the first odd-numbered dielectric layer on the first surface of the substrate; forming a first even-numbered electrode layer on the first even-numbered dielectric layer, wherein the first even-numbered electrode layer is exposed to the plane where the third surface of the substrate is located, and a second preset distance exists between the first even-numbered electrode layer and the plane where the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate is located; Form a surface passivation layer.

2. The method for manufacturing a multilayer silicon capacitor structure according to claim 1, It is characterized in that Forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer on the first surface of the substrate includes: Etching the first odd-numbered dielectric layer on the first surface of the substrate to form a first groove structure in the first odd-numbered dielectric layer; forming a first odd-numbered electrode layer in the first groove structure; or, forming a metal electrode layer on the first odd-numbered dielectric layer on the first surface of the substrate; and patterning the metal electrode layer to form a first odd-numbered electrode layer; and / or, Forming a first even-numbered electrode layer on the first even-numbered dielectric layer comprises: Etching the first even-numbered dielectric layer to form a second groove structure in the first even-numbered dielectric layer; forming a first even-numbered electrode layer in the second groove structure; or, A metal electrode layer is formed on the first even-numbered dielectric layer; and the metal electrode layer is patterned to form a first even-numbered electrode layer.

3. The method for manufacturing the multilayer silicon capacitor structure according to claim 1, It is characterized in that Before the step of forming the surface passivation layer, the method further comprises: forming a second odd-numbered dielectric layer on the first even-numbered electrode layer and the first even-numbered dielectric layer; A second odd-numbered electrode layer is formed on the second odd-numbered dielectric layer, wherein the second odd-numbered electrode layer has a first preset distance from a plane where the third surface of the substrate is located, and the second odd-numbered electrode layer is exposed to a plane where the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate is located.

4. The method for manufacturing a multilayer silicon capacitor structure as claimed in claim 3, It is characterized in that Forming a second odd-numbered electrode layer on the second odd-numbered dielectric layer, comprising: Etching the second odd-numbered dielectric layer to form a third groove structure in the second odd-numbered dielectric layer; forming a second odd-numbered electrode layer in the third groove structure; or, A metal electrode layer is formed on the second odd-numbered dielectric layer; and the metal electrode layer is patterned to form a second odd-numbered electrode layer.

5. The method for manufacturing a multilayer silicon capacitor structure according to claim 1, It is characterized in that The first preset distance and the second preset distance are equal; and / or, The first preset distance and the second preset distance are constants greater than zero.

6. A multilayer silicon capacitor structure, It is characterized in that include: A substrate having a first surface and a second surface disposed opposite to each other, and a third surface and a fourth surface connected to the first surface and the second surface and disposed opposite to each other; An electrode layer group is disposed on the first surface of the substrate, wherein the electrode layer group comprises odd-numbered electrode layers and even-numbered electrode layers that are alternately disposed; A dielectric layer, disposed on the first surface, the second surface and the fourth surface of the substrate and filled between the odd-numbered electrode layers and the even-numbered electrode layers; A passivation layer formed on the surface of the electrode layer group; The odd-numbered electrode layers have a first preset distance from the plane where the third surface of the substrate is located, the odd-numbered electrode layers are exposed to the plane where the outer side of the dielectric layer on the fourth surface of the substrate is located, the even-numbered electrode layers are exposed to the plane where the third surface of the substrate is located, and the even-numbered electrode layers have a second preset distance from the plane where the outer side of the dielectric layer on the fourth surface of the substrate is located.

7. The multilayer silicon capacitor structure according to claim 6, It is characterized in that The first preset distance is equal to the second preset distance; and / or, The first preset distance and the second preset distance are constants greater than zero.

8. The multilayer silicon capacitor structure as claimed in claim 6, It is characterized in that The first preset distance H 1 The range is 0.1μm-5μm.

9. A method for manufacturing a multilayer silicon capacitor structure, It is characterized in that include: Providing a substrate having a first surface and a third surface and a fourth surface connected to the first surface and disposed opposite to each other; forming a first odd-numbered dielectric layer on the first surface of the substrate; forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer, wherein the first odd-numbered electrode layer has a first preset distance from a plane where the third surface of the substrate is located; forming a first even-numbered dielectric layer on the first odd-numbered electrode layer and the first odd-numbered dielectric layer; forming a first even-numbered electrode layer on the first even-numbered dielectric layer, wherein the first even-numbered electrode layer has a second preset distance from a plane where the fourth surface of the substrate is located; Form a surface passivation layer.

10. The method for manufacturing a multi-layer silicon capacitor structure according to claim 9, It is characterized in that The first preset distance is equal to the second preset distance.

11. The method for manufacturing a multi-layer silicon capacitor structure according to claim 9, It is characterized in that A third preset distance exists between the first odd-numbered electrode layer and a plane where the fourth surface of the substrate is located, and the third preset distance is smaller than the second preset distance.

12. The method for manufacturing a multi-layer silicon capacitor structure according to claim 11, It is characterized in that A fourth preset distance exists between the first even-numbered electrode layer and a plane where the third surface of the substrate is located, and the fourth preset distance is smaller than the first preset distance.

13. The method for manufacturing a multi-layer silicon capacitor structure according to claim 12, It is characterized in that The third preset distance is equal to the fourth preset distance; and / or, The third preset distance is 0; and / or, The fourth preset distance is 0.

14. The method for manufacturing a multi-layer silicon capacitor structure according to claim 10, It is characterized in that Forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer comprises: Etching the first odd-numbered dielectric layer to form a first groove structure in the first odd-numbered dielectric layer; forming a first odd-numbered electrode layer in the first groove structure; or, forming a metal electrode layer on the first odd-numbered dielectric layer; and patterning the metal electrode layer to form a first odd-numbered electrode layer; and / or, Forming a first even-numbered electrode layer on the first even-numbered dielectric layer comprises: Etching the first even-numbered dielectric layer to form a second groove structure in the first even-numbered dielectric layer; forming a first even-numbered electrode layer in the second groove structure; or, A metal electrode layer is formed on the first even-numbered dielectric layer; and the metal electrode layer is patterned to form a first even-numbered electrode layer.

15. The method for manufacturing a multi-layer silicon capacitor structure according to claim 10, It is characterized in that Before the step of forming the surface passivation layer, the method further comprises: forming a second odd-numbered dielectric layer on the first even-numbered electrode layer and the first even-numbered dielectric layer; A second odd-numbered electrode layer is formed on the second odd-numbered dielectric layer, wherein the second odd-numbered electrode layer has a first preset distance from a plane where the third surface of the substrate is located, and the second odd-numbered electrode layer has a third preset distance from a plane where the fourth surface of the substrate is located.

16. The method for manufacturing a multi-layer silicon capacitor structure according to claim 15, It is characterized in that Forming a second odd-numbered electrode layer on the second odd-numbered dielectric layer, comprising: Etching the second odd-numbered dielectric layer to form a third groove structure in the second odd-numbered dielectric layer; forming a second odd-numbered electrode layer in the third groove structure; or, A metal electrode layer is formed on the second odd-numbered dielectric layer; and the metal electrode layer is patterned to form a second odd-numbered electrode layer.

17. A multilayer silicon capacitor structure, It is characterized in that include: a substrate having a first surface, and a third surface and a fourth surface connected to the first surface and disposed opposite to each other; an electrode layer group disposed on the first surface of the substrate, the electrode layer group comprising odd-numbered electrode layers and even-numbered electrode layers alternately disposed, the odd-numbered electrode layers having a first preset distance from a plane where the third surface of the substrate is located, and the even-numbered electrode layers having a second preset distance from a plane where the fourth surface of the substrate is located; a dielectric layer, disposed between the electrode layer group and the substrate, between the odd-numbered electrode layers and the even-numbered electrode layers, and in a space formed by the first preset distance and the second preset distance; A passivation layer is formed on the surface of the electrode layer group.

18. The multi-layer silicon capacitor structure according to claim 17, It is characterized in that The first preset distance is equal to the second preset distance.

19. The multilayer silicon capacitor structure according to claim 17, It is characterized in that A third preset distance exists between the odd-numbered electrode layer and a plane where the fourth surface of the substrate is located, and the third preset distance is smaller than the second preset distance.

20. The multilayer silicon capacitor structure according to claim 19, It is characterized in that A fourth preset distance exists between the even-numbered electrode layer and the plane where the third surface of the substrate is located, and the fourth preset distance is smaller than the first preset distance.

21. The method for manufacturing a multi-layer silicon capacitor structure according to claim 20, It is characterized in that The third preset distance is equal to the fourth preset distance; and / or, The third preset distance is 0; and / or, The fourth preset distance is 0.

22. A method for manufacturing a multilayer silicon capacitor structure, It is characterized in that include: Providing a substrate having a first surface and a second surface disposed opposite to each other, and a third surface and a fourth surface connected to the first surface and the second surface and disposed opposite to each other; forming a first odd-numbered dielectric layer on the first surface, the second surface, and the fourth surface of the substrate; forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer on the first surface of the substrate, wherein the first odd-numbered electrode layer has a first preset distance from a plane where the third surface of the substrate is located, the first preset distance is a constant greater than zero, and the first odd-numbered electrode layer is exposed to a plane where the outer side of the first odd-numbered dielectric layer is located on the fourth surface of the substrate; forming a first even-numbered dielectric layer on the first odd-numbered electrode layer and the first odd-numbered dielectric layer on the first surface of the substrate; forming a first even-numbered electrode layer on the first even-numbered dielectric layer, wherein the first even-numbered electrode layer is exposed to the plane where the third surface of the substrate is located, and a second preset distance is formed between the first even-numbered electrode layer and the plane where the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate is located, and the second preset distance is equal to the first preset distance; forming a second odd-numbered dielectric layer on the first even-numbered electrode layer and the first even-numbered dielectric layer; forming a second odd-numbered electrode layer on the second odd-numbered dielectric layer, wherein the second odd-numbered electrode layer has a first preset distance from a plane where the third surface of the substrate is located, and the second odd-numbered electrode layer is exposed to a plane where the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate is located; Forming a surface passivation layer; preparing a first end electrode on one side of the third surface of the substrate, so that the first end electrode is connected to the first even-numbered electrode layer and the exposed end of the substrate; A second end electrode is prepared on the outer side of the first odd-numbered dielectric layer on the fourth surface of the substrate, so that the second end electrode is connected to the exposed ends of the first odd-numbered electrode layer and the second odd-numbered electrode layer.

23. A multilayer silicon capacitor structure, It is characterized in that include: A substrate having a first surface and a second surface disposed opposite to each other, and a third surface and a fourth surface connected to the first surface and the second surface and disposed opposite to each other; An electrode layer group is disposed on the first surface of the substrate, wherein the electrode layer group comprises odd-numbered electrode layers and even-numbered electrode layers that are alternately disposed; A dielectric layer, disposed on the first surface, the second surface and the fourth surface of the substrate and filled between the odd-numbered electrode layers and the even-numbered electrode layers; The odd-numbered electrode layers are at a first preset distance from the plane where the third surface of the substrate is located, the odd-numbered electrode layers are exposed to the plane where the outer side of the dielectric layer on the fourth surface of the substrate is located, the even-numbered electrode layers are exposed to the plane where the third surface of the substrate is located, and the even-numbered electrode layers are at a second preset distance from the plane where the outer side of the dielectric layer on the fourth surface of the substrate is located; A passivation layer formed on the surface of the electrode layer group; A first end electrode is formed on the third surface of the substrate, the first end electrode is arranged in contact with the even-numbered electrode layer and the exposed end of the substrate; The second end electrode is formed on the outer side of the dielectric layer on the fourth surface of the substrate, and the second end electrode is arranged in contact with the exposed end of the odd-numbered electrode layer.

24. A method for manufacturing a multilayer silicon capacitor structure, It is characterized in that include: Providing a substrate having a first surface and a third surface and a fourth surface connected to the first surface and disposed opposite to each other; forming a first odd-numbered dielectric layer on the first surface of the substrate; forming a first odd-numbered electrode layer on the first odd-numbered dielectric layer, wherein the first odd-numbered electrode layer has a first preset distance from a plane where the third surface of the substrate is located, and the first odd-numbered electrode layer has a third preset distance from a plane where the fourth surface of the substrate is located, and the first preset distance is greater than the third preset distance; forming a first even-numbered dielectric layer on the first odd-numbered electrode layer and the first odd-numbered dielectric layer; A first even-numbered electrode layer is formed on the first even-numbered dielectric layer, wherein the first even-numbered electrode layer and the plane where the fourth surface of the substrate is located have a second preset distance greater than the third preset distance, and the first even-numbered electrode layer and the plane where the third surface of the substrate is located have a fourth preset distance less than the first preset distance, the first preset distance and the second preset distance are equal, the first preset distance and the second preset distance are constants greater than zero, and the third preset distance and the fourth preset distance are equal; forming a second odd-numbered dielectric layer on the first even-numbered electrode layer and the first even-numbered dielectric layer; forming a second odd-numbered electrode layer on the second odd-numbered dielectric layer, wherein the second odd-numbered electrode layer has a first preset distance from a plane where the third surface of the substrate is located, and the second odd-numbered electrode layer has a third preset distance from a plane where the fourth surface of the substrate is located; Forming a surface passivation layer; A via hole is formed by etching in the area to which the first preset distance belongs, which passes through the first even-numbered electrode layer, exposes the substrate and has a diameter or side length smaller than the first preset distance, and a conductive material is filled in the via hole to form a first extraction electrode, wherein the first extraction electrode is connected to the first even-numbered electrode layer and the substrate; A via hole is formed by etching in the area to which the second preset distance belongs, which passes through the second odd-numbered electrode layer, exposes the first odd-numbered electrode layer and has a diameter or side length smaller than the second preset distance, and a conductive material is filled in the via hole to form a second lead-out electrode, and the second lead-out electrode is connected to the first odd-numbered electrode layer and the second odd-numbered electrode layer.

25. A multilayer silicon capacitor structure, It is characterized in that include: a substrate having a first surface, and a third surface and a fourth surface connected to the first surface and disposed opposite to each other; an electrode layer group, arranged on the first surface of the substrate, the electrode layer group comprising odd-numbered electrode layers and even-numbered electrode layers arranged alternately, the odd-numbered electrode layers having a first preset distance from a plane where the third surface of the substrate is located, the odd-numbered electrode layers having a third preset distance from a plane where the fourth surface of the substrate is located, the even-numbered electrode layers having a second preset distance from a plane where the fourth surface of the substrate is located that is greater than the third preset distance, and the even-numbered electrode layers having a fourth preset distance from a plane where the third surface of the substrate is located that is less than the first preset distance; a dielectric layer, disposed between the electrode layer group and the substrate, between the odd-numbered electrode layers and the even-numbered electrode layers, and in a space formed by the first preset distance, the third preset distance, the fourth preset distance, and the second preset distance; A passivation layer formed on the surface of the electrode layer group; A first extraction electrode is formed in the area to which the first preset distance belongs and is in contact with the even-numbered electrode layer and the substrate; The second extraction electrode is formed in the area to which the second preset distance belongs and contacts the odd-numbered electrode layer.

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