Method and apparatus for information and data transmission

Abstract

Methods, apparatus, and systems related to rate matching scheme design for polarization coding, PAC coding, or other pre-transformed polarization coding are disclosed. In one example aspect, a method for digital communication includes determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, where the output bit sequence is determined by performing a polarization transform having H components and a pre-transform; wherein the polarization transformation is based on H polarization matrixes # imgabs0 #, E, K and H are integers greater than 1, and the size of the polarization matrix # imgabs1 # is Ni. The method further includes transmitting, by the first node to a second node, a signal including the output bit sequence.

Description

Technical Field

[0001] The present patent application is generally directed to channel coding techniques in communication systems. Background Art

[0002] Mobile communication technology is driving the world towards an increasingly connected and networked society. Compared with existing wireless networks, next-generation systems and communication technologies will need to support a wider range of use case characteristics and provide more complex and sophisticated access requirements and flexibility.

[0003] Long Term Evolution (LTE) is a wireless communication standard for mobile devices and data terminals developed by the Third Generation Partnership Project (3GPP). LTE Evolution (LTE-A) is a wireless communication standard that enhances the LTE standard. The fifth-generation wireless system, known as 5G, advances the LTE and LTE-A wireless standards and is committed to supporting higher data rates, a large number of connections, ultra-low latency, high reliability, and other emerging business requirements. Summary of the invention

[0004] Among other things, the present patent application discloses techniques for rate matching design for polar coding, PAC coding, and / or other pre-transformed polar coding schemes.

[0005] In one example aspect, a first digital communication method is disclosed. The method includes: determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined by performing a polarization transformation and a pre-transformation having H components; wherein the polarization transformation is based on H polarization matrices Among them, E, K, H are integers greater than 1, and the polarization matrix The size is N i ; and, sending a signal including an output bit sequence by the first node to the second node.

[0006] In another example aspect, another method of wireless communication is disclosed. The method includes: receiving, by a second node, a signal including an output bit sequence having E bits from a first node; and determining, by the second node, an input bit sequence having K bits based on the signal, wherein the output bit sequence is determined by performing a polarization transformation and a pre-transformation having H components; wherein the polarization transformation is based on H polarization matrices Among them, E, K, H are integers greater than 1, and the polarization matrix The size is N i .

[0007] In another example aspect, a wireless communication device is disclosed, the wireless communication device comprising a process configured or operable to perform the above method.

[0008] In another exemplary aspect, a computer-readable storage medium is disclosed. The computer-readable storage medium stores codes, which, when executed by a processor, cause the processor to implement the above method. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Provides the polarization matrix G (32) An example diagram of a factor graph of .

[0010] Figure 2A An exemplary diagram of polar coding with rate matching in the 3GPP 5G standard is provided.

[0011] Figure 2B An exemplary diagram of PAC encoding is provided.

[0012] Figure 3 It shows that the convolution vector g = [g0, g1, ..., g m ] or convolution polynomial g(D) = g0+g1·D+...+g m-1 ·D m-1 +g m ·D m An exemplary block diagram of the convolution transform performed.

[0013] FIG. 4A to FIG. 4C An example of polar coding after rate matching pre-transformation is shown.

[0014] Figure 5 An exemplary block diagram of a pre-transform defined by a recursive feedback polynomial is shown.

[0015] Figure 6 An exemplary block diagram of a pre-transform defined by both a generator polynomial and a recursive feedback polynomial is shown.

[0016] Figure 7 An exemplary block diagram of a hardware platform that may be part of a network device or a communication device is shown.

[0017] Figure 8 An example of network communication including a base station (BS) and a user equipment (UE) based on some embodiments of the disclosed technology is shown.

[0018] Fig. 9 is a flowchart representation of a method for digital communications in accordance with one or more embodiments of the present technology.

[0019] Fig.10 is a flowchart representation of another method for digital communications in accordance with one or more embodiments of the present technology. DETAILED DESCRIPTION

[0020] The titles of the following sections are used to facilitate understanding of the disclosed subject matter and do not limit the scope of the claimed subject matter in any way. Therefore, one or more features of one section may be combined with one or more features of another section. In addition, for clarity of explanation, 5G terminology is used, but the technology disclosed in this application is not limited to 5G technology and can be used in wireless systems implementing other protocols.

[0021] The present application proposes a method and an apparatus related to a rate matching scheme for pre-transformed polarization coding in a wireless communication system.

[0022] In the fifth generation (5G) mobile communication standard of the 3rd Generation Partnership Project (3GPP), low-density parity-check (LDPC) codes are used for data transmission. However, LDPC codes are inferior to polar codes in terms of short payload size, also known as transport block size (TBS). In addition, LDPC codes have a high error floor (block error rate (BLER) of 0.0001). In order to meet the future ultra-reliable low-latency communication (URLLC), we must design more powerful channel codes.

[0023] Polarization adjusted convolutional (PAC) codes can achieve finite length boundaries with moderate decoding complexity. PAC codes are a revolution of polar codes. Therefore, PAC codes have a power of 2 (N = 2 n , where n is a positive integer) as a polar code. However, in order to effectively transmit the payload (or transport block (TB)) in different wireless channel environments, it is not always necessary to have N=2 in the time and frequency resources allocated by the base station (BS). n Therefore, the application of PAC code in wireless communication requires a rate matching scheme. In this application, a method and apparatus for rate matching design with good performance for polar code, PAC coding or other pre-transformed polar code are proposed.

[0024] Introduction

[0025] Notes

[0026] GF(2) represents a Galois field of size 2 having two elements "0" and "1".

[0027] br(i) is the bit reversal function.

[0028] floor(x) represents the largest integer not greater than x.

[0029] ceil(x) represents the smallest integer not less than x.

[0030] round(x) is a rounding function that makes round(x) the integer closest to x, for example, round(3.2)=3, round(4.8)=5, round(2.5)=3, round(-1.9)=-2, round(-3.4)=-3.

[0031] max(x,y) represents the maximum value between x and y, that is

[0032] mod(x,y) represents the remainder when x is divided by y. For example, mod(5,3)=2, and mod(3,5)=3.

[0033] X i,j represents the element in the i-th row and j-th column of the matrix X, where bold uppercase letters are used to represent matrices.

[0034] [x0,x1,...,x Y-1 ] represents a list of length Y containing elements x0, x1, ..., x Y-1 A bold lowercase letter x is used to denote a sequence (or vector) [x0, x1, …, x Y-1 ].

[0035] {x0,x1,...,x Y-1} means there are Y different elements x0, x1, ..., x Y-1 The set of x, that is, for any i≠j, i ≠x j .

[0036] <x0,x1,...,x Y-1 > represents a number of Y different elements x0, x1, ..., x Y-1 An ordered set, that is, for any i≠j, x i ≠x j . Let X = <x0,x1,...,x Y-1 >, X(i) represents the i-th element x in the ordered set X i .

[0037] For a set X, |X| represents the set size, that is, the number of elements in set X.

[0038] Z N ={0,1,...,N-2,N-1} represents the set of integers containing all non-negative integers less than N.

[0039] Indexing of sequences, vectors, or matrices starts at zero.

[0040] Introduction to Polarization Matrix

[0041] This section introduces some concepts using polarization matrices according to various embodiments.

[0042] We denote G (N) as a polarization transformation matrix (or simply polarization matrix) with N rows and N columns, where N is a power of 2, i.e., N = 2 n , and n is a positive integer. n is called the order of the polarization matrix of G (N) , and N is called the size of the polarization matrix of G (N) , i.e., the size of G (N) is N.

[0043] G (N) can be one of the following:

[0044] 1)

[0045] 2)

[0046] 3) G (N) = P (N) ;

[0047] 4) G (N) = B (N) ·P (N) ;

[0048] Here, all matrix operations are performed over GF(2). For example, P (1) = [1], is the nth Kronecker power of the matrix P (2) , and B (N) is the bit-reversal permutation matrix with N rows and N columns, 0 is the all-zero matrix with N / 2 rows and N / 2 columns.

[0049] Let be the element in the i-th row and j-th column of the bit-reversal permutation matrix B (N) . Then, for 0 ≤ i < N and 0 ≤ j < N, where br(i) is the bit-reversal function, defined as and [b n-1 , b n-2 , …, b1, b0] is the n-bit binary expansion of the integer i, i.e.,

[0050] The multiplication of a sequence (or vector) x of length N over GF(2) with the polarization matrix G (N) is called the polarization transformation of the sequence (vector) x. Denoted as y = x·G(N) , where the vector matrix multiplication is performed over GF(2). Then, y is the polarization transform of x.

[0051] Figure 1 shows the polarization matrix G of size N = 32 (32) of the factor graph, and the matrix G (32) is as follows:

[0052]

[0053] Polarization matrix G (32)

[0054] Introduction to 3GPP 5G Polarization Coding

[0055] Some example embodiments using polarization coding according to the 3GPP 5G standard are disclosed in this section.

[0056] In the 3GPP 5G standard, polarization codes are used for control channel transmission. The graph of 5G polarization coding and rate matching is as Figure 2A shown.

[0057] Let Q be a set of data bit indices of size K, i.e., |Q| = K, where Q is a subset of the set of integers Z N = {0, 1, …, N - 2, N - 1} that contains all non-negative integers less than N. Then, for 5G polarization coding through the polarization matrix G (N) , encoding the input bit sequence c = [c0, c1, …, c K-2 , c K-1 into the output bit sequence e = [e0, e1, …, e E-2 , e E-1 includes the following operations, where K is the length of the input bit sequence, E is the length of the output bit sequence, K and E are positive integers, K < N and K < E.

[0058] As Figure 2A shown, there are 3 main steps involved in this process: adding frozen bits, polarization transform, and rate matching. The rate matching step also includes sub-block interleaving and bit selection.

[0059] (1) Adding frozen bits: The operation of adding frozen bits combines N - K zero bits with the input bit sequence c to form a polarization transform input sequence u = [u0, u1, …, u N-2 , u N-1 of length N according to the data bit index set Q.

[0060] The polarization transform input sequence u is determined by the input bit sequence c, the data bit index set Q, and the polarization matrix size N as follows:

[0061]

[0062] (2) Polarization transformation: Polarization transformation is to transform the bit sequence of the first length N into the polarization matrix G on GF(2) (N) Multiply by , and convert the bit sequence of the first length N into a bit sequence of the second length N. The polarization conversion output bit sequence of length N is d = [d0, d1, ..., d N-2 ,d N-1 ] is composed of the polarization transformation input sequence u and the polarization matrix G (N) Determined as d = u·G (N) , where the vector-matrix multiplication is performed over GF(2).

[0063] (3) Rate matching: The rate matching of polarization coding in 5G includes two operations: sub-block interleaving and bit selection.

[0064] (3.1) Sub-block interleaving: The interleaved output bit sequence of length N is d' = [d'0, d'1, ..., d' N-2 ,d' N-1 ] is determined by the sub-block interleaving pattern π of length 32, the polarization transformation output bit sequence d and the polarization matrix size N as follows.

[0065]

[0066]

[0067] Among them, π=[π0,π1,π2,π3,π4,π5,π6,π7,π8,π9,π 10 ,π 11 ,π 12 ,π 13 ,π 14 ,π 15 ,π 16 ,π 17 ,π 18 ,π 19 ,π 20 ,π 21 ,π 22 ,π 23 ,π 24 ,π 25 ,π 26 ,π 27 ,π 28 ,π 29 ,π 30 ,π 31= [0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31], and J = [J0, J1, …, J N-2 , J N-1 is an interleaving pattern of length N determined by the sub-block interleaving pattern π and the polarization matrix size N. The interleaving pattern J is a permutation of the integer sequence [0, 1, 2, ..., N - 2, N - 1].

[0068] (3.2) Bit Selection: There are three types of bit selection: repetition, puncturing, and truncation. According to the interleaved output bit sequence d', the length K of the input bit sequence, the length E of the output bit sequence, and the polarization matrix size N, the output bit sequence e is determined as follows:

[0069] · Repetition: For E ≥ N, e k = d' mod(k,N) , k = 0, 1, 2, …, E - 2, E - 1.

[0070] · Puncturing: For E < N and K / E ≤ 7 / 16, e k = d' N-E+k , k = 0, 1, 2, …, E - 2, E - 1.

[0071] · Truncation: For E < N and K / E > 7 / 16, e k = d' k , k = 0, 1, 2, …, E - 2, E - 1.

[0072] Polarization Adjusted Convolutional (PAC) Coding

[0073] Some exemplary embodiments of PAC coding are disclosed in this section.

[0074] PAC codes are a class of pre-transformed polar codes. Specifically, PAC codes are polar codes using convolutional transforms.

[0075] The schematic diagram of PAC coding is as Figure 2B shown. Denote Q as the set of data bit indices of size K, i.e., |Q| = K, where Q is a subset of the set of integers Z N = {0, 1, …, N - 2, N - 1} that contains all non-negative integers less than N. Then, through the polarization matrix G (N) encode the input bit sequence c = [c0, c1, …, c K-2 , c K-1 into the output bit sequence e = [e0, e1, …, e E-2 , e E-1It includes the following operations, where K is the length of the input bit sequence, E is the length of the output bit sequence, K < N, K < E, and both K and E are positive integers.

[0076] Figure 3 Disclosed is a schematic diagram of a convolutional transform using a convolutional vector g = [g0, g1,..., g m or a convolutional polynomial g(D) = g0 + g1·D +... + g m-1 ·D m-1 +g m ·D m on GF(2).

[0077] (1) Rate configuration: The rate configuration is the same operation as the operation of adding frozen bits in 5G polar coding. Therefore, in this application, the two terms "adding frozen bits" and "rate configuration" can be used interchangeably to refer to the same operation. The rate configuration operation combines N - K zero bits with the input bit sequence c to form a rate configuration output sequence v = [v0, v1,..., v N-2 , v N-1 of length N according to the data bit index set Q. Specifically, the rate configuration output bit sequence v is determined by the input bit sequence c, the data bit index set Q, and the polarization matrix size N as follows.

[0078]

[0079] (2) Convolutional transform: The convolutional transform is an operation that performs convolution on a convolutional input bit sequence of length N and a generator bit sequence g = [g0, g1,..., g m-1 ·D m-1 +g m ·D m of length -(m + 1) that defines the generator polynomial g(D) = g0 + g1·D +... + g m-1 , g m on GF(2) to convert the convolutional input bit sequence of length N into a convolutional output bit sequence of length N, where m is the memory length of the convolutional transform, or equivalently, the order of the generator polynomial of the generator polynomial g(D), and D is a dummy variable representing delay in a digital circuit.

[0080] Figure 3 shows a convolutional transform with a generator polynomial g(D). Specifically, the convolutional transform output bit sequence u = [u0, u1,..., u N-2 , u N-1 of length N is determined by the rate configuration output bit sequence v, the generator polynomial g(D) (or equivalently, the generator bit sequence g), and the polarization matrix size N as follows, where for i < k, vi-k = 0.

[0081]

[0082] Polarization transformation: The polarization transformation is the same as the polarization transformation in 5G polarization coding. The output bit sequence d = [d0, d1, …, d N-2 , d N-1 of length N is determined from the output bit sequence u of the convolutional transformation and the polarization matrix G (N) as d = u · G (N) , where the vector-matrix multiplication is performed over GF(2).

[0083] Example Introduction

[0084] This section discloses multiple examples related to rate matching for polarization coding, PAC coding, or other pre-transformed polarization codings with good performance.

[0085] FIG. 4 shows schematic diagrams of three example rate matching methods. Details of the examples will be explained in the following embodiments.

[0086] Example 1

[0087] This section discloses a coding method used in a wireless communication system.

[0088] In one example, a digital communication method includes: obtaining, by a first node, an input bit sequence c = [c0, c1, ..., c K-1 ; and determining, by the first node, an output bit sequence of E bits based on the input bit sequence of K bits, where the output bit sequence is determined by performing a polarization transformation and a pre-transformation having H components; where the polarization transformation is based on H polarization matrices and, sending, by the first node, a signal including the output bit sequence e to a second node.

[0089] Here, K is the input length of the input bit sequence c.

[0090] E is the output length of the output bit sequence e.

[0091] H is the number of component polarization matrices.

[0092] K, E, and H are all positive integers. In one example, K, E, and H satisfy K < E and H < E.

[0093] H is an integer greater than 1.

[0094] For h = 0, 1, ..., H - 1, the h-th component polarization transformation is based on the h-th component polarization matrix Among them, N h is the size of the h-th component polarization matrix, and is a power of 2, where n h is a non-negative integer.

[0095] In one example, the sum of the sizes of the H component polarization matrices is equal to the output length E, i.e., N0 + N1 +... + N H-1 = E.

[0096] In another example, a method of digital communication may include: obtaining an input bit sequence c = [c0, c1,..., c K-1 by a first node; and determining an output bit sequence e = [e0, e1,..., e E-1 by the first node by performing at least one of the following: repetition, H component rate configuration, first concatenation, pre-transformation, segmentation, H component polarization transformation based on H polarization matrices ; W component interleaving, second concatenation; and transmitting, by the first node, a signal including the output bit sequence e to a second node.

[0097] Here, K is the input length of the input bit sequence c; E is the output length of the output bit sequence e; H is the number of component polarization matrices; and W is the number of component interleavings.

[0098] In one example, K, E, and H are positive integers, and W is an integer not greater than H.

[0099] In another example, K, E, and H satisfy K < E and H < E.

[0100] H is an integer greater than 1.

[0101] For h = 0, 1,..., H - 1, the h-th component polarization transformation is based on the h-th component polarization matrix where N h is the size of the h-th component polarization matrix, and is a power of 2, where n h is a non-negative integer.

[0102] The sum of the sizes of the H component polarization matrices is equal to the output length E, i.e., N0 + N1 +... + N H-1 = E.

[0103] Example 2

[0104] This section discloses a decoding method used in a wireless communication system.

[0105] A digital communication method includes: receiving, by a second node, a signal including an output bit sequence e = [e0, e1,..., e E-1 sent by a first node; and determining, by the second node, an estimate of an input bit sequence c = [c0, c1,..., c K-1 .

[0106] In one example, the output bit sequence e can be determined by performing a polarization transform and a pre-transform having H components; wherein the polarization transform is based on H polarization matrices where E, K, and H are integers greater than 1, and the polarization matrix has a size of N i .

[0107] In one example, the output bit sequence e can be determined by the first node by at least one of the following: repetition, H-component rate configuration, first concatenation, pre-transform, segmentation, H-component polarization transform based on H polarization matrices , W-component interleaving, second concatenation.

[0108] Here, K is the input length of the input bit sequence c; E is the output length of the output bit sequence e; H is the number of component polarization matrices; W is the number of component interleavings; K, E, and H are positive integers; K < E and H < E; H is an integer greater than 1; W is an integer not greater than H; for h = 0, 1,..., H - 1, the h-th component polarization transform is based on the h-th component polarization matrix where N h is the size of the h-th component polarization matrix, and is a power of 2, where n h is a non-negative integer; the sum of the sizes of the H component polarization matrices is equal to the output length E, i.e., N0 + N1 +... + N H-1 = E.

[0109] Example 3

[0110] This section discloses parameters related to determining the output bit sequence e.

[0111] Example 3 is based on the above example.

[0112] The output bit sequence e is determined by the first node by at least one of the following:[[]]

[0113] The input bit sequence length K,

[0114] The output bit sequence length E,

[0115] The sizes N0, N1,..., N of the H component polarization matrices H-1 ,

[0116] H components have repetition lengths K0, K1, ..., K H-1 ,

[0117] H components repeated index set R (0) ,R (1) ,...,R (H-1) ,

[0118] The first data bit index set Q={Q0,Q1,...,Q K-1},

[0119] H component data bit index set Q (0) ,Q (1) ,...,Q (H-1) ,

[0120] Generator polynomial g(D)=g0+g1·D+g2·D on GF(2) 2 +...+g m ·D m ,

[0121] Recursive feedback polynomial q(D)=q0+q1·D+q2·D on GF(2) 2 +...+q m D,

[0122] H component polarization matrices

[0123] W component interleaving patterns J (0) ,J (1) ,...,J (W-1) ,

[0124] Where K is the input sequence length; E is the output sequence length; H is the number of component polarization matrices; m is the memory length or the degree of the generator polynomial g(D) or the degree of the recursive feedback polynomial q(D); W is the number of component interleaving patterns, and W is a non-negative integer not greater than H; for h = 0, 1, ..., H-1, the hth component repetition length K h is a positive integer and the hth component repetition length is K h Smaller than the size N of the polarization matrix of the hth component h .

[0125] H component polarization matrices of size N0,N1,...,N H-1

[0126] For h = 0, 1, ..., H-1, the component polarization matrix size N h is the hth component polarization matrix The size of the polarization matrix.

[0127] In some embodiments, all H component polarization matrices have sizes N0, N1, ..., N H-1 are the same, that is, N0=N1=...=N H-1 For an output length E=24, a specific example with H=3 polarization matrix sizes is N0=N1=N2=8.

[0128] In some embodiments, not all H component polarization matrices have sizes N0, N1, ..., N H-1 are the same, that is, there exists h≠k such that N h ≠N k A specific example of H=3 polarization matrix sizes for an output length E=24 is N0=16, N1=4 and N2=4, where N0≠N1.

[0129] In some embodiments, all H component polarization matrices have sizes N0, N1, ..., N H-1 are all different, that is, if h≠K, N h ≠N k .. A first specific example of H=2 polarization matrix sizes for an output length E=24 is N0=16 and N1=8, where N0≠N1. A second specific example of H=3 polarization matrix sizes for an output length E=26 is N0=16, N1=8, and N2=2, where N0≠N1, N0≠N2, and N1≠N2.

[0130] H components have repetition lengths K0, K1, ..., K H-1

[0131] In some embodiments, the H components have repetition lengths K0, K1, ..., K H-1 At least one of is equal to the input length K. In the first specific example of H=3 polarization matrix sizes and K=6, there are K0=6, K1=3 and K2=1, where K0=K=6. In the second specific example of H=3 polarization matrix sizes and K=6, there are K0=6, K1=6 and K2=1, where K0=K1=K=6.

[0132] In some embodiments, all H components have repetition lengths K0, K1, ..., K H-1 are the same, that is, K0=K1=…=K H-1 In the specific example of H=3 polarization matrix sizes, K0=K1=K2=2 exists.

[0133] In some embodiments, not all H components have the same length K0, K1, ..., K H-1 are the same, that is, there exists h≠k such that K h ≠K kIn a specific example of H=3 polarization matrix sizes, there are K0=6, K1=2 and K2=2, where K0≠K1.

[0134] In some embodiments, all H components have repetition lengths K0, K1, ..., K H-1 are all different, that is, if h≠k, K h ≠K k In a specific example of H=3 polarization matrix sizes, there are K0=6, K1=3, and K2=1, where K0≠K1, K0≠K2, and K1≠K2.

[0135] Component repeat index set R (0) ,R (1) ,...,R (H - 1)

[0136] For h = 0, 1, ..., H-1, the hth component repeats the set With K h elements, that is, the size of the h-th component repetition set is |R (h) |=K h , where K h is the hth component repetition length. For h=0,1,...,H-1, the hth component repetition index set is the set Z of integers of the first type K = a subset of {0, 1, ..., K-2, K-1}, where the first type integer set Z K ={0,1,...,K-2,K-1} includes all non-negative integers less than K.

[0137] In some embodiments, the H component repetition index set R (0) ,R (1) ,...,R (H-1) At least one of them is equal to the first type integer set Z K ={0,1,2,...,K-1}, where the first type integer set Z K = {0, 1, 2, ..., K-1} includes all non-negative integers less than K. In the specific example where K = 6, E = 24, and H = 2 polarization matrices of size N0 = 16 and N1 = 8, the H = 2 component repetition index set R (0) and R (1) R (0) = Z6 = {0, 1, 2, 3, 4, 5} (where K0 = K = 6) and R (1) ={0,1,2}(where K1=3).

[0138] In some embodiments, the H component repetition index set R (0) ,R(1) ,...,R (H-1) There is no set Z that is equal to the first type integer set K ={0,1,2,...,K-1}, where the first type integer set Z K ={0,1,2,...,K-1} includes all non-negative integers less than K.

[0139] In the specific example where K=6, E=24 and H=3 polarization matrix sizes are N0=16, N1=4 and N2=4, the H=3 component repetition index sets are R (0) ={0,1,2,3,4}(where K0=5), R (1) = {5,0} (where K1 = 2) and R (2) ={1,2}(where K2=2), where R (0) ≠Z6, R (1) ≠Z6, and R (2) ≠Z6, where Z 6＝ {0,1,2,3,4,5}.

[0140] In some embodiments, for h=0, 1, ..., H-2, the (h+1)th component repeats the index set R (h+1) is the hth component repetition index set A subset of In the specific example where K=6, E=24 and H=3 polarization matrix sizes are N0=8, N1=8 and N2=8, H=3 component repetition index sets R (0) , R (1) , R (2) R (0) = Z6 = {0, 1, 2, 3, 4, 5} (where K0 = K = 6), R (1) = {0,2,1} (where K1 = 3) and R (2) ={0}(where K2=1), where, and

[0141] In some embodiments, for h, h' being non-negative integers less than H and h not equal to h', the hth component repeats the index set R (h) Repeat the index set R with the h'th component (h') The intersection of is an empty set, that is, R (h) ∩R (h') =Φ={}, where Φ represents an empty set. In the specific example where K=6, E=24, and H=3 polarization matrix sizes are N0=16, N1=4, and N2=4, the H=3 component repetition index sets are R (0)= {0,1} (where K0 = 2), R (1) = {2,3} (where K1 = 2) and R (2) ={4,5}(where K1=2).

[0142] In some embodiments, there exists a non-negative integer where h and k are less than H, and h is not equal to k (h≠k), such that the hth component repeats the index set R (h) and the kth component repeats the index set R (k) The intersection of is not an empty set, that is, R (h) ∩R (k) ≠Φ, where Φ={} is the empty set.

[0143] In the first specific example where K=6, E=24 and H=2 polarization matrices of size N0=16 and N1=8, the H=2 component repetition index set R (0) and R (1) They are R (0) = Z6 = {0, 1, 2, 3, 4, 5} (where K0 = K = 6) and R (1) ={0,1,2}(where K1=3), where R (0) ∩R (1) ={0,1,2}≠{}=Φ; where Φ represents the empty set.

[0144] In the second specific example where K=6, E=24 and H=3 polarization matrix sizes N0=8, N1=8 and N2=8, H=3 component repetition index sets R (0) , R (1) , R (2) They are R (0) = Z6 = {0, 1, 2, 3, 4, 5} (where K0 = K = 6), R (1) = {0, 1, 2} (where K1 = 3) and R (2) = {4} (where K2 = 1), where R (0) ∩R (1) ={0,1,2}≠Φ and R (0) ∩R (2) ={4}≠Φ; where Φ represents the empty set.

[0145] In the third specific example where K=6, E=26 and H=3 polarization matrix sizes N0=8, N1=8 and N2=8, H=3 component repetition index sets R (0) , R (1) , R (2) They are R (0) ={0,1,2,3,4}(where K0=5), R (1) = {0,5} (where K1 = 2) and R(2) ={4} (where K2 = 1), where R (0) ∩R (1) ={0}≠Φ and R (0) ∩R (2) ={4}≠Φ; where Φ represents the empty set.

[0146] In some embodiments, all H component repetition index sets R (0) , R (1) ,..., R (H-1) include the index k, where k is a non - negative integer. A specific example with H = 3 component repetition index sets R (0) , R (1) , R (2) are respectively R (0) ={0, 1, 2, 3, 4} (where K0 = 5), R (1) ={5, 0, 2} (where K1 = 2) and R (2) ={4, 0} (where K2 = 2), where the H = 3 component repetition index sets R (0) , R (1) , R (2) include the index k = 0. Component data bit index set Q (0) ,Q (1) ,...,Q (H-1)

[0147] For h = 0, 1,..., H - 1, the h - th component data bit index set has K h elements, that is, the size of the h - th component data bit index set is |Q (h) | = K h , where K h is the h - th component repetition length. For h = 0, 1,..., H - 1, the h - th component data bit index set is a subset of the h - th set of integers of the second type , where N h is the h - th polarization matrix size, and the h - th set of integers of the second type includes all non - negative integers less than N h . For h = 0, 1,..., H - 1, the elements in the h - th data bit index set Q (h) are non - negative integers less than the polarization matrix size N of the h - th component polarization matrix h .

[0148] In some embodiments, for some h, if k < k', then the k - th element in the h - th component data bit index set Q (h) is less than the k - th element in the h - th component data bit index set Q ​(h) the k'-th element in i.e., the h-th component data bit index set Q (h) According to Q0 < Q1 <... < Q K-2 <Q K-1 the index values are sorted in ascending order. In some embodiments, for some h, if k < k', then the k-th element in the h-th component data bit index set Q (h) is greater than the k'-th element in the h-th component data bit index set Q i.e., the h-th component data bit index set Q (h) the k'-th element in i.e., the h-th component data bit index set Q (h) According to Q0 > Q1 >... > Q K-2 >Q K-1 the index values are sorted in descending order. In some embodiments, for some h, if k < k', then the -th polaron channel corresponding to the h-th component polarization matrix (denoted as ) has a lower reliability than the -th polaron channel corresponding to the h-th component polarization matrix (denoted as ), i.e., the h-th component data bit index set Q (h) is sorted in ascending order according to the polaron channel reliability In some embodiments, for some h, if k < k', then the -th polaron channel corresponding to the h-th component polarization matrix (denoted as ) has a higher reliability than the -th polaron channel corresponding to the h-th component polarization matrix (denoted as ), i.e., the h-th component data bit index set Q (h) is sorted in descending order according to the polaron channel reliability .

[0149] In some embodiments, at least one of the sizes K0, K1,..., K of the H component data bit index sets H-1 is equal to the input length K.

[0150] In the first specific example where K = 6, E = 24, and H = 2 with polarization matrix sizes N0 = 16 and N1 = 8, the H = 2 component data bit index sets Q (0) and Q (1) are Q (0)={12,7,11,13,14,15} (where K0=K=6) and Q (1) = {12,7,11} (where K1 = 3), where the 0th component data bit index set Q (0) ={12,7,11,13,14,15} corresponds to the 0th component polarization matrix And the first component data bit index set Q (1) ={5,6,7} corresponds to the first component polarization matrix

[0151] In the second specific example where K=6, E=24 and H=3 polarization matrix sizes N0=8, N1=8 and N2=8, H=3 component data bit index sets Q (0) , Q (1) , Q (2) Q (0) ={2,4,3,5,6,7}(where K0=K=6), Q (1) = {2, 4, 5} (where K1 = 3) and Q (2) ={3} (where K2=1). In a third specific example where K=6, E=26 and H=3 polarization matrix sizes N0=16, N1=8 and N2=2, the H=3 component repetition index sets Q (0) , Q (1) , Q (2) Q (0) ={7,11,13,14,15}(where K0=5), Q (1) = {6,7} (where K1 = 2) and Q (2) ={1}(where K2=1).

[0152] The first data bit index set Q

[0153] The first data bit index set Q={Q0,Q1,...,Q K-1} has K elements, that is, the size of the input data bit index set is |Q|=K, where K is the input length. The first data bit index set Q={Q0,Q1,…,Q K-1} is a set of integers of the third type A subset of m There are H polarization matrices of size N0,N1,...,N H-1 The maximum value among them, that is, N m =max 0≤h＜H N h , and the set of integers of the third type Includes all values ​​less than N mIn some embodiments, the H component data bit index set Q (0) ,Q (1) ,...,Q (H-1) At least one of them is equal to the first data bit index set Q={Q0,Q1,...,Q K-1}.

[0154] Where K = 6, N m In the first specific example where E=16 and E=24, the first data bit index set is Q={12, 7, 11, 13, 14, 15}.

[0155] In the second specific example where K=6 and H=3 polarization matrix sizes are N0=8, N1=8, and N2=8, we obtain N m = max(max(N0, N1), N2) = 8, data bit index set Q = {2, 4, 3, 5, 6, 7}, and H = 3 component data bit index sets

[0156]

[0157] In the third specific example where K=6 and H=3 polarization matrices of size N0=16, N1=8 and N2=2, we obtain N m =max(max(N0,N1),N2)=16, and data bit index set Q={12,7,11,13,14,15}.

[0158] In some embodiments, for k=0, 1, ..., K-2, the element Q in the first data bit index set Q k Less than Q k+1 , that is, the first data bit index set Q is based on Q0 <Q1<...<Q K-2 K-1 The index values ​​are sorted in ascending order.

[0159] In some embodiments, for k=0, 1, ..., K-2, the Qth k polarization subchannel (denoted as W(Q k )) is less reliable than Q k+1 polarization subchannel (denoted as W(Q k+1 )) reliability, that is, the first data bit index set Q is calculated according to the polarization subchannel reliability according to W(Q0) <W(Q1)<...<W(Q K-2 ) <W(Q K-1 ) in ascending order.

[0160] In which N m ​=8 and K=4, the first data bit index set is {Q0, Q1, Q2, Q3}={3, 5, 6, 7}, where Q0 <Q1<Q2<Q3。

[0161] In which N m =32 and K=25, the first data bit index set is Q={Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q 10 ,Q 11 ,Q 12 ,Q 13 ,Q 14 ,Q 15 ,Q 16 ,Q 17 ,Q 18 ,Q 19 ,Q 20 ,Q 21 ,Q 22 ,Q 23 ,Q 24} = {5,9,6,17,10,18,12,20,24,7,11,19,13,14,21,26,25,22,28,15,23,31,27,29,30}, where the polarimetric channel reliability is W(Q0) <W(Q1)<W(Q2)<W(Q3)<W(Q4)<W(Q5)<W(Q6)<W(Q7)<W(Q8)<W(Q9)<W(Q 10 ) <W(Q 11 ) <W(Q 12 ) <W(Q 13 ) <W(Q 14 ) <W(Q 15 ) <W(Q 16 ) <W(Q 17 ) <W(Q 18 ) <W(Q 19 ) <W(Q 20 ) <W(Q 21 ) <W(Q 22 ) <W(Q 23 ) <W(Q 24 ).

[0162] Generator polynomial g(D)

[0163] Generating polynomial g(D) = g0+g1·D+...+g m ·D m It can be any bivariate polynomial over GF(2), where h is the memory length of the generating polynomial g(D) or the order of the generating polynomial g(D). Generating polynomial g(D) = g0+g1·D+...+gm ·D m The corresponding generated bit sequence g = [g0, g1, ..., g m ]. The generating polynomial g(D) and its corresponding generating bit sequence g are used interchangeably in this application.

[0164] In the first specific example in which the memory length m=6, the generating polynomial g(D)=g0+g1·D+...+g m ·D m =g0+g1·D+g2·D 2 +g3·D 3 +g4·D 4 +g5·D 5 +g6·D 6 =1+D 2 +D 3 +D 5 +D 6 In the second specific example where the memory length m=3, the generating polynomial g(D)=g0+g1·D+...+g m ·D m =g0+g1·D+g2·D 2 +g3·D 3 =1+D+D 3 .

[0165] For the generating polynomial g(D) = g0+g1·D+...+g m ·D m A more specific example is as follows:

[0166] 1. For m = 1, g(D) = g0 + g1·D + ... + g m ·D m =g0+g1·D=1+D;

[0167] 2. For m = 2, g(D) = g0 + g1·D + ... + g m ·D m =g0+g1·D+g2·D 2 =1+D;

[0168] 3. For m = 3, g(D) = g0 + g1·D + ... + g m ·D m =g0+g1·D+g2·D 2 +g3·D 3 =1+D+D 2 +D 3 ;

[0169] 4. For m = 4, g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 + g3·D 3 + g4·D 4 = 1 + D + D 2 + D 4 and g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 + g3·D 3 + g4·D 4 = 1 + D 2 + D 3 + D 4 ;

[0170] 5. For m = 5, g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g5·D 5 = 1 + D + D 3 + D 5 and g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g5·D 5 = 1 + D 2 + D 4 + D 5 ;

[0171] 6. For m = 6, g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g6·D 6 = 1 + D 6 ; 7. For m = 7, g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g7·D 7 = 1 + D 3 + D 5 + D 7 and g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g7·D7 = 1 + D 2 + D 4 + D 7 ;

[0172] 8. For m = 8, g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g8·D 8 = 1 + D 4 + D 8 ;

[0173] 9. For m = 9, g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g9·D 9 = 1 + D 3 + D 4 + D 5 + D 7 + D 9 and g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g9·D 9 = 1 + D 2 + D 4 + D 5 + D 6 + D 9 ;

[0174] 10. For m = 10, g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g 10 ·D 10 = 1 + D 2 + D 6 + D 7 + D 10 and g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g 10 ·D 10 = 1 + D 3 + D 4 + D 8 + D 10 ;

[0175] 11. For m = 11, g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g 11 ·D 11 = 1 + D + D 2 + D 4 + D 8 + D 10 + D 11 and g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g 11 ·D 11 = 1 + D + D 3 + D 7 + D 9 + D 10 + D 11 ;

[0176] 12. For m = 12, g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g 12 ·D 12 = 1 + D 2 + D 5 + D 6 + D 7 + D 8 + D 9 + D 10 + D 11 + D 12 and g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g 12 ·D 12 = 1 + D + D 2 + D 3 + D 4 + D 5 + D 6 + D 7 + D 10 + D 12 ; 13. For m = 13, g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g13 ·D 13 = 1 + D + D 4 + D 5 + D 9 + D 10 + D 13 and g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g 13 ·D 13 = 1 + D 3 + D 4 + D 8 + D 9 + D 12 + D 13 ;

[0177] 14. For m = 14, g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g 14 ·D 14 = 1 + D + D 2 + D 7 + D 8 + D 10 + D 12 + D 14 and g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g 14 ·D 14 = 1 + D 2 + D 4 + D 6 + D 7 + D 12 + D 13 + D 14 ;

[0178] 15. For m = 15, g(D) = g0 + g1·D +... + g m ·D m = g0 + g1·D + g2·D 2 +... + g 15 ·D 15 = 1 + D + D 4 + D 6 + D 7 + D 8 + D 9 + D 15and g(D)=g0+g1·D+...+g m ·D m =g0+g1·D+g2·D 2 +...+g 15 ·D 15 =1+D 6 +D 7 +D 8 +D 9 +D 11 +D 14 +D 15 ;

[0179] 16. For m = 16, g(D) = g0 + g1·D + ... + g m ·D m =g0+g1·D+g2·D 2 +...+g 16 ·D 16 =1+D 2 +D 4 +D 6 +D 8 +D 13 +D 14 +D 16 and g(D)=g0+g1·D+...+g m ·D m =g0+g1·D+g2·D 2 +...+g 16 ·D 16 =1+D 2 +D 3 +D 8 +D 10 +D 12 +D 14 +D 16 ;

[0180] Where m is the memory length.

[0181] Recursive feedback polynomial q(D)

[0182] Recursive feedback polynomial q(D) = q0 + q1·D + ... + q m ·D m It can be any bivariate polynomial over GF(2), where m is the memory length of the recursive feedback polynomial q(D) or the order of the recursive feedback polynomial q(D). Recursive feedback polynomial q(D) = q0 + q1·D + ... + q m ·D m The corresponding recursive feedback bit sequence q=[q0,q1,...,q m]. The recursive feedback polynomial q(D) and its corresponding recursive feedback bit sequence q are used interchangeably in this article.

[0183] In some embodiments, the value of q0 is bit one "1" in the recursive feedback polynomial q(D).

[0184] In the first specific example where the memory length m=6, the recursive feedback polynomial is q(D)=q0+q1·D+...+q m ·D m =q0+q1·D+q2·D 2 +q3·D 3 +q4·D 4 +q5·D 5 +q6·D 6 =1+D 2 +D 4 +D 5 +D 6 .

[0185] In the second specific example where the memory length m=3, the recursive feedback polynomial is q(D)=q0+q1·D+...+q m ·D m =q0+q1·D+q2·D 2 +q3·D 3 =1+D 2 +D 3 .

[0186] Component interleaving pattern J (0) ,J (1) ,...,J (W-1)

[0187] For h = 0, 1, ..., W-1, the hth component interleaving pattern The size is N h , where N h is the size of the h-th polarization matrix, and J (h) is the sequence [0,1,2,...,N h -1].

[0188] In the first specific example where H=2, W=2, N0=16, N1=8, the 0th component interleaving pattern

[0189] is a permutation of the array [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15], and the first component is interleaved pattern is a permutation of the array [0,1,2,3,4,5,6,7].

[0190] In the second specific example where H=3, W=2, N0=N1=N2=8, the 0th component interleaving pattern is a permutation of the array [0,1,2,3,4,5,6,7], and the first component is interleaved

[0191] is a permutation of the array [0,1,2,3,4,5,6,7].

[0192] In the third specific example where H=3, W=3, N0=16, N1=8, and N2=2, the 0th component interleaving pattern

[0193] is a permutation of the array [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15], and the first component is interleaved pattern is a permutation of the array [0,1,2,3,4,5,6,7], and the second component is interleaved is a permutation of the array [0,1].

[0194] In the fourth specific example where H=3, W=1, N0=8, N1=16, and N2=2, the second component interleaving pattern is a permutation of the array [0,1].

[0195] Figure 4A A first example of polar coding after rate matching pre-transform with repetition and single pre-transform is shown, with no component interleaving pattern.

[0196] Figure 4B A second example of polar coding after rate matching pre-transformation with repetition and single pre-transformation is shown, where the number of component interleaving patterns is equal to the number of component matrices.

[0197] Figure 4C A third example of polar coding after rate matching pre-transformation with repetition and single pre-transformation is shown, where the number of component interleaving patterns is less than the number of component matrices.

[0198] In some embodiments, the first node obtains an input bit sequence c of length K and determines H components to repeatedly output a bit sequence c. (0) ,c (1) ,c (2) ,...,c (H-1)To perform repetition, where for h = 0, 1, 2, ..., H-1, the hth component repeats the output bit sequence The length is K h .

[0199] In some embodiments, for h=0, 1, 2, ..., H-1, the first node repeatedly outputs the bit sequence by obtaining the hth component And determine the length to be N h The component rate configuration output bit sequence To perform component rate configuration, where N h is the hth component polarization matrix The size of the polarization matrix.

[0200] In some embodiments, the first node configures the output bit sequence v by obtaining H component rates (0) ,v (1) ,v (2) ,...,v (H-1) And determine the cascade output bit sequence y=[y0,y1,y2,...,y E-1 ] to perform the first cascade, where, for h = 0, 1, ..., H-1, the hth component rate configuration outputs the bit sequence The length is N h ; E=N0+N1+...+N H-1 is the output bit sequence e = [e0, e1, e2, ..., e E-1 ], where N h is the hth component polarization matrix The size of the polarization matrix.

[0201] In some embodiments, the first node obtains a concatenated output bit sequence y=[y0, y1, y2, ..., y E-1 ] and determine the pre-transformed output bit sequence u=[u0,u1,u2,...,u E-1 ] to perform pre-transformation: Generator polynomial g(D) = g0+g1·D+g2·D on GF(2) 2 +...+g m ·D m , the recursive feedback polynomial q(D)=q0+q1·D+q2·D on GF(2) 2 +...+q m ·D m , where E is the output bit sequence e = [e0, e1, e2, ..., e E-1 ]'s length.

[0202] In some embodiments, the first node obtains a pre-transformed output bit sequence u=[u0,u1,u2,...,u E-1 ] and according to the H component polarization matrix sizes N0, N1, ..., N H-1 Determine H segment output bit sequences u (0) ,u (1) ,...,u (H-1) to perform segmentation, where H is the number of component polarization matrices; for h = 0, 1, ..., H-1, the hth segment outputs the bit sequence u (h) The length is N h , where N h is the size of the polarization matrix of the hth component, and E is the output bit sequence e = [e0, e1, e2, ..., e E-1 ]'s length.

[0203] In some embodiments, for h=0, 1, 2, ..., H-1, the first node obtains a length of N h The hth segment outputs the bit sequence u (h) And according to the hth component polarization matrix Set the length to N h The hth component of the polarization transformation outputs the bit sequence Determined as to perform component polarization transformation, where is the component polarization transformation, which is the transformation of length N on GF(2). h The hth segment outputs the bit sequence u (h) With the component polarization matrix Perform vector-matrix multiplication to obtain the polarization-transformed output bit sequence of the hth component

[0204] FIG. 4A to FIG. 4C Three examples are shown in FIG.

[0205] In some embodiments, the first node obtains the H components by polarization transformation and outputting the bit sequence d (0) ,d (1) ,d (2) ,...,d (H-1) And determine the output bit sequence of length E = [e0,e1,...,e E-1 ] to perform the second cascade, where Figure 4A A specific example is shown in FIG.

[0206] In some embodiments, the number of interleaving patterns W is equal to the number of component polarization matrices H, and for h=0, 1, 2, ..., H-1, the first node obtains a length of N h The hth component of the polarization transformation outputs the bit sequence And determine the length to be N h The hth component of the interleaved output bit sequence To perform component interleaving, where N h yes In some embodiments, the first node obtains the H component interleaved output bit sequence d' (0) ,d' (1) ,d' (2) ,...,d' (H-1) And determine the output bit sequence of length E = [e0,e1,...,e E-1 ] to perform the second cascade, where Figure 4B A specific example is shown in FIG.

[0207] In some embodiments, the number of interleaving patterns W is less than the number of component polarization matrices H, and for h=0, 1, 2, ..., W-1, the first node obtains a length of N h The hth component of the polarization transformation outputs the bit sequence And determine the length to be N h The hth component of the interleaved output bit sequence To perform component interleaving, where N h yes In some embodiments, the first node obtains the W component interleaved output bit sequence d' (0) ,d' (0) ,d' (1) ,d' (2) ,...,d' (W-1) and HW components polarization conversion output bit sequence d (W) ,d (W+1) ,...,d (H-1) , and then determine the output bit sequence of length E e = [e0, e1, ..., e E-1 ] to perform the second cascade, where Figure 4C A specific example is shown in FIG.

[0208] In some embodiments, the first node performs polarization transformation on the H components and outputs a bit sequence d (0) ,d (1) ,d (2) ,...,d (H-1)Component interleaving is performed on the W bit sequences to determine W component interleaved output bit sequences, where W is a non-negative integer not greater than H. Where H=3 component polarization transformed output bit sequences d (0) d (1) d (2) In the first specific example where W=2, the first node performs polarization transformation on W=2 components and outputs a bit sequence d (0) d (2) Perform component interleaving to determine W = 2 component interleaved output bit sequences d' (0) , d' (2) , where the 0th component interleaved output bit sequence d' (0) Corresponding to the polarization transformation output bit sequence d of the 0th component (0) ; The second component interleaved output bit sequence d' (2) Corresponding to the second component polarization conversion output bit sequence d (2) .

[0209] In which H = 3 components polarization conversion output bit sequence d (0) d (1) d (2) In the second specific example where W=1, the first node performs polarization transformation on W=1 components and outputs a bit sequence d (1) Perform component interleaving to determine W = 1 component interleaved output bit sequence d' (1) , where the first component interleaved output bit sequence d' (1) Corresponding to the polarization transformation output bit sequence d of the first component (1) .

[0210] Example 4

[0211] This section discloses examples involving repetition.

[0212] Embodiment 4 is based on the above embodiment.

[0213] FIG. 4A to FIG. 4C Three specific examples for repetition are shown. In some embodiments, repetition includes: obtaining, by the first node, a repetitive input bit sequence; and determining, by the first node, H component repetitive output bit sequences c by at least one of the following: (0) ,c (1) ,...,c (H-1) :H components have repetition lengths K0, K1, ..., K H-1 , H components repeated index set R (0) ,R (1) ,...,R (H-1) .

[0214] Here, the repeated input bit sequence may be an input bit sequence c=[c0, c1, ..., c K-1 ]; for h = 0, 1, ..., H-1, the hth component repeats the output bit sequence The length is K h .

[0215] In some embodiments, for h=0, 1, ..., H-1, the bit sequence c is repeatedly output by repetition of the hth component (h) The kth bit in Set as input bit sequence c = [c0, c1, ..., c K-1 ] is the index bits (i.e. ), to determine the hth component repeated output bit sequence c (h) , where the pseudo code is as follows.

[0216]

[0217] Where K = 6, input bit sequence c = [c0, c1, c2, c3, c4, c5], H = 2 component repetition index set R (0) = {0, 1, 2, 3, 4, 5} (where K0 = 6) and R (1) ={0,1,2} (where K1=3), the 0th component repeatedly outputs the bit sequence The first component repeats the output bit sequence

[0218] Where K = 6, input bit sequence c = [c0, c1, c2, c3, c4, c5], H = 3 component repetition index set R (0) ={0,1,2,3,4,5}(where K0=6), R (1) = {0,1,2} (where K1 = 3) and R (2) ={4} (where K2=1) in the second specific example, the 0th component repeatedly outputs the bit sequence

[0219] The first component repeats the output bit sequence The second component repeats the output bit sequence Where K = 6, input bit sequence c = [c0, c1, c2, c3, c4, c5], H = 3 component repetition index set R (0) ={0,1,2,4,3}(where K0=5), R (1)= {0,5} (where K1 = 2) and R (2) ={4} (where K2=1), the 0th component repeatedly outputs the bit sequence The first component repeats the output bit sequence The second component repeats the output bit sequence

[0220] In some embodiments, the repetition includes: obtaining, by the first node, an input bit sequence c=[c0, c1, ..., c K-1 ]; and the first node uses a first data bit index set Q = {Q0, Q1, ..., Q K-1} For the input bit sequence c = [c0, c1, ..., c K-1 ] performs rate configuration to obtain a repetitive rate-configured output bit sequence v'=[v'0, v'1, ..., v' N-1 ],as follows

[0221]

[0222]

[0223] The first node determines the H component repeated output bit sequence c by at least one of the following items: (0) ,c (1) ,...,c (H-1) :

[0224] The first data bit index set Q={Q0,Q1,...,Q K-1},

[0225] H components have repetition lengths K0, K1, ..., K H-1 ,

[0226] Where, for h = 0, 1, ..., H-1, the hth component repeats the output bit sequence The length is K h .

[0227] In some embodiments, for h=0, 1, ..., H-1, the bit sequence c is repeatedly output by repetition of the hth component (h) The kth bit in Set to repetition rate configuration output bit sequence v' = [v'0, v'1, ..., v' N-1 ] is indexed by Q k bits (i.e. ), to determine the hth component repeated output bit sequence c (h) , where Q k is the kth element in the first data bit index set Q, and the pseudo code is as follows.

[0228]

[0229]

[0230] Where K = 6, input bit sequence c = [c0, c1, c2, c3, c4, c5], H = 2 polarization matrix size N0 = 16 and N 1＝ 8. In the first specific example of the first data bit index set Q = {12, 7, 11, 13, 14, 15}, K0 = 6, K1 = 3, we get a length of N m = max(N0,N1) = 16 repetition rate configuration output bit sequence v' = [v'0,v'1,...,v' N-1 ]=[v'0,v'1,v'2,v'3,v'4,v'5,v'6,v'7,v'8,v'9,v' 10 ,v' 11 ,v' 12 ,v' 13 ,v' 14 ,v' 15 ], then we get the 0th component repeated output bit sequence

[0231] And the first component repeats the output bit sequence

[0232] In some embodiments, the H repeated output bit sequences c (0) ,c (1) ,...,c (H-1) The at least two repetitive output bit sequences in the output bit sequence include a repetitive rate configuration output bit sequence v'=[v'0, v'1, ..., v' N-1 Q in ] k Bits Wherein k is a non-negative integer less than the size of the first data bit index set Q; Q k is the kth element in the first data bit index set Q. A specific example is all repeated output bit sequences c (0) ,c (1) ,c (H-1) The repetition rate configuration output bit sequence v'=[v'0,v'1,...,v' N-1The Q0th bit in A specific example is

[0233] In some embodiments, the H repeated output bit sequences c (0) ,c (1) ,...,c (H-1) The at least two repeated output bit sequences in the input bit sequence c=[c0,c1,...,c K-1 The kth bit c in ] k A specific example is all repeated output bit sequences c (0) ,c (1) ,c (H-1) The input bit sequence c=[c0,c1,...,c K-1 ], where a specific example is

[0234] In some embodiments, the H repeated output bit sequences c (0) ,c (1) ,...,c (H-1) At least two repeated output bit sequences in have the same length, that is, there exists h≠k such that K h =K k , where for h = 0, 1, ..., H-1, K h The length c of the h-th repeated output bit sequence (h) In the specific example where H=3, all repeated output bit sequences c (0) ,c (1) ,c (2) The length of is K0=K1=K2=2.

[0235] In some embodiments, not all repeated output bit sequences c (0) ,c (1) ,...,c (H-1) have the same length, that is, there exists h≠k such that K h ≠K k , where K h is the hth repeated output bit sequence c (h) The length of K k is the kth repeated output bit sequence c (k) In the specific example where h=3, the 0th repetition outputs the bit sequence c (0) The length is K0=6, and the first repeated output bit sequence c (1) The length is K1=3, where K0≠K1.

[0236] In some embodiments, all repeated output bit sequences c (0) ,c (1) ,...,c (H-1) have different lengths, i.e., if h≠k, K h ≠K k , where K h Output bit sequence c for the hth repetition (h) The length of K k Output bit sequence c for the kth repetition (k) In a specific example where H = 3, the 0th repetition outputs the bit sequence c (0) The length is K0=6, the first repeated output bit sequence c (1) The length is K1=3, and the second repeated output bit sequence c (2) The length is K2=1, where K0≠K1, K0≠K2, and K1≠K2.

[0237] Example 5

[0238] This section discloses examples involving component rate configuration.

[0239] Example 5 is based on the above example.

[0240] In some embodiments, for h=0, 1, ..., H-1, a length of K is h The hth component of the output bit sequence is repeated Input to the component rate configuration to use the hth component data bit index set To determine the length N h The hth component rate configuration output bit sequence Among them, N h is the hth component polarization matrix The size of the polarization matrix is ​​shown in FIG. 4A to FIG. 4C Given in.

[0241] The component rate configuration determines the component rate configuration output bit sequence v = [u0, v1, ..., v N-1 ] includes: obtaining a component rate configuration input bit sequence c'=[c'0, c'1, ..., c' K'-1 ]; and by the first node by using a component data bit index set Q'={Q'0, Q'1, ..., Q' K'-1} component rate configuration to determine the component rate configuration output bit sequence v = [v0, v1, ..., v N-1]; where K' is the component repetition length; N is the component polarization matrix G (N) The size of the polarization matrix.

[0242] Component data bit index set Q'

[0243] In some embodiments, the component data bit index set Q' is a fourth type of integer set Z N = a subset of {0, 1, 2, ..., N-2, N-1}, where the fourth type integer set Z N = {0, 1, 2, ..., N-2, N-1} includes and only includes all non-negative integers less than N. Component data bit index set Q' = {Q'0, Q'1, ..., Q' K'-1} has K' non-negative elements Q'0,Q'1,...,Q' K-2 ,Q' K-1 , that is, the size of the component data bit index set Q' is K'. In some embodiments, for k = 0, 1, ..., K'-2, the element Q' in the component data bit index set Q' k Less than Q' k+1 , that is, the component data bit index set Q' is based on the index value Q'0 <Q'1<...<Q' K'-2 <Q' K'-1 In some embodiments, for k=0, 1, ..., K'-2, the Q' k polarization subchannel (denoted as W(Q' k )) is less reliable than Q' k+1 polarization subchannel (denoted as W(Q' k+1 )) reliability, that is, the component data bit index set Q' is calculated according to the polarization channel reliability according to W(Q'0) <W(Q'1)<...<W(Q' K'-2 ) <W(Q' K'-1 ) in ascending order. In some embodiments, for k=0, 1, ..., K'-2, the element Q' in the component data bit index set Q' k Greater than Q' k+1 , that is, the component data bit index set Q' is based on the index value according to Q'0>Q'1>...>Q' K'-2 >Q' K'-1 In some embodiments, for k=0, 1, ..., K'-2, the Q' k polarization subchannel (denoted as W(Q' k )) is more reliable than Q' k+1 polarization subchannel (denoted as W(Q' k+1)) reliability, that is, the component data bit index set Q' is based on the reliability of the polarization subchannel according to W(Q'0)>W(Q'1)>...>W(Q' K'-2 )>W(Q' K'-1 ) in descending order.

[0244] In a first specific example where N=8 and K'=4, the set of component data bit indices is Q'={Q'0, Q'1, Q'2, Q'3}={3,5,6,7}. In a second specific example where N=32 and K'=25, the set of component data bit indices is Q'={Q'0, Q'1, Q'2, Q'3, Q'4, Q'5, Q'6, Q'7, Q'8, Q'9, Q' 10 ,Q' 11 ,Q' 12 ,Q' 13 ,Q' 14 ,Q' 15 ,Q' 16 ,Q' 17 ,Q' 18 ,Q' 19 ,Q' 20 ,Q' 21 ,Q' 22 ,Q' 23 ,Q' 24} = {5,9,6,17,10,18,12,20,24,7,11,19,13,14,21,26,25,22,28,15,23,31,27,29,30}, where the polarimetric channel reliability is calculated according to W(Q'0) <W(Q'1)<W(Q'2)<W(Q'3)<W(Q'4)<W(Q'5)<W(Q'6)<W(Q'7)<W(Q'8)<W(Q'9)<W(Q' 10 ) <W(Q' 11 ) <W(Q' 12 ) <W(Q' 13 ) <W(Q' 14 ) <W(Q' 15 ) <W(Q' 16 ) <W(Q' 17 ) <W(Q' 18 ) <W(Q' 19 ) <W(Q' 20 ) <W(Q' 21 ) <W(Q' 22 ) <W(Q' 23 ) <W(Q' 24 ). In the third specific example where N=8 and K'=4, the component data bit index set is Q'={Q'0,Q'1,Q'2,Q'3}={7,6,5,3}.

[0245] In some embodiments, the component rate configuration is determined based on the component data bit index set Q' and the component rate configuration input bit sequence c'=[c'0, c'1, ..., c' K'-1 ] The corresponding component rate configuration output bit sequence v = [v0, v1, ..., v N-1 ]as follows.

[0246]

[0247] The specific example pseudo code for rate configuration is as follows.

[0248]

[0249] In some embodiments, for an index i belonging to a component data bit index set Q', bit v in the component rate configuration output bit sequence v i Set to the bits in the component rate configuration input bit sequence c'.

[0250] In the first specific example where N=8, K'=3, component data bit index set Q'={5,6,7}, and component rate configuration input bit sequence c'=[c'0,c'1,c'2], bits v5, v6, v7 indexed as indexes belonging to component data bit index set Q'={5,6,7} in the component rate configuration output bit sequence v=[v0,v1,v2,v3,v4,v5,v6,v7] are set to v5=c'0, v6=c'1, and v7=c'2.

[0251] In the second specific example where N=16, K'=6 and the component data bit index set Q'={12,7,11,13,14,15}, the component rate configuration input bit sequence c'=[c'0,c'1,c'2,c'3,c'4,c'5], the component rate configuration output bit sequence v=[v0,v1,v2,v3,v4,v5,v6,v7,v8,v9,v 10 ,v 11 ,v 12 ,v 13 ,v 14 ,v 15 ] is the bit v whose index belongs to the data bit index set Q' = {12,7,11,13,14,15} 12 、v7、v 11 、v 13 ,v 14 、v 15 is set to v 12 =c'0、v7=c'1、v 11 =c'2、v13 =c'3、v 14 =c'4 and v 15 =c'5.

[0252] A third specific example is given as

[0253]

[0254] In some embodiments, for an index i that does not belong to the component data bit index set Q', bit v in the component rate configuration output bit sequence v i is equal to 0.

[0255] In the first specific example where N=8, K'=3 and Q'={5,6,7}, the bits v0, v1, v2, v3, v4 in the component rate configuration output bit sequence v=[v0,v1,v2,v3,v4,v5,v6,v7] whose indexes are not in the component data bit index set Q'={5,6,7} are set to v0=0, v1=0, v2=0, v3=0 and v4=0.

[0256] In the second specific example where N=16, K'=6 and Q'={7,11,12,13,14,15}, the component rate configuration output bit sequence v=[v0,v1,v2,v3,v4,v5,v6,v7,v8,v9,v 10 ,v 11 ,v 12 ,v 13 ,v 14 ,v 15 ] are bits v0, v1, v2, v3, v4, v5, v6, v8, v9, v10, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51, v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62, v63, v64, v65, 10 is set to v0=0, v1=0, v2=0, v3=0, v4=0, v5=0, v6=0, v8=0, v9=0, and v 10 =0.

[0257] A third specific example is given as

[0258]

[0259] In some embodiments, the component rate configuration output bit sequence v is a multiplex of the component rate configuration input bit sequence c' and an all-zero sequence of length N-K', where N is the polarization matrix size and K' is the component rate configuration input bit sequence length.

[0260] A first specific example where N=8 and K'=3 is a component rate configuration input bit sequence c'=[c'0,c'1,c'2] and an all-zero sequence of length N-K'=8-3=5, then a component rate configuration output bit sequence v=[v0,v1,v2,v3,v4,v5,v6,v7]=[0,0,0,0,0,c0,c1,c2].

[0261] In the second specific example where N=16, K'=6, the component rate configuration input bit sequence c'=[c'0,c'1,c'2,c'3,c'4,c'5] and the all-zero sequence of length N-K'=16-4=12, then the component rate configuration output bit sequence v=[v0,v1,v2,v3,v4,v5,v6,v7,v8,v9,v 10 ,v 11 ,v 12 ,v 13 ,v 14 ,v 15 ]=[0,0,0,0,0,0,0,0,0,0,c0,0,c1,c2,c3] is determined.

[0262] Example 6

[0263] This section discloses examples involving the first cascade.

[0264] Example 6 is based on the above example.

[0265] The input to the cascade operation may be based on the input sequence c.

[0266] In some examples, the concatenation block may be connected to one or more component rate configuration blocks.

[0267] In some embodiments, the H component rate configuration output bit sequence v (0) ,v (1) ,...,v (H-1) are input to the first cascade to determine the cascade output bit sequence y=[y0,y1,y2,...,y E-1 ], where for h = 0, 1, ..., H-1, N h Configure the output bit sequence for the hth component rate Length; E = N0 + N1 + ... + N H-1 The output bit sequence is e = [e0, e1, e2, ..., e E-1 ], where N h It is also the h-th component polarization matrix The size of the polarization matrix;

[0268] FIG. 4A to FIG. 4C An example of a system involving a first cascade block is given in .

[0269] In some embodiments, the first cascade includes: obtaining, by the first node, H component cascade input bit sequences v (0) ,v (1) ,...,v (H-1) ; and the first node outputs the cascaded output bit sequence y = [y0, y1, y2, ..., y E-1 ]Determined as

[0270] Here, E is the output bit sequence e = [e0, e1, e2, ..., e E-1 ]; for h=0,1,...,H-1, the hth component concatenates the input bit sequence The length is N h ; Among them, N h is the size of the polarization matrix of the hth component; the output length is equal to the concatenated input bit sequence v of the H components (0) ,v (1) ,...,v (H-1) The sum of the lengths of H-1 In some embodiments, for h=0, 1, ..., H-1, the hth component concatenated input bit sequence is the hth component rate-configured output bit sequence.

[0271] The purpose of the Cascade block is to combine multiple input sequences to generate an output sequence that can be used as input to other blocks within the system.

[0272] In some examples, the first cascade may include: obtaining, by the first node, H component cascade input bit sequences v (0) ,v (1) ,...,v (H-1) ; and the first node outputs the cascaded output bit sequence y = [y0, y1, y2, ..., y E-1 ]Determined as

[0273]

[0274] Here, E is the output bit sequence e = [e0, e1, e2, ..., e E-1 ]; for h=0,1,...,H-1, the hth component concatenates the input bit sequence The length is N h ; Among them, N h is the size of the polarization matrix of the hth component; the output length is equal to the H concatenated input bit sequences v(0) ,v (1) ,...,v (H-1) The sum of the lengths of H-1 In some embodiments, for h=0, 1, ..., H-1, the hth component concatenated input bit sequence is the hth component rate-configured output bit sequence.

[0275] Example 7

[0276] This section discloses examples related to pre-transformation.

[0277] Example 7 is based on the above example.

[0278] The pre-transformed input may be based on the input sequence.

[0279] In some examples, the pre-transform block is connected to the concatenation block.

[0280] In some embodiments, the concatenated output bit sequence y=[y0, y1, y2, ..., y E-1 ] is input to the pre-transformation to determine the output bit sequence u=[u0,u1,u2,...,u E-1 ]:Generating polynomial g(D)=g0+g1·D+g2·D on GF(2) 2 +...+g m ·D m , the recursive feedback polynomial q(D)=q0+q1·D+q2·D on GF(2) 2 +...+q m ·D m .

[0281] The pre-transformation operation can be performed based on a generator polynomial or a recursive feedback polynomial.

[0282] In some embodiments, the pre-transformation includes: obtaining, by the first node, a pre-transformation input bit sequence of length N, and determining, by the first node, a pre-transformation output bit sequence u=[u0, u1, ..., u N-1 ]:The generating polynomial g(D)=g0+g1·D+...+g on GF(2) m ·D m , recursive feedback polynomial q(D)=q0+q1·D+...+q m ·D m .

[0283] In the above example, N can be any positive integer; m is the memory length; the specific example is FIG. 4A to FIG. 4CIn some embodiments, the pre-transformed input bit sequence of length N is a concatenated output bit sequence of length E y = [y0, y1, y2, ..., y E-1 ], where N = E, and the cascade output bit sequence y = [y0, y1, y2, ..., y E-1 ] includes more than one component rate configuration output bit sequence. In some embodiments, the pre-transformed input bit sequence of length N includes more than one component rate configuration output bit sequence.

[0284] (Use the generating polynomial g(D) for pre-transformation)

[0285] In some embodiments, the pre-transformation is based on a generating polynomial g(D)=g0+g1·D+g2·D+···+g m-1 ·D+g m D determines the pre-transformed input bit sequence y = [y0, y1, ..., y E-1 ] The corresponding pre-transformed output bit sequence u, where m is called the memory length of the generating polynomial g(D). Generating polynomial g(D) = g0+g1·D+...+g m-1 ·D m-1 +g m ·D m It can be any bivariate polynomial over GF(2), where m is the polynomial order or memory length. In the specific example where the memory length m=6, the generating polynomial is g(D)=g0+g1·D+g2·D 2 +g3·D 3 +g4·D 4 +g5·D 5 +g6·D 6 =1+0·D+1·D 2 +1·D 3 +0·D 4 +1·D 5 +1·D 6 =1+D 2 +D 3 +D 5 +D 6 In another specific example where the memory length m=3, the generating polynomial is g(D)=g0+g1·D+g2·D 2 +g3·D 3 =1+1·D+0·D 2 +1·D 3 =1+D+D 3 .

[0286] Figure 3Shows an example diagram of a pre - transformation using a generating polynomial \(g(D)=g_0 + g_1\cdot D+\cdots+g\) m-1 \(\cdot D\) m-1 +g m \(\cdot D\) m where the bit \(u_i\) at index \(i\) in the pre - transformation output bit sequence \(u\) is determined by \(m + 1\) bits \(y_i,y_{i - 1},y_{i - 2},\cdots,y_{i - m}\) with consecutive indices \(i,i - 1,i - 2,\cdots,i - m\) in the pre - transformation input bit sequence \(y\) and the generating polynomial \(g(D)=g_0 + g_1\cdot D+\cdots+g\) i i i-1 ,y i-2 ,y i-m ,\(\cdots,y\) i-m m-1 \(\cdot D\) m-1 m +g m \(\cdot D\) m as

[0287]

[0288] where the summation and multiplication are performed over GF(2); for \(i\lt k\), the bit \(y_i = 0\); \(g_k\) is the coefficient of the \(k\) - th term in the generating polynomial \(g(D)=g_0 + g_1\cdot D+\cdots+g\) i-k k m-1 \(\cdot D\) m-1 m m +g m \(\cdot D\) m Specific pseudo - code is as follows.

[0289]

[0290] Figure 5 Shows a specific example of a pre - transformation defined by a recursive feedback polynomial \(q(D)=q_0 + q_1\cdot D+\cdots+q\) m-1 \(\cdot D\) m-1 m +q m \(\cdot D\) m

[0291] (Pre - transformation using the recursive feedback polynomial \(q(D)\))

[0292] In some embodiments, the pre - transformation determines a pre - transformation output bit sequence \(u\) corresponding to a pre - transformation input bit sequence \(y\) according to a recursive feedback polynomial \(q(D)=q_0 + q_1\cdot D+q_2\cdot D+\cdots+q\) m-1 \(\cdot D+q\) m \(\cdot D\), where \(m\) is called the memory length of the recursive feedback polynomial \(q(D)\).

[0293] The feedback polynomial \(q(D)=q_0 + q_1\cdot D+\cdots+q\)m-1 ·D m-1 +q m ·D m is a bivariate polynomial whose zeroth-degree coefficient q0 is 1 and whose other coefficients q1,...,q m is any binary value over GF(2), where m is the memory length. In the specific example where the memory length m=6, the feedback polynomial is q(D)=q0+q1·D+q2·D 2 +q3·D 3 +q4·D 4 +q5·D 5 +q6·D 6 =1+0·D+1·D 2 +0·D 3 +1·D 4 +1·D 5 +1·D 6 =1+D 2 +D 4 +D 5 +D 6 In another specific example where the memory length m=3, the feedback polynomial is q(D)=q0+q1·D+q2·D 2 +q3·D 3 =1+0·D+1·D 2 +1·D 3 =1+D 2 +D 3 .

[0294] Figure 5 The use of a recursive feedback polynomial q(D)=q0+q1·D+...+q0 where q0=1 and the memory length is m is shown. m-1 ·D m-1 +q m ·D m An example diagram of pre-transformation, where the bit u with index i in the pre-transformation output bit sequence u i Determined by:

[0295] In the pre-transformation input bit sequence y=[y0,y1,...,y E-1 ] bit v with index i i ,

[0296] The first m bits u in the pre-transformed output bit sequence u have consecutive indices i-1, i-2, ..., im i-1 ,u i-2 ,...,u i-m ,

[0297] where the recursive feedback polynomial q(D) with q0 = 1 is q(D) = q0 + q1·D +... + q m-1 ·D m-1 + q m ·D m .

[0298] where a specific example is where both the summation and multiplication are performed over GF(2); for i < k, the bit u i-k = 0; q k is the coefficient of the k-th term in the recursive feedback polynomial q(D) = q0 + q1·D +... + q m-1 ·D m-1 + q m ·D m ; the specific pseudocode is as follows.

[0299]

[0300] Figure 6 illustrates another specific example of the pre-transformation jointly defined by the generating polynomial g(D) = g0 + g1·D +... + g m-1 ·D m-1 + g m ·D m and the recursive feedback polynomial q(D) = q0 + q1·D +... + q m-1 ·D m-1 + q m ·D m .

[0301] (Pre-transformation using both the generator polynomial g(D) and the recursive feedback polynomial q(D))

[0302] In some embodiments, the pre-transformation determines the pre-transformation output bit sequence u corresponding to the pre-transformation input bit sequence y according to the generating polynomial g(D) = g0 + g1·D + g2·D + ··· + g m-1 ·D + g m ·D and the recursive feedback polynomial q(D) = q0 + q1·D +... + q m-1 ·D m-1 + q m ·D m , where m is referred to as the memory length of both the generating polynomial g(D) and the recursive feedback polynomial q(D).

[0303] The generating polynomial g(D) = g0 + g1·D +... + g m-1 ·D m-1 + g m ·D mIt can be any bivariate polynomial over GF(2), where m is the polynomial order or memory length. In a specific example where the memory length m=6, the generating polynomial is g(D)=g0+g1·D+g2·D 2 +g3·D 3 +g4·D 4 +g5·D 5 +g6·D 6 =1+0·D+1·D 2 +1·D 3 +0·D 4 +1·D 5 +1·D 6 =1+D 2 +D 3 +D 5 +D 6 In another specific example where the memory length m=3, the generating polynomial is g(D)=g0+g1·D+g2·D 2 +g3·D 3 =1+1·D+0·D 2 +1·D 3 =1+D+D 3 . Recursive feedback polynomial q(D)=q0+q1·D+...+q m-1 ·D m-1 +q m ·D m is a bivariate polynomial whose zeroth-degree coefficient q0 is 1 and whose other coefficients q1,...,q m is any binary value over GF(2), where m is the memory length. In a specific example where the memory length m=6, the recursive feedback polynomial is q(D)=q0+q1·D+q2·D 2 +q3·D 3 +q4·D 4 +q5·D 5 +q6·D 6 =1+0·D+1·D 2 +0·D 3 +1·D 4 +1·D 5 +1·D 6 =1+D 2 +D 4 +D 5 +D 6 In another specific example where the memory length m=3, the recursive feedback polynomial is q(D)=q0+q1·D+q2·D 2 +q3·D 3 +q4·D 4 +q5·D 5 +q6·D6 =1+0·D+1·D 2 +0·D 3 +1·D 4 +1·D 5 +1·D 6 =1+D 2 +D 4 +D 5 +D 6 .

[0304] Figure 6 A diagram showing a pre-transformation using both a generator polynomial and a recursive feedback polynomial.

[0305] like Figure 6 As shown, the generating polynomial g(D) = g0+g1·D+...+g m-1 ·D m-1 +g m ·D m and a recursive feedback polynomial q(D), where the pre-transform determines the bit u with index i in the pre-transform output bit sequence u i ,include:

[0306] The first node sets the state bit sequence t = [t0, t1, t2, ..., t m ] is set to the pre-transformed input bit sequence y = [y0, y1, y2, ..., y E-1 ] bit y with index i i , that is, t0 = y i ;as well as

[0307] From the first node, through the recursive feedback polynomial q(D)=q0+q1·D+...+q on GF(2) m ·D m and the updated state bit sequence t=[t0,t1,t2...,t m-1 ,t m ] The summation bit s is determined as as well as

[0308] The first node sets the state bit sequence t = [t0, t1, t2..., t m-1 ,t m ], the bit t0 with index 0 is set to the sum bit s, i.e., t0 = s, and

[0309] From the first node through the generating polynomial g(D)=g0+g1·D+...+g m ·D m (Or equivalently, generate the bit sequence g = [g0, g1, ..., g m]) and the updated state bit sequence t=[t0,t1,t2...,t m-1 ,t m ] The pre-transformed output bit sequence u = [u0, u1, u2, ..., u N-1 ] bit u with index i i Determined as

[0310] The first node generates a state bit sequence t=[t0, t1, ..., t m-1 ,t m ] performs a right shift, where the state bit sequence t = [t0, t1, ..., t m-1 ,t m ] is set to 0, as shown below:

[0311]

[0312] The specific pseudo code for the above steps is as follows.

[0313]

[0314]

[0315] Example 8

[0316] This section discloses examples related to segmentation.

[0317] Example 8 is based on all the above examples.

[0318] In some examples, the input to the segmentation block is based on the input sequence c.

[0319] In some examples, the segmentation block may relate to a pre-transformation block.

[0320] In some embodiments, the pre-transformed output bit sequence u=[u0,u1,u2,...,u E-1 ] is input into the segment to pass through the H component polarization matrix sizes N0, N1, ..., N H-1 Determine H segment output bit sequences u (0) ,u (1) ,...,u (H-1) , where H is the number of component polarization matrices; for h = 0, 1, ..., H-1, the h-th segment outputs the bit sequence u (h) The length is N h , where N h is the size of the hth component polarization matrix, and E is the length of the pre-transformed output bit sequence u and E = N0 + N1 + ... + N H-1 .

[0321] In some examples, the segmenting operation includes obtaining, by the first node, a segmented input bit sequence of length E; and

[0322] The first node passes through H component polarization matrices of size N0, N1, ..., N H-1 Determine H segment output bit sequences u (0) ,u (1) ,...,u (H-1) as follows:

[0323]

[0324] In the above example, the segmented input bit sequence of length E is the pre-transformed output bit sequence of length E u=[u0,u1,u2,...,u E-1 ]; for h = 0, 1, ..., H-1, the hth segment outputs the bit sequence u (h) The length of is equal to the size of the polarization matrix N of the hth component h In some embodiments, a segmented input bit sequence of length E is composed of H segmented output bit sequences u (0) ,u (1) ,...,u (H-1) composition.

[0325] In some examples, the segmentation block may be connected with one or more component polarization transformation blocks.

[0326] Examples are FIG. 4A to FIG. 4C Given in.

[0327] Example 9

[0328] This section discloses examples involving polarization transformations.

[0329] Example 9 is based on all the above examples.

[0330] An encoding or decoding system may include multiple component polarization transformations.

[0331] The input for the component polarization transformation may be based on the input sequence c.

[0332] In some examples, the component polarization transformation block can be connected with the segmentation block.

[0333] In one example, for h=0, 1, 2, ..., H-1, the length is N h The hth segment outputs the bit sequence u (h) is input to the component polarization transformation to pass the hth component polarization matrix Set the length to N hThe hth component of the polarization transformation outputs the bit sequence Determined as Among them, the component polarization transformation is to transform the length N h The hth segment outputs the bit sequence u (h) With the component polarization matrix Perform vector-matrix multiplication on GF(2) to obtain the polarization-transformed output bit sequence of the hth component Right now

[0334] In some examples, the component polarization transformation block may be connected to the component interleaving block. In one example, the input of the component interleaving block is based on the output of the component polarization transformation block.

[0335] Some examples are FIG. 4A to FIG. 4C shown.

[0336] Example 10

[0337] This section discloses examples involving output bit sequences (including component polarization transformed output bit sequences).

[0338] Example 10 is based on the above example.

[0339] In one example, the output bit sequence e=[e0,e1,...,e E-1 ] includes H components polarization conversion output bit sequence d (0) ,d (1) ,...,d (H-1) , where for h = 0, 1, ..., H-1, the hth component polarization transformation output bit sequence The length of is equal to the size of the polarization matrix N of the hth component h .

[0340] In another example, the output bit sequence e=[e0, e1, ..., e E-1 ] is the H component polarization coded output bit sequence d (0) ,d (1) ,...,d (H-1) The second cascade is as follows:

[0341] In yet another example, the output bit sequence e=[e0, e1, ..., e E-1 ] is the H component polarization coded output bit sequence d (0) ,d (1) ,...,d (H-1) The second cascade is as follows:

[0342]

[0343]

[0344] Figure 4A An example of an output bit sequence e is given, which is the H component polar coding output bit sequence d (0) ,d (1) ,...,d (H-1) cascade.

[0345] Embodiment 11

[0346] This section discloses example systems that include component interleaving.

[0347] Example 11 is based on all the above examples.

[0348] The component interleaving operation may be implemented based on the interleaving pattern J.

[0349] In some examples, for h=0, 1, ..., W-1, the hth component polarization transform outputs the bit sequence is input to the hth component interleaver to determine the hth component interleaver output bit sequence Among them, the hth component interleaving is composed of length N h The hth component interleaving pattern Determined, where N h is the size of the polarization matrix of the hth component.

[0350] In some embodiments, a polarization matrix size N=N is used. h The method in Example 1 determines the hth component interleaving pattern J (h) , where N h is the size of the polarization matrix of the hth component. In some embodiments, the polarization matrix size N=N is used. h The method in Example 2 determines the hth component interleaving pattern J (h) , where N h is the size of the polarization matrix of the hth component.

[0351] In another example, the component interleaving pattern J=[J0, J1, ..., J N-2 ,J N-1 ] The component interleaving determined includes: obtaining a component interleaving input bit sequence d=[d0, d1, ..., d N-1 ]; and the first node outputs the interleaved output bit sequence d'=[d'0, d'1, ..., d' N-1 ]Determined as

[0352] In other words, the i-th bit of the interleaved output bit sequence d' is equal to the interleaved input bit sequence d = [d0, d1, ..., d N-1 ] i bits, where the component interleaving pattern J can be any permutation of the integer sequence [0, 1, 2, ..., N-2, N-1].

[0353] Several examples are discussed below to illustrate the above mentioned interleaving process.

[0354] Example 1: Component interleaving pattern J = [J0, J1, ..., J N-2 ,J N-1 The first specific example of ] is composed of polarization matrix size N and sub-block interleaving pattern π = [π0,π1,π2,π3,π4,π5,π6,π7,π8,π9,π 10 ,π 11 ,π 12 ,π 13 ,π 14 ,π 15 ,π 16 ,π 17 ,π 18 ,π 19 ,π 20 ,π 21 ,π 22 ,π 23 ,π 24 ,π 25 ,π 26 ,π 27 ,π 28 ,π 29 ,π 30 ,π 31 ]=[0,1,2,4,3,5,6,7,8,16,9,17,10,18,11,19,12,20,13,21,14,22,15,23,24,25,26,28,27,29,30,31], as determined below.

[0355]

[0356] Example 2: A second specific example of an interlaced pattern J = [J0, J1, ..., J N-2 ,J N-1 ] is the index i and the i-th element J in the interleaved pattern J i The relationship between satisfies the following quadratic form:

[0357] J i =mod(f1·i+f2·i 2 ,N),

[0358] Some examples of parameters f1 and f2 depending on the polarization matrix size N are summarized in Table 1.

[0359]

[0360]

[0361] Table 1 Interleaving parameters for Example 2

[0362] Example 3: Component interleaving pattern J = [J0, J1, ..., J N-2 ,J N-1 ] is J=[J0,J1,J2,J3,J4,J5,J6,J7]=[5,4,7,1,6,0,2,3].

[0363] Example 12

[0364] This section discloses examples of output bit sequences including component interleaved output bit sequences.

[0365] Example 12 is based on all the examples disclosed above.

[0366] In some embodiments, the output bit sequence e=[e0,e1,...,e E-1 ] includes W components interleaved output bit sequence d' (0) ,d' (1) ,...,d' (W-1) and HW components polarization conversion output bit sequence d (W) ,d (W+1) ,...,d (H-1) , where, for h = 0, 1, ..., W-1, the hth component interleaved output bit sequence The length of is equal to the size of the polarization matrix N of the hth component h , and for h = W, W + 1, ..., H-1, the h-th polarization transformation output bit sequence The length of is equal to the size of the polarization matrix N of the hth component h .

[0367] In some embodiments, the output bit sequence e=[e0,e1,...,e E-1 ] is the W=H component interleaved output bit sequence d' (0) ,d' (1) ,...,d' (H-1) The second cascade is as follows:

[0368]

[0369] In some embodiments, the output bit sequence e=[e0,e1,...,e E-1 ] is W = H component output bit sequence d' (0) ,d' (1) ,...,d' (H-1) The second cascade is as follows:

[0370]

[0371]

[0372] Figure 4B An example for an output bit sequence e is disclosed, which is a W=H component interleaved output bit sequence d' (0) ,d' (1) ,...,d' (H-1) cascade.

[0373] In some examples, the output bit sequence e = [e0, e1, ..., e E-1 ] is the W component interleaved output bit sequence d' (0) ,d' (1) ,...,d' (W-1) and HW components polarization conversion output bit sequence d (W) ,d (W+1) ,...,d (H-1) The second cascade is as follows:

[0374]

[0375] In some embodiments, the output bit sequence e=[e0,e1,...,e E-1 ] is the W component interleaved output bit sequence d' (0) ,d' (1) ,...,d' (W-1) and HW components polarization conversion output bit sequence d (W) ,d (W+1) ,...,d (H-1) The second cascade is as follows:

[0376]

[0377]

[0378] Figure 4C A specific example of an output bit sequence e is given, which is a W-component interleaved output bit sequence d' (0) ,d' (1) ,...,d' (W-1) and H-W components polarization conversion output bit sequence d (W) ,d' (W+1) ,...,d' (H-1) cascade, where the number of interleaving patterns is less than the number of component polarization matrices, i.e., W <H。

[0379] Figure 7 An exemplary block diagram of a hardware platform 700 that may be part of a network device (e.g., a base station) or a communication device (e.g., a user equipment (UE)) is shown. The hardware platform 700 includes at least one processor 710 and a memory 705 storing instructions. The instructions executed by the processor 710 configure the hardware platform 700 to perform Figures 1 to 6 The operations described in and the operations described in various embodiments described in this patent application. Transmitter 715 transmits or sends information or data to another device. For example, a network device transmitter can send a message to a user device. Receiver 720 receives information or data transmitted or sent by another device. For example, a user device can receive a message from a network device.

[0380] The embodiments discussed above will apply to network communications. Figure 8 An example of a communication system (e.g., a 5G or NR cellular network) including a base station 820 and one or more user equipment (UE) 811, 812, and 813 is shown. In some embodiments, the UE accesses the BS (e.g., the network) using a communication link to the network (sometimes referred to as an uplink direction, as depicted by dashed arrows 831, 832, 833), which then enables subsequent communication from the BS to the UE (e.g., shown in the direction from the network to the UE, sometimes referred to as a downlink direction, as shown by arrows 841, 842, 843). In some embodiments, the BS sends information to the UE (sometimes referred to as a downlink direction, as depicted by arrows 841, 842, 843), which then enables subsequent communication from the UE to the BS (e.g., shown in the direction from the UE to the BS, sometimes referred to as an uplink direction, as shown by dashed arrows 831, 832, 833). The UE can be, for example, a smartphone, a tablet, a mobile computer, a machine to machine (M2M) device, an Internet of Things (IoT) device, and the like.

[0381] Fig. 9 An example flow chart representation of a method for digital communication according to one or more embodiments of the present technology is shown. Operation 902 includes: determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined by performing a polarization transformation and a pre-transformation having H components; wherein the polarization transformation is based on H polarization matrices Where E, K, and H are all integers greater than 1, and the polarization matrix Size is N i Operation 904 includes transmitting, by the first node to the second node, a signal including the output bit sequence.

[0382] Fig.10 Another example flow chart of a method for digital communication according to one or more embodiments of the present technology is shown. Operation 1002 includes: receiving, by a second node, a signal including an output bit sequence having E bits from a first node. Operation 1004 includes: determining, by the second node, an input bit sequence having K bits based on the signal, wherein the output bit sequence is determined by performing a polarization transformation and a pre-transformation having H components; wherein the polarization transformation is based on H polarization matrices Among them, E, K, and H are all integers greater than 1, and the polarization matrix Size is N i .

[0383] Fig. 9 and Fig.10 Various preferred embodiments and additional features of the above method are as follows. Further examples are described with reference to embodiments 1 to 12. In some embodiments, at least two of the H polarization matrices have different sizes. In some embodiments, at least two of the H polarization matrices are different. In some embodiments, at least two of the H polarization matrices have a size greater than 2. In some embodiments, N0, N1 ... N H-1 and E satisfies N0+N1…+N H-1 = E. In some embodiments, E is composed of N0, N1, ..., N H-1 In some embodiments, N0, N1, ..., N H-1 Each of is an integer that is a power of 2. In some embodiments, the output bit sequence is also determined by performing a repetition operation, wherein an input of the repetition operation is based on the input bit sequence.

[0384] In some embodiments, the repetition operation includes: obtaining, by the first node, a repetitive input bit sequence; and determining, by the first node, H component repetitive output bit sequences c based on at least one of the following: (0) ,c (1) ,...,c (H-1) :1) Length list (K0, K1, ..., K H-1 ), where K i Indication c (i) length, or 2) of the repeated index list (R (0) ,R (1) ,...,R (H-1)). In some embodiments, the H components repeatedly output the bit sequence c (0) ,c (1) ,...,c (H-1) At least one of the component repeated output bit sequences has a length equal to the length of the input bit sequence. (0) ,c (1) ,...,c (H-1) None of the component repeated output bit sequences has a length equal to the length of the input bit sequence. (0) ,c (1) ,...,c (H-1) At least one component in the output bit sequence is repeated to be equal to the input bit sequence. In some embodiments, the length list (K0, K1, ..., K H-1 ) in which at least one element K i is equal to K, where K is the length of the input bit sequence. In some embodiments, the repetition index list (R (0) ,R (1) ,...,R (H-1) ) in the element R (i) is a set of integers. In some embodiments, the repetition index list (R (0) ,R (1) ,...,R (H -1) ) at least one element R (i) Equal to the set Z of integers of the first type K ={0,1,2,...,K-1}, where the first type integer set Z K = {0, 1, 2, ..., K-1} includes all non-negative integers less than K, and K is the length of the input bit sequence. In some embodiments, for h = 0, 1, ..., H-2, R (h+1) YesR (h) In some embodiments, at least two of the H component repeated output bit sequences share at least one common element. In some embodiments, Where K h is a positive integer. In some embodiments, at least two of the H component repeated output bit sequences c (i) and c (j) is based on at least one element c k In some embodiments, the at least one element c kIn some embodiments, at least two of the H component repeated output bit sequences are determined based on at least one identical bit in the input bit sequence. (i) and c (j) In some embodiments, at least two of the H component repeated output bit sequences are repeated output bit sequences c (i) and c (j) Includes common subsequences of the input bit sequence.

[0385] In some embodiments, the H components repeatedly output the bit sequence c (i) and c (j) The at least two component repetitive output bit sequences in the output bit sequence include matching subsequences generated based on the input bit sequence. In one example, the input bit sequence c = [c0, c1, c2, c3, c4, c5, c6, c7, c8], c (i) =[c0,c1,c7,c3] and c (j) =[c3,c2,c7,c5]. Here, c (i) and c (j) Correspondingly, there are matching subsequences [c7,c3] and [c3,c7]. Both matching subsequences are generated based on the input sequence c, that is, elements c3 and c7 are in the input sequence c. Moreover, the two subsequences [c7,c3] and [c3,c7] have a matching relationship, for example, c (i) The third and fourth elements (c7 and c3) in determine c (j) The two matching subsequences do not need to be in the same order as each other. In addition, the elements in the matching subsequence do not need to be in the same order as each other. (i) or c (j) consecutive positions in .

[0386] In some embodiments, the output bit sequence is further determined by performing a rate configuration operation, wherein the input of the rate configuration operation is based on the input bit sequence. K-1 ] Using the first data bit index set Q = {Q0, Q1, ..., Q K-1}Perform rate configuration operation to obtain a repetitive rate configuration output bit sequence v'=[v'0,v'1,...,v' N-1 ].

[0387] In some embodiments, the output bit sequence is further determined by performing a repetition operation, wherein the repetition operation includes: configuring the output bit sequence v'=[v'0, v'1, ..., v' N-1] The H component repeated output bit sequences c are determined by at least one of the following (0) ,c (1) ,...,c (H-1) :1) Length list (K0, K1, ..., K H-1 ), where K i Indication c (i) or 2) the first data bit index set Q = {Q0, Q1, ..., Q K-1 In some embodiments, the H components repeatedly output the bit sequence c (0) ,c (1) ,...,c (H-1) At least one of the component repeated output bit sequences has a length equal to the length of the input bit sequence. (0) ,c (1) ,...,c (H-1) None of the component repeated output bit sequences has a length equal to the length of the input bit sequence. (0) ,c (1) ,...,c (H-1) At least one component in the output bit sequence is repeated to be equal to the input bit sequence. In some embodiments, the length list (K0, K1, ..., K H-1 ) in which at least one element K i = K, where K is the length of the input bit sequence. In some embodiments, the first data bit index set Q = {Q0, Q1, ..., Q K-1 In some embodiments, at least two of the H component repeated output bit sequences share at least one common element. In some embodiments, Where K h is a positive integer. In some embodiments, at least two of the H component repeated output bit sequences are repeated output bit sequences c (i) and c (j) is based on at least one element v′ k In some embodiments, based on v′ k At least one bit in determines whether the element is based on the repetition rate configuration output bit sequence v'=[v'0, v'1, ..., v' N-1 ], where N is an integer greater than 1. In some embodiments, at least two of the H component repeated output bit sequences c (i) and c (j)The output bit sequence v'=[v'0,v'1,...,v' N-1 ], where N is an integer greater than 1. In some embodiments, at least two of the H component repeated output bit sequences c (i) and c (j) Including repetition rate configuration output bit sequence v'=[v'0,v'1,...,v' N-1 ], where N is an integer greater than 1.

[0388] In some embodiments, at least two of the H component repeated output bit sequences c (i) and c (j) Including repetition rate configuration output bit sequence v'=[v'0,v'1,...,v' N-1 ], where N is an integer greater than 1. In one example, the repetition rate configuration outputs a bit sequence v'=[v'0, v'1, v'2, v'3, v'4, v'5, v'6, v'7], c (i) = [v'0, v'1, v'2] and c (j) = [v'2, v'1, v'4]. Here, c (i) and c (j) Accordingly, there are matching subsequences [v'1, v'2] and [v'2, v'1]. Both matching subsequences are generated based on the repetition rate configuration output bit sequence v', that is, elements v'1 and v'2 are in the repetition rate configuration output bit sequence v'. In addition, the two subsequences [v'1, v'2] and [v'2, v'1] have a matching relationship, for example, c (i) The second and third elements in (v'1 and v'2) are mapped to c (j) The second and first elements in c (v'1 and v'2). The two matching subsequences do not need to be in the same order as each other. In addition, the elements in the matching subsequence do not need to be in the same order as each other. (i) or c (j) consecutive positions in .

[0389] In some embodiments, the rate configuration operation is performed using H components. In some embodiments, based on the component data bit set To perform the hth component of the rate configuration operation, where K h is the input length of the hth component of the rate configuration operation.

[0390] In some embodiments, the method described above also includes performing a first cascade operation, wherein the input of the first cascade operation is based on the input sequence. In some embodiments, the first cascade operation generates an intermediate output sequence having E bits. In some embodiments, the first cascade operation is performed on the first H component bit sequences generated based on the input sequence.

[0391] In some embodiments, the method described above further comprises performing a second concatenation operation, wherein the input of the second concatenation operation is based on the input sequence. In some embodiments, the second concatenation operation is performed on a second H component bit sequences generated based on the input sequence.

[0392] In some embodiments, the pre-transform generates an intermediate bit sequence having E bits. In some embodiments, the bits of the intermediate bit sequence are determined by a convolution bit sequence or a convolution polynomial. In some embodiments, the convolution bit sequence includes generating a bit sequence g=[g0, g1, ..., g m ], or the recursive feedback bit sequence q = [q0, q1, ..., q m ], where m is a positive integer. In some embodiments, the convolution polynomial includes a generating polynomial g(D)=g0+g1·D+...+g m-1 ·D m-1 +g m ·D m , or the recursive feedback polynomial q(D) = q0 + q1·D + ... + q m-1 ·D m-1 +q m ·D m , where m is a positive integer. In some embodiments, the output bit sequence is determined by performing a segmentation operation, wherein the input of the segmentation operation is based on the input bit sequence.

[0393] In some embodiments, the output bit sequence is further determined by performing an interleaving operation, wherein the input to the interleaving operation is based on the input bit sequence. In some embodiments, the interleaving operation is performed with W components, where W is an integer less than or equal to H. In some embodiments, the interleaving operation for any one of the W components is performed by a length N h Interwoven pattern Determine, where N h is an integer greater than 1.

[0394] It should be understood that the present application discloses methods and devices related to rate matching schemes applied to polarization coding, PAC coding or other pre-transformed polarization coding. In the 5G mobile communication standard of 3GPP, low-density parity-check (LDPC) codes are used for data transmission. However, compared with polar codes, LDPC has certain disadvantages in short payload size (also known as transport block size (TBS)). Alternatively, PAC codes can achieve finite length boundaries at moderate decoding complexity. The code length of the PAC code is a power of 2 (N=2 n , where n is a positive integer), as a polar code. However, in order to efficiently transmit payloads (or transport blocks (TBs)) in different wireless channel environments, it is not always necessary to have N=2 in the time and frequency resources allocated by the base station (BS). n Therefore, a rate matching scheme is needed for applying PAC codes in wireless communications.

[0395] The disclosed and other embodiments, illustrated modules and functional operations in this application may be implemented in digital electronic circuits, or in computer software, firmware or hardware (including the structures disclosed in this application and their equivalents), or in a combination of one or more of them. The disclosed and other embodiments may be implemented as one or more computer program products (i.e., modules of one or more computer program instructions encoded on a computer-readable medium) for execution by a data processing device or for controlling the operation of the data processing device. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, a combination of substances that affect machine-readable propagation signals, or a combination of one or more of them. The term "data processing device" includes all devices, equipment and machines for processing data, such as programmable processors, computers or multiple processors or computers. In addition to hardware, the device may also include code that creates an execution environment for the computer program in question, such as code that constitutes processor firmware, protocol stacks, database management systems, operating systems, or a combination of one or more of them. A propagation signal is an artificially generated signal, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information for transmission to a suitable receiver device.

[0396] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language (including compiled or interpreted languages) and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple collaborative files (e.g., files that store portions of one or more modules, subroutines, or codes). A computer program may be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communications network.

[0397] The processes and logic flows described in this application can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special-purpose logic circuits, and the apparatus can also be implemented as special-purpose logic circuits, such as FPGAs (field programmable gate arrays) or ASICs (application specific integrated circuits).

[0398] Processors suitable for executing computer programs include, by way of example, both general-purpose microprocessors and special-purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer are a processor for executing instructions and one or more storage devices for storing instructions and data. Typically, a computer will also include or be operatively coupled to one or more mass storage devices (such as magnetic disks, magneto-optical disks, or optical disks) for storing data, to receive data from the mass storage device or to transfer data to it, or both. However, a computer need not have such a device. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM optical disks. The processor and memory may be supplemented by or incorporated into a dedicated logic circuit.

[0399] Although the present application contains many details, these details should not be interpreted as limitations on the scope of the claimed invention or the content that can be claimed, but should be interpreted as an explanation of the specific features of a particular embodiment. Some of the features described herein in the context of a separate embodiment can also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment can also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although the above-mentioned features may be described as working in the form of certain combinations, or even initially claimed as such, in some cases, one or more features in the claimed combination can be deleted from the combination, and the claimed combination can be for a sub-combination or a variant of a sub-combination. Similarly, although the operations are described in a specific order in the accompanying drawings, this should not be understood as requiring the operations to be performed in the specific order or sequential order shown, or requiring the execution of all illustrated operations to achieve the desired result.

[0400] Only a few examples and implementations are disclosed. Variations, modifications, and enhancements to the illustrated examples and implementations, as well as other implementations, may be made based on what is disclosed.

Claims

1. A method for digital communication, comprising: The first node determines an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined by performing a polarization transformation and a pre-transformation having H components; wherein the polarization transformation is based on H polarization matrices Among them, E, K, H are integers greater than 1, and the polarization matrix Size is N i ;as well as The first node sends a signal including the output bit sequence to the second node 2. A method for digital communication, comprising: receiving, by the second node from the first node, a signal comprising an output bit sequence having E bits; as well as The second node determines an input bit sequence having K bits based on the signal, wherein the output bit sequence is determined by performing a polarization transformation and a pre-transformation having H components; wherein the polarization transformation is based on H polarization matrices Among them, E, K, H are integers greater than 1, and the polarization matrix The size is N i .

3. The method according to claim 1 or 2, wherein: At least two of the H polarization matrices have different sizes.

4. The method according to claim 1 or 2, wherein: At least two polarization matrices among the H polarization matrices are different.

5. The method according to claim 1 or 2, wherein: At least two of the H polarization matrices have a size greater than 2.

6. The method according to claim 1 or 2, wherein N0, N1, ..., N H-1 and E satisfies N0+N1+…+N H-1 =E.

7. The method according to claim 1 or 2, wherein N0, N1, ..., N H-1 Each of is an integer that is a power of 2.

8. The method according to claim 1 or 2, wherein: The output bit sequence is also determined by performing a repetitive operation, wherein an input to the repetitive operation is based on the input bit sequence.

9. The method according to claim 8, wherein: The repeated operation includes: Obtaining, by the first node, a repeated input bit sequence; and The first node determines the H component repeated output bit sequences c based on at least one of the following items: (0) ,c (1) ,...,c (H-1) :1) Length list (K0, K1, ..., K H-1 ), where K i Indicates the c (i) length or 2) of the repeated index list (R (0) ,R (1) ,...,R (H-1) ),in And K i Is a positive integer.

10. The method according to claim 9, wherein: At least two of the H component repeated output bit sequences share at least one common element.

11. The method according to claim 9, wherein: The H components repeatedly output the bit sequence c (0) ,c (1) ,...,c (H-1) At least one component repetition in the output bit sequence has a length equal to the length of the input bit sequence.

12. The method according to claim 9, wherein: At least two of the H component repeated output bit sequences are repeated output bit sequences c (i) and c (j) is determined based on at least one identical bit in the input bit sequence.

13. The method according to claim 9, wherein: At least two of the H component repeated output bit sequences are repeated output bit sequences c (i) and c (j) The method comprises generating a matching subsequence based on the input bit sequence.

14. The method according to claim 9, wherein: The repeated index set R (0) ,R (1) ,...,R (H-1) At least one element R (i) Equal to the set Z of integers of the first type K ={0,1,2,...,K-1}, where the first type integer set Z K ={0,1,2,...,K-1} includes all non-negative integers less than K.

15. The method according to claim 1 or 2, wherein: The output bit sequence is also determined by performing a rate configuration operation, wherein an input to the rate configuration operation is based on the input bit sequence.

16. The method according to claim 15, wherein: For the input bit sequence c=[c0,c1,...,c K-1 ] Using the first data bit index set Q = {Q0, Q1, ..., Q K-1 } to perform the rate configuration operation to obtain a repetitive rate configuration output bit sequence v'=[v'0, v'1, ..., v' N-1 ].

17. The method according to claim 16, wherein: The output bit sequence is also determined by performing a repetition operation, wherein the repetition operation comprises: configuring the output bit sequence v'=[v'0, v'1, ..., v' N-1 ], the H component repeated output bit sequence c is determined by at least one of the following items: (0) ,c (1) ,...,c (H-1) :1) Length list (K0, K1, ..., K H-1 ), where K i Indicates the c (i) or 2) the first data bit index set Q = {Q0, Q1, ..., Q K-1 },in 18. The method according to claim 17, wherein: At least two of the H component repeated output bit sequences share at least one common element.

19. The method according to claim 17, wherein: The H components repeatedly output the bit sequence c (0) ,c (1) ,...,c (H-1) At least one component repetition in the output bit sequence has a length equal to the length of the input bit sequence.

20. The method according to claim 17, wherein: At least two of the H component repeated output bit sequences are repeated output bit sequences c (i) and c (j) is based on the input bit sequence v'=[v'0,v'1,...,v' N-1 ] is determined by at least one identical bit in , where N is an integer greater than 1.

21. The method according to claim 17, wherein: At least two of the H component repeated output bit sequences are repeated output bit sequences c (i) and c (j) comprising configuring an output bit sequence v'=[v'0, v'1, ..., v' N-1 ] where N is an integer greater than 1.

22. The method according to claim 17, wherein: The first data bit index set Q={Q0, Q1, ..., Q K-1 }Sort by the index value or reliability of the polarization sub-channel.

23. The method according to claim 15, wherein: The rate configuration operation is performed with H components.

24. The method according to claim 23, wherein: Component data bit index set to perform the hth component of the rate configuration operation, where K h is the input length of the hth component of the rate configuration operation.

25. The method according to claim 1 or 2, wherein: Also included is performing a first cascade operation, wherein an input of the first cascade operation is based on the input sequence.

26. The method according to claim 25, wherein: The first concatenation operation generates an intermediate output sequence having E bits.

27. The method according to claim 25, wherein: The first concatenation operation is performed on first H component bit sequences generated based on the input sequence.

28. The method according to claim 27, wherein: Also included is performing a second cascade operation, wherein an input to the second cascade operation is based on the input sequence.

29. The method according to claim 28, wherein: The second concatenation operation is performed on second H component bit sequences generated based on the input sequence.

30. The method according to claim 1 or 2, wherein: The pre-transformation generates an intermediate bit sequence having E bits.

31. The method according to claim 30, wherein: The bits of the intermediate bit sequence are determined by a convolution bit sequence or a convolution polynomial.

32. The method according to claim 31, wherein: The convolution bit sequence includes generating a bit sequence g=[g0, g1, ..., g m ], or the recursive feedback bit sequence q = [q0, q1, ..., q m ], where m is a positive integer.

33. The method according to claim 31, wherein: The convolution polynomial includes a generating polynomial g(D)=g0+g1·D+...+g m-1 ·D m-1 +g m ·D m , or the recursive feedback polynomial q(D) = q0 + q1·D + ... + q m-1 ·D m-1 +q m ·D m , where m is a positive integer.

34. The method according to claim 1 or 2, wherein: The output bit sequence is determined by performing a segmentation operation, wherein an input to the segmentation operation is based on the input bit sequence.

35. The method according to claim 1 or 2, wherein: The output bit sequence is also determined by performing an interleaving operation, wherein an input to the interleaving operation is based on the input bit sequence.

36. The method of claim 35, wherein: The interleaving operation is performed with W components, where W is an integer less than or equal to H.

37. The method of claim 36, wherein: The interleaving operation of any one of the W components is performed by a length N h Interwoven pattern Determine, where N h is an integer greater than 1.

38. An apparatus for a communication network, the apparatus of the communication network comprising: A processor configured to implement the method according to any one of claims 1 to 37.

39. A computer readable storage medium having code stored thereon which, when executed by a processor, causes the processor to implement the method of any one of claims 1 to 37.

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