Method, apparatus and article of manufacture for improving performance of network operating in multiple frequency bands

Abstract

An example device (200) includes interface circuitry (212), a memory (218) configured to store machine-readable instructions (220), and processing circuitry (202) configured to instantiate or execute at least one of the machine-readable instructions (220). The example processing circuitry (202) is configured to instantiate or execute at least one of the machine-readable instructions (220) to determine a connectivity metric for a first device synchronized with a second device, and cause, via the interface circuitry (212), to send the connectivity metric to a third device with which the first device is not synchronized. In addition, the example processing circuitry (202) is configured to at least one of instantiate or execute the machine-readable instructions (220) to cause, based on a first communication from the third device, to send a second communication to the first device to synchronize the first device with the third device.

Description

Technical Field

[0001] The present specification relates generally to wireless communications and, more particularly, to methods, apparatus, and articles of manufacture for improving performance of networks operating in multiple frequency bands. Background Art

[0002] The Institute of Electrical and Electronics Engineers (IEEE) 802.15.4 is a technical standard that defines the operation of low-rate wireless personal area networks (LR-WPANs). and IEEE 802.15.4 is the foundation of the IEEE 802.15.4 standard, each of which further extends the standard by developing upper layers not defined in IEEE 802.15.4. Many deployments of IEEE 802.15.4-based technologies use asynchronous non-beacon mode personal area network (PAN) operation in the global 2.4 gigahertz (GHz) industrial, scientific, and medical (ISM) radio frequency (RF) band. and An example of a commonly used mesh network technology based on this mode of operation is PAN. PAN operation is also implemented in Internet of Things (IoT) networks. Summary of the Invention

[0003] An example apparatus includes an interface circuit system, a memory configured to store machine-readable instructions, and a processing circuit system configured to instantiate and / or execute the machine-readable instructions. The example processing circuit system is configured to instantiate and / or execute the machine-readable instructions to determine a connectivity metric of a first device that is synchronized with a second device, and to cause the connectivity metric to be sent to a third device with which the first device is not synchronized, via the interface circuit system. Furthermore, the example processing circuit system is configured to instantiate and / or execute the machine-readable instructions to cause, based on a first communication from the third device, a second communication to be sent to the first device to synchronize the first device with the third device. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of an example network including devices capable of communicating in multiple frequency bands.

[0005] Figure 2 yes Figure 1 Block diagram of an example implementation of a parent device in a network.

[0006] Figure 3 yes Figure 1 A block diagram of an example implementation of a sub-device in a network.

[0007] Figure 4It is an explanation Figure 1 Timing diagram of example channel hopping in a network with, for example, parent devices having different dwell times.

[0008] Figure 5 It is an explanation Figure 1 1 is a timing diagram of example channel hopping for an example child device in a sleep mode of operation and an example parent device in a network of FIG.

[0009] Figure 6 Yes means you can use Figure 2 A flowchart of example machine-readable instructions and / or example operations for executing, instantiating, and / or implementing example processing circuitry embodiments of a parent device of the present invention to implement channel hopping across multiple frequency bands.

[0010] Figure 7 Yes means you can use Figure 2 A flowchart of example machine-readable instructions and / or example operations to be executed, instantiated, and / or implemented by an example processing circuitry implementation of a parent device of the present invention to implement channel hopping in a base frequency band.

[0011] Figure 8 Yes means you can use Figure 3 Flowcharts of example processing circuitry embodiments of a child device of the present invention to execute, instantiate, and / or implement example machine-readable instructions and / or example operations in synchronization with an example parent device.

[0012] Figure 9 Yes means you can use Figure 3 A flowchart of example machine-readable instructions and / or example operations to be executed, instantiated, and / or implemented by example processing circuitry embodiments of sub-devices of the present invention to implement coordinated sampling and sensing with channel hopping.

[0013] Figure 10 Yes means you can use Figure 2 A flowchart of example machine-readable instructions and / or example operations to be executed, instantiated, and / or implemented by an example processing circuitry embodiment of a parent device to utilize an alternate frequency band to assist a child device in performing parent selection.

[0014] Figure 11 Yes means you can use Figure 2 A flowchart of example machine-readable instructions and / or example operations to be executed, instantiated, and / or implemented by an example processing circuitry embodiment of a parent device to utilize an alternate frequency band to assist a child device in performing parent selection.

[0015] Figure 12 Yes means you can use Figure 3 A flowchart of example machine-readable instructions and / or example operations for executing, instantiating, and / or implementing example processing circuitry embodiments of a child device to select a parent device.

[0016] Figure 13 is a program comprising example machine-readable instructions and / or implementations structured to execute, instantiate, and / or implement Figure 6 、 7 , 10 and / or 11 example operations to implement Figure 2 Block diagram of an example processing circuitry platform of a parent device's processing circuitry.

[0017] Figure 14 is a program comprising example machine-readable instructions and / or implementations structured to execute, instantiate, and / or implement Figure 8 、 9 and / or 12 example operations to implement Figure 3 Block diagram of an example processing circuit system platform of a processing circuit system of a sub-device.

[0018] Figure 15 yes Figure 13 Processing circuitry and / or Figure 14 A block diagram of an example embodiment of a processing circuit system.

[0019] Figure 16 yes Figure 13 Processing circuitry and / or Figure 14 A block diagram of another example embodiment of a processing circuit system.

[0020] Figure 17 is a program for transferring software, instructions and / or firmware (e.g., corresponding to Figure 6 、 7 , 8, 9, 10, 11 and / or 12) to client devices associated with end users and / or consumers (e.g., for licensing, sale and / or use), retailers (e.g., for sale, resale, licensing and / or sublicensing) and / or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to other end users such as retailers and / or direct purchasing customers).

[0021] The use of the same reference numbers or other reference designators in the drawings indicates the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0022] The drawings are not necessarily drawn to scale. Generally, like reference numerals in the drawings and this specification refer to like or similar parts. Although the drawings show regions with distinct lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, boundaries and / or lines may be unobservable, intermingled, and / or irregular.

[0023] It is desirable to operate in the sub-1 GHz RF spectrum (e.g., radio frequencies below 1 GHz) as well as the widely utilized 2.4 GHz spectrum. For example, operating in the sub-1 GHz spectrum and the 2.4 GHz spectrum enables longer links within the network (e.g., long-range propagation), more robust links through media such as concrete, and will avoid the congested 2.4 GHz band. Additionally, it is desirable to maintain operation within the existing 2.4 GHz RF spectrum. For example, operating in the 2.4 GHz band maintains the global ISM operating mode and leverages the ubiquity of 2.4 GHz solutions. Additional example details of operating in the sub-1 GHz and 2.4 GHz spectrum can be found in commonly assigned U.S. patent application publication No. 2023 / 0052555, entitled “Devices and Methods for Asynchronous and Synchronous Wireless Communications Utilizing a Single Radio,” filed on August 10, 2022, which is incorporated herein by reference in its entirety.

[0024] However, in most IEEE 802.15.4 implementations, operating a single network across two RF bands using a single radio presents challenges. One challenge with sub-1 GHz operation is the duty cycle (e.g., channel hopping) mandated by RF regulatory agencies in certain regions, such as the Federal Communications Commission (FCC) in the United States. For example, if a device operates with a bandwidth less than a threshold bandwidth (e.g., less than 400 kHz bandwidth) and a transmitter power greater than a threshold power (e.g., greater than 30 dBm), the FCC requires the device to perform channel hopping across at least 50 channels. An example frequency band can be divided into one or more channels, where a channel refers to a frequency range within the band. Existing channel hopping techniques are limited to a single frequency range. Existing channel hopping techniques also require all coordinators (e.g., routers, gateways, etc.) that are part of the network to support the same frequency band. Furthermore, existing channel hopping techniques impose a high computational burden on the coordinator to synchronize with neighboring devices. For example, existing channel hopping techniques require the coordinator to maintain synchronization information about all neighboring devices, which in a real-world network may exceed 50 devices.

[0025] In addition, existing channel hopping technology requires all coordinators in the network to send data on all channels periodically so that sub-devices in the network can select parent devices that may have a stronger connection with one or more sub-devices, thereby complicating device operation. In addition, existing channel hopping technology does not support coordinated sampling listening (CSL). CSL is a feature of IEEE802.15.4 that enables low-power sub-devices to transition from a sleep operating mode to a wake-up operating mode under specific periodic circumstances synchronized with the parent device. For example, a parent device can schedule data exchange with a sub-device under specific periodic circumstances. However, existing channel hopping technology does not support this feature of IEEE 802.15.4. In addition, existing channel hopping technology does not support the discovery of other devices operating in different frequency bands. For example, a sub-device operating according to existing CSL technology cannot discover other devices that may operate in a different frequency band from the sub-device.

[0026] The examples described herein enable channel hopping in sub-1 GHz bands (e.g., to enable range extension links) while reducing (e.g., minimizing) changes in operations in the 2.4 GHz band (e.g., to enable reuse of existing software stacks for 2.4 GHz operations). For example, the methods, apparatus, and articles of manufacture described herein process multiple frequency bands as part of a channel hopping sequence. Additionally, the examples described herein reduce the computational burden on synchronization devices by synchronizing channel hopping in sub-networks (e.g., without synchronizing one device with all neighboring devices). Additionally, the examples described herein enable frequency hopping utilizing CSL. The examples described herein also utilize overlapping channel hopping sequences between parent devices to help a child device select a parent device that is likely to have a stronger connection with the child device. Additionally, the methods, apparatus, and articles of manufacture described herein utilize alternative frequency bands supported by the parent device to enable selection of a parent device that is likely to have a stronger connection with the child device.

[0027] Figure 1 is a block diagram of an example network 100 that includes devices capable of communicating in multiple frequency bands. For example, network 100 includes devices operating in sub-1 GHz frequency bands and devices operating in the 2.4 GHz frequency band. Figure 1 In the example of FIG, the network 100 includes an example gateway 102, a first example dual-band router 104 A Second example dual-band router 104 B , example single-band router 106 , first example endpoint device 108 A , second example endpoint device 108 B , third example endpoint device 108 C , fourth example endpoint device 108 D Fifth example endpoint device 110 A , Sixth example endpoint device 110B , Seventh example endpoint device 110 C and the eighth example endpoint device 110 D .

[0028] exist Figure 1 In the illustrated example, network 100 includes one or more parent devices and one or more child devices. Example parent devices are devices that direct data packets between devices and / or networks. For example, parent devices include gateways and routers. Example child devices are devices that synchronize with parent devices. For example, child devices include endpoint devices and internal routers (e.g., routers that synchronize with gateways).

[0029] exist Figure 1 In the illustrated example, gateway 102 is coupled to the Internet, first dual-band router 104 A , second dual-band router 104 B and single-band router 106. Figure 1 In an example of , the gateway 102 includes one or more protocol converters, one or more impedance matchers, one or more rate converters, one or more fault isolators, and / or one or more signal converters. Figure 1 In the example of , the gateway 102 operates in a single frequency band. For example, the gateway 102 operates in the 2.4 GHz frequency band. Figure 1 In the example of the gateway 102, the first dual-band router 104 A , second dual-band router 104 B and single-band router 106. For example, gateway 102 allows data packets to flow from network 100 to the Internet. Figure 1 In the example of FIG. 1 , the gateway 102 serves as the first dual-band router 104. A , a single-band router 106 and a second dual-band router 104 B The parent device.

[0030] exist Figure 1 In the illustrated example, the first dual-band router 104 A Coupled to the gateway 102, the single-band router 106, and the first endpoint device 108 A , the second endpoint device 108 B , the fifth endpoint device 110 A and the sixth endpoint device 110 B .exist Figure 1 In the example of the first dual-band router 104 A Contains software and / or hardware circuitry. For example, the first dual-band router 104 A The first dual-band router 104 may include routing software executed on a central processing unit (CPU).A Contains one or more application-specific integrated circuits (ASICs). Figure 1 In the example of the first dual-band router 104 A Operate in multiple frequency bands. For example, the first dual-band router 104 A Able to operate in sub-1GHz and 2.4GHz bands. Figure 1 In the example of the first dual-band router 104 A Using the basic band as the first dual-band router 104 A The first dual-band router 104 operates in a synchronous operation mode. A The sub-1 GHz frequency band is used as the basic frequency band. In the example synchronous operation mode, the first dual-band router 104 A and the first dual-band router 104 A The sub-device synchronizes channel hopping. Figure 1 In the example of the first dual-band router 104 A Utilizes an alternative frequency band as the first dual-band router 104 A The frequency band in which the router is located is operated in an asynchronous operation mode. For example, the first dual-band router 104 A The 2.4 GHz band is used as an alternative band. In the example asynchronous operation mode, the first dual-band router 104 A and the first dual-band router 104 A The sub-devices can hop channels asynchronously.

[0031] exist Figure 1 In the illustrated example, the first dual-band router 104 A The gateway 102, the single-band router 106, and the first endpoint device 108 A , the second endpoint device 108 B , the fifth endpoint device 110 A and the sixth endpoint device 110 B For example, the first dual-band router 104 A The information contained in the routing table and / or routing policy is used to route traffic between the gateway 102, the single-band router 106, and the first endpoint device 108. A , the second endpoint device 108 B , the fifth endpoint device 110 A and the sixth endpoint device 110 B Therefore, the first dual-band router 104 A The first endpoint device 108 A , the second endpoint device 108 B, the fifth endpoint device 110 A and the sixth endpoint device 110 B Connects to other devices in the network 100. In some examples, the first dual-band router 104 A Using the first dual-band router 104 A and the second dual-band router 104 B Supporting alternative frequency bands with the second dual-band router 104 B Establish a communication session. Figure 1 In the example of the first dual-band router 104 A With respect to the first endpoint device 108 A , the second endpoint device 108 B , the fifth endpoint device 110 A and the sixth endpoint device 110 B Serves as the parent device.

[0032] exist Figure 1 In the illustrated example, the second dual-band router 104 B Coupled to the gateway 102, the single-band router 106, and the seventh endpoint device 110 C and the eighth endpoint device 110 D .exist Figure 1 In the example of B Contains software and / or hardware circuitry. For example, the second dual-band router 104 B In addition or alternatively, the second dual-band router 104 B Contains one or more ASICs. Figure 1 In the example of B Operate in multiple frequency bands. For example, the second dual-band router 104 B Able to operate in sub-1GHz and 2.4GHz bands. Figure 1 In the example of B Using the basic band as the second dual-band router 104 B The second dual-band router 104 operates in a synchronous operation mode. B The sub-1 GHz frequency band is used as the basic frequency band. In the example synchronous operation mode, the second dual-band router 104 B and the second dual-band router 104 B The sub-device synchronizes channel hopping. Figure 1 In the example of B Utilizes an alternative frequency band as a second dual-band router 104 BThe second dual-band router 104 operates in an asynchronous mode. B The 2.4 GHz band is used as an alternative band. In the example asynchronous operation mode, the second dual-band router 104 B and the second dual-band router 104 B The sub-devices can hop channels asynchronously.

[0033] exist Figure 1 In the illustrated example, the second dual-band router 104 B The gateway 102, the single-band router 106, and the seventh endpoint device 110 C and the eighth endpoint device 110 D For example, the second dual-band router 104 B The information contained in the routing table and / or routing policy is used to route packets between the gateway 102, the single-band router 106, and the seventh endpoint device 110. C and the eighth endpoint device 110 D Therefore, the second dual-band router 104 B The seventh endpoint device 110 C and the eighth endpoint device 110 D Connects to other devices in network 100. In some examples, the second dual-band router 104 B Using the second dual-band router 104 B and the first dual-band router 104 A Supporting alternative frequency bands with the first dual-band router 104 A Establish a communication session. Figure 1 In the example of B With respect to the seventh endpoint device 110 C and the eighth endpoint device 110 D Serves as the parent device.

[0034] exist Figure 1 In the illustrated example, the single-band router 106 is coupled to the gateway 102, the first dual-band router 104, and the A , second dual-band router 104 B , the third endpoint device 108 C and the fourth endpoint device 108 D .exist Figure 1 In the example of , the single-band router 106 includes software and / or hardware circuitry. For example, the single-band router 106 includes routing software executed on a CPU. Additionally or alternatively, the single-band router 106 includes one or more ASICs. Figure 1In the example of , the single-band router 106 operates in a single frequency band. For example, the single-band router 106 operates in the 2.4 GHz frequency band. Figure 1 In the example of the single-band router 106, the gateway 102, the first dual-band router 104 A , second dual-band router 104 B , and the third endpoint device 108 C and the fourth endpoint device 108 D For example, the single-band router 106 utilizes information contained in the routing table and / or routing policy to route data packets between the gateway 102, the first dual-band router 104, and the endpoint devices in the routing table. A , second dual-band router 104 B , and the third endpoint device 108 C and the fourth endpoint device 108 D Therefore, the single-band router 106 directs the packets between the third endpoint device 108. C and the fourth endpoint device 108 D Connect to other devices in the network 100. Figure 1 In the example of the single-band router 106, the third endpoint device 108 C and the fourth endpoint device 108 D Serves as the parent device.

[0035] exist Figure 1 In the illustrated example, the first endpoint device 108 A and the second endpoint device 108 B coupled to the first dual-band router 104 A In addition, the third endpoint device 108 C and the fourth endpoint device 108 D is coupled to the single-band router 106. Figure 1 In the example of A , the second endpoint device 108 B , the third endpoint device 108 C and the fourth endpoint device 108 D Operates in the 2.4GHz band. Figure 1 In the example of A , the second endpoint device 108 B , the third endpoint device 108 C and / or the fourth endpoint device 108 D One or more of the above can be implemented by a smart speaker, a smart socket, a smart faucet (e.g., a smart faucet), a contact sensor (e.g., to detect whether a window or door is open), a smart light, etc.

[0036] exist Figure 1 In the illustrated example, the fifth endpoint device 110 A and the sixth endpoint device 110 B coupled to the first dual-band router 104 A In addition, the seventh endpoint device 110 C and the eighth endpoint device 110 D Coupled to the second dual-band router 104 B .exist Figure 1 In the example of A , the sixth endpoint device 110 B , the seventh endpoint device 110 C and the eighth endpoint device 110 D Operates in the sub-1GHz frequency band. Figure 1 In the example of A , the sixth endpoint device 110 B , the seventh endpoint device 110 C and / or the eighth endpoint device 110 D One or more of the above can be implemented by a smart speaker, a smart socket, a smart faucet (e.g., a smart faucet), a contact sensor (e.g., to detect whether a window or door is open), a smart light, etc.

[0037] exist Figure 1 In the illustrated example, when joining the network 100, the child device sends a message to one or more parent devices (eg, the first dual-band router 104) in the network 100. A , second dual-band router 104 B and single-band router 106). In response to receiving the discovery request, the parent device sends a response containing synchronization information to be used by the candidate child device to synchronize with the parent device. Thus, in response to a discovery request, a child device attempting to join network 100 may receive multiple responses from candidate parent devices. After the child device synchronizes with the parent device, the parent device sends a timing element (e.g., a timing packet) to the child device for each data packet and / or acknowledgement packet sent to the child device. An example timing element includes information identifying the time that has elapsed since the parent device last hopped channels.

[0038] exist Figure 1 In the illustrated example, channel hopping in network 100 is limited to a sub-network of network 100. For example, a sub-device operating in a frequency band below 1 GHz synchronizes with the channel hopping schedule of the parent device with which the sub-device is synchronized. Thus, the sub-device stores synchronization information of the parent device with which the sub-device is synchronized. Additionally, the parent device need not, but may, store synchronization information of neighboring peer devices and / or sub-devices. Figure 1In the example of A and the sixth endpoint device 110 B With the first dual-band router 104 A In addition, Figure 1 In the example of C and the eighth endpoint device 110 D With the second dual-band router 104 B In some instances, the child device also stores synchronization information for one or more candidate parent devices with which the child device is not synchronized. Thus, the child device can synchronize with other candidate parent devices at different times.

[0039] exist Figure 1 In the illustrated example, although all child devices synchronize with a given sub-1 GHz capable parent device and the sub-1 GHz capable parent device performs channel hopping according to a synchronized schedule, each group of such devices performs channel hopping according to a different schedule, thereby achieving frequency diversity between the sub-networks of network 100. For example, in Figure 1 In the example of the first dual-band router 104 A and the second dual-band router 104 B For example, the first dual-band router 104 operates in a sub-1 GHz frequency band. A and the second dual-band router 104 B The sub-networks do not interfere with each other. Thus, the frequency diversity in the network 100 is improved.

[0040] Figure 2 yes Figure 1 1. For example, the first dual-band router 104 A or the second dual-band router 104 B One or more of may be implemented by the parent device 200. Figure 2 In the example of , parent device 200 includes example processing circuitry 202 . Figure 2 The example processing circuitry 202 includes example communication control circuitry 204 , example channel timing circuitry 206 , and example counter circuitry 208 . Figure 2 The example parent device 200 also includes an antenna 210 and an example interface circuit system 212. The example interface circuit system 212 includes an example transmitter circuit system 214 and an example receiver circuit system 216. Figure 2 In the example of , parent device 200 includes example memory 218. Example memory 218 includes example instructions 220.

[0041] exist Figure 2 In an example of , parent device 200 may be instantiated (e.g., created as an instance, produced for any length of time, realized, implemented, etc.) by processing circuitry, such as a central processing unit (CPU), executing the first instruction. Additionally or alternatively, Figure 2 The parent device 200 may be instantiated (e.g., created as an example, produced for any length of time, realized, implemented, etc.) by (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA) that is structured and / or configured to perform operations corresponding to the first instruction in response to executing the second instruction. It should be understood that Figure 2 Some or all of the circuitry may thus be instantiated at the same or different times. Figure 2 Some or all of the circuitry of can be instantiated, for example, in one or more threads that execute in parallel on hardware and / or execute serially on hardware. Furthermore, in some instances, Figure 2 Some or all of the circuitry may be implemented by microprocessor circuitry executing instructions and / or FPGA circuitry performing operations to implement one or more virtual machines and / or containers.

[0042] exist Figure 2 In the illustrated example, processing circuitry 202 is coupled to interface circuitry 212 and memory 218. For example, processing circuitry 202 is coupled to transmitter circuitry 214, receiver circuitry 216, and memory 218. Figure 2 In some examples, processing circuitry 202 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. In some examples, processing circuitry 202 is instantiated and / or configured to implement, for example, a processing circuitry that executes a parent instruction. Figure 6 、 7 , 10 and / or 11 and other operations.

[0043] exist Figure 2 In the illustrated example, the communication control circuitry 204 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. Figure 2 In an example of , communication control circuitry 204 monitors network 100 for one or more discovery requests from a candidate child device. For example, before a candidate child device synchronizes with parent device 200, the candidate child device sends a discovery request to parent device 200. As described below, the discovery request identifies a specific channel to which the interface circuitry of the candidate child device will be tuned within a predetermined period of time. Figure 2 In the example of , upon receiving the discovery request, the communication control circuitry 204 causes a response to the discovery request to be sent via the transmitter circuitry 214 on the channel specified in the discovery request.

[0044] exist Figure 2 In the illustrated example, the response to the discovery request includes synchronization information. The example synchronization information includes data identifying the number of the channel to which communication control circuitry 204 is to tune interface circuitry 212, a pseudo-random sequence according to which communication control circuitry 204 is to hop between channels, two or more dwell times (e.g., 50 milliseconds (ms), 250 ms, etc.) that channel timing circuitry 206 is to use to program counter circuitry 208, and a period after which channel timing circuitry 206 is to alternate dwell times (e.g., a DWELL_TIME_SWITCH parameter). In addition, the example synchronization information includes data identifying the following: a primary frequency band of the parent device 200 (e.g., a sub-1 GHz frequency band), an alternate frequency band of the parent device 200 (e.g., a 2.4 GHz frequency band), a period after which the communication control circuit system 204 is to switch from the primary frequency band to the alternate frequency band (e.g., FREQ_SWITCH_CHANNEL_PARAMETER), and a period after which the communication control circuit system 204 is to switch from the alternate frequency band to the primary frequency band (e.g., ALT_FREQ_SLOT_RANGE). The example synchronization information may be formatted as illustrated in Table 1 below.

[0045] Table 1

[0046] Number of channels 9 Pseudorandom sequence 9,6,2,3,7,1,8,5,4 DWELL_TIME_1(ms) 50 DWELL_TIME_2(ms) 250 DWELL_TIME_SWITCH(time slot) 50 Basic frequency band Sub-1GHz Alternative frequency band (GHz) 2.4 FREQUENCY_SWITCH_CHANNEL_PARAMETER(time slot) 50 ALT_FREQ_SLOT_RANGE(time slot) 10

[0047] exist Figure 2 In the illustrated example, the unit of measurement for the FREQ_SWITCH_CHANNEL_PARAMETER and ALT_FREQ_SLOT_RANGE parameters is time slots. In the examples described herein, a time slot represents a period of time dedicated to a channel. For example, the duration of a time slot is equal to the dwell time. By including the FREQ_SWITCH_CHANNEL_PARAMETER and ALT_FREQ_SLOT_RANGE parameters in synchronization information, the communication control circuit system 204 enables child devices synchronized with the parent device 200 to follow a channel hopping sequence across multiple frequency bands (e.g., both the sub-1 GHz band and the 2.4 GHz band).

[0048] exist Figure 2In the illustrated example, the example synchronization information of Table 1 indicates to the child device that every 50 time slots, the parent device 200 is to switch the interface circuit system 212 from being tuned to the fundamental frequency band to being tuned to the alternative frequency band and remain in the alternative frequency band for 10 time slots. In the example of Table 1, the fundamental frequency band is a sub-1 GHz frequency band for synchronous operation mode, and the alternative frequency band is a 2.4 GHz frequency band for asynchronous operation mode. Example sub-1 GHz frequency bands include the 915 megahertz (MHz) frequency band (which may be applicable in regions regulated by the FCC), the 868 MHz frequency band (which may be applicable in regions regulated by regulations following standards provided by the European Telecommunications Standards Institute (ETSI), and the 470 MHz frequency band (which may be applicable in regions regulated by the Ministry of Industry and Information Technology of China). Additionally, the example synchronization information of Table 1 indicates to the child device that at the end of 10 time slots (e.g., the end of the ALT_FREQ_SLOT_RANGE), the parent device 200 is to switch the interface circuitry 212 from being tuned to the 2.4 GHz band to being tuned to the sub-1 GHz band. Figure 2 In the example of FIG. 1 , when communication control circuitry 204 selects a channel (e.g., in the sub-1 GHz band or the 2.4 GHz band), communication control circuitry 204 will follow the hopping sequence on the corresponding channel as if no interruption had occurred. For example, in the example synchronization information of Table 1 , regardless of whether the switch to the 2.4 GHz band occurs at time slot 50, time slot number 65 will obtain the same channel according to the selected channel hopping sequence.

[0049] exist Figure 2 In the illustrated example, the pseudo-random sequence identified in the synchronization information identifies N+M channels, where N represents the number of time slots dedicated to channels in the sub-1 GHz band, and M represents the number of time slots dedicated to channels in the 2.4 GHz band. Thus, a channel hopping indication having N+M time slots will be dedicated to the 2.4 GHz band, and will be dedicated to the sub-1 GHz band (NM). As described above, when the communication control circuitry 204 tunes the interface circuitry 212 to a channel in the sub-1 GHz band, the communication control circuitry 204 maintains the interface circuitry 212 operating in the channel in the sub-1 GHz band, and after the dwell time expires, the channel hops to another channel in the sub-1 GHz band. Additionally, in Figure 2 In the example of , when communication control circuitry 204 tunes interface circuitry 212 to a channel in the 2.4 GHz band, communication control circuitry 204 does not follow the channel hopping sequence. Figure 2In an example, communication control circuitry 204 causes interface circuitry 212 to remain tuned to a single channel for the number of time slots specified by the ALT_FREQ_SLOT_RANGE parameter. For example, when a device operates in the 2.4 GHz band, RF regulatory agencies in certain regions may not mandate channel hopping. Therefore, when parent device 200 operates in the 2.4 GHz band, parent device 200 is considered to be operating in an asynchronous operating mode. In additional or alternative examples, communication control circuitry 204 implements channel hopping in the 2.4 GHz band.

[0050] exist Figure 2 In the illustrated example, after the child device synchronizes with parent device 200 (eg, using synchronization information), communication control circuitry 204 and channel timing circuitry 206 implement channel hopping within the baseband of parent device 200. Figure 2 In the example of , based on the synchronization information, the communication control circuit system 204 tunes the interface circuit system 212 to a channel and operates in the channel for a duration. For example, based on the pseudo-random sequence identified in the synchronization information, the communication control circuit system 204 calculates the channel to which the interface circuit system 212 is to be tuned. In addition, for example, the communication control circuit system 204 communicates (e.g., exchanges data) with the sub-device in the channel for a duration. Figure 2 In the example of FIG, based on the expiration of the dwell time, communication control circuitry 204 determines whether the data exchange in the first channel has expired. For example, for a child device utilizing CSL, if the child device and parent device 200 are exchanging data when the dwell time expires, communication control circuitry 204 maintains the current tuning of interface circuitry 212 until the data exchange is complete (e.g., until communication control circuitry 204 receives an acknowledgment packet from the child device and / or sends an acknowledgment packet to the child device).

[0051] exist Figure 2 In the illustrated example, the parent device 200 can collaborate with other parent devices in the network 100 to help the child device select a parent device with which the child device has a stronger connection. For example, if the child device is synchronized with the parent device 200, there may be a candidate parent device that has a stronger connectivity with the child device than the parent device 200 has with the child device. Therefore, the parent device 200 can collaborate with the candidate parent devices to notify the child device of the existence of the candidate parent device. Similarly, the parent device 200 can receive communications from other parent devices indicating candidate child devices with which the parent device 200 may have a stronger connection. In some examples, the communication control circuitry 204 is instantiated and / or configured to implement, for example, processing circuitry that executes communication control instructions. Figure 6 、 7 , 10 and / or 11 and other operations.

[0052] exist Figure 2 In the illustrated example, channel timing circuitry 206 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. Figure 2 In an example of , the channel timing circuitry 206 controls the counter circuitry 208. For example, the channel timing circuitry 206 sets one or more counters of the counter circuitry 208 to track the dwell time of the parent device 200. For example, the channel timing circuitry 206 sets one or more counters of the counter circuitry 208 to count down from the dwell time identified in the synchronization information. Additionally or alternatively, the channel timing circuitry 206 sets one or more counters of the counter circuitry 208 to count up to the dwell time identified in the synchronization information. Figure 2 In an example of the channel timing circuitry 206, the channel timing circuitry 206 determines whether one or more dwell times have expired. For example, the channel timing circuitry 206 determines whether one or more counters have counted down from a predefined value. Additionally or alternatively, the channel timing circuitry 206 determines whether one or more counters have counted up to a predefined value.

[0053] exist Figure 2 In the illustrated example, the channel timing circuitry 206 sets one or more counters of the counter circuitry 208 to track the number of time slots utilized for each dwell time of the parent device 200. For example, the channel timing circuitry 206 sets one or more counters of the counter circuitry 208 to count down from the DWELL_TIME_SWITCH parameter identified in the synchronization information. Additionally or alternatively, the channel timing circuitry 206 sets one or more counters of the counter circuitry 208 to count up to the DWELL_TIME_SWITCH parameter identified in the synchronization information. Figure 2 In the example of , channel timing circuitry 206 determines whether the DWELL_TIME_SWITCH period has expired. For example, channel timing circuitry 206 determines whether one or more counters have counted down from a predefined value. Additionally or alternatively, channel timing circuitry 206 determines whether one or more counters have counted up to a predefined value. Based on channel timing circuitry 206's determination that the DWELL_TIME_SWITCH period has expired, channel timing circuitry 206 utilizes a second dwell time. For example, channel timing circuitry 206 sets one or more counters of counter circuitry 208 to track the second dwell time. In this manner, channel timing circuitry 206 advantageously enables a child device to select a parent device with which the child device is likely to have a stronger connection.

[0054] For example, once a child device is synchronized with parent device 200, it may be advantageous for the child device to switch to a different parent device to which the child device has a stronger connection, if one such parent device is available. If the entire network operates on a single channel (e.g., channel hopping is not implemented), then the child device may detect different parent devices. However, when a network implements channel hopping (e.g., network 100), different parent devices may hop on different channels. Therefore, without adjustments, existing channel hopping techniques have a low probability of different parent devices transmitting on the same channel as the parent device to which the child device is synchronized. Advantageously, by utilizing different dwell times in the channel hopping sequence, the channel timing circuitry 206 increases the probability that the child device will detect a different parent device to which the child device has a stronger connection. For example, Figure 4 1 illustrates an example of utilizing different dwell times across parent devices. As described below, utilizing different dwell times across parent devices increases the probability that two independent parent devices will hop on different sequences to have a common overlapping channel. In some examples, channel timing circuitry 206 is instantiated and / or configured to implement, for example, processing circuitry that executes channel timing instructions. Figure 6 and / or operations such as those represented by the flowchart in FIG7.

[0055] exist Figure 2 In the illustrated example, the counter circuitry 208 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. Figure 2 In an example, counter circuitry 208 includes one or more counters to track: one or more dwell times, a period (in time slots) after which parent device 200 switches interface circuitry 212 from a base frequency band (e.g., a sub-1 GHz frequency band) to an alternate frequency band (e.g., a 2.4 GHz frequency band), a period (in time slots) after which parent device 200 switches interface circuitry 212 from an alternate frequency band to a base frequency band, and / or a period (in time slots) after which channel timing circuitry 206 alternates dwell times. In some examples, counter circuitry 208 is instantiated and / or configured to perform operations by processing circuitry that executes counter instructions.

[0056] In some examples, parent device 200 includes means for processing. For example, means for processing may be implemented by processing circuitry 202. In some examples, processing circuitry 202 may be implemented by, for example, Figure 13 For example, the processing circuit system 202 may be instantiated by the example processing circuit system 1312 of Figure 15 The example microprocessor 1500 that executes machine-executable instructions is instantiated, and the machine-executable instructions are, for example, composed of at least Figure 6 Boxes 604, 606, 608, 610, 612, 614, 616, and 618, at least Figure 7 Boxes 702, 704, 706, 708, 710, 712, 714, 716, 718, 720, 722, 724, and 726, at least Figure 10 Boxes 1002, 1004, 1006, 1008, and 1010 and / or at least Figure 11 In some examples, processing circuitry 202 may be instantiated by hardware logic circuitry, which may be comprised of an ASIC, XPU, or other processor configured and / or structured to perform operations corresponding to the machine-readable instructions. Figure 16 FPGA circuitry 1600. Additionally or alternatively, processing circuitry 202 may be instantiated by any other combination of hardware, software, and / or firmware. For example, processing circuitry 202 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.) configured and / or structured to execute some or all machine-readable instructions and / or perform some or all operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally applicable.

[0057] In some examples, the means for processing includes means for controlling communications. For example, the means for controlling communications may be implemented by the communications control circuitry 204. In some examples, the communications control circuitry 204 may be implemented by, for example, Figure 13 For example, the communication control circuit system 204 may be instantiated by the example processing circuit system 1312 of Figure 15 The example microprocessor 1500 that executes machine-executable instructions is instantiated, and the machine-executable instructions are, for example, composed of at least Figure 6 Blocks 604, 610, 612, 616, and 618, at least Figure 7 Boxes 702, 704, 708, 710, 714, 718, 722, and 726, at least Figure 10 Boxes 1002, 1004, 1006, 1008, and 1010 and / or at least Figure 11In some examples, communication control circuitry 204 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or other processor configured and / or structured to implement operations corresponding to the machine-readable instructions. Figure 16 FPGA circuitry 1600. Additionally or alternatively, communication control circuitry 204 may be instantiated by any other combination of hardware, software, and / or firmware. For example, communication control circuitry 204 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.) configured and / or structured to execute some or all machine-readable instructions and / or perform some or all operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally applicable.

[0058] In some examples, the means for processing includes means for controlling timing. For example, the means for controlling timing can be implemented by channel timing circuitry 206. In some examples, channel timing circuitry 206 can be implemented by, for example, Figure 13 For example, the channel timing circuitry 206 may be instantiated by processing circuitry such as the example processing circuitry 1312 of FIG. Figure 15 The example microprocessor 1500 that executes machine-executable instructions is instantiated, and the machine-executable instructions are, for example, composed of at least Figure 6 Blocks 608 and 614 and / or at least Figure 7 In some examples, channel timing circuitry 206 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or other processor configured and / or structured to perform operations corresponding to the machine-readable instructions. Figure 16 FPGA circuitry 1600. Additionally or alternatively, channel timing circuitry 206 may be instantiated by any other combination of hardware, software, and / or firmware. For example, channel timing circuitry 206 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.) configured and / or structured to execute some or all machine-readable instructions and / or perform some or all operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally applicable.

[0059] exist Figure 2 In the illustrated example, antenna 210 is coupled to transmitter circuitry 214 and receiver circuitry 216. Figure 2 In the example of , the antenna 210 can be implemented by a monopole antenna, a dipole antenna, an array antenna, a large loop antenna, a traveling wave antenna, an aperture antenna, etc. Figure 2 In an example of , the antenna 210 transmits a signal into an environment where the parent device 200 is placed and detects a signal from the environment.

[0060] exist Figure 2 In the illustrated example, interface circuitry 212 is coupled to processing circuitry 202 and antenna 210. In some examples, interface circuitry 212 is implemented by one or more transmitters and one or more receivers. Additionally or alternatively, interface circuitry 212 is implemented by one or more transceivers. As described above, Figure 2 In the example of , interface circuitry 212 includes transmitter circuitry 214 and receiver circuitry 216. Figure 2 In the example of , transmitter circuitry 214 is coupled to processing circuitry 202 and antenna 210 . Figure 2 The example transmitter circuitry 214 is implemented by physical layer circuitry. For example, the transmitter circuitry 214 includes physical coding sublayer circuitry and physical medium dependent layer circuitry. Figure 2 In the example of , receiver circuitry 216 is coupled to processing circuitry 202 and antenna 210 . Figure 2 The example receiver circuitry 216 is implemented by physical layer circuitry. For example, the receiver circuitry 216 includes physical coding sublayer circuitry and physical medium dependent layer circuitry.

[0061] exist Figure 2 In the illustrated example, memory 218 is coupled to processing circuitry 202 . Figure 2 The example memory 218 is configured to store data. For example, the memory 218 may store one or more files indicating synchronization information, information transmitted in a discovery request from a candidate child device, information transmitted from one or more parent devices, one or more connectivity metrics of child devices synchronized with the parent device 200, and / or any other values. In addition, the memory 218 stores one or more files indicating instructions 220. For example, the instructions 220 may be generated by Figure 6 、 7 , 10 and / or 11 are implemented by machine readable instructions. Figure 2In the example of , the memory 218 can be implemented by volatile memory (e.g., synchronous dynamic random access memory (SDRAM), DRAM, RAMBUS dynamic random access memory (RDRAM), etc.) and / or non-volatile memory (e.g., flash memory). Additionally or alternatively, the example memory 218 can be implemented by one or more double data rate (DDR) memories, such as DDR, DDR2, DDR3, DDR4, mobile DDR (mDDR), etc.

[0062] In additional or alternative examples, the example memory 218 can be implemented by one or more mass storage devices, such as a hard drive, an optical drive, a digital versatile disk drive, a solid-state drive, etc. Although the memory 218 is illustrated as a single database in the illustrated example, the memory 218 can be implemented by any number and / or type of databases. Furthermore, the data stored in the memory 218 can be in any data format, such as binary data, comma-delimited data, tab-delimited data, Structured Query Language (SQL) structures, etc.

[0063] Figure 3 yes Figure 1 100. For example, the first endpoint device 108 A , the second endpoint device 108 B , the third endpoint device 108 C , the fourth endpoint device 108 D , the fifth endpoint device 110 A , the sixth endpoint device 110 B , the seventh endpoint device 110 C and the eighth endpoint device 110 D One or more of can be implemented by sub-device 300. Figure 3 In the example of , sub-device 300 includes example processing circuitry 302 . Figure 3 The example processing circuitry 302 includes example communication control circuitry 304 , example channel timing circuitry 306 , and example counter circuitry 308 . Figure 3 The example sub-device 300 also includes an antenna 310 and an example interface circuit system 312. The example interface circuit system 312 includes an example transmitter circuit system 314 and an example receiver circuit system 316. Figure 3 In the example of , sub-device 300 includes example memory 318. Example memory 318 includes example instructions 320.

[0064] exist Figure 3In the example of , the sub-device 300 can be instantiated (e.g., created as an example, generated for any length of time, realized, implemented, etc.) by a processing circuit system such as a CPU executing the first instruction. Additionally or alternatively, Figure 3 The sub-device 300 may be instantiated (e.g., created as an example, produced for any length of time, realized, implemented, etc.) by (i) an ASIC and / or (ii) an FPGA that is structured and / or configured to perform operations corresponding to the first instruction in response to executing the second instruction. It should be understood that Figure 3 Some or all of the circuitry may thus be instantiated at the same or different times. Figure 3 Some or all of the circuitry of can be instantiated, for example, in one or more threads that execute in parallel on hardware and / or execute serially on hardware. Furthermore, in some instances, Figure 3 Some or all of the circuitry may be implemented by microprocessor circuitry executing instructions and / or FPGA circuitry performing operations to implement one or more virtual machines and / or containers.

[0065] exist Figure 3 In the illustrated example, processing circuitry 302 is coupled to interface circuitry 312 and memory 318. For example, processing circuitry 302 is coupled to transmitter circuitry 314, receiver circuitry 316, and memory 318. Figure 3 In some examples, processing circuitry 302 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. In some examples, processing circuitry 302 is instantiated and / or configured to implement, for example, a processing circuitry that executes a parent instruction. Figure 8 、 9 and / or operations such as those represented by the flowchart of 12.

[0066] exist Figure 3 In the illustrated example, the communication control circuitry 304 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. Figure 3 In an example of , the communication control circuitry 304 searches the network for one or more candidate parent devices. For example, the communication control circuitry 304 causes one or more discovery requests to be sent. Figure 3 In the example of FIG, communication control circuitry 304 repeatedly causes one or more discovery requests to be sent on all channels supported by child device 300. Consequently, at least one of the channels will overlap with the channel to which the candidate parent device is tuned. The example discovery request includes information identifying the channel to which communication control circuitry 304 will tune interface circuitry 312 within a predetermined period of time. Thus, after receiving the discovery request, when the candidate parent device is tuned to the channel identified in the discovery request, the candidate parent device sends a response to the discovery request including synchronization information.

[0067] exist Figure 3 In the illustrated example, after child device 300 (e.g., receiver circuitry 316) receives one or more responses to one or more discovery requests, communication control circuitry 304 selects one of the one or more candidate parent devices with which child device 300 is to synchronize. For example, communication control circuitry 304 selects the candidate parent device that has the strongest connectivity with child device 300 from among the one or more candidate parent devices. Figure 3 In the example of , communication control circuit system 304 calculates the received signal strength indicator (RSSI) value of each candidate parent device from which child device 300 receives a response, and selects the candidate parent device with the highest RSSI value. Connectivity strength can also be measured in units of bit error rate (BER), link quality indicator (LQI), and other connectivity metrics. Figure 3 In the example of , communication control circuitry 304 causes synchronization information for the selected parent device to be stored in memory 318 .

[0068] exist Figure 3 In the illustrated example, based on the synchronization information, processing circuitry 302 synchronizes channel hopping with the selected parent device. For example, communication control circuitry 304 and channel timing circuitry 306 implement channel hopping based on the synchronization information. For example, based on the synchronization information, communication control circuitry 304 tunes interface circuitry 312 to a channel and operates in the channel for a dwell time. Additionally, for example, based on a pseudo-random sequence identified in the synchronization information, communication control circuitry 304 calculates the channel to which interface circuitry 312 is to be tuned. Figure 3 In an example, the communication control circuitry 304 communicates (eg, performs one or more data exchanges) with the parent device in the channel for a dwell time.

[0069] exist Figure 3 In the illustrated example, the child device 300 can utilize CSL. For example, when the parent device is not communicating with the child device 300, the communication control circuit system 304 places the child device 300 in a sleep mode of operation. For example, to place the child device 300 in the sleep mode of operation, the communication control circuit system 304 turns off the interface circuit system 312. At a specified time, the communication control circuit system 304 places the child device 300 in a wake-up mode of operation. For example, to place the child device 300 in the wake-up mode of operation, the communication control circuit system 304 turns on the interface circuit system 312. In addition, at a specified time, the communication control circuit system 304 tunes the interface circuit system 312 to the channel in which the parent device is expected to operate and operates in that channel. Figure 3In the example of , based on the expiration of the dwell time, communication control circuitry 304 determines whether the data exchange in the channel has expired. For example, when child device 300 utilizes CSL and child device 300 and the parent device are exchanging data when the dwell time expires, communication control circuitry 304 maintains the current tuning of interface circuitry 312 until the data exchange is complete (e.g., until communication control circuitry 304 receives an acknowledgment packet from the parent device and / or causes an acknowledgment packet to be sent to the parent device).

[0070] exist Figure 3 In the illustrated example, the parent device with which the child device 300 is synchronized can notify the child device 300 of another parent device with which the child device 300 has a stronger connection. For example, if the child device 300 is synchronized with a first parent device, the first parent device can notify the child device 300 of a second parent device that has a stronger connection to the child device 300 than the first parent device. Based on receiving this notification from the first parent device, the communication control circuit system 304 causes a discovery request to be sent to the second parent device and synchronizes with the second parent device after receiving a response from the second parent device. In some examples, the communication control circuit system 304 is instantiated and / or configured to implement, for example, processing circuit system that executes communication control instructions. Figure 8 、 9 and / or operations such as those represented by the flowchart of 12.

[0071] exist Figure 3 In the illustrated example, channel timing circuitry 306 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. Figure 3 In an example of , channel timing circuitry 306 controls counter circuitry 308. For example, channel timing circuitry 306 sets one or more counters of counter circuitry 308 to track the dwell time of the parent device with which child device 300 is synchronized. For example, channel timing circuitry 306 sets one or more counters of counter circuitry 308 to count down from the dwell time identified in the synchronization information. Additionally or alternatively, channel timing circuitry 306 sets one or more counters of counter circuitry 308 to count up to the dwell time identified in the synchronization information. Figure 3 In an example of the embodiment of the present invention, the channel timing circuitry 306 determines whether one or more dwell times have expired. For example, the channel timing circuitry 306 determines whether one or more counters have counted down from a predefined value. Additionally or alternatively, the channel timing circuitry 306 determines whether one or more counters have counted up to a predefined value.

[0072] exist Figure 3In the illustrated example, the channel timing circuitry 306 sets one or more counters of the counter circuitry 308 to track the number of time slots utilized for each dwell time of the parent device with which the child device 300 is synchronized. For example, the channel timing circuitry 306 sets one or more counters of the counter circuitry 308 to count down from the DWELL_TIME_SWITCH parameter identified in the synchronization information. Additionally or alternatively, the channel timing circuitry 306 sets one or more counters of the counter circuitry 308 to count up to the DWELL_TIME_SWITCH parameter identified in the synchronization information. Figure 3 In an example of the embodiment of the present invention, the channel timing circuitry 306 determines whether the DWELL_TIME_SWITCH period has expired. For example, the channel timing circuitry 306 determines whether one or more counters have counted down from a predefined value. Additionally or alternatively, the channel timing circuitry 306 determines whether one or more counters have counted up to a predefined value.

[0073] exist Figure 3 In the illustrated example, based on the channel timing circuitry 306 determining that the DWELL_TIME_SWITCH period has expired, the channel timing circuitry 306 utilizes a second dwell time. For example, the channel timing circuitry 306 sets one or more counters of the counter circuitry 308 to track the second dwell time. As described above, other parent devices (e.g., parent devices with which the child device 300 is not synchronized) utilize a different dwell time than the parent. Therefore, if the other parent device has stronger connectivity with the child device 300, the child device 300 can detect the other parent device and connect to the parent device. In some examples, the channel timing circuitry 306 is instantiated and / or configured to implement, for example, processing circuitry that executes channel timing instructions. Figure 8 and / or operations such as the operations represented by the flowchart in 9.

[0074] exist Figure 3 In the illustrated example, the counter circuitry 308 may be implemented by one or more CPUs, one or more ASICs, and / or one or more FPGAs. Figure 3 In an example, counter circuitry 308 includes one or more counters to track: one or more dwell times, a period (in time slots) after which a parent device switches from a base frequency band (e.g., a sub-1 GHz frequency band) to an alternate frequency band (e.g., a 2.4 GHz frequency band), a period (in time slots) after which a parent device switches from an alternate frequency band to a base frequency band, and / or a period (in time slots) after which channel timing circuitry 306 alternates dwell times. In some examples, counter circuitry 308 is instantiated and / or configured to perform operations by processing circuitry that executes counter instructions.

[0075] In some examples, sub-device 300 includes means for processing. For example, means for processing can be implemented by processing circuitry 302. In some examples, processing circuitry 302 can be implemented by, for example, Figure 14 For example, the processing circuit system 302 may be instantiated by the example processing circuit system 1412 of Figure 15 The example microprocessor 1500 that executes machine-executable instructions is instantiated, and the machine-executable instructions are, for example, composed of at least Figure 8 Boxes 802, 806, 808, 810, 812, 814, 816, 818, and 820, at least Figure 9 Boxes 902, 904, 906, 908, 910, 912, 914, and 916 and / or at least Figure 12 In some examples, processing circuitry 302 may be instantiated by hardware logic circuitry, which may be comprised of an ASIC, XPU, or other processor configured and / or structured to perform operations corresponding to the machine-readable instructions. Figure 16 FPGA circuitry 1600. Additionally or alternatively, processing circuitry 302 may be instantiated by any other combination of hardware, software, and / or firmware. For example, processing circuitry 302 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.) configured and / or structured to execute some or all machine-readable instructions and / or perform some or all operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally applicable.

[0076] In some examples, the means for processing includes means for controlling communications. For example, the means for controlling communications may be implemented by the communications control circuitry 304. In some examples, the communications control circuitry 304 may be implemented by, for example, Figure 14 For example, the communication control circuit system 304 may be instantiated by a processing circuit system such as the example processing circuit system 1412 of FIG. Figure 15 The example microprocessor 1500 that executes machine-executable instructions is instantiated, and the machine-executable instructions are, for example, composed of at least Figure 8 Blocks 802, 806, 812, 814, 818, and 820, at least Figure 9 Blocks 902, 908, 910, 914, and 916 and / or at least Figure 12In some examples, the communication control circuitry 304 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or other processor configured and / or structured to perform operations corresponding to the machine-readable instructions. Figure 16 FPGA circuitry 1600. Additionally or alternatively, communication control circuitry 304 may be instantiated by any other combination of hardware, software, and / or firmware. For example, communication control circuitry 304 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.) configured and / or structured to execute some or all machine-readable instructions and / or perform some or all operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally applicable.

[0077] In some examples, the means for processing includes means for controlling timing. For example, the means for controlling timing can be implemented by channel timing circuitry 306. In some examples, channel timing circuitry 306 can be implemented by, for example, Figure 14 For example, the channel timing circuitry 306 may be instantiated by processing circuitry such as the example processing circuitry 1412 of FIG. Figure 15 The example microprocessor 1500 that executes machine-executable instructions is instantiated, and the machine-executable instructions are, for example, composed of at least Figure 8 Blocks 810 and 816 and / or at least Figure 9 In some examples, channel timing circuitry 306 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or other processor configured and / or structured to perform operations corresponding to the machine-readable instructions. Figure 16 FPGA circuitry 1600. Additionally or alternatively, channel timing circuitry 306 may be instantiated by any other combination of hardware, software, and / or firmware. For example, channel timing circuitry 306 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.) configured and / or structured to execute some or all machine-readable instructions and / or perform some or all operations corresponding to the machine-readable instructions without executing software or firmware, although other structures are equally applicable.

[0078] exist Figure 3In the illustrated example, antenna 310 is coupled to transmitter circuitry 314 and receiver circuitry 316. Figure 3 In the example of , the antenna 310 can be implemented by a monopole antenna, a dipole antenna, an array antenna, a large loop antenna, a traveling wave antenna, an aperture antenna, etc. Figure 3 In the example of FIG. 3 , the antenna 310 transmits a signal into an environment where the sub-device 300 is placed and detects a signal from the environment.

[0079] exist Figure 3 In the illustrated example, interface circuitry 312 is coupled to processing circuitry 302 and antenna 310. In some examples, interface circuitry 312 is implemented by one or more transmitters and one or more receivers. Additionally or alternatively, interface circuitry 312 is implemented by one or more transceivers. As described above, Figure 3 In the example of , interface circuitry 312 includes transmitter circuitry 314 and receiver circuitry 316. Figure 3 In the example of , transmitter circuitry 314 is coupled to processing circuitry 302 and antenna 310 . Figure 3 The example transmitter circuitry 314 is implemented by physical layer circuitry. For example, the transmitter circuitry 314 includes physical coding sublayer circuitry and physical medium dependent layer circuitry. Figure 3 In the example of , receiver circuitry 316 is coupled to processing circuitry 302 and antenna 310 . Figure 3 The example receiver circuitry 316 is implemented by physical layer circuitry. For example, the receiver circuitry 316 includes physical coding sublayer circuitry and physical medium dependent layer circuitry.

[0080] exist Figure 3 In the illustrated example, memory 318 is coupled to processing circuitry 302 . Figure 3 The example memory 318 is configured to store data. For example, the memory 318 may store one or more files indicating synchronization information of a parent device with which the child device is synchronized, information transmitted in a discovery request from the candidate child device 300, one or more connectivity metrics of one or more candidate parent devices, and / or any other values. In addition, the memory 318 stores one or more files indicating instructions 320. For example, the instructions 320 may be generated by Figure 8 、 9 and / or 12 are implemented by machine-readable instructions. Figure 3 In the example of , the memory 318 can be implemented by volatile memory (e.g., SDRAM, DRAM, RDRAM, etc.) and / or non-volatile memory (e.g., flash memory). Additionally or alternatively, the example memory 318 can be implemented by one or more DDR memories, such as DDR, DDR2, DDR3, DDR4, mDDR, etc.

[0081] In additional or alternative examples, the example memory 318 can be implemented by one or more mass storage devices, such as a hard drive, an optical drive, a digital versatile disk drive, a solid-state drive, etc. Although the memory 318 is illustrated as a single database in the illustrated example, the memory 318 can be implemented by any number and / or type of databases. Furthermore, the data stored in the memory 318 can be in any data format, such as binary data, comma-delimited data, tab-delimited data, SQL structures, etc.

[0082] Figure 4 It is an explanation Figure 1 Timing diagram 400 of example channel hopping with different dwell times for a parent device in network 100. Figure 4 In the example of , the example child device 402 is synchronized with the first example parent device 404. Figure 4 In the example of , the child device 402 is out of sync with the second example parent device 406. Figure 4 In the example, first parent device 404 and second parent device 406 utilize different dwell times. Therefore, the channel hopping sequence of first parent device 404 overlaps with the channel hopping sequence of second parent device 406. Due to the different dwell times, the probability of child device 402 being tuned to the same channel as second parent device 406 increases. For example, first example time slot 408 of the channel hopping sequence of first parent device 404 overlaps with second example time slot 410 of the channel hopping sequence of second parent device 406. Furthermore, during first time slot 408, the receiver circuitry of child device 402 is tuned to channel "4," and during second time slot 410, the transmitter circuitry of second parent device 406 is tuned to channel "4." Therefore, during the period of overlap between first time slot 408 and second time slot 410, child device 402 can detect communications from second parent device 406 and determine whether child device 402 has a stronger connection to second parent device 406 than first parent device 404 does to the second parent device.

[0083] In addition, by dynamically modifying the dwell time through the channel hopping sequence, the example parent device further increases the probability that the child device will detect communications from a parent device with which the child device is not synchronized. For example, each parent device may include a DWELL_TIME_SWITCH parameter that defines the period (in time slots) after which each parent device is to alternate dwell times. For example, the example synchronization information illustrated in Table 1 above indicates that the parent device (e.g., parent device 200) will alternate between a dwell time of 50 ms and 250 ms every 50 time slots. In the example of Table 1, the parent device (e.g., parent device 200) will use a dwell time of 50 ms for time slots 0-49, 100-149, 200-249, etc., and will use a dwell time of 250 ms for time slots 50-99, 150-199, etc. The number of dwell times utilized by the parent device can vary from two different dwell times to any N different dwell times.

[0084] Figure 5 It is an explanation Figure 1 A timing diagram 500 of example channel hopping for an example child device 502 and an example parent device 504 in a sleep mode of operation in a network 100 of FIG. Figure 5 In the example of FIG, child device 502 is synchronized with parent device 504, and child device 502 is utilizing CSL. For example, during a period when child device 502 is not scheduled to exchange data with parent device 504, child device 502 switches from the awake mode of operation to the sleep mode of operation (e.g., the interface circuitry of child device 502 is turned off). Additionally, during a period when child device 502 is scheduled to exchange data with parent device 504, child device 502 switches from the sleep mode of operation to the awake mode of operation (e.g., the interface circuitry of child device 502 is turned on).

[0085] exist Figure 5 In the illustrated example, when child device 502 switches to the awake mode of operation, child device 502 tunes to the specific channel that parent device 504 intends to operate in. For example, if child device 502 will receive data during example scheduled awake period 506, child device 502 tunes the receiver circuitry of child device 502 to the channel that the transmitter circuitry of parent device 504 intends to operate in. Additionally, for example, if child device 502 will transmit data during example scheduled awake period 506, child device 502 tunes the transmitter circuitry of child device 502 to the channel that the receiver circuitry of parent device 504 intends to operate in.

[0086] exist Figure 5In the illustrated example, if the example data exchange 508 between the child device 502 and the parent device 504 exceeds the duration of the scheduled awake period 506 (e.g., the time slot duration), the child device 502 and the parent device 504 will continue to operate in the channel to which the devices (e.g., the child device 502 and the parent device 504) were tuned at the beginning of the scheduled awake period 506. Thus, the example data exchange 508 during the scheduled awake period 506 occurs in the same channel. In other words, the child device 502 and the parent device 504 can be configured to communicate on a single channel to complete the entire data exchange 508 that will occur during the scheduled awake period 506. Additionally, Figure 5 In an example of , if the start of the scheduled awake period 506 is within a threshold amount of time of a transition on a channel on the parent device 504, the child device 502 and the parent device 504 may be configured to utilize the next channel in the channel hopping sequence for the scheduled awake period 506. In such an example, the child device 502 and the parent device 504 may be configured to communicate on the next channel during the scheduled awake period 506 based on (e.g., in response to) determining that the scheduled transition to the next channel will occur less than the threshold amount of time from the start of the scheduled awake period 506. Thus, the examples described herein enable channel hopping utilizing CSL-capable devices.

[0087] Although Figure 2 Description Figure 2 Example implementation of the parent device 200, but Figure 2 One or more elements, procedures and / or devices described in the may be combined, divided, rearranged, omitted, removed and / or implemented in any other manner. Figure 3 Description Figure 3 Example implementation of the sub-device 300, but Figure 3 One or more elements, procedures and / or means described in the examples may be combined, divided, rearranged, omitted, removed and / or implemented in any other manner. In addition, the example processing circuitry 202, the example communication control circuitry 204, the example channel timing circuitry 206, the example counter circuitry 208, the example antenna 210, the example interface circuitry 212, the example transmitter circuitry 214, the example receiver circuitry 216, the example memory 218, and / or more generally Figure 2 The example parent device 200 and / or the example processing circuitry 302, the example communication control circuitry 304, the example channel timing circuitry 306, the example counter circuitry 308, the example antenna 310, the example interface circuitry 312, the example transmitter circuitry 314, the example receiver circuitry 316, the example memory 318, and / or more generally Figure 3The example sub-assembly 300 may be implemented in hardware alone or in combination with software and / or firmware. Thus, for example, the example communication control circuitry 204, the example channel timing circuitry 206, the example counter circuitry 208, and / or more generally Figure 2 The example processing circuitry 202 and / or the example communication control circuitry 304, the example channel timing circuitry 306, the example counter circuitry 308, and / or more generally Figure 3 Any of the example processing circuit systems 302 may be implemented by processing circuit systems in combination with machine-readable instructions (e.g., firmware or software), processor circuit systems, analog circuits, digital circuits, logic circuits, programmable processors, programmable microcontrollers, graphics processing units (GPUs), digital signal processors (DSPs), ASICs, programmable logic devices (PLDs), and / or field programmable logic devices (FPLDs) (e.g., FPGAs). Still further, Figure 2 The example parent device 200 may include one or more elements, processes and / or devices as Figure 2 The components, processes and / or devices described may be in addition to or in place of those described, and / or may include more than one of any or all of the described components, processes and devices. Figure 3 The example sub-device 300 may include one or more elements, processes and / or devices as Figure 3 The elements, processes and / or devices described may be in addition to or instead of those described, and / or may include more than one of any or all of the described elements, processes and devices.

[0088] Figure 6 、 7 , 10 and / or 11 show representations that may be executed by processing circuitry to implement and / or instantiate Figure 2 Example machine-readable instructions (eg, instructions that cause a processing circuitry to perform actions) and / or representations of the parent device 200 may be implemented by the processing circuitry to implement and / or instantiate Figure 2 Flowchart of example operations of the parent device 200. In addition, Figure 8 、 9 and / or 12 illustrate representations that may be executed by processing circuitry to implement and / or instantiate Figure 3 Example machine-readable instructions (eg, instructions that cause a processing circuit system to perform actions) and / or representations of sub-device 300 may be implemented by a processing circuit system to implement and / or instantiate Figure 3 The machine readable instructions may be for example, in conjunction with Figure 13 The processing circuitry 1312 shown in the example processing circuitry platform 1300 described below in conjunction with Figure 14The processing circuitry 1412 shown in the example processing circuitry platform 1400 described may execute one or more executable programs or portions of one or more executable programs, and / or may be described below in conjunction with Figure 15 In some examples, machine-readable instructions enable operations, tasks, and the like to be performed and / or executed in an automated manner in the real world. As used herein, "automatic" means without human intervention.

[0089] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical disks (e.g., Blu-ray Discs, compact disks (CDs), digital versatile disks (DVDs), etc.), redundant arrays of independent disks (RAIDs), registers, ROM, solid-state drives (SSDs), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM), etc.), and / or any other storage device or storage disk. The instructions of the non-transitory computer-readable and / or machine-readable media may be programmed and / or executed by processing circuitry located in one or more hardware devices, but the entire program and / or portions of the program may alternatively be executed and / or instantiated by one or more hardware devices other than the processing circuitry and / or embodied in dedicated hardware. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between the server and the endpoint client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media. Additionally, although reference is made to Figure 6 、 7 , 10 and / or 11 illustrate example procedures, but may alternatively be implemented using Figure 2 Many other methods of the example parent device 200. In addition, although reference is made to Figure 8 、 9 The flowcharts illustrated in and / or 12 describe example procedures, but may alternatively be implemented using Figure 3Many other methods of the example sub-device 300 of the present invention are provided. For example, the order of execution of the blocks of the flowchart can be changed, and / or some of the described blocks can be changed, removed, or combined. Additionally or alternatively, any or all blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are structured to perform the corresponding operations without executing software or firmware. The processing circuitry can be distributed across different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.). For example, the processing circuitry can be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., and / or any combination thereof. An example XPU may be implemented by a heterogeneous computing system that includes multiple types of processing circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more network processing units (NPUs), one or more DSPs, etc., and / or any combination thereof) and orchestration technology (e.g., an application programming interface (API)) that can distribute computing tasks to any one or more of the multiple types of processing circuitry in the multiple types of programmable circuitry that are suitable and available to perform the computing tasks.

[0090] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, and the like. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or a data structure (e.g., a portion of an instruction, code, a representation of code, etc.), which may be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located in the same or different locations (e.g., in the cloud, on an edge device, etc.) on a network or collection of networks. The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, decapsulation, distribution, redistribution, compilation, and the like in order to make them directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, machine-readable instructions may be stored in multiple portions that are individually compressed, encrypted, and / or stored on separate computing devices, where the portions, when decrypted, decompressed, and / or combined, form a set of machine-executable and / or machine-executable instructions that implement one or more functions and / or operations that may together form, for example, the programs described herein.

[0091] In another example, the machine-readable instructions may be stored in a state where they can be read by the processing circuitry, but a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc. may need to be added in order for the machine-readable instructions to be executed on a particular computing device or another device. In another example, the machine-readable instructions and / or corresponding program may need to be configured (e.g., stored settings, data inputs, recorded network addresses, etc.) before they can be executed in whole or in part. Therefore, as used herein, machine-readable, computer-readable, and / or machine-readable media may contain instructions and / or programs regardless of the specific format or state of the machine-readable instructions and / or programs.

[0092] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0093] As mentioned above, Figure 6 、 7The example operations of , 8, 9, 10, 11 and / or 12 can be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium and / or non-transitory machine-readable storage medium are expressly defined to include any type of computer-readable storage device and / or storage disk, and exclude propagation signals and exclude transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media and / or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memories, read-only memories (ROMs), CDs, DVDs, cache memories, any type of RAM, registers, and / or any other storage devices or storage disks in which information is stored for any duration (e.g., for an extended period, permanently, temporarily, temporarily buffered and / or cached information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware to retain information over a period of time, but to exclude propagating signals and to exclude transmission media. Examples of non-transitory computer-readable storage devices and non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical and / or electrical device, hardware, and / or circuitry, that may or may not be configured by computer-readable instructions, machine-readable instructions, etc., and / or manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0094] "Including" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim uses any form of "includes" or "comprising" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within any type of claim recitation, it should be understood that additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or recitation. As used herein, the phrase "at least" when used as a transition term, such as in the preamble of a claim, is open-ended in the same manner as the terms "includes" and "comprising" are open-ended.

[0095] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude plural references. As used herein, the term "a" or "an" object refers to one or more of the objects described. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different examples or claims, these features may be combined, and their inclusion in different examples or claims does not imply that a combination of features is not feasible and / or disadvantageous.

[0096] Figure 6 Yes means you can use Figure 2 The example machine-readable instructions and / or example operations 600 are executed, instantiated, and / or implemented by an example processing circuitry embodiment of a parent device 200 to implement channel hopping across multiple frequency bands. The example machine-readable instructions and / or example operations 600 as described may be implemented by a parent device (e.g., parent device 200). Figure 6 The example machine-readable instructions and / or example operations 600 begin at block 602, where the interface circuitry 212 receives a discovery request from a candidate sub-device. For example, at block 602, the receiver circuitry 216 receives the discovery request from the candidate sub-device. As described above, the discovery request identifies a specific channel to which the interface circuitry of the candidate sub-device is to tune within a predetermined period of time.

[0097] exist Figure 6 In the illustrated example, at block 604, the processing circuitry 202 causes a response to the discovery request to be sent, the response including synchronization information. For example, at block 604, the communication control circuitry 204 causes a response to the discovery request to be sent via the interface circuitry 212, the response including synchronization information. Figure 6 In an example of , the communication control circuitry 204 causes a response to the discovery request to be sent in the channel identified by the discovery request. Example synchronization information includes data identifying: a base frequency band of the parent device 200, an alternative frequency band of the parent device 200, a first time period (in time slots) after which to switch from the base frequency band to the alternative frequency band, and a second time period (in time slots) after which to switch from the alternative frequency band to the base frequency band.

[0098] exist Figure 6 In the illustrated example, at block 606, the processing circuitry 202 performs channel hopping in the base frequency band. For example, Figure 7 Yes means you can use Figure 2The example processing circuitry implementation of the parent device 200 is executed, instantiated, and / or implemented to implement channel hopping in a base frequency band, and / or a flowchart of example machine-readable instructions and / or example operations 700. The example operations in the channel and / or frequency band generally include data exchange and / or other communications between the parent device 200 and a child device of the parent device 200. For example, the data exchange and / or other communications are implemented in a normal manner (e.g., the devices send data packets and / or acknowledged packets between each other, and the parent device 200 sends timing elements (e.g., timing packets) to the child device to facilitate synchronization). Figure 6 In the example of , at block 608, processing circuitry 202 determines whether the first time period has expired. For example, at block 608, channel timing circuitry 206 determines whether the first time period after which the switch from the base frequency band to the alternate frequency band is to be made has expired based on one or more counters of counter circuitry 208. Based on (e.g., in response to) processing circuitry 202 determining that the first time period has not expired (block 608: No), machine-readable instructions and / or operations 600 return to block 606. Based on (e.g., in response to) processing circuitry 202 determining that the first time period has expired (block 608: Yes), machine-readable instructions and / or operations 600 continue to block 610.

[0099] exist Figure 6 In the illustrated example, at block 610, processing circuitry 202 tunes interface circuitry 212 of parent device 200 to the alternative frequency band. For example, at block 610, communication control circuitry 204 tunes interface circuitry 212 of parent device 200 to the alternative frequency band. At block 612, processing circuitry 202 operates in the alternative frequency band. For example, at block 612, communication control circuitry 204 operates in the alternative frequency band. As described above, example operations include data exchange and / or other communications between parent device 200 and a child device of parent device 200 (e.g., the devices sending data packets and / or acknowledgement packets between each other, and parent device 200 sending timing elements (e.g., timing packets) to the child device to facilitate synchronization). At block 614, processing circuitry 202 determines whether the second time period has expired. For example, at block 614 , the channel timing circuitry 206 determines whether a second time period after which to switch from the alternate frequency band to the base frequency band has expired based on one or more counters of the counter circuitry 208 .

[0100] exist Figure 6In the illustrated example, based on (e.g., in response to) the processing circuitry 202 determining that the second time period has not expired (block 614: No), the machine-readable instructions and / or operations 600 return to block 612. Based on (e.g., in response to) the processing circuitry 202 determining that the second time period has expired (block 614: Yes), the machine-readable instructions and / or operations 600 continue to block 616. At block 616, the processing circuitry 202 tunes the interface circuitry 212 of the parent device 200 to the base frequency band. For example, at block 616, the communication control circuitry 204 tunes the interface circuitry 212 of the parent device 200 to the base frequency band.

[0101] exist Figure 6 In the illustrated example, at block 618, processing circuitry 202 determines whether to continue operation. For example, at block 618, communications control circuitry 204 determines whether to continue operation based on whether parent device 200 is powered. Based on (e.g., in response to) processing circuitry 202 determining that parent device 200 will continue operation (block 618: Yes), machine-readable instructions and / or operations 600 return to block 606. Based on (e.g., in response to) processing circuitry 202 determining that parent device 200 will not continue operation (block 618: No), machine-readable instructions and / or operations 600 terminate.

[0102] Figure 7 Yes means you can use Figure 2 Flowchart of example machine readable instructions and / or example operations 700 to be executed, instantiated, and / or implemented by an example processing circuitry embodiment of a parent device 200 to implement channel hopping in a base frequency band. The example machine readable instructions and / or example operations 700 as described may be implemented by a parent device (e.g., parent device 200). As described above, the example machine readable instructions and / or example operations 700 may be executed, instantiated, and / or implemented. Figure 7 Example machine readable instructions and / or example operations 700 to implement Figure 6 Block 606 of the example machine readable instructions and / or example operations 600 . Figure 7 The example machine-readable instructions and / or example operations 700 begin at block 702, where the processing circuitry 202 tunes the interface circuitry 212 of the parent device 200 to a first channel in a base frequency band. For example, at block 702, the communication control circuitry 204 tunes the interface circuitry 212 of the parent device 200 to a first channel in a base frequency band.

[0103] exist Figure 7In the illustrated example, at block 704, processing circuitry 202 operates in a first channel. For example, at block 704, communication control circuitry 204 operates in the first channel. As described above, example operations include data exchange and / or other communications between parent device 200 and a child device of parent device 200 (e.g., the devices sending data packets and / or acknowledgement packets between each other, and parent device 200 sending timing elements (e.g., timing packets) to the child device to facilitate synchronization). At block 706, processing circuitry 202 determines whether a first dwell time of parent device 200 has expired. For example, at block 706, channel timing circuitry 206 determines whether the first dwell time of parent device 200 has expired based on one or more counters of counter circuitry 208. Based on (e.g., in response to) processing circuitry 202 determining that the first dwell time has not expired (block 706: No), machine-readable instructions and / or operations 700 return to block 704. For example, based on (e.g., in response to) the processing circuitry 202 (e.g., channel timing circuitry 206) determining at block 706 that the first dwell time has not expired, the processing circuitry 202 (e.g., communication control circuitry 204) may be configured to continue operating in the first channel at block 704. Based on (e.g., in response to) the processing circuitry 202 determining that the first dwell time has expired (block 706: YES), the machine-readable instructions and / or operations 700 continue to block 708.

[0104] exist Figure 7 In the illustrated example, at block 708, the processing circuitry 202 determines whether the first data exchange in the first channel has completed. For example, at block 708, the communications control circuitry 204 determines whether the first data exchange in the first channel has completed. Based on (e.g., in response to) the processing circuitry 202 determining that the first data exchange in the first channel has not completed (block 708: No), the machine-readable instructions and / or operations 700 return to block 704. For example, based on (e.g., in response to) the processing circuitry 202 (e.g., communications control circuitry 204) determining at block 708 that the first data exchange in the first channel has not completed, the processing circuitry 202 (e.g., communications control circuitry 204) may be configured to continue operating in the first channel at block 704. Based on (e.g., in response to) the processing circuitry 202 determining that the first data exchange in the first channel has completed (block 708: Yes), the machine-readable instructions and / or operations 700 continue to block 710. Figure 7 In the illustrated example, processing circuitry 202 tunes interface circuitry 212 of parent device 200 to a second channel in the base frequency band at block 710. For example, communication control circuitry 204 tunes interface circuitry 212 of parent device 200 to a second channel in the base frequency band at block 710.

[0105] exist Figure 7 In the illustrated example, at block 712, processing circuitry 202 determines whether the period after which parent device 200 is to alternate dwell times has expired. For example, at block 712, channel timing circuitry 206 determines whether the period after which parent device 200 is to alternate dwell times has expired. Based on (e.g., in response to) processing circuitry 202 determining that the period after which parent device 200 is to alternate dwell times has not expired (block 712: No), machine-readable instructions and / or operations 700 proceed to block 714. Based on (e.g., in response to) processing circuitry 202 determining that the period after which parent device 200 is to alternate dwell times has expired (block 712: Yes), machine-readable instructions and / or operations 700 proceed to block 720.

[0106] exist Figure 7 In the illustrated example, at block 714, processing circuitry 202 operates in the second channel. For example, at block 714, communication control circuitry 204 operates in the second channel. As described above, example operations include data exchange and / or other communications between parent device 200 and a child device of parent device 200 (e.g., the devices sending data packets and / or acknowledgement packets between each other, and parent device 200 sending timing elements (e.g., timing packets) to the child device to facilitate synchronization). At block 716, processing circuitry 202 determines whether a first dwell time of parent device 200 has expired. For example, at block 716, channel timing circuitry 206 determines whether the first dwell time of parent device 200 has expired based on one or more counters of counter circuitry 208. Based on (e.g., in response to) processing circuitry 202 determining that the first dwell time has not expired (block 716: No), machine-readable instructions and / or operations 700 return to block 714. Based on (eg, in response to) the processing circuitry 202 determining that the first dwell time has expired (block 716 : YES), the machine readable instructions and / or operations 700 continue to block 718 .

[0107] exist Figure 7 In the illustrated example, at block 718, the processing circuitry 202 determines whether the second data exchange in the second channel has completed. For example, at block 718, the communication control circuitry 204 determines whether the second data exchange in the second channel has completed. Based on (e.g., in response to) the processing circuitry 202 determining that the second data exchange in the second channel has not completed (block 718: No), the machine-readable instructions and / or operations 700 return to block 714. Based on (e.g., in response to) the processing circuitry 202 determining that the second data exchange in the second channel has completed (block 718: Yes), the machine-readable instructions and / or operations 700 return to block 608 of the machine-readable instructions and / or operations 600.

[0108] exist Figure 7 In the illustrated example, at block 720, processing circuitry 202 utilizes a second dwell time for parent device 200 based on the expiration of the time period after which parent device 200 is to alternate dwell times. For example, at block 720, channel timing circuitry 206 utilizes the second dwell time for parent device 200 based on the expiration of the time period after which parent device 200 is to alternate dwell times. At block 722, processing circuitry 202 operates in the second channel. For example, at block 722, communication control circuitry 204 operates in the second channel. As described above, example operations include data exchange and / or other communications between parent device 200 and a child device of parent device 200 (e.g., the devices sending data packets and / or acknowledgement packets between each other, and the parent device 200 sending timing elements (e.g., timing packets) to the child device to facilitate synchronization). At block 724, processing circuitry 202 determines whether the second dwell time for parent device 200 has expired. For example, at block 724 , the channel timing circuitry 206 determines whether the second dwell time of the parent device 200 has expired based on one or more counters of the counter circuitry 208 .

[0109] exist Figure 7 In the illustrated example, based on (e.g., in response to) the processing circuitry 202 determining that the second dwell time has not expired (block 724: No), the machine-readable instructions and / or operations 700 return to block 722. Based on (e.g., in response to) the processing circuitry 202 determining that the second dwell time has expired (block 724: Yes), the machine-readable instructions and / or operations 700 continue to block 726. At block 726, the processing circuitry 202 determines whether the third data exchange in the second channel has completed. For example, at block 726, the communication control circuitry 204 determines whether the third data exchange in the second channel has completed. Based on (e.g., in response to) the processing circuitry 202 determining that the third data exchange in the second channel has not completed (block 726: No), the machine-readable instructions and / or operations 700 return to block 722. Based on (eg, in response to) the processing circuitry 202 determining that the third data exchange in the second channel is complete (block 726 : YES), the machine-readable instructions and / or operations 700 return to block 608 of the machine-readable instructions and / or operations 600 .

[0110] Figure 8 Yes means you can use Figure 3 Flowchart of example machine-readable instructions and / or example operations 800 executed, instantiated, and / or implemented by an example processing circuitry embodiment of a child device 300 to synchronize with an example parent device. The example machine-readable instructions and / or example operations 800 as described may be implemented by a child device (e.g., child device 300). Figure 8The example machine-readable instructions and / or example operations 800 begin at block 802, where the processing circuitry 302 causes one or more discovery requests to be sent to one or more candidate parent devices. For example, at block 802, the communication control circuitry 304 causes one or more discovery requests to be sent to one or more candidate parent devices. The example discovery request includes information identifying a channel to which the communication control circuitry 304 will tune the interface circuitry 312 for a predetermined period of time.

[0111] exist Figure 8 In the illustrated example, at block 804, interface circuitry 312 receives one or more responses to one or more discovery requests from one or more candidate parent devices. For example, after causing the one or more discovery requests to be sent, communication control circuitry 304 tunes receiver circuitry 316 to the channel identified in the discovery request. Thus, at block 804, receiver circuitry 316 receives one or more responses to the one or more discovery requests from one or more candidate parent devices on the channel identified in the one or more discovery requests. At block 806, processing circuitry 302 selects a first parent device to synchronize with from the one or more candidate parent devices. For example, at block 806, communication control circuitry 304 selects a first parent device to synchronize with from the one or more candidate parent devices based on one or more connectivity metrics between child device 300 and the one or more candidate parent devices. Processing circuitry 302 may be configured to determine the one or more connectivity metrics based on, for example, the signal strength of each response received at block 804. Additionally or alternatively, each response may include an indication of a connectivity metric between child device 300 and the corresponding parent device.

[0112] exist Figure 8In the illustrated example, at block 808, processing circuitry 302 follows the channel hopping sequence of the first parent device in the primary frequency band of the first parent device. Example operations in the channel and / or frequency band generally include data exchange and / or other communications between the child device 300 and the parent device with which the child device 300 is synchronized. For example, data exchange and / or other communications are conducted in a normal manner (e.g., the devices send data packets and / or acknowledgement packets between each other, and the parent device with which the child device 300 is synchronized sends timing elements (e.g., timing packets) to the child device 300 to facilitate synchronization). At block 810, processing circuitry 302 determines whether a first time period after which the first parent device is to switch from the primary frequency band to the alternative frequency band has expired. For example, at block 810, channel timing circuitry 306 determines whether a first time period after which the first parent device is to switch from the primary frequency band to the alternative frequency band has expired. Based on (e.g., in response to) the processing circuitry 302 determining that the first time period has not expired (block 810: No), the machine-readable instructions and / or operations 800 return to block 808. Based on (e.g., in response to) the processing circuitry 302 determining that the first time period has expired (block 810: Yes), the machine-readable instructions and / or operations 800 continue to block 812.

[0113] exist Figure 8 In the illustrated example, at block 812, processing circuitry 302 tunes interface circuitry 312 of child device 300 to the alternative frequency band. For example, at block 812, communication control circuitry 304 tunes interface circuitry 312 of child device 300 to the alternative frequency band. At block 814, processing circuitry 302 operates in the alternative frequency band. For example, at block 814, communication control circuitry 304 operates in the alternative frequency band. As described above, example operations include data exchange and / or other communications between child device 300 and a parent device with which child device 300 is synchronized (e.g., the devices sending data packets and / or acknowledgement packets between each other, and the parent device with which child device 300 is synchronized sending timing elements (e.g., timing packets) to child device 300 to facilitate synchronization). At block 816, processing circuitry 302 determines whether a second time period, after which the first parent device is to switch from the alternative frequency band to the primary frequency band, has expired. For example, at block 816 , the channel timing circuitry 306 determines whether a second time period after which the first parent device is to switch from the alternate frequency band to the base frequency band has expired based on the one or more counters of the counter circuitry 308 .

[0114] exist Figure 8In the illustrated example, based on (e.g., in response to) the processing circuitry 302 determining that the second time period has not expired (block 816: No), the machine-readable instructions and / or operations 800 return to block 814. Based on (e.g., in response to) the processing circuitry 302 determining that the second time period has expired (block 816: Yes), the machine-readable instructions and / or operations 800 continue to block 818. At block 818, the processing circuitry 302 tunes the interface circuitry 312 of the sub-device 300 to the base frequency band. For example, at block 818, the communication control circuitry 304 tunes the interface circuitry 312 of the sub-device 300 to the base frequency band.

[0115] exist Figure 8 In the illustrated example, at block 820, processing circuitry 302 determines whether to continue operation. For example, at block 820, communications control circuitry 304 determines whether to continue operation based on whether sub-device 300 is powered. Based on (e.g., in response to) processing circuitry 302 determining that sub-device 300 will continue operation (block 820: Yes), machine-readable instructions and / or operations 800 return to block 808. For example, after determining at block 820 that sub-device 300 will continue operation, processing circuitry 302 may be configured to follow the channel hopping sequence of the first parent device at block 808. Based on (e.g., in response to) processing circuitry 302 determining that sub-device 300 will not continue operation (block 820: No), machine-readable instructions and / or operations 800 terminate.

[0116] Figure 9 Yes means you can use Figure 3 The example machine-readable instructions and / or example operations 900 are executed, instantiated, and / or implemented by an example processing circuitry embodiment of a sub-device 300 to implement coordinated sampling and sensing with channel hopping. The example machine-readable instructions and / or example operations 900 as described may be implemented by a sub-device (e.g., sub-device 300). Figure 9 The example machine readable instructions and / or example operations 900 begin at block 902, where the processing circuitry 302 places the sub-device 300 in a sleep mode of operation. For example, at block 902, the communication control circuitry 304 places the sub-device 300 in a sleep mode of operation by disconnecting the interface circuitry 312.

[0117] exist Figure 9In the illustrated example, at block 904, processing circuitry 302 determines a time after which the device is placed in the awake mode of operation. For example, at block 904, channel timing circuitry 306 determines a time after which the device is placed in the awake mode of operation. At block 906, processing circuitry 302 determines whether the time has occurred. For example, at block 906, channel timing circuitry 306 determines whether the time has occurred based on one or more counters of counter circuitry 308. Based on (e.g., in response to) processing circuitry 302 determining that the time has not occurred (block 906: No), machine-readable instructions and / or operations 900 return to block 906. Based on (e.g., in response to) processing circuitry 302 determining that the time has occurred (block 906: Yes), machine-readable instructions and / or operations 900 continue to block 908.

[0118] exist Figure 9 In the illustrated example, at block 908, processing circuitry 302 tunes interface circuitry 312 of child device 300 to the channel in which the parent device is expected to operate, synchronizing child device 300 with the parent device. For example, at block 908, communication control circuitry 304 tunes interface circuitry 312 of child device 300 to the channel in which the parent device is expected to operate during the awake period of child device 300, synchronizing child device 300 with the parent device. At block 910, processing circuitry 302 operates in the channel. For example, at block 910, communication control circuitry 204 operates in the channel during the awake period of child device 300. As described above, example operations include data exchange and / or other communications between child device 300 and the parent device with which child device 300 is synchronized (e.g., the devices sending data packets and / or acknowledgement packets between each other, and the parent device with which child device 300 is synchronized sending timing elements (e.g., timing packets) to child device 300 to facilitate synchronization). The above about Figure 5 An example of a wake-up period is described in conjunction with blocks 908 and 910. At block 912, processing circuitry 302 determines whether a dwell time of the parent device has expired. For example, at block 912, channel timing circuitry 306 determines whether a dwell time of the parent device has expired based on one or more counters of counter circuitry 308.

[0119] exist Figure 9In the illustrated example, based on (e.g., in response to) the processing circuitry 302 determining that the dwell time has not expired (block 912: No), the machine-readable instructions and / or operations 900 return to block 910. Based on (e.g., in response to) the processing circuitry 302 determining that the dwell time has expired (block 912: Yes), the machine-readable instructions and / or operations 900 continue to block 914. At block 914, the processing circuitry 302 determines whether the data exchange in the channel has completed. For example, at block 914, the communication control circuitry 304 determines whether the data exchange in the channel has completed. Based on (e.g., in response to) the processing circuitry 302 determining that the data exchange in the channel has not completed (block 914: No), the machine-readable instructions and / or operations 900 return to block 910. Based on (e.g., in response to) the processing circuitry 302 determining that the data exchange in the channel has completed (block 914: Yes), the machine-readable instructions and / or operations 900 continue to block 916.

[0120] exist Figure 9 In the illustrated example, at block 916, processing circuitry 302 determines whether to continue operation. For example, at block 916, communications control circuitry 304 determines whether to continue operation based on whether sub-device 300 is powered. Based on (e.g., in response to) processing circuitry 302 determining that sub-device 300 will continue operation (block 916: Yes), machine-readable instructions and / or operations 900 return to block 902. For example, after determining at block 916 that sub-device 300 will continue operation, processing circuitry 302 may be configured to place sub-device 300 in a sleep mode of operation at block 902. Based on (e.g., in response to) processing circuitry 302 determining that sub-device 300 will not continue operation (block 916: No), machine-readable instructions and / or operations 900 terminate.

[0121] Figure 10 Yes means you can use Figure 2 1000 to be executed, instantiated, and / or implemented by an example processing circuitry embodiment of a parent device 200 to utilize an alternate frequency band to assist a child device in performing parent selection. The example machine-readable instructions and / or example operations 1000, as described, may be implemented by a first parent device (e.g., parent device 200) that initially synchronizes with a child device. Figure 10 The example machine readable instructions and / or example operations 1000 begin at block 1002 where the processing circuitry 202 determines a connectivity metric for a child device that is synchronized with a first parent device. For example, at block 1002, the communication control circuitry 204 determines a connectivity metric for a child device that is synchronized with the parent device 200. Figure 10In the example of FIG. 1 , at block 1002, the communication control circuitry 204 determines a connectivity metric for the child device based on communications from the child device in a base frequency band (e.g., a sub-1 GHz frequency band) of the parent device 200. Example connectivity metrics include a single strength metric, an RSSI value, a BER value, and / or an LQI value.

[0122] exist Figure 10 In the illustrated example, at block 1004, the processing circuitry 202 causes the connectivity metric to be sent to the second parent device with which the child device is not synchronized. For example, at block 1004, the communication control circuitry 204 causes the connectivity metric to be sent to the second parent device with which the child device is not synchronized. Figure 10 In an example of a method of transmitting a signal to a second parent device in an alternate frequency band (e.g., a 2.4 GHz frequency band) at block 1004, the communication control circuitry 204 causes the second parent device to transmit a connectivity metric to the second parent device in an alternate frequency band (e.g., a 2.4 GHz frequency band) of the parent device 200. In some examples, at block 1004, the communication control circuitry 204 includes requesting the second parent device to determine a second connectivity metric representing connectivity between the second parent device and the child device using the connectivity metric. At block 1006, the processing circuitry 202 determines whether a first communication has been received (e.g., from the second parent device) indicating that the child device has stronger connectivity with the second parent device than the first parent device has with the second parent device. For example, at block 1006, the communication control circuitry 204 determines whether a first communication has been received indicating that the child device has stronger connectivity with the second parent device than the first parent device has with the second parent device. For example, the receiver circuitry 216 may receive the first communication in the alternate frequency band (e.g., a 2.4 GHz frequency band) of the parent device 200.

[0123] exist Figure 10 In the illustrated example, based on (e.g., in response to) the processing circuitry 202 determining that the first communication has not been received (block 1006: No), the first communication indicates that the child device has stronger connectivity with the second parent device than the first parent device has with the second parent device, and the machine-readable instructions and / or operations 1000 return to block 1002. Accordingly, the first parent device may be configured to maintain synchronization with the child device based on (e.g., in response to) not receiving a response from the second parent device (e.g., within a threshold amount of time). Additionally or alternatively, the first parent device may be configured to maintain synchronization with the child device based on (e.g., in response to) receiving the first communication from the second parent device indicating that the second parent device has a weaker connection with the child device than the first child device has with the child device. Based on (e.g., in response to) the processing circuitry 202 determining that the first communication has been received (block 1006: Yes), the first communication indicates that the child device has stronger connectivity with the second parent device than the first parent device has with the second parent device, and the machine-readable instructions and / or operations 1000 continue to block 1008.

[0124] exist Figure 10 In the illustrated example, at block 1008, processing circuitry 202 causes a second communication to be sent to the child device, the second communication indicating that the child device is to desynchronize with the first parent device and synchronize with the second parent device. For example, at block 1008, communication control circuitry 204 causes a second communication to be sent to the child device, the second communication indicating that the child device is to desynchronize with the first parent device and synchronize with the second parent device. Figure 10 In the example of FIG. 1 , at block 1008, communication control circuitry 204 causes a second communication to be sent to the child device in a base frequency band (e.g., a sub-1 GHz frequency band) of parent device 200. At block 1010, processing circuitry 202 determines whether to continue operation. For example, at block 1010, communication control circuitry 204 determines whether to continue operation based on whether parent device 200 is powered. Based on (e.g., in response to) processing circuitry 202 determining that parent device 200 will continue operation (block 1010: Yes), machine-readable instructions and / or operations 1000 return to block 1002. Based on (e.g., in response to) processing circuitry 202 determining that parent device 200 will not continue operation (block 1010: No), machine-readable instructions and / or operations 1000 terminate.

[0125] Figure 11 Yes means you can use Figure 2 100 is a flowchart of example machine-readable instructions and / or example operations 1100 to be executed, instantiated, and / or performed by an example processing circuitry embodiment of a parent device 200 to utilize an alternate frequency band to assist a child device in performing parent selection. The example machine-readable instructions and / or example operations 1100 as described may be implemented by a second parent device (e.g., parent device 200) that is not initially synchronized with the child device. Figure 11 The example machine-readable instructions and / or example operations 1100 begin at block 1102, where the interface circuitry 212 receives a first connectivity metric representing a first connectivity between a first parent device and a child device synchronized with the first parent device. For example, at block 1102, the receiver circuitry 216 receives a first connectivity metric representing a first connectivity between the first parent device and the child device synchronized with the first parent device. Figure 11 In the example of , at block 1102 , the receiver circuitry 216 receives a first connectivity metric in an alternative frequency band (eg, a 2.4 GHz frequency band) of the parent device 200 .

[0126] exist Figure 11In the illustrated example, at block 1104, the processing circuitry 202 detects a first communication from a child device at the second parent device, the child device being out of sync with the second parent device. For example, at block 1104, the communication control circuitry 204 detects a first communication from a child device at the second parent device, the child device being out of sync with the second parent device. Figure 11 In the example of , at block 1106, the communication control circuitry 204 detects a first communication from the child device in a base frequency band (e.g., a sub-1 GHz frequency band) of the parent device 200. At block 1106, the processing circuitry 202 determines a second connectivity metric for the child device, the second connectivity metric representing a second connectivity between the second parent device and the child device. For example, at block 1106, the communication control circuitry 204 determines a second connectivity metric for the child device, the second connectivity metric representing a second connectivity between the second parent device and the child device. Figure 11 In an example of , the communication control circuitry 204 may be configured to determine a second connectivity metric based on the signal strength and / or other characteristics of the first communication detected at block 1104 .

[0127] exist Figure 11 In the illustrated example, at block 1108, processing circuitry 202 determines whether the second connectivity between the second parent device and the child device is better than the first connectivity between the first parent device and the child device. For example, at block 1108, communication control circuitry 204 determines whether the second connectivity between the second parent device and the child device is better than the first connectivity between the first parent device and the child device. Based on (e.g., in response to) processing circuitry 202 determining that the second connectivity is not better than the first connectivity (block 1108: No), machine-readable instructions and / or operations 1100 return to block 1102. For example, based on processing circuitry 202 determining that the second connectivity is not better than the first connectivity, parent device 200 may be configured to avoid (e.g., for a threshold amount of time) attempting to synchronize with the child device. Based on (e.g., in response to) processing circuitry 202 determining that the second connectivity is better than the first connectivity (block 1108: Yes), machine-readable instructions and / or operations 1100 continue to block 1110. For example, in blocks 1110 , 1112 , and 1114 , parent device 200 attempts to synchronize with the child device based on (eg, in response to) determining that the second connectivity is superior to the first connectivity.

[0128] exist Figure 11In the illustrated example, at block 1110, the processing circuitry 202 causes a second communication to be sent to the first parent device, the second communication indicating that the second parent device has better connectivity with the child device than the first parent device has with the child device. For example, at block 1110, the communication control circuitry 204 causes a second communication to be sent to the first parent device, the second communication indicating that the second parent device has better connectivity with the child device than the first parent device has with the child device. Figure 11 In the example of FIG. 1 , at block 1110, the communication control circuitry 204 causes a second communication to be sent to the first parent device in an alternate frequency band (e.g., a 2.4 GHz frequency band) of the parent device 200. In some examples, the second communication sent by the parent device 200 may include an indication of the second connectivity metric and / or an identification of the child device.

[0129] exist Figure 11 In the illustrated example, at block 1112, the interface circuitry 212 receives a discovery request from a sub-device. For example, at block 1112, the receiver circuitry 216 receives a discovery request from a sub-device. Figure 11 In an example, at block 1112, receiver circuitry 216 receives a discovery request from a child device in a base frequency band of parent device 200 (e.g., a frequency band below 1 GHz). In some examples, the discovery request received at block 1112 may include an indication of the first parent device. At block 1114, processing circuitry 202 causes a response to the discovery request to be sent. For example, communication control circuitry 204 causes a response to the discovery request to be sent. As described above, the example discovery request identifies a specific channel to which the interface circuitry of the child device will be tuned within a predetermined period of time. Therefore, at block 1114, communication control circuitry 204 causes a response to the discovery request to be sent in a channel identified in the discovery request. For example, the identified channel is in a base frequency band of parent device 200 (e.g., the same frequency band as the frequency band in which the discovery request was received at block 1112).

[0130] exist Figure 11 In the illustrated example, at block 1116, processing circuitry 202 determines whether to continue operation. For example, at block 1116, communications control circuitry 204 determines whether to continue operation based on whether parent device 200 is powered. Based on (e.g., in response to) processing circuitry 202 determining that parent device 200 will continue operation (block 1116: Yes), machine-readable instructions and / or operations 1100 return to block 1102. Based on (e.g., in response to) processing circuitry 202 determining that parent device 200 will not continue operation (block 1116: No), machine-readable instructions and / or operations 1100 terminate.

[0131] Figure 12 Yes means you can use Figure 3Flowchart of example machine-readable instructions and / or example operations 1200 for executing, instantiating, and / or implementing an example processing circuitry embodiment of a child device 300 to select a parent device. The example machine-readable instructions and / or example operations 1200 as described may be implemented by a child device (e.g., child device 300). Figure 12 Example machine-readable instructions and / or example operations 1200 begin at block 1202, where the interface circuitry 312 receives a communication indicating that a first parent device, with which the child device is not synchronized, has better connectivity to the child device than a second parent device, with which the child device is synchronized. For example, at block 1202, the receiver circuitry 316 receives a communication indicating that a first parent device, with which the child device is not synchronized, has better connectivity to the child device than a second parent device, with which the child device is synchronized. In some examples, the communication received at block 1202 includes an indication of the first parent device and / or an indication of one or more connectivity metrics. As described with respect to Figure 10 As described, child device 300 may receive communications from the second parent device. Alternatively, in some instances, child device 300 may receive communications from the first parent device.

[0132] exist Figure 12 In the illustrated example, at block 1204, the processing circuitry 302 causes a discovery request to be sent to the first parent device. For example, at block 1204, the communication control circuitry 304 causes a discovery request to be sent to the first parent device. In some examples, the discovery request may include an indication of the second parent device and / or an indication of a connectivity metric. Figure 12 In the example of , at block 1204, the communication control circuitry 304 causes a discovery request to be sent in the base frequency band. The example discovery request identifies a specific channel to which the interface circuitry 312 of the child device 300 is to be tuned within a predetermined period of time. At block 1206, the interface circuitry 312 receives a response to the discovery request from the first parent device. For example, at block 1206, the receiver circuitry 316 receives a response to the discovery request from the first parent device. Figure 12 In the example of , at block 1206 , the receiver circuitry 316 receives a response to the discovery request in a base frequency band (eg, the same frequency band as the frequency band in which the discovery request was sent at block 1204 ).

[0133] exist Figure 12In the illustrated example, at block 1208, processing circuitry 302 determines whether to continue operation. For example, at block 1208, communications control circuitry 304 determines whether to continue operation based on whether sub-device 300 is powered. Based on (e.g., in response to) processing circuitry 302 determining that sub-device 300 will continue operation (block 1208: Yes), machine-readable instructions and / or operations 1200 return to block 1202. Based on (e.g., in response to) processing circuitry 302 determining that sub-device 300 will not continue operation (block 1208: No), machine-readable instructions and / or operations 1200 terminate.

[0134] like Figure 10-12 As illustrated, since the parent device supports multiple frequency bands, the parent device can improve network operation. Thus, using the 2.4 GHz frequency band, the parent device can exchange information about the child device and / or other network details useful for operation of a sub-1 GHz network. For example, a first parent device (e.g., first dual-band router 104 A ) can send data to other parent devices (eg, the second dual-band router 104 B ) notifies the first parent device of connectivity metrics (e.g., RSSI values, BER values, and / or LQI values) of transmissions by any other device heard in the sub-1 GHz frequency band and of transmissions received by the device. Thus, if the first parent device identifies a synchronized child device having a first connectivity metric that is worse than a second connectivity metric between the synchronized child device and the second parent, the first parent device can notify the synchronized child device of the availability of the second parent device. Additionally or alternatively, if the first parent device identifies a first connectivity metric corresponding to the child device and reported to the first parent device by the second parent device that is better than the second connectivity metric between the child device and the second parent device (with which the second parent device is synchronized), the first parent device can notify the second parent device that the connectivity between the child device and the first parent device is stronger than the connectivity between the second parent device and the first parent device. Thus, the second parent device can notify the child device of the availability of the first parent device. After being notified of the availability of another parent device with which the child device has stronger connectivity, the child device can initiate a new discovery request to locate and join the other parent device if the child device makes a choice.

[0135] Figure 13 is structured to execute and / or instantiate Figure 6 、 7 , 10 and / or 11 example machine readable instructions and / or example operations to implement Figure 2 The processing circuit system platform 1300 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smartphone, an iPad, etc.). TMtablets, such as tablets), personal digital assistants (PDAs), internet appliances, DVD players, CD players, digital video recorders, Blu-ray players, game consoles, personal video recorders, set-top boxes, head-mounted devices (e.g., augmented reality (AR) headsets, virtual reality (VR) headsets, etc.) or other wearable devices, or any other type of computing and / or electronic device.

[0136] The processing circuitry platform 1300 of the illustrated example includes processing circuitry 1312. The processing circuitry 1312 of the illustrated example is hardware. For example, the processing circuitry 1312 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The processing circuitry 1312 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the processing circuitry 1312 implements the example communication control circuitry 204, the example channel timing circuitry 206, and the example counter circuitry 208.

[0137] The processing circuitry 1312 of the illustrated example includes a local memory 1313 (e.g., cache memory, registers, etc.). The processing circuitry 1312 of the illustrated example communicates with main memory 1314, 1316, including volatile memory 1314 and non-volatile memory 1316, via a bus 1318. The volatile memory 1314 may be comprised of synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), Dynamic Random Access Memory 1316. The non-volatile memory 1316 may be implemented by flash memory and / or any other desired type of memory device. In this example, one or more of the volatile memory 1314 or the non-volatile memory 1316 implements the example memory 218. Access to the main memories 1314, 1316 of the illustrated example is controlled by a memory controller 1317. In some examples, the memory controller 1317 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data to and from the main memories 1314, 1316.

[0138] The processing circuitry platform 1300 of the illustrated example also includes an interface circuitry 1320. The interface circuitry 1320 may be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0139] In the illustrated example, one or more input devices 1322 are connected to the interface circuitry 1320. The input devices 1322 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the processing circuitry 1312. The input devices 1322 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, an isochronous device, and / or a speech recognition system.

[0140] One or more output devices 1324 are also connected to the interface circuitry 1320 of the illustrated example. Output devices 1324 may be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Thus, the interface circuitry 1320 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuitry such as a GPU.

[0141] The interface circuitry 1320 of the illustrated example also includes a communication device, such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and / or a network interface, to facilitate exchanging data with an external machine (e.g., any type of computing device) over a network 1326. Communication can occur over, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc. In this example, the interface circuitry 1320 implements the example antenna 210, the example transmitter circuitry 214, and the example receiver circuitry 216.

[0142] The processing circuitry platform 1300 of the illustrated example also includes one or more mass storage disks or devices 1328 to store firmware, software, and / or data. Examples of such mass storage disks or devices 1328 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs.

[0143] Can be achieved through Figure 6 、 7, 10 and / or 11 may be stored in a mass storage device 1328, in a volatile memory 1314, in a non-volatile memory 1316 and / or on at least one non-transitory computer-readable storage medium that may be removable, such as a CD or DVD.

[0144] Figure 14 is structured to execute and / or instantiate Figure 8 、 9 and / or 12 example machine readable instructions and / or example operations to implement Figure 3 The processing circuit system platform 1400 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smart phone, an iPad, etc.). TM tablets, such as tablets), personal digital assistants (PDAs), internet appliances, DVD players, CD players, digital video recorders, Blu-ray players, game consoles, personal video recorders, set-top boxes, head-mounted devices (e.g., augmented reality (AR) headsets, virtual reality (VR) headsets, etc.) or other wearable devices, or any other type of computing and / or electronic device.

[0145] The processing circuitry platform 1400 of the illustrated example includes processing circuitry 1412. The processing circuitry 1412 of the illustrated example is hardware. For example, the processing circuitry 1412 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The processing circuitry 1412 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the processing circuitry 1412 implements the example communication control circuitry 304, the example channel timing circuitry 306, and the example counter circuitry 308.

[0146] The processing circuitry 1412 of the illustrated example includes a local memory 1413 (e.g., cache memory, registers, etc.). The processing circuitry 1412 of the illustrated example communicates with main memory 1414, 1416, including volatile memory 1414 and non-volatile memory 1416, via a bus 1418. The volatile memory 1414 may be comprised of synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), Dynamic Random Access Memory 1416. The non-volatile memory 1416 may be implemented by flash memory and / or any other desired type of memory device. In this example, one or more of the volatile memory 1414 or the non-volatile memory 1416 implements example memory 318. Access to the main memories 1414, 1416 of the illustrated example is controlled by a memory controller 1417. In some examples, the memory controller 1417 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data to and from the main memories 1414, 1416.

[0147] The processing circuitry platform 1400 of the illustrated example also includes an interface circuitry 1420. The interface circuitry 1420 may be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0148] In the illustrated example, one or more input devices 1422 are connected to the interface circuitry 1420. The input devices 1422 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the processing circuitry 1412. The input devices 1422 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, an isochronous device, and / or a speech recognition system.

[0149] One or more output devices 1424 are also connected to the interface circuitry 1420 of the illustrated example. Output devices 1424 may be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Thus, the interface circuitry 1420 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuitry such as a GPU.

[0150] The interface circuitry 1420 of the illustrated example also includes a communication device, such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and / or a network interface, to facilitate exchanging data with an external machine (e.g., any type of computing device) over a network 1426. Communication can occur over, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc. In this example, the interface circuitry 1420 implements the example antenna 310, the example transmitter circuitry 314, and the example receiver circuitry 316.

[0151] The processing circuitry platform 1400 of the illustrated example also includes one or more mass storage disks or devices 1428 to store firmware, software, and / or data. Examples of such mass storage disks or devices 1428 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs.

[0152] Can be achieved through Figure 8 、 9 The machine-readable instructions 1432 implemented by the machine-readable instructions of and / or 12 may be stored in the mass storage device 1428, in the volatile memory 1414, in the non-volatile memory 1416, and / or on at least one non-transitory computer-readable storage medium such as a CD or DVD that may be removable.

[0153] Figure 15 yes Figure 13 The processing circuit system 1312 and / or Figure 14 1412. In this example, Figure 13 The processing circuit system 1312 and / or Figure 14 The processing circuit system 1412 is implemented by the microprocessor 1500. For example, the microprocessor 1500 can be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit system). The microprocessor 1500 executes Figure 6 、 7 , 8, 9, 10, 11 and / or 12 of the flowchart to effectively Figure 2 and / or 3 are instantiated as logic circuits for performing operations corresponding to those machine-readable instructions. In some such instances, Figure 2The circuit system of and / or 3 is instantiated by the hardware circuit of the microprocessor 1500 in combination with machine-readable instructions. For example, the microprocessor 1500 can be implemented by a multi-core hardware circuit system such as a CPU, DSP, GPU, XPU, etc. Although the microprocessor can include any number of example cores 1502 (for example, 1 core), the microprocessor 1500 of this instance is a multi-core semiconductor device including N cores. The cores 1502 of the microprocessor 1500 can operate independently or can cooperate to execute machine-readable instructions. For example, the machine code corresponding to the firmware program, embedded software program, or software program can be executed by one of the cores 1502, or can be executed by multiple of the cores 1502 at the same or different times. In some instances, the machine code corresponding to the firmware program, embedded software program, or software program is split into threads and executed in parallel by two or more of the cores 1502. The software program can correspond to Figure 6 、 7 , 8, 9, 10, 11 and / or 12 represent a portion or all of the machine-readable instructions and / or operations.

[0154] The cores 1502 can communicate via a first example bus 1504. In some examples, the first bus 1504 can be implemented as a communication bus to facilitate communications associated with one or more of the cores 1502. For example, the first bus 1504 can be implemented as at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1504 can be implemented as any other type of computing or electrical bus. The cores 1502 can obtain data, instructions, and / or signals from one or more external devices via example interface circuitry 1506. The cores 1502 can output data, instructions, and / or signals to the one or more external devices via interface circuitry 1506. While the cores 1502 of this example include example local memory 1520 (e.g., a level 1 (L1) cache memory that may be split into an L1 data cache memory and an L1 instruction cache memory), the microprocessor 1500 also includes example shared memory 1510 (e.g., a level 2 (L2 cache)) that may be shared by the cores for high-speed access to data and / or instructions. Data and / or instructions may be transferred (e.g., shared) by writing to and / or reading from the shared memory 1510. The local memory 1520 and shared memory 1510 of each of the cores 1502 may be a plurality of levels of cache memory and main memory (e.g., a plurality of levels of main memory). Figure 13 Main memory 1314, 1316 and / or Figure 14Cache memory is part of a storage hierarchy of main memories 1414, 1416. Typically, higher-level memories in the hierarchy exhibit shorter access times and have smaller storage capacities than lower-level memories. Changes to various levels of the cache memory hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0155] Each core 1502 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core 1502 includes a control unit circuitry 1514, an arithmetic and logic (AL) circuitry 1516 (sometimes referred to as an ALU), a plurality of registers 1518, a local memory 1520, and a second example bus 1522. Other configurations are possible. For example, each core 1502 may include a vector unit circuitry, a single instruction multiple data (SIMD) unit circuitry, a load / store unit (LSU) circuitry, a branch / jump unit circuitry, a floating point unit (FPU) circuitry, etc. The control unit circuitry 1514 includes semiconductor-based circuitry structured to control (e.g., coordinate) data movement within the corresponding core 1502. The AL circuitry 1516 includes semiconductor-based circuitry structured to perform one or more mathematical and / or logical operations on data within the corresponding core 1502. Some examples of the AL circuitry 1516 implement integer-based operations. In other examples, AL circuitry 1516 also performs floating-point operations. In still other examples, AL circuitry 1516 may include a first AL circuitry that performs integer-based operations and a second AL circuitry that performs floating-point operations. In some examples, AL circuitry 1516 may be referred to as an arithmetic logic unit (ALU).

[0156] Registers 1518 are semiconductor-based structures for storing data and / or instructions, such as the results of one or more operations performed by the AL circuit system 1516 of the corresponding core 1502. For example, registers 1518 may include vector registers, SIMD registers, general registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Registers 1518 may be as follows: Figure 15 Alternatively, registers 1518 may be organized in any other arrangement, format, or structure, such as by being distributed across core 1502 to reduce access time. Second bus 1522 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0157] Each core 1502 and / or more generally the microprocessor 1500 may include additional and / or alternative structures to those shown and described above. For example, there may be one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergence / common grid stoppers (CMSs), one or more shifters (e.g., barrel shifters), and / or other circuitry. The microprocessor 1500 is a semiconductor device fabricated to include many transistors interconnected to implement the structures described above in one or more integrated circuits (ICs) contained in one or more packages.

[0158] The microprocessor 1500 may include and / or collaborate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some instances, the accelerator is implemented by logic circuitry to perform certain tasks more quickly and / or efficiently than a general-purpose processor can. Examples of accelerators include ASICs and FPGAs, such as those described herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. The accelerator may be onboard the microprocessor 1500, in the same chip package as the microprocessor 1500, and / or in one or more separate packages from the microprocessor 1500.

[0159] Figure 16 yes Figure 13 The processing circuit system 1312 and / or Figure 14 FIG. 14 is a block diagram of another example embodiment of a processing circuit system 1412 of FIG. Figure 13 The processing circuit system 1312 and / or Figure 14 The processing circuit system 1412 is implemented by the FPGA circuit system 1600. For example, the FPGA circuit system 1600 can be implemented by an FPGA. For example, the FPGA circuit system 1600 can be used to implement a program that can be executed by a corresponding machine-readable instruction. Figure 15 However, once configured, FPGA circuitry 1600 instantiates operations and / or functions corresponding to machine-readable instructions in hardware and, therefore, can typically perform operations / functions faster than if the operations / functions could be performed by a general-purpose microprocessor executing corresponding software.

[0160] More specifically, as described above Figure 15 The microprocessor 1500 (which can be programmed to execute Figure 6 、 7 , 8, 9, 10, 11 and / or 12 are generally machine-readable instructions, but the interconnections and logic circuitry thereof are fixed once manufactured. Figure 16The FPGA circuit system 1600 of the example includes circuits that can be configured, structured, programmed and / or interconnected in different ways after manufacture to instantiate, for example, corresponding to Figure 6 、 7 , 8, 9, 10, 11 and / or 12. Specifically, FPGA circuitry 1600 can be thought of as an array of logic gates, interconnects, and switches. The switches can be programmed to change the way the logic gates are interconnected via the interconnects, effectively forming one or more dedicated logic circuits (unless and until FPGA circuitry 1600 is reprogrammed). The logic circuitry is configured so that the logic gates can cooperate in different ways to perform different operations on data received by the input circuitry. Those operations may correspond to the operations performed by Figure 6 、 7 , 8, 9, 10, 11 and / or 12 represent some or all of the instructions (e.g., software and / or firmware). Thus, FPGA circuit system 1600 can be configured and / or structured to effectively Figure 6 、 7 , 8, 9, 10, 11 and / or 12 are instantiated as dedicated logic circuits to implement the operations / functions corresponding to those software instructions in a dedicated manner similar to an ASIC. Thus, the FPGA circuit system 1600 can be used with a general-purpose microprocessor that can execute the corresponding Figure 6 、 7 , 8, 9, 10, 11 and / or 12. The operations / functions of some or all of the machine-readable instructions are performed faster than those of FIG.

[0161] exist Figure 16 In an example, the FPGA circuit system 1600 is configured and / or structured in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some examples, the binary file can be compiled and / or generated based on instructions in a hardware description language (HDL) such as Lucid, a very high speed integrated circuit (VHSIC) hardware description language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write code or a program corresponding to one or more operations / functions in the HDL; the code / program can be converted to a low-level language as needed; and the code / program (e.g., code / program in the low-level language) can be converted (e.g., by a compiler, a software application, etc.) into a binary file. In some examples, Figure 16 The FPGA circuit system 1600 can access and / or load binary files to enable Figure 16The FPGA circuit system 1600 is configured and / or structured to implement one or more operations / functions. For example, a binary file can be generated by Figure 16 FPGA circuit system 1600 is implemented by a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) and / or machine-readable instructions accessible to cause Figure 16 Configuration and / or structuring of FPGA circuit system 1600 or a portion thereof.

[0162] In some instances, the binary file is compiled, generated, converted, and / or otherwise output from a unified software platform for programming the FPGA. For example, the unified software platform can convert first instructions (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to one or more operations / functions in an HDL. In some such instances, the binary file is compiled, generated, and / or otherwise output from the unified software platform based on the second instructions. In some instances, Figure 16 The FPGA circuit system 1600 can access and / or load binary files to enable Figure 16 The FPGA circuit system 1600 is configured and / or structured to implement one or more operations / functions. For example, a binary file can be generated by Figure 16 FPGA circuit system 1600 is implemented by a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) and / or machine-readable instructions accessible to cause Figure 16 Configuration and / or structuring of FPGA circuit system 1600 or a portion thereof.

[0163] Figure 16 The FPGA circuit system 1600 includes an example input / output (I / O) circuit system 1602 to obtain data from and / or output data to the example configuration circuit system 1604 and / or external hardware 1606. For example, the configuration circuit system 1604 can be implemented by an interface circuit system that can obtain a binary file, which can be implemented by a bitstream, data and / or machine-readable instructions to configure the FPGA circuit system 1600 or a portion thereof. In some such instances, the configuration circuit system 1604 can obtain the binary file from a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that can implement an artificial intelligence / machine learning (AI / ML) model to generate a binary file), etc. and / or any combination thereof. In some instances, the external hardware 1606 can be implemented by an external hardware circuit system. For example, the external hardware 1606 can be implemented by Figure 15The microprocessor 1500 is implemented.

[0164] FPGA circuitry 1600 also includes an array of example logic gate circuitry 1608, a plurality of example configurable interconnects 1610, and example storage circuitry 1612. Logic gate circuitry 1608 and configurable interconnects 1610 may be configured to instantiate a logic gate circuitry corresponding to a logic gate. Figure 6 、 7 , 8, 9, 10, 11 and / or 12 of at least some of the machine-readable instructions, and / or other desired operations. Figure 16 Logic gate circuitry 1608 is shown fabricated in blocks or groups. Each block includes semiconductor-based electrical structures that can be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide basic building blocks for logic circuits. Electrically controlled switches (e.g., transistors) are present within each logic gate circuitry 1608 to enable configuration of the electrical structures and / or logic gates to form circuits that implement the desired operation / function. Logic gate circuitry 1608 may include other electrical structures, such as lookup tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0165] The configurable interconnect 1610 of the illustrated example is a conductive path, trace, via, etc. that may include an electrically controlled switch (e.g., a transistor), the state of which can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more logic gate circuit systems 1608 to program a desired logic circuit.

[0166] The storage circuitry 1612 of the illustrated example is structured to store the results of one or more operations performed by corresponding logic gates. The storage circuitry 1612 may be implemented by registers, etc. In the illustrated example, the storage circuitry 1612 is distributed among the logic gate circuitry 1608 to facilitate access and increase execution speed.

[0167] Figure 16The example FPGA circuit system 1600 also includes an example special-purpose operating circuit system 1614. In this example, the special-purpose operating circuit system 1614 includes a special-purpose circuit system 1616, which can be called to implement common functions, thereby eliminating the need to program those functions on site. Examples of such special-purpose circuit systems 1616 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory, and multiplier-accumulator circuit systems. Other types of special-purpose circuit systems may exist. In some examples, the FPGA circuit system 1600 may also include an example general-purpose programmable circuit system 1618, such as an example CPU 1620 and / or an example DSP 1622. In addition or alternatively, there may be other general-purpose programmable circuit systems 1618 that can be programmed to implement other operations, such as a GPU, XPU, etc.

[0168] Although Figure 15 and 16 Explained Figure 13 The processing circuit system 1312 and / or Figure 14 These are two example implementations of the processing circuitry 1412, but many other approaches are contemplated. For example, the FPGA circuitry may include an onboard CPU, such as one or more Figure 16 The example CPU is 1620. Therefore, Figure 13 The processing circuit system 1312 and / or Figure 14 The processing circuitry 1412 may additionally be configured by combining at least Figure 15 An example microprocessor 1500 and Figure 16 In some such hybrid examples, Figure 15 One or more cores 1502 may execute Figure 6 、 7 , 8, 9, 10, 11 and / or 12 to implement a first operation / function, Figure 16 The FPGA circuit system 1600 may be configured and / or structured to implement the Figure 6 、 7 , 8, 9, 10, 11 and / or 12, and / or the ASIC may be configured and / or structured to implement the second operation / function of the second portion of the machine readable instructions represented by the flowchart of Figure 6 、 7 , 8, 9, 10, 11 and / or 12 represent a third operation / function of the third portion of the machine-readable instructions.

[0169] It should be understood that Figure 2Some or all of the circuitry of and / or 3 may therefore be instantiated at the same or different times. For example, Figure 15 The same and / or different portions of the microprocessor 1500 may be programmed to execute portions of the machine-readable instructions at the same and / or different times. In some examples, Figure 16 The same and / or different portions of FPGA circuitry 1600 may be configured and / or structured to perform operations / functions corresponding to portions of the machine-readable instructions at the same and / or different times.

[0170] In some instances, Figure 2 Some or all of the circuitry of and / or 3 may be instantiated, for example, in one or more threads that execute in parallel and / or serially. Figure 15 The microprocessor 1500 can execute machine-readable instructions in one or more threads of execution in parallel and / or serially. In some examples, Figure 16 The FPGA circuit system 1600 can be configured and / or structured to perform operations / functions in parallel and / or serially. In addition, in some examples, Figure 2 and / or some or all of the circuitry of 3 may be in Figure 15 The system is implemented within one or more virtual machines and / or containers executed on the microprocessor 1500.

[0171] In some instances, Figure 13 The processing circuit system 1312 and / or Figure 14 The processing circuit system 1412 can be in one or more packages. For example, Figure 15 The microprocessor 1500 and / or Figure 16 The FPGA circuit system 1600 can be in one or more packages. In some examples, the XPU can be composed of Figure 13 The processing circuit system 1312 and / or Figure 14 The processing circuit system 1412 is implemented. For example, the XPU can be included in a CPU package (e.g., Figure 15 Microprocessor 1500, Figure 16 1620, etc.), a DSP in another package (e.g., Figure 16 DSP 1622), a GPU in yet another package, and an FPGA in yet another package (e.g., Figure 16 FPGA circuit system 1600).

[0172] Figure 17 A block diagram illustrating an example software distribution platform 1705 is shown for distributing, for example, Figure 13 Example machine readable instructions 1332 and / or Figure 14The example software distribution platform 1705 may be implemented by any computer server, data infrastructure, cloud service, etc. that is capable of storing and delivering software to other computing devices. The third party may be a customer of the entity that owns and / or operates the software distribution platform 1705. For example, the entity that owns and / or operates the software distribution platform 1705 may be a developer, seller, and / or licensor of software, such as the software that is used to distribute the software to other hardware devices (e.g., hardware devices owned and / or operated by a third party to the owner and / or operator of the software distribution platform). Figure 13 Example machine readable instructions 1332 and / or Figure 14 The third party may be a consumer, user, retailer, OEM, etc. who purchases and / or licenses the software for use and / or resale and / or sublicense. In the illustrated example, the software distribution platform 1705 includes one or more servers and one or more storage devices. The storage device stores the software that may correspond to the software described above. Figure 6 、 7 , 8, 9, 10, 11 and / or 12 of the example machine-readable instructions 1332 and / or machine-readable instructions 1432. One or more servers of the example software distribution platform 1705 communicate with the example network 1710, which may correspond to any one or more of the Internet and / or any of the example networks described above. In some instances, one or more servers send the software to the requesting party as part of a commercial transaction in response to the request. The delivery, sale and / or payment of the license for the software may be processed by one or more servers of the software distribution platform and / or a third-party payment entity. The server enables buyers and / or licensors to download the machine-readable instructions 1332 and / or machine-readable instructions 1432 from the software distribution platform 1705. For example, it may correspond to Figure 6 、 7 , 10 and / or 11 can be downloaded to the example processing circuit system platform 1300, which is used to execute the machine readable instructions 1332 to implement the parent device 200. In addition, for example, Figure 8 、 9 12 can be downloaded to the example processing circuit system platform 1400, which is used to execute the machine readable instructions 1432 to implement the sub-device 300. In some examples, one or more servers of the software distribution platform 1705 periodically provide, send and / or enforce the execution of software (e.g., Figure 13 Example machine readable instructions 1332 and / or Figure 14The example machine readable instructions 1432 of the embodiment of the present invention are to ensure that improvements, patches, updates, etc. are distributed and applied to the software at the end user device. Although referred to as software above, the distributed "software" may alternatively be firmware.

[0173] In this specification, the term "and / or" (when used in the form of, for example, A, B, and / or C) refers to any combination or subset of A, B, C, for example: (a) A alone; (b) B alone; (c) C alone; (d) A and B; (e) A and C; (f) B and C; and (g) A and B and C. In addition, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to embodiments that include any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0174] The term "coupled" is used throughout this specification. This term encompasses any connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then: in the first instance, device A is coupled to device B; or in the second instance, if the intermediate component C does not substantially alter the functional relationship between devices A and B, then device A is coupled to device B through an intermediate component C, such that device B is controlled by device A via the control signal provided by device A.

[0175] Numeric identifiers such as "first," "second," "third," etc. are only used to distinguish elements of substantially the same type in terms of structure and / or function. These identifiers used in the detailed description are not necessarily consistent with the identifiers used in the claims.

[0176] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0177] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection between or terminations of a device element, circuit element, integrated circuit, device, or other electronic device or semiconductor component.

[0178] Circuits or devices described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure during manufacture or after manufacture, for example, by an end user and / or a third party.

[0179] The circuits described herein can be reconfigured to include replacement components to provide functionality that is at least partially similar to functionality available before component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the impedance amount represented by the resistor shown. For example, a resistor or capacitor shown and described as a single component in this article may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described as a single component in this article may alternatively be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor. Although some elements of the described examples are included in the integrated circuit and other elements are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as being outside the integrated circuit may be included in the integrated circuit, and / or some features described as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0180] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. Unless otherwise stated, the words "about," "substantially," or "substantially" preceding a value mean + / - 10% of the value, or, if the value is zero, a reasonable range of values ​​around zero.

[0181] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

[0182] In light of the foregoing, it should be appreciated that example systems, devices, articles, and methods for implementing channel hopping across different frequency bands have been described. In addition, the example systems, devices, articles, and methods described herein reduce the computational overhead for synchronizing devices in a network. For example, the example child device described herein tracks the synchronization information of the parent device, and the example parent device does not track the synchronization information of other devices. The examples described herein also implement channel hopping on CSL-capable devices. The described systems, devices, articles, and methods improve the efficiency of using computing devices by increasing the strength of connectivity between parent and child devices. For example, the described systems, devices, articles, and methods improve the efficiency of using computing devices by supporting better parent selection and lower synchronization overhead. The described systems, devices, articles, and methods accordingly relate to one or more improvements in the operation of machines, such as computers or other electronic and / or mechanical devices.

[0183] The appended claims are hereby incorporated by reference into this detailed description. Although certain example systems, devices, articles, and methods have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles, and methods that fully fall within the scope of the claims of this patent.

Claims

1. A device for improving the performance of a network operating in multiple frequency bands, the device include: Interface circuit system; a memory configured to store machine-readable instructions; as well as processing circuitry configured to instantiate or execute at least one of the machine-readable instructions to: determining a connectivity metric of a first device synchronized with a second device; causing, via the interface circuitry, transmission of the connectivity metric to a third device with which the first device is not synchronized; as well as Based on the first communication from the third device, causing a second communication to be sent to the first device to synchronize the first device with the third device. 2 . The apparatus of claim 1 , wherein the processing circuitry is configured to determine whether the first communication indicates that the first device has stronger connectivity with the third device than the second device has with the third device.

3. The apparatus of claim 1 , wherein the processing circuitry is configured to: causing transmission of the connectivity metric to the third device in a first radio frequency (RF) band; and The second communication is caused to be sent to the first device in a second RF frequency band different from the first RF frequency band.

4. The device according to claim 1, wherein the connectivity metric is a first connectivity metric, wherein the processing circuitry is configured to determine a second connectivity metric of a fourth device, wherein the fourth device is not synchronized with the second device, and The second connectivity metric represents the connectivity strength between the second device and the fourth device.

5. The apparatus of claim 4, wherein the processing circuitry is configured to determine whether the fourth device has stronger connectivity to the second device than a fifth device has to the second device based on the second connectivity metric and a third connectivity metric, wherein the fourth device is synchronized with the fifth device, and The third connectivity metric represents a second connectivity strength between the fifth device and the fourth device.

6. The apparatus of claim 4, wherein the processing circuitry is configured to cause a third communication to be sent to the fifth device based on the fourth device having a stronger connectivity to the second device than the fifth device having a stronger connectivity to the second device, wherein the fourth device is synchronized with the fifth device, and The third communication indicates that connectivity between the fourth device and the second device is stronger than connectivity between the fifth device and the second device.

7. The apparatus of claim 1, wherein the connectivity metric comprises at least one of a received signal strength indicator, a bit error rate, or a link quality indicator.

8. A non-transitory machine-readable storage medium comprising instructions that cause a processing circuit system to at least: determining a connectivity metric of a first device synchronized with a second device; causing the connectivity metric to be sent to a third device with which the first device is not synchronized; and Based on the first communication from the third device, causing a second communication to be sent to the first device, the second communication being used to synchronize the first device with the third device. 9 . The non-transitory machine-readable storage medium of claim 8 , wherein the instructions cause the processing circuitry to determine whether the first communication indicates that the first device has stronger connectivity with the third device than the second device has with the third device.

10. The non-transitory machine-readable storage medium of claim 8, wherein the instructions cause the processing circuitry to: causing transmission of the connectivity metric to the third device in a first radio frequency (RF) band; and The second communication is caused to be sent to the first device in a second RF frequency band different from the first RF frequency band.

11. The non-transitory machine-readable storage medium of claim 8, wherein the connectivity metric is a first connectivity metric, wherein the instructions cause the processing circuitry to determine a second connectivity metric for a fourth device, wherein the fourth device is not synchronized with the second device, and The second connectivity metric represents the connectivity strength between the second device and the fourth device.

12. The non-transitory machine-readable storage medium of claim 11, wherein the instructions cause the processing circuitry to determine whether the fourth device has stronger connectivity to the second device than a fifth device has to the second device based on the second connectivity metric and a third connectivity metric, wherein the fourth device is synchronized with the fifth device, and The third connectivity metric represents a second connectivity strength between the fifth device and the fourth device.

13. The non-transitory machine-readable storage medium of claim 11, wherein the instructions cause the processing circuitry to cause a third communication to be sent to the fifth device based on the fourth device having a stronger connectivity to the second device than the fifth device having a stronger connectivity to the second device, wherein the fourth device is synchronized with the fifth device, and The third communication indicates that connectivity between the fourth device and the second device is stronger than connectivity between the fifth device and the second device.

14. The non-transitory machine-readable storage medium of claim 8, wherein the connectivity metric comprises at least one of a received signal strength indicator, a bit error rate, or a link quality indicator.

15. A method for improving the performance of a network operating in multiple frequency bands, the method include: determining a connectivity metric of a first device synchronized with a second device by executing instructions with processing circuitry; sending the connectivity metric to a third device with which the first device is not synchronized; as well as Based on the first communication from the third device, a second communication is sent to the first device, the second communication being used to synchronize the first device with the third device.

16. The method of claim 15, further comprising determining whether the first communication indicates that the first device has stronger connectivity with the third device than the second device has with the third device.

17. The method of claim 15, further comprising: transmitting the connectivity metric to the third device in a first radio frequency (RF) band; and The second communication is sent to the first device in a second RF frequency band different from the first RF frequency band.

18. The method according to claim 15, wherein the connectivity metric is a first connectivity metric, wherein the method further comprises determining a second connectivity metric of the fourth device, wherein the fourth device is not synchronized with the second device, and The second connectivity metric represents the connectivity strength between the second device and the fourth device.

19. The method of claim 18, further comprising determining whether the fourth device has stronger connectivity to the second device than the fifth device has to the second device based on the second connectivity metric and a third connectivity metric, wherein the fourth device is synchronized with the fifth device, and The third connectivity metric represents a second connectivity strength between the fifth device and the fourth device.

20. The method of claim 18, further comprising sending a third communication to the fifth device based on the fourth device having stronger connectivity to the second device than the fifth device having stronger connectivity to the second device, wherein the fourth device is synchronized with the fifth device, and The third communication indicates that connectivity between the fourth device and the second device is stronger than connectivity between the fifth device and the second device.

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