Low-cost amplitude demodulation implementation method applied to secondary radar
The FPGA processed the response signal of the secondary radar and used the segmented linear calculation method to realize logarithmic conversion, which solved the problem of traditional logarithmic detection circuits increasing costs and being susceptible to environmental impact, and achieved low-cost and high-precision amplitude demodulation effect .
Patent Information
- Application Number
- CN202411435410.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2024-12-17
AI Technical Summary
Traditional secondary radars use logarithmic detection circuits to process response signals, increasing hardware cost and board space, and performance parameters are easily affected by temperature and environment, making the debugging process difficult.
The logarithmic compression processing function of the secondary radar is handed over to the FPGA. By digitizing the intermediate frequency and orthogonal demodulation of the response signal, the logarithmic conversion characteristics are approximateed by segmented linear calculation method to obtain the logarithmic digital amplitude.
It realizes low-cost amplitude demodulation, reduces hardware costs and board space, simplifies the debugging process, and meets high-precision requirements and is not affected by temperature and environment.
Smart Images
Figure CN119148094A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of secondary radar, and in particular to a low-cost amplitude demodulation implementation method applied to secondary radar. Background Art
[0002] In today's rapidly developing civil aviation environment, secondary radar, as an important equipment for air traffic control, plays an indispensable role in airspace monitoring and flight safety. Therefore, secondary radar must have high measurement accuracy, the reception and processing of reply signals must be accurate, and the amplitude extraction must meet high-precision requirements.
[0003] Under normal circumstances, the secondary radar must be able to detect all reply signals within the entire signal strength dynamic range, which is from the largest possible signal -20dBm to the smallest possible signal -90dBm, a voltage difference of 3000 times. Therefore, the traditional secondary radar uses a logarithmic detection circuit to logarithmically compress the received reply signal. The use of the logarithmic detection circuit not only increases the hardware cost, but also increases the board space. In addition, the performance parameters of the logarithmic detection circuit are easily affected by temperature, environment, etc., and the performance index debugging process is very difficult. Summary of the invention
[0004] Aiming at the traditional processing method of secondary radar for reply signal, it is necessary to use logarithmic detection circuit, which increases hardware cost and board space. In addition, the performance parameters of the logarithmic detection circuit are easily affected by temperature, environment, etc., and the performance index debugging process is very difficult. The present invention proposes a low-cost amplitude demodulation implementation method for secondary radar, in which the logarithmic compression processing function of the secondary radar for reply signal is completed by FPGA. After the intermediate frequency of the reply signal is digitized, the digital amplitude value is obtained by orthogonal demodulation. The digital amplitude adopts a piecewise linear calculation method in FPGA to approximate the logarithmic conversion characteristics to obtain the logarithmic digital amplitude, which is very simple.
[0005] The present invention discloses a low-cost amplitude demodulation implementation method applied to a secondary radar, which comprises:
[0006] Step 1: Mix the response signal to obtain an intermediate frequency signal;
[0007] Step 2: Perform A / D quantization on the intermediate frequency signal;
[0008] Step 3: Perform orthogonal demodulation on the quantized intermediate frequency signal to obtain a digital amplitude value, and use a piecewise linear calculation method to obtain a logarithmic digital amplitude.
[0009] Furthermore, the step 1 comprises:
[0010] The local oscillator is mixed with the reply signal received by the secondary radar to obtain an intermediate frequency signal of the required frequency.
[0011] Furthermore, the step 2 comprises:
[0012] According to the frequency, bandwidth and amplitude range of the intermediate frequency signal, the required A / D chip is selected; according to the frequency and bandwidth of the intermediate frequency signal, the required sampling frequency is selected, the intermediate frequency signal is quantized, and the A / D quantization value is obtained.
[0013] Furthermore, the step 3 comprises:
[0014] Step 31: FPGA generates local digital sine carrier and cosine carrier through DDS; the local digital sine carrier and cosine carrier are multiplied by the A / D quantized value of the intermediate frequency signal respectively, and digital mixing is performed. After digital mixing, they are respectively passed through filters to obtain an I-channel in-phase component and a Q-channel orthogonal component;
[0015] Step 32: Calculate the intermediate frequency signal amplitude value according to the I-path in-phase component and the Q-path orthogonal component;
[0016] Step 33: According to the data correspondence between the intermediate frequency signal amplitude value and the logarithmic amplitude value, a lookup table is prepared, and a piecewise linear calculation method is used to approximate the logarithmic conversion characteristics. Correction compensation is performed on the basis of the lookup table to obtain the logarithmic amplitude value.
[0017] Further, the step 32 comprises:
[0018] The intermediate frequency signal amplitude value is calculated by the following formula:
[0019]
[0020] Among them, powerdbamp is the amplitude value of the intermediate frequency signal.
[0021] Further, the step 33 comprises:
[0022] Step 331: Divide the intermediate frequency signal amplitude value powerdbamp into K value intervals, and in the first value interval, find the mapping relationship of the logarithmic digital amplitude corresponding to the response signal, the corresponding logarithmic amplitude value uses the intermediate frequency signal amplitude value as an array index, and the corresponding logarithmic amplitude value is used as an array element to construct a reference lookup table look_table of the mapping relationship between the intermediate frequency signal amplitude value and the logarithmic amplitude value of P elements;
[0023] Step 332: For the second value interval to the Kth value interval, determine the array indexes according to the intermediate frequency signal amplitude values, find out the corresponding logarithmic amplitude values, select the correction values, and obtain the required logarithmic amplitude values.
[0024] Furthermore, in step 331, the intermediate frequency signal amplitude value powerdbamp is divided into K value intervals in order from small to large, and there is no overlap between each value interval.
[0025] Furthermore, the mapping relationship between the intermediate frequency signal amplitude value powerdbamp and the logarithmic digital amplitude corresponding to the response signal is expressed as:
[0026] The logarithmic amplitude value is logamp=20*lg(powerdbamp), where powerdbamp is the amplitude value of the intermediate frequency signal.
[0027] Furthermore, the intermediate frequency signal amplitude value powerdbamp is approximately expressed as m*2 n , then the voltage amplitude value is ulogamp:
[0028] ulogamp=20*lg(powerdbamp)≈20*lg(m*2 n )=20*lg(m)+
[0029] 20*lg(2 n )=20*lg(m)+20*n*lg2≈20*lg(m)+6*n
[0030] The voltage amplitude value ulogamp is equal to the logarithmic amplitude value logamp, and m and n are both positive integers.
[0031] Further, the step 332 includes:
[0032] For the i-th value period, divide powerdbamp by 2 n The obtained quotient is used as the index value of the reference lookup table to find the corresponding logarithmic amplitude value. At this time, n=i-1, the correction value is 6*n, and the sum of the found logarithmic amplitude value and the correction value is the final required logarithmic amplitude value.
[0033] Due to the adoption of the above technical solution, the present invention has the following advantages:
[0034] 1. The traditional processing method of the secondary radar for the reply signal requires the use of a logarithmic detection circuit. The present invention transfers the logarithmic compression processing function of the secondary radar for the reply signal to FPGA. After the intermediate frequency of the reply signal is digitized, the digital amplitude value is obtained by orthogonal demodulation. The digital amplitude adopts a piecewise linear calculation method in the FPGA to approximate the logarithmic conversion characteristics to obtain the logarithmic digital amplitude. It is very simple and does not require the use of a logarithmic detection circuit, saving hardware costs and reducing board layout space.
[0035] 2. The performance parameters of the logarithmic detection circuit used in the traditional processing method of the secondary radar for the reply signal are easily affected by temperature, environment, etc., and the performance index debugging process is very difficult. The present invention uses a digital processing method as much as possible for the amplitude processing of the secondary radar for the reply signal, and replaces the complicated analog circuit debugging with FPGA software processing. The debugging process is very simple, and the performance indicators fully meet the measurement accuracy requirements and are not affected by external conditions such as temperature and environment. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.
[0037] Figure 1 It is a schematic diagram of the overall flow of a low-cost amplitude demodulation implementation method applied to a secondary radar according to an embodiment of the present invention;
[0038] Figure 2 It is a principle block diagram of a radio frequency receiving front-end unit according to an embodiment of the present invention;
[0039] Figure 3 4 is an A / D quantization circuit diagram of an embodiment of the present invention. DETAILED DESCRIPTION
[0040] The present invention is further described in conjunction with the accompanying drawings and embodiments, and the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present invention.
[0041] Aiming at the traditional processing method of secondary radar for reply signal, it is necessary to use logarithmic detection circuit, which increases hardware cost and board space. In addition, the performance parameters of the logarithmic detection circuit are easily affected by temperature, environment, etc., and the performance index debugging process is very difficult. The present invention proposes a low-cost amplitude demodulation implementation method for secondary radar, in which the logarithmic compression processing function of the secondary radar for reply signal is completed by FPGA. After the intermediate frequency of the reply signal is digitized, the digital amplitude value is obtained by orthogonal demodulation. The digital amplitude adopts a piecewise linear calculation method in FPGA to approximate the logarithmic conversion characteristics to obtain the logarithmic digital amplitude, which is very simple.
[0042] See also Figure 1 The present invention provides an embodiment of a low-cost amplitude demodulation implementation method for secondary radar, which includes:
[0043] Step 1: Mix the response signal to obtain an intermediate frequency signal;
[0044] Step 2: A / D (analog-to-digital) quantization of the intermediate frequency signal;
[0045] Step 3: Perform orthogonal demodulation on the quantized intermediate frequency signal to obtain a digital amplitude value, and use a piecewise linear calculation method to obtain a logarithmic amplitude value.
[0046] In this embodiment, step 1 includes:
[0047] The local oscillator is mixed with the reply signal received by the secondary radar to obtain an intermediate frequency signal of the required frequency.
[0048] Specifically, see Figure 2 , input 1090MHz RF signal, after filtering and amplification, it is mixed with the 1160MHz local oscillator signal generated by the local oscillator unit to generate an intermediate frequency 70MHz signal, which is processed by 8MHz bandwidth intermediate frequency filtering to output the intermediate frequency signal.
[0049] In this embodiment, step 2 includes:
[0050] According to the frequency, bandwidth and amplitude range of the intermediate frequency signal, the required A / D chip is selected; according to the frequency and bandwidth of the intermediate frequency signal, the required sampling frequency is selected, the intermediate frequency signal is quantized, and the A / D quantization value is obtained. Figure 3 An A / D chip is given, whose model is AD9265BCPZ-125.
[0051] In this embodiment, step 3 includes:
[0052] Step 31: FPGA generates local digital sine carrier and cosine carrier through DDS (internal direct frequency synthesizer); the local digital sine carrier and cosine carrier are multiplied with the A / D quantization value of the intermediate frequency signal respectively, and digital mixing is performed. After digital mixing, they are respectively passed through filters to obtain the I-way in-phase component and the Q-way orthogonal component; wherein the filter can be a low-pass filter.
[0053] Step 32: Calculate the intermediate frequency signal amplitude value according to the I-path in-phase component and the Q-path orthogonal component;
[0054] Step 33: According to the data correspondence between the intermediate frequency signal amplitude value and the logarithmic amplitude value, a lookup table is prepared, and a piecewise linear calculation method is used to approximate the logarithmic conversion characteristics. Correction compensation is performed on the basis of the lookup table to obtain the logarithmic amplitude value.
[0055] In this embodiment, step 32 includes:
[0056] The intermediate frequency signal amplitude value is calculated by the following formula:
[0057]
[0058] Among them, powerdbamp is the amplitude value of the intermediate frequency signal.
[0059] In this embodiment, step 33 includes:
[0060] Step 331: Divide the intermediate frequency signal amplitude value powerdbamp into K value intervals, and in the first value interval, find the mapping relationship of the logarithmic amplitude value corresponding to the response signal, the corresponding logarithmic amplitude value uses the intermediate frequency signal amplitude value as an array index, and uses the corresponding logarithmic amplitude value as an array element to construct a reference lookup table look_table of the mapping relationship between the intermediate frequency signal amplitude value and the logarithmic amplitude value with P elements;
[0061] Step 332: For the second value interval to the Kth value interval, determine the array indexes according to the intermediate frequency signal amplitude values, find out the corresponding logarithmic amplitude values, select the correction values, and obtain the required logarithmic amplitude values.
[0062] In this embodiment, in step 331, the intermediate frequency signal amplitude value powerdbamp is divided into K value intervals in order from small to large, and there is no overlap between each value interval.
[0063] In this embodiment, in step 331:
[0064] The power gain of the reply signal is:
[0065]
[0066] Among them, V recv is the voltage amplitude effective value of the intermediate frequency signal after the response signal is converted, V ref is the voltage amplitude effective value of the intermediate frequency reference signal after the response reference signal is converted, and the voltage effective value of the sine wave signal is Where VPP is the peak-to-peak value of the sine wave signal, and the logarithmic amplitude required for conversion is Therefore, the logarithmic amplitude value is logamp=20lg(powerdbamp), where powerdbamp is the amplitude value of the intermediate frequency signal.
[0067] In principle, FPGA can only obtain 20lg(powerdbamp) by table lookup. However, the value range of powerdbamp is too large, and too many resources are required to construct the lookup table. The workload is large and difficult to implement. The embodiment of the present invention adopts a piecewise linear calculation method to approximate the logarithmic conversion characteristics and approximate the intermediate frequency signal amplitude value powerdbamp as m*2 n, then the voltage amplitude value ulogamp=20*lg(powerdbamp)≈20*lg(m*2 n )=20*lg(m)+20*
[0068] lg(2 n )=20*lg(m)+20*n*lg2≈20*lg(m)+6*n
[0069] The voltage amplitude value ulogamp is equal to the logarithmic amplitude value logamp, and m and n are both positive integers.
[0070] In this embodiment, step 332 includes:
[0071] For the i-th value period, divide powerdbamp by 2 n The obtained quotient is used as the index value of the reference lookup table to find the corresponding logarithmic amplitude value. At this time, n=i-1, the correction value is 6*n, and the sum of the found logarithmic amplitude value and the correction value is the final required logarithmic amplitude value.
[0072] Specifically, the present application provides a more specific technical solution, which includes:
[0073] Based on 0≤powerdbamp≤255, find the mapping relationship of the logarithmic digital amplitude corresponding to the low-power response signal, that is, the intermediate frequency signal amplitude value is within [0,255], the corresponding logarithmic amplitude value, the intermediate frequency signal amplitude value is the array index, the corresponding logarithmic amplitude value is the array element, and a 256-element benchmark lookup table of the mapping relationship between the intermediate frequency signal amplitude value and the logarithmic amplitude value is constructed, look_table=[a0,a1,a2,a3…a255], and the remaining intermediate frequency signal amplitude values powerdbamp greater than or equal to 256 are piecewise linearly calculated according to the intervals of [256,511], [512,1023], [1024,2047], [2048,4095], [4096,8191]… First determine the interval where the power digital amplitude powerdbamp value is located, and divide it by 2 when it is [256,511]. 1 The obtained quotient is used as the index value of the benchmark lookup table to find the corresponding logarithmic amplitude value. At this time, n=1, the correction value is 6*1, and the sum of the two is the final required logarithmic amplitude value; when [512,1023], divide by 2 2 The obtained quotient is used as the index value of the benchmark lookup table to find the corresponding logarithmic amplitude value. At this time, n=2, the correction value is 6*2, and the sum of the two is the final required logarithmic amplitude value; when [1024,2047], divide by 2 3The obtained quotient is used as the index value of the benchmark lookup table to find the corresponding logarithmic amplitude value. At this time, n=3, the correction value is 6*3, and the sum of the two is the final required logarithmic amplitude value. The rest is deduced in the same way, so as to obtain the logarithmic amplitude value within the entire dynamic range, greatly reducing the consumption of FPGA resources and the workload of program developers.
[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A low-cost amplitude demodulation implementation method for secondary radar, characterized in that: include: Step 1: Mix the response signal to obtain an intermediate frequency signal; Step 2: Perform A / D quantization on the intermediate frequency signal; Step 3: Perform orthogonal demodulation on the quantized intermediate frequency signal to obtain a digital amplitude value, and use a piecewise linear calculation method to obtain a logarithmic digital amplitude.
2. The low-cost amplitude demodulation implementation method for secondary radar according to claim 1 is characterized in that: The step 1 comprises: The local oscillator is mixed with the reply signal received by the secondary radar to obtain an intermediate frequency signal of the required frequency.
3. The low-cost amplitude demodulation implementation method for secondary radar according to claim 1, characterized in that: The step 2 comprises: According to the frequency, bandwidth and amplitude range of the intermediate frequency signal, the required A / D chip is selected; according to the frequency and bandwidth of the intermediate frequency signal, the required sampling frequency is selected, the intermediate frequency signal is quantized, and the A / D quantization value is obtained.
4. The low-cost amplitude demodulation implementation method for secondary radar according to claim 1, characterized in that: The step 3 comprises: Step 31: FPGA generates local digital sine carrier and cosine carrier through DDS; the local digital sine carrier and cosine carrier are multiplied by the A / D quantized value of the intermediate frequency signal respectively, and digital mixing is performed. After digital mixing, they are respectively passed through filters to obtain an I-channel in-phase component and a Q-channel orthogonal component; Step 32: FPGA calculates the amplitude value of the intermediate frequency signal according to the I-channel in-phase component and the Q-channel orthogonal component; Step 33: FPGA creates a lookup table based on the data correspondence between the intermediate frequency signal amplitude value and the logarithmic amplitude value, uses a piecewise linear calculation method to approximate the logarithmic conversion characteristics, performs correction and compensation based on the lookup table, and obtains the logarithmic amplitude value.
5. The low-cost amplitude demodulation implementation method for secondary radar according to claim 4 is characterized in that: The step 32 comprises: The intermediate frequency signal amplitude value is calculated by the following formula: Among them, powerdbamp is the amplitude value of the intermediate frequency signal.
6. The low-cost amplitude demodulation implementation method for secondary radar according to claim 4 is characterized in that: The step 33 comprises: Step 331: Divide the intermediate frequency signal amplitude value powerdbamp into K value intervals, and in the first value interval, find the mapping relationship of the logarithmic digital amplitude corresponding to the response signal, the corresponding logarithmic amplitude value uses the intermediate frequency signal amplitude value as an array index, and the corresponding logarithmic amplitude value is used as an array element to construct a reference lookup table look_table of the mapping relationship between the intermediate frequency signal amplitude value and the logarithmic amplitude value of P elements; Step 332: For the second value interval to the Kth value interval, determine the array indexes according to the intermediate frequency signal amplitude values, find out the corresponding logarithmic amplitude values, select the correction values, and obtain the required logarithmic amplitude values.
7. The low-cost amplitude demodulation implementation method for secondary radar according to claim 6, characterized in that: In step 331, the intermediate frequency signal amplitude value powerdbamp is divided into K value intervals in order from small to large, and there is no overlap between each value interval.
8. The low-cost amplitude demodulation implementation method for secondary radar according to claim 6 or 7, characterized in that: The mapping relationship between the intermediate frequency signal amplitude value powerdbamp and the logarithmic digital amplitude corresponding to the response signal is expressed as: The logarithmic amplitude value is logamp=20*lg(powerdbamp), where powerdbamp is the amplitude value of the intermediate frequency signal.
9. The low-cost amplitude demodulation implementation method for secondary radar according to claim 8, characterized in that: The intermediate frequency signal amplitude value powerdbamp is approximately expressed as m*2 n , then the voltage amplitude value is ulogamp: logamp=20*lg(powerdbamp)≈20*lg(m*2 n )=20*log(m)+ 20*lg(2 n )=20*lg(m)+20*n*lg2≈20*lg(m)+6*n The voltage amplitude value ulogamp is equal to the logarithmic amplitude value logamp, and m and n are both positive integers.
10. The low-cost amplitude demodulation implementation method for secondary radar according to claim 9, characterized in that: The step 332 includes: For the i-th value period, divide powerdbamp by 2 n The obtained quotient is used as the index value of the reference lookup table to find the corresponding logarithmic amplitude value. At this time, n=i-1, the correction value is 6*n, and the sum of the found logarithmic amplitude value and the correction value is the final required logarithmic amplitude value.