Clock taming and holding methods, systems, devices and media

Abstract

The invention relates to clock taming and holding methods, systems, devices, and media. The method comprises the steps of obtaining a clock signal waveform of a clock generator; taking the jump edge of the pulse signal waveform as a reference, and respectively measuring time differences between a plurality of continuous jump edges in the clock signal waveform and the jump edge of the pulse signal waveform; calculating the output frequency of the clock generator through the time difference of the jump edges; and adjusting the frequency of the clock generator by calculating the difference value between the output frequency and the expected frequency, and outputting a tamed clock signal. According to the invention, extra reference signals are not required to be introduced, the time difference of the clock signals can be quickly obtained, and the taming time of the clock generator is reduced, so that the frequency can be more quickly tamed, and the stability and accuracy of clock output are improved.

Description

Technical Field

[0001] The present invention relates to the field of precise time service technology, and in particular to a clock taming and maintaining method, system, device and medium. Background Art

[0002] With the rapid development of communication systems, navigation systems and other applications that require high-precision clock synchronization, the systems have put forward higher and higher requirements for the accuracy, stability and continuity of clock signals. Traditional clock taming technology relies on external reference clock signals, such as satellite timing signals or network synchronization clocks, to ensure the synchronization of system clocks by comparing and adjusting with local clocks. This technology relies on the stability and accuracy of external reference signals. Any instability of external reference signals will directly affect the accuracy of local clocks, and thus affect the normal operation of the system.

[0003] However, in practical applications, the quality of external reference clock signals often cannot meet the high requirements of the system. For example, in satellite timing systems, the stability and continuity of external reference signals are particularly important. However, ground equipment is often intermittent due to the limitations of the satellite's receiving angle. In addition, atmospheric interference may also cause the accuracy and stability of the received satellite reference clock signal to be substandard. These factors jointly affect the performance of the satellite-based timing clock system, which cannot reliably provide high-precision clock signals.

[0004] Similarly, for clock systems that rely on network synchronization, load changes in the routing network can cause problems with the accuracy and stability of the clock synchronization signal. In this case, the uncertainty of the network load increases the difficulty of clock synchronization, thereby affecting the overall performance of the system. Summary of the invention

[0005] Based on this, it is necessary to provide a clock taming and maintenance method, system, device and medium that can ensure the stability of the system's input clock without relying on an external reference signal to address the above technical problems.

[0006] A clock taming and maintaining method, the method comprising:

[0007] Acquire a clock signal waveform of a clock generator;

[0008] Taking the transition edge of the pulse signal waveform as a reference, respectively measuring the time difference between a plurality of consecutive transition edges in the clock signal waveform and the transition edge of the pulse signal waveform;

[0009] The output frequency of the clock generator is calculated by the time difference of the transition edge;

[0010] The difference between the output frequency and the expected frequency is calculated, the frequency of the clock generator is adjusted according to the difference, and a tamed clock signal is output.

[0011] A clock taming and maintaining system, the system comprising:

[0012] The clock generator is used to generate a clock signal.

[0013] The measuring device is connected to the clock generator and is used for measuring the waveform of the clock signal.

[0014] The processing chip is connected to the measuring device and is used to obtain a clock signal waveform and provide a pulse signal waveform; and calculate the clock signal waveform based on the pulse signal waveform to obtain an output frequency;

[0015] The digital-to-analog converter is connected to the processing chip and the clock generator respectively, and is used to obtain the output frequency, adjust the output frequency based on the difference between the output frequency and the expected frequency, and obtain a tamed clock signal; and convert the tamed clock signal into an analog signal, and then send it to the clock generator for output.

[0016] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the clock taming and maintaining method when executing the computer program.

[0017] A computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the clock taming and maintaining method when executed by a processor.

[0018] Compared with the prior art, the clock taming and maintaining method, system, device and medium provided by the present invention have the following effects:

[0019] 1. In terms of method, there is no need to introduce additional reference signals. Instead, the pulse signal that the chip can provide is used as a reference to directly calculate the time difference of the clock signal waveform, and then the output frequency is calculated based on the time difference. The frequency of the clock generator is adjusted according to the difference between the output frequency and the expected frequency. The time difference of the clock signal can be quickly obtained, and the taming time of the clock generator can be reduced, so that the frequency can be tamed more quickly, thereby improving the stability and accuracy of the clock output.

[0020] 2. It can effectively reduce risks such as external electromagnetic interference and enhance the system's anti-interference ability.

[0021] 3. It avoids the problem of accuracy loss during the propagation of the reference signal and the signal synchronization problem when introducing an external reference signal, making the clock adjustment process more direct and efficient.

[0022] 4. Since no external reference signal is required, the clock taming process can better adapt to changes in chip working conditions and ensure reliable operation in different environments.

[0023] 5. In terms of the system, it eliminates the need for additional reference signal sources such as external crystal oscillators, GPS signals, etc., simplifies system design, reduces hardware costs, and reduces the complexity of external reference sources in connection, configuration, and debugging. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0025] Figure 1 A schematic flow chart of a clock taming and maintaining method in one embodiment;

[0026] Figure 2 A schematic diagram of a waveform reference when calculating a time difference in an embodiment;

[0027] Figure 3 A block diagram of a clock taming and maintaining system in one embodiment;

[0028] Figure 4 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment.

[0029] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0032] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0033] Unless otherwise clearly defined and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, a physical connection, or a wireless communication connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0035] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0036] Example 1

[0037] This embodiment discloses a clock taming and maintenance method, which does not require the introduction of additional reference signals. Instead, the pulse signal that the chip can provide is used as a reference to directly calculate the time difference of the clock signal waveform, and then the output frequency is calculated according to the time difference. The frequency of the clock generator is adjusted according to the difference between the output frequency and the expected frequency. The time difference of the clock signal can be quickly obtained, and the output convergence time can be improved, so that the frequency adjustment can be performed more quickly and the stability of the clock can be improved. At the same time, it can effectively reduce the risks of external electromagnetic interference and enhance the anti-interference ability of the system. The delay problem in the propagation process of the reference signal is avoided to obtain a more accurate clock adjustment; and the signal synchronization problem when introducing an external reference signal makes the clock adjustment process more direct and efficient. In addition, since the chip's own pulse signal is used, the clock taming process can better adapt to changes in the chip's working conditions and ensure reliable operation in different environments.

[0038] refer to Figure 1 , a clock taming and maintaining method is provided, comprising the following steps:

[0039] Step 201, obtaining a clock signal waveform of a clock generator.

[0040] It is understood that when clock training is performed, the obtained signal waveform is usually required to have clear rising and falling edges to ensure accurate time measurement. Therefore, if the clock signal waveform is a non-square wave signal, it is generally necessary to convert it into a square wave.

[0041] Step 202, taking the transition edge of the pulse signal waveform as a reference, respectively measuring the time difference between a plurality of consecutive transition edges in the clock signal waveform and the transition edge of the pulse signal waveform.

[0042] It can be understood that pulse signals are generally periodic, the length of each cycle is determined by the chip's clock frequency, and its waveform has obvious rising and falling edges. Using the pulse signal waveform as a reference can provide clear rising and falling edges, facilitating the calculation of accurate clock signal time differences. In addition, pulse signals usually have strict level and time characteristics, so they can provide a more consistent reference for the clock during taming, helping to maintain the accuracy of data transmission. In addition, pulse signals can be measured periodically at a very fast speed, thereby quickly adjusting the clock signal, which is suitable for systems that require fast response. Error detection and correction during the taming process can be more timely, reducing error accumulation caused by clock drift.

[0043] Step 203: Calculate the output frequency of the clock generator by the time difference of the transition edge.

[0044] Step 204, calculating the difference between the output frequency and the expected frequency, adjusting the frequency of the clock generator according to the difference, and outputting a tamed clock signal.

[0045] In the specific implementation process of step 202, taking the transition edge of the pulse signal waveform as a reference, respectively calculating the time difference between a plurality of consecutive transition edges in the clock signal waveform and the transition edge of the pulse signal waveform, including:

[0046] In the measurement cycle, the initial jump edge of the pulse signal waveform is taken as a reference, and the time difference between the continuous jump edges and the initial jump edge in the clock signal waveform is calculated respectively.

[0047] It is worth noting that the transition edge type of the pulse signal waveform should be the same as the transition edge type of the clock signal waveform.

[0048] Specifically, within the measurement period, the initial rising edge of the pulse signal waveform is used as a reference to calculate the time difference between the multiple consecutive rising edges and the initial rising edge in the clock signal waveform. Or within the measurement period, the initial falling edge of the pulse signal waveform is used as a reference to calculate the time difference between the multiple consecutive falling edges and the initial falling edge in the clock signal waveform.

[0049] like Figure 2 As shown in the figure, an example of calculating the time difference with the rising edge is given. The START signal is a pulse signal waveform, which is mainly used to control the measurement behavior of the measuring device; the STOP signal is a clock signal waveform. In the measurement cycle, the clock signal waveform has 3 rising edges; the first rising edge of the START signal is used as the initial jump edge, and the leftmost of the initial jump edge is used as the reference to calculate the time difference between the three consecutive jump edges in the clock signal waveform and the initial jump edge, which are: TIME 1, TIME 2 and TIME 3.

[0050] In the specific implementation process of step 203, the output frequency of the clock generator is calculated by the time difference, and the calculation expression is:

[0051]

[0052] In the formula, f out Indicates the output frequency; TIME>>TIMEn indicates the time difference between the nth clock signal transition edge and the pulse signal waveform transition edge starting from the clock signal waveform.

[0053] It can be understood that by calculating the output frequency of the clock generator through the time difference between two adjacent transition edges and averaging a plurality of consecutive output frequencies, the output error can be reduced and the accuracy can be improved.

[0054] In one embodiment, the output frequency of the clock generator is filtered.

[0055] It can be understood that the output frequency of the clock generator is affected by the ambient temperature (for constant temperature crystal oscillators, this factor has little effect), material aging, input voltage ripple, etc., as well as the measurement error of the measuring device. The output frequency of the clock generator needs to be filtered to reduce the frequency regulation caused by the output frequency jitter caused by other factors, resulting in the instability of the system output. Software filtering algorithms such as Kalman filtering or extremely low-frequency digital filters can be applied to improve the impact of system noise.

[0056] It is worth noting that the clock taming and maintenance method provided by the present invention is aimed at a multi-device system, and there is clock synchronization or phase synchronization between multiple devices. For such a system, the clock taming system still requires the input of an external reference signal for phase synchronization, but since the taming of the clock frequency does not need to rely on an external reference signal, after the taming accuracy is reached, after the phase synchronization is performed according to the external reference signal, even if the external reference signal is lost, it will not affect the output of the clock system. This is because for a stable clock taming system, its output phase is long-term stable, and the discontinuity of the phase reference signal will not affect the output of the system.

[0057] Although this embodiment Figure 1The steps in the process are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0058] Example 2

[0059] Based on the clock taming and maintaining method in Example 1, this embodiment discloses a clock taming and maintaining system, such as Figure 3 As shown, the clock taming and holding system includes: a clock generator, a measuring device, a processing chip and a digital-to-analog converter. Among them:

[0060] The clock generator is used to generate a clock signal.

[0061] The measuring device is connected to the clock generator and is used for measuring the waveform of the clock signal.

[0062] The processing chip is connected to the measuring device and is used to obtain a clock signal waveform and provide a pulse signal waveform; and calculate the clock signal waveform based on the pulse signal waveform to obtain an output frequency;

[0063] The digital-to-analog converter is connected to the processing chip and the clock generator respectively, and is used to obtain the output frequency, adjust the output frequency based on the difference between the output frequency and the expected frequency, and obtain a tamed clock signal; and convert the tamed clock signal into an analog signal, and then send it to the clock generator for output.

[0064] from Figure 3 It can be seen that the clock generator, measuring device, processing chip, and digital-to-analog converter form an inner loop data processing process. Through such a design, the system does not rely on the validity of the external reference signal. When the system is in working state, the pulse signal can be used as a reference to tame and calibrate the clock generator all the time, thereby improving the long-term stability of the clock generator.

[0065] Preferably, the measuring device may employ a time-to-digital converter.

[0066] The clock taming and holding system proposed in the present invention does not rely on an external reference signal, reduces the complexity and calculation amount of the clock holding system, and avoids the situation where the system output clock signal does not meet expectations due to production and materials.

[0067] In this embodiment, the specific working process and working principle of the clock generator, the measuring device, the processing chip and the digital-to-analog converter are the same as those in the method of Embodiment 1, so they are not described in detail in this embodiment. Each unit module can be implemented in whole or in part by software, hardware and a combination thereof, and each unit module can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above unit modules.

[0068] Example 3

[0069] like Figure 4 The terminal device disclosed in this embodiment includes a transmitter, a receiver, a memory, and a processor. The transmitter is used to send instructions and data, the receiver is used to receive instructions and data, the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions stored in the memory to implement the method in the above-mentioned embodiment 1.

[0070] It should be noted that the above memory can be independent or integrated with the processor. When the memory is independently provided, the terminal device further includes a bus for connecting the memory and the processor.

[0071] Example 4

[0072] This embodiment discloses a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the method in the above-mentioned embodiment 1 is implemented.

[0073] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0074] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The above-mentioned embodiments only express several implementation modes of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.

Claims

1. A clock taming and maintaining method, characterized in that: The method comprises: Acquire a clock signal waveform of a clock generator; Taking the transition edge of the pulse signal waveform as a reference, respectively measuring the time difference between a plurality of consecutive transition edges in the clock signal waveform and the transition edge of the pulse signal waveform; The output frequency of the clock generator is calculated by the time difference of the transition edge; The difference between the output frequency and the expected frequency is calculated, the frequency of the clock generator is adjusted according to the difference, and a tamed clock signal is output.

2. The clock taming and maintaining method according to claim 1, characterized in that: It also includes that if the clock signal waveform is not a square wave, it needs to be converted into a square wave.

3. The clock taming and maintaining method according to claim 1 or 2, characterized in that: Taking the transition edge of the pulse signal waveform as a reference, respectively calculating the time difference between a plurality of consecutive transition edges in the clock signal waveform and the transition edge of the pulse signal waveform, including: In a measurement cycle, the time difference between a plurality of consecutive transition edges in the clock signal waveform and the initial transition edge is calculated respectively with reference to the initial transition edge of the pulse signal waveform.

4. The clock taming and maintaining method according to claim 3, characterized in that: In a measurement cycle, taking an initial jump edge of the pulse signal waveform as a reference, respectively calculating the time difference between a plurality of consecutive jump edges in the clock signal waveform and the initial jump edge, including: In a measurement cycle, the time difference between a plurality of consecutive rising edges in the clock signal waveform and the initial rising edge is calculated respectively with reference to the initial rising edge of the pulse signal waveform.

5. The clock taming and maintaining method according to claim 3, characterized in that: In a measurement cycle, taking an initial jump edge of the pulse signal waveform as a reference, respectively calculating the time difference between a plurality of consecutive jump edges in the clock signal waveform and the initial jump edge, including: In a measurement cycle, the time difference between a plurality of consecutive falling edges in the clock signal waveform and the initial falling edge is calculated respectively with reference to the initial falling edge of the pulse signal waveform.

6. The clock taming and maintaining method according to claim 4 or 5, characterized in that: The output frequency of the clock generator is calculated by the time difference, and the calculation expression is: In the formula, f out Indicates the output frequency; TIME>>TIMEn indicates the time difference between the nth clock signal transition edge and the pulse signal waveform transition edge starting from the clock signal waveform.

7. The clock taming and maintaining method according to claim 6, characterized in that: Also includes: The output frequency of the clock generator is filtered.

8. A clock taming and maintaining system, characterized in that, The system comprises: The clock generator is used to generate a clock signal. The measuring device is connected to the clock generator and is used for measuring the waveform of the clock signal. The processing chip is connected to the measuring device and is used to obtain a clock signal waveform and provide a pulse signal waveform; and calculate the clock signal waveform based on the pulse signal waveform to obtain an output frequency; The digital-to-analog converter is connected to the processing chip and the clock generator respectively, and is used to obtain the output frequency, adjust the output frequency based on the difference between the output frequency and the expected frequency, and obtain a tamed clock signal; and convert the tamed clock signal into an analog signal, and then send it to the clock generator for output.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the clock taming and maintaining method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the clock taming and maintaining method according to any one of claims 1 to 7 are implemented.

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