Linear voltage regulator and voltage regulation method

Abstract

The invention provides a linear voltage regulator and a voltage stabilization regulation method. The linear voltage regulator comprises a voltage stabilization module, a first acquisition module, a second acquisition module and a comparison regulation and control module, the voltage stabilizing module receives an input voltage signal and a control signal, and is used for stably adjusting a voltage amplitude to a preset value and adjusting a current value of the voltage stabilizing module based on the control signal; the first acquisition module and the second acquisition module are respectively used for acquiring current signals and voltage difference signals and outputting the current signals and the voltage difference signals to the comparison regulation and control module; the comparison regulation and control module simultaneously receives the current signal and the voltage difference signal, processes the current signal and the voltage difference signal to obtain a current-limiting value of the voltage-stabilizing module, and outputs a control signal based on the current-limiting value. According to the linear voltage regulator, the loaded voltage difference signal is detected, the current limiting value is dynamically adjusted, the current of the linear amplifier is limited, device damage and even load short circuit and overload caused by too large current are avoided, and the problem that the linear amplifier is possibly heated and damaged due to too large power is also avoided.

Description

Technical Field

[0001] The present invention relates to the field of power supplies, and in particular to a linear voltage regulator and a voltage regulation method. Background Art

[0002] When using the power supply system, it is necessary to prevent the current from exceeding the maximum tolerance range of its design. Once the current exceeds this limit, the circuit may be damaged due to overheating or breakdown.

[0003] Low Dropout Regulator (LDO) is a widely used power supply device. In the design of integrated circuit LDO, a current limiting protection mechanism must be integrated to monitor the current and implement overcurrent protection, which can prevent the LDO from being damaged due to load short circuit or load overload.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a linear voltage regulator and a voltage regulation method for solving the problems in the prior art such as damage of the LDO caused by load short circuit or load overload.

[0006] To achieve the above object and other related objects, the present invention provides a linear regulator, comprising:

[0007] A voltage stabilizing module, a first acquisition module, a second acquisition module and a comparison and control module;

[0008] The voltage stabilizing module receives an input voltage signal and a control signal, and is used to stably adjust the voltage amplitude to a preset value and output it as an output voltage signal, and to adjust the current value of the voltage stabilizing module based on the control signal;

[0009] The first acquisition module is used to acquire the current signal of the voltage stabilization module and output it to the comparison and control module;

[0010] The second acquisition module is used to collect the pressure difference signal at both ends of the voltage stabilization module and output it to the comparison and control module;

[0011] The comparison and regulation module simultaneously receives the current signal and the pressure difference signal and processes them to obtain the current limiting value of the voltage stabilization module, and outputs the control signal based on the current limiting value.

[0012] Optionally, the voltage stabilization module includes a first transistor, a first resistor, a second resistor and a first amplifier;

[0013] The first end of the first transistor receives the input voltage signal, the second end is connected to the reference ground via the second resistor and the first resistor in sequence and outputs the output voltage signal, and the control end is connected to the output end of the first amplifier and receives the control signal;

[0014] The first input terminal of the first amplifier is connected to a connection node between the first resistor and the second resistor, and the second input terminal is connected to a first preset voltage.

[0015] Optionally, the first acquisition module includes a second transistor, a third transistor, a fourth transistor, a current source and a third resistor;

[0016] A first end of the second transistor is connected to the output voltage signal, a second end is connected to a current source, and a control end is connected to the second end;

[0017] The control end of the third transistor is connected to the control end of the second transistor, the first end is connected to the second end of the fourth transistor, and the second end is connected to the reference ground via the third resistor;

[0018] The first terminal of the fourth transistor receives the input voltage signal, and the control terminal receives the control signal;

[0019] The connection node between the third transistor and the third resistor is connected to the comparison and regulation module as the output end of the first acquisition module.

[0020] Optionally, the second acquisition module includes a fifth transistor, a resistance unit and a sixth transistor;

[0021] The first end of the fifth transistor receives the input voltage signal, the control end receives the control signal, and the second end is connected to the first end of the sixth transistor via the resistor unit;

[0022] The control end of the sixth transistor receives the output voltage signal, and the second end is connected to the comparison and regulation module as the output end of the second acquisition module.

[0023] Optionally, the resistance unit includes a fourth resistor.

[0024] Optionally, the second acquisition module further includes a conduction unit; the conduction unit is arranged in series between the resistance unit and the first end of the sixth transistor, and is used to adjust a first threshold value of the current limiting of the second acquisition module that changes with the voltage difference value.

[0025] Optionally, the conduction unit includes n diodes, where n is an integer greater than or equal to 1; when n=1, the anode of the diode is connected to the resistance unit, and the cathode is connected to the first end of the sixth transistor; when n≥2, the anode of the first-level diode is connected to the resistance unit, the cathode of the n-th-level diode is connected to the first end of the sixth transistor, and the anode of the i-th-level diode is connected to the cathode of the i-1-th-level diode, where i is an integer greater than or equal to 2.

[0026] Optionally, the comparison and regulation module includes a second amplifier and a seventh transistor;

[0027] The first input end of the second amplifier is connected to the first acquisition module and the second acquisition module, the second input end is connected to a second preset voltage, and the output end is connected to the control end of the seventh transistor;

[0028] The first end of the seventh transistor is connected to the input voltage signal, and the second end thereof outputs the control signal.

[0029] To achieve the above objectives and other related objectives, the present invention provides a voltage stabilization and regulation method, which is implemented based on the above voltage stabilizer and includes:

[0030] When the pressure difference signal is less than a first threshold, the current limiting value of the voltage stabilizing module is a first preset value;

[0031] When the pressure difference signal is greater than or equal to the first threshold value and less than the second threshold value, the current limiting value of the voltage stabilizing module decreases as the pressure difference value increases;

[0032] When the pressure difference signal is greater than or equal to a second threshold, the current limiting value of the voltage stabilizing module is a second preset value; and the first preset value is greater than or equal to the second preset value.

[0033] Optionally, the resistance value of the resistor unit is regulated to change the rate at which the current limiting value of the voltage stabilizing module decreases as the pressure difference value increases when the pressure difference signal is greater than or equal to a first threshold and less than a second threshold.

[0034] Optionally, when the second acquisition module further includes a conduction unit and the conduction unit includes n diodes, the number of diodes in the conduction unit is regulated to change a first threshold value at which the current limiting value of the voltage stabilizing module changes with the pressure difference value.

[0035] As described above, the linear voltage regulator and voltage regulation method of the present invention have the following beneficial effects:

[0036] The linear voltage regulator of the present invention dynamically adjusts the current limit value by detecting the loaded differential pressure signal, which not only limits the current of the linear amplifier, avoids device damage caused by excessive current and even load short circuit and overload, but also avoids the problem of heat damage that may occur to the linear amplifier due to excessive power. In addition, the rate at which the current limit value changes with the differential pressure value is regulated by changing the resistance value in the second acquisition module, and the first threshold value of the minimum differential pressure value at which the current limit value changes with the differential pressure value is regulated by adjusting the number of diodes in the conduction unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It shows a structural schematic diagram of a low voltage difference signal linear voltage regulator source.

[0038] Figure 2 Shown is a schematic diagram of a linear amplifier of the present invention.

[0039] Figure 3 Shown is a schematic structural diagram of the linear amplifier of the present invention.

[0040] Figure 4 It shows the working mechanism diagram of the fifth PMOS tube of the present invention as the voltage changes.

[0041] Figure 5 It shows the relationship between the current limiting value and the pressure difference signal of the voltage stabilizing module of the present invention.

[0042] Component number description

[0043] 1 Low voltage dropout signal linear regulator source

[0044] 11. First Amplifier

[0045] 12 Second Amplifier

[0046] 2 Linear Amplifier

[0047] 21 Voltage regulator module

[0048] 211 First Amplifier

[0049] 22. First acquisition module

[0050] 23 Second acquisition module

[0051] 231 resistance unit

[0052] 232 conduction unit

[0053] 24 Comparison and Control Module

[0054] 241 Second Amplifier DETAILED DESCRIPTION

[0055] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] See also Figure 1 to Figure 5 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0057] Comparative Example 1

[0058] like Figure 1 As shown, this comparative example provides a low voltage difference signal linear regulator 1 (Low Dropout Regulator, LDO), including: a first amplifier 11, a second amplifier 12, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a first resistor R1, a second resistor R2 and a third resistor R3.

[0059] Specifically, the source of the first PMOS tube P1 receives the input voltage signal VIN, the drain is connected to the reference ground GND via the second resistor R2 and the first resistor R1 connected in series and obtains the output voltage signal VOUT output, and the gate is connected to the output end of the first amplifier 11; the inverting input end of the first amplifier 11 is connected to the first reference voltage, and the non-inverting input end is connected to the node connected between the first resistor and the second resistor; the source of the second PMOS tube P2 receives the input voltage signal VIN, the drain is connected to the source of the fourth PMOS tube P4, and the gate is connected to the drain of the fifth PMOS tube; the third PMOS tube P3 The source is connected to the drain of the first PMOS tube P1, the drain is connected to the current source Ir, and the gate is connected to the drain; the drain of the fourth PMOS tube P4 is connected to the reference ground via the third resistor R3, and the gate is connected to the gate of the third PMOS tube P3; the source of the fifth PMOS tube P5 receives the input voltage signal VIN, the drain is respectively connected to the gate of the first PMOS tube P1 and the gate of the second PMOS tube P2, and the gate is connected to the output end of the second amplifier 12; the inverting input end of the second amplifier 12 is connected to the node connected between the fourth PMOS tube P4 and the third resistor R3, and the non-inverting input end is connected to the second reference voltage.

[0060] In this comparative example, the first PMOS transistor P1 in the low voltage difference signal linear regulator source 1 needs to be connected to a power source (i.e., input voltage signal VIN) and a load (i.e., output voltage signal VOUT); wherein, the power loss of the low voltage difference signal linear regulator source 1 almost all comes from the power consumed by the first PMOS transistor P1. The current passing through the first PMOS transistor P1 is I OUT , the current consumed by other parts of the low voltage dropout signal linear regulator 1 is compared with I OUT , can be ignored. The first resistor R1 and the second resistor R2 sample the output voltage VOUT and divide the voltage, and connect the sampled voltage value to the non-inverting input terminal of the first amplifier 11. The first amplifier 11 is an error amplifier, which is used to compare the sampled value with the first reference voltage Vr1, and output a bias voltage to adjust the gate voltage of the first PMOS tube P1, thereby forming a negative feedback loop to maintain the output voltage VOUT stable; after this negative feedback loop is stable, the voltages of the two input terminals of the first low voltage difference signal linear voltage regulator 11 are equal: VOUT = Vr1*(R1+R2) / R1.

[0061] In this comparative example, the low voltage difference signal linear voltage regulator 1 may have a situation where the current passing through the first PMOS tube P1 is too large, which may cause a load short circuit or load overload, and ultimately damage the low voltage difference signal linear voltage regulator 1. Therefore, in this comparative example, the current of the low voltage difference signal linear voltage regulator 1 is limited to below the rated value, and the current monitoring and overcurrent protection of the low voltage difference signal linear voltage regulator 1 are performed based on the rated value.

[0062] Specifically, the third PMOS tube P3 is connected to the current source Ir to form a bias circuit, the fourth PMOS tube acts as a source follower, the first PMOS tube P1 and the second PMOS tube P2 form a current mirror, and the second PMOS tube P2 acts as a current detection tube to collect the current I OUT Reduced in proportion to I OUT / N; N is the ratio of the width to length ratio between the first PMOS tube and the second PMOS tube. The second amplifier 12 collects the sampled current signal (I OUT / N), by comparing the size between the third resistor R3 and the second reference voltage Vr2, it is determined whether the sampled current signal exceeds the preset value. If it exceeds, the gate voltage of the fifth PMOS tube P5 is adjusted to control the drain output of the fifth PMOS tube (control the gate of the first PMOS tube P1 and the gate of the second PMOS tube P2), and finally the circuit current of the branch where the first PMOS tube P1 is located is controlled.

[0063] However, at this time, the current limit value I limitis a fixed value. When the low voltage difference signal linear voltage regulator 1 is current limited, the power loaded on the low voltage difference signal linear voltage regulator 1 is: P LDO =(VIN-VOUT)*I limit ; Where (VIN-VOUT) is the voltage difference signal between the input voltage signal and the output voltage signal of the low voltage difference signal linear voltage regulator 1, at the current limit value I limit Under the same premise, as the voltage difference signal between the input voltage signal and the output voltage signal increases, the power of the low voltage difference signal linear voltage regulator 1 will also increase accordingly, and there is still a risk of damage due to excessive power and heat.

[0064] Example

[0065] In order to solve the above problems, this embodiment provides a linear amplifier 2, which dynamically adjusts the current limiting value based on the loaded voltage difference signal, which not only limits the current of the linear amplifier 2, avoiding device damage caused by excessive current and even load short circuit and overload, but also avoids the problem of heat damage of the linear amplifier 2 due to excessive power.

[0066] like Figure 2 and Figure 3 As shown, this embodiment provides a linear amplifier 2, including: a voltage stabilizing module 21, a first acquisition module 22, a second acquisition module 23 and a comparison and regulation module 24.

[0067] like Figure 2 and Figure 3 As shown, the voltage stabilizing module 21 receives the input voltage signal VIN and the control signal, and is used to stably adjust the voltage amplitude to a preset value and output it as an output voltage signal VOUT, and based on the control signal, the current value I OUT Make adjustments.

[0068] Specifically, the voltage stabilizing module 21 includes a first transistor, a first resistor R1 , a second resistor R2 and a first amplifier 211 .

[0069] As an example, the first end of the first transistor receives an input voltage signal VIN, the second end outputs an output voltage signal VOUT, and the control end is connected to the output end of the first amplifier 211 and receives a control signal.

[0070] In this embodiment, the first transistor is configured as a PMOS transistor, which is denoted as the first PMOS transistor P1 , wherein the source of the first PMOS transistor is connected to the input voltage signal VIN, and the drain outputs the output voltage signal VOUT.

[0071] As an example, the second end of the first transistor is connected to the reference ground via the second resistor R2 and the first resistor R1 in sequence. The first resistor R1 and the second resistor R2 convert the current I OUTThe signal is sampled and output to the subsequent first amplifier 211 .

[0072] As an example, the first input terminal of the first amplifier 211 is connected to a connection node between the first resistor R1 and the second resistor R2 , and the second input terminal is connected to the first preset voltage Vr1 .

[0073] In this embodiment, the inverting input terminal of the first amplifier 211 is used as the first input terminal, and the non-inverting input terminal is used as the second input terminal. Based on the first resistor R1 and the second resistor R2, the output voltage signal VOUT is continuously sampled and output to the first amplifier 211 to form a negative feedback loop, so as to adjust the gate of the first PMOS tube P1 through the first amplifier 211 to ensure the output voltage stability. After the negative feedback loop is stable, the voltages of the two input terminals of the amplifier 1 are equal: VOUT = Vr1*(R1+R2) / R1.

[0074] It should be noted that, in this embodiment, the linear amplifier 2 performs a step-down operation, and adjusts the voltage amplitude by setting the first preset voltage Vr1 to ensure the amplitude of the output voltage signal VOUT. In addition, the specific structure of the voltage stabilizing module 21 is not limited to this embodiment, and any circuit that can perform stable output and change the voltage amplitude is within the protection scope of this embodiment.

[0075] As an example, the gate of the first transistor is connected to the output terminal of the first amplifier 211 and receives a control signal, and the current value IOUT of the voltage regulation module 21 is adjusted based on the control signal.

[0076] In this embodiment, since the control signal is directly connected to the gate of the first PMOS transistor P1 in the voltage stabilizing module, the conduction state of the first PMOS transistor can be controlled by changing the gate voltage of the first PMOS transistor to control the output of the drain current, thereby controlling the current value I of the voltage stabilizing module 21. OUT Make adjustments.

[0077] like Figure 2 and Figure 3 As shown, the first acquisition module 22 is used to acquire the current signal of the voltage stabilization module 21 and output it to the comparison and control module 24 .

[0078] Specifically, the first acquisition module 22 includes a second transistor, a third transistor, a fourth transistor, a current source Ir and a third resistor R3.

[0079] As an example, the first end of the second transistor is connected to the output voltage signal VOUT, the second end is connected to the current source Ir, and the control end is connected to the second end. The control end of the third transistor is connected to the control end of the second transistor, the first end is connected to the first end of the fourth transistor, and the second end is connected to the reference ground via the third resistor R3. The second end of the fourth transistor receives the input voltage signal VIN, and the control end receives the control signal. Among them, the connection node of the third transistor and the third resistor R3 is connected to the comparison and control module 24 as the output end of the first acquisition module 22.

[0080] In this embodiment, the second transistor, the third transistor, and the fourth transistor are all PMOS tubes, which are recorded as the second PMOS tube P2, the third PMOS tube P3, and the fourth PMOS tube P4. Among them, the source of the second PMOS tube P2 is connected to the output voltage signal VOUT, the drain is connected to the current source Ir, and the drain is connected to the gate. The gate of the third PMOS tube P3 is connected to the gate of the second PMOS tube P2, the source is connected to the drain of the fourth PMOS tube, and the drain is connected to the ground via the third resistor R3. The source of the fourth PMOS tube 4 receives the input voltage signal VIN, and the gate receives the control signal. The connection node between the third PMOS tube P3 and the third resistor R3 is connected to the comparison control module 24 as the output end of the first acquisition module 22.

[0081] In this embodiment, the control terminal of the fourth transistor (i.e., the gate of the fourth PMOS transistor P4) receives a control signal to ensure that it changes synchronously with the current change of the first PMOS transistor P1 during current limiting regulation. In addition, in this embodiment, the current signal of the voltage stabilizing module 21 refers to the current signal of the branch where the first PMOS transistor P1 is located, that is, the signal received by the load connected to the output terminal (output voltage signal VOUT). The third PMOS transistor P3 constitutes a source follower, so the voltage at the source of the third PMOS transistor P3 is V S_P3 =VOUT-V TH_P2 +V TH_P3 ≈VOUT; V TH_P2 is the threshold voltage of the second PMOS tube P2; V TH_P3 is the threshold voltage of the second PMOS tube P2. The source voltage of the second PMOS tube P2 is equal to that of the second PMOS tube P2, and the drain voltage is also equal. The first PMOS tube P1 and the fourth PMOS tube P4 form a current mirror, and the ratio of the width to length ratio of the first PMOS tube P1 and the fourth PMOS tube P4 is set to N:1. At this time, the ratio between the drain current of the first PMOS tube P1 and the fourth PMOS tube P4 is N:1, and the current of the first PMOS tube P1 obtained by sampling the branch where the fourth PMOS tube P4 is located is (I OUT / N) and outputted through the third PMOS tube P3, so as to facilitate the subsequent judgment through the sampled current to determine whether the current in the voltage stabilizing module 21 is overcurrent. Among them, N is much greater than 1. Specifically, in this embodiment, the value of N can be set based on needs. For example, if the drain current of the first PMOS tube P1 to be collected is 1A, then N is set to 10 6 ~10 4 That is, the current sampled by the branch where the fourth PMOS tube P4 is located is between 1uA and 100uA, which can ensure that the power consumption of the current limiting circuit is small.

[0082] It should be further explained that the first acquisition module 22 can also be set based on NMOS tubes and other other transistors. The actual setting of the first acquisition module 22 is not limited to this embodiment. Any setting that can copy the current of the voltage stabilizing module 21 to facilitate subsequent current limiting is within the protection scope of this embodiment.

[0083] like Figure 2 and Figure 3 As shown, the second acquisition module 23 is used to collect the pressure difference signal at both ends of the voltage stabilization module 21 and output it to the comparison and control module 24.

[0084] Specifically, the second acquisition module 23 includes a fifth transistor, a resistance unit 231 and a sixth transistor.

[0085] As an example, the first end of the fifth transistor receives the input voltage signal VIN, the control end receives the control signal, and the second end is connected to the first end of the sixth transistor via the resistor unit 231. The control end of the sixth transistor receives the output voltage signal, and the second end is connected to the comparison and regulation module 24 as the output end of the second acquisition module 23.

[0086] In this embodiment, the fifth transistor and the sixth transistor are both configured as PMOS transistors, which are respectively recorded as the fifth PMOS transistor P5 and the sixth PMOS transistor P6. The source of the fifth PMOS transistor P5 is connected to the input voltage signal VIN, the gate receives the control signal, and the drain is connected to the source of the sixth PMOS transistor P6 through the resistor unit 231. The gate of the sixth PMOS transistor P6 is connected to the output voltage signal, and the drain is connected to the comparison control module 24.

[0087] In this embodiment, the resistor unit 231 includes a fourth resistor R4, and the current limiting value I is adjusted by setting the resistance value of the fourth resistor R4. limit The ratio of the change with the voltage difference (VIN-VOUT) is to change the resistance value inside the second acquisition module 23, so that the ratio of the current between the voltage stabilizing module 21 and the second acquisition module 23 is different, so as to control the rate at which the current limit value changes with the voltage difference, that is: Figure 5The slope between point A and point B in the figure is such that when the resistance value of the fourth resistor R4 is changed to a higher resistance, the slope of the current limiting value changing with the voltage difference value is slowed down; when the resistance value of the fourth resistor R4 is adjusted to a lower resistance, the slope of the current limiting value changing with the voltage difference value is increased. Specifically, the resistance value of the fourth resistor R4 can be set based on actual needs.

[0088] As an example, the second acquisition module 23 also includes a conduction unit 232; the conduction unit 232 is arranged in series between the resistance unit and the first end of the sixth transistor, and is used to adjust the first threshold value ( Figure 5 (shown as point B in the figure).

[0089] In this embodiment, the conduction unit 232 includes n diodes, where n is an integer greater than or equal to 1.

[0090] As a first embodiment, when n=1 (such as Figure 1 As shown), the anode of the diode is connected to the resistor unit 231, and the cathode is connected to the first end of the sixth transistor.

[0091] As a second embodiment, when n≥2, the anode of the first-level diode is connected to the resistance unit, the cathode of the n-th-level diode is connected to the first end of the sixth transistor, the anode of the i-th-level diode is connected to the cathode of the i-1-th-level diode, and i is an integer greater than or equal to 2. By setting multiple diodes to adjust the current limiting value I limit The first threshold value starts to change with the pressure difference value.

[0092] In this embodiment, when the number of diodes increases, the current limiting value I can be effectively increased. limit The first threshold corresponding to the start of the change (such as Figure 5 Point B in the middle moves to the right), that is, a larger voltage difference signal is required to enter the state where the current limit value changes with the voltage difference value. When the number of diodes is reduced or even short-circuited, the current limit value I can be effectively reduced. limit The first threshold corresponding to the start of the change (such as Figure 5 Point B moves to the left), and a smaller pressure difference signal can enter the current limit value I limit The state changes with the pressure difference value.

[0093] It should be noted that the two ends of the second acquisition module 23 are respectively connected to the two ends of the voltage stabilizing module, linking the voltages at both ends of VIN-VOUT and constructing a voltage difference relationship, so as to facilitate the subsequent regulation of the current of the voltage stabilizing module 21 based on the voltage difference signal by the comparison and regulation module 24.

[0094] It should be further explained that the configuration of the second acquisition module 23 is not limited to the present embodiment, and any two-terminal relationship can be constructed and output to the subsequent comparison and control module 24, so as to facilitate the subsequent control of the current limiting value I based on the pressure difference signal relationship.limit The settings are all within the protection scope of this embodiment.

[0095] As Figure 2 and Figure 3 shown, the comparison and regulation module 24 simultaneously receives a current signal and a pressure difference signal and processes them to obtain the current limiting value I of the voltage regulation module 21 limit , and, based on the current limiting value I limit outputs a control signal.

[0096] Specifically, the comparison and regulation module 24 includes a second amplifier 241 and a seventh transistor.

[0097] As an example, the first input terminal of the second amplifier 241 is connected to the first acquisition module 22 and the second acquisition module 23, the second input terminal is connected to the second preset voltage Vr2, and the output terminal is connected to the control terminal of the seventh transistor. The first terminal of the seventh transistor is connected to the input voltage signal VIN, the control terminal is connected to the output terminal of the second amplifier 241, and the second terminal outputs a control signal.

[0098] In this embodiment, the seventh transistor is set as the seventh PMOS transistor P7. Among them, the source of the seventh PMOS transistor P7 is connected to the input voltage signal VIN, the gate is connected to the output terminal of the second amplifier 241, and the drain outputs a control signal. The second amplifier 241 compares the signals at the two input terminals. When V R3 <Vr2, the output voltage Vx of the second amplifier 241 is at a high level, causing the seventh PMOS transistor P7 to turn off; when V R3 >Vr2, the output voltage Vx of the second amplifier 241 drops, causing the seventh PMOS transistor P7 to turn on. Since in this embodiment, the drain of the seventh PMOS transistor P7 is respectively connected to the gates of the first PMOS transistor P1, the fourth PMOS transistor P4, and the fifth PMOS transistor P5, that is, the control gate voltage is output through the drain of the seventh PMOS transistor P7 to adjust the current of each branch.

[0099] It should be noted that when designing the second amplifier 241, frequency compensation needs to be performed on the second amplifier 241 so that the phase margin of the system is greater than 45 degrees and the loop is stable. When the linear voltage regulator 2 outputs current limiting and the loop is stable, the voltages at the two input terminals of the second amplifier 241 are equal, thereby realizing stable current limiting for the voltage regulation module 21.

[0100] It should be further noted that the specific settings of the comparison and regulation module 24 are not limited to this embodiment, and any setting that compares the signal magnitudes and outputs a control signal for controlling the current change is within the protection scope of this embodiment.

[0101] This embodiment also provides a voltage regulation condition method, which is implemented based on the above-mentioned linear voltage regulator 2 and includes:

[0102] Provide an input voltage signal VIN, stably adjust the voltage amplitude to a preset value and output it as an output voltage signal VOUT, and limit the current value of the voltage stabilizing module 21 based on the control signal. The current signal of the voltage stabilizing module 21 and the voltage difference signal at both ends of the voltage stabilizing module 21 are collected, and the current limiting value I of the voltage stabilizing module 21 is obtained by processing. limit , and based on the current limit value I limit Output control signal.

[0103] Specifically, when the pressure difference signal is less than the first threshold value, the current limiting value of the voltage stabilizing module 21 is a first preset value; when the pressure difference signal is greater than or equal to the first threshold value and less than the second threshold value, the current limiting value of the voltage stabilizing module 21 decreases as the pressure difference value increases; when the pressure difference signal is greater than or equal to the second threshold value, the current limiting value of the voltage stabilizing module is a second preset value; the first preset value is greater than or equal to the second preset value.

[0104] In this embodiment, when the conduction unit 232 is a diode D1, when the voltage difference signal is less than the first threshold value (Vth_P6+VD1), the current limiting value of the voltage stabilizing module 21 is the first preset value (Vr2N / R3); when the voltage difference signal is greater than or equal to the first threshold value (Vth_P6+VD1) and less than the second threshold value, the current limiting value of the voltage stabilizing module 21 decreases as the voltage difference value increases; when the voltage difference signal is greater than or equal to the second threshold value, the current limiting value of the voltage stabilizing module 21 is the second preset value (Vr2MN / (M+N)R3); the first preset value (Vr2N / R3) ​​is greater than or equal to the second preset value (Vr2MN / (M+N)R3).

[0105] Combine the following Figure 2 to Figure 5 For the current limit value above I limit To perform the analysis:

[0106] In order to facilitate understanding of the principle of the first acquisition module 22, the second acquisition module 23 is initially ignored, and the current passing through the third resistor R3 is considered to be entirely from the drain current of the third PMOS tube P5. At this time, the voltage on the third resistor R3 satisfies: V R3 =R3*I OUT / N. The second amplifier 241 compares the relationship between the sampling voltage on the third resistor R3 and the second reference voltage Vr2, and performs error amplification. Since the second amplifier 241 outputs current limiting and the loop is stable, the voltages at the two input terminals of the corresponding second amplifier 241 are equal, that is, V R3 =Vr2=R3*I OUT / N, so the output current limit value of linear regulator 2 is I limit It is Vr2*N / R3.

[0107] Next, the second acquisition module 23 is included in the analysis. In this embodiment, the threshold voltage of the sixth PMOS transistor P6 in the second acquisition module 23 is V TH_P6 , the forward voltage of diode D1 is VD1. Therefore, when VIN-VOUT <V TH_P6 +V D1 , the sixth PMOS transistor P6 and the diode D1 cannot be turned on at the same time, the drain current of the sixth PMOS transistor P6 is 0, and the voltage of the third resistor R3 will not be changed; when V IN -V OUT >V TH_P6 +V D1 When the sixth PMOS tube P6 and the diode D1 are turned on at the same time, the drain current of the sixth PMOS tube P6 needs to be calculated. Since the first PMOS tube P1 and the fifth PMOS tube P5 form a current mirror structure, the width-to-length ratio between the first PMOS tube P1 and the fifth PMOS tube P5 is set to M:1, where M is much greater than 1. The source voltages of the first PMOS tube P1 and the fifth PMOS tube P5 are equal, the gate voltages are equal, but the drain voltages are not equal, so the current ratio between the first PMOS tube P1 and the fifth PMOS tube P5 is not a simple M:1, such as Figure 4 As shown:

[0108] When (VIN-VOUT-V TH_P6 -V D1 ) / R4 OUT / M, the fifth PMOS tube P5 works in the linear region. At this time, the drain current of the sixth PMOS tube P6 is (VIN-VOUT-V TH_P7 -V D1 ) / R3.

[0109] When (VIN-VOUT-V TH_P6 -V D1 ) / R4>I OUT / M, the fifth PMOS tube P5 operates in the saturation region. At this time, the drain current of the sixth PMOS tube P6 is I OUT / M.

[0110] Therefore, based on the above analysis, we can know that: when VIN-VOUT <V TH_P6 +V D1 When VIN-VOUT increases until V TH_P6 +V D1 ≤(VIN-VOUT-V TH_P6 -V D1 ) / R4 OUT / M, the drain current of the sixth PMOS tube P6 is (VIN-VOUT-V​​TH_P7 -V D1 ) / R4; As VIN-VOUT increases, I OUT / M≤(VIN-VOUT-V TH_P6 -V D1 ) / R4, the drain current of the sixth PMOS tube P6 is I OUT / M.

[0111] like Figure 5 As shown, the drain currents of the third PMOS transistor P3 and the sixth PMOS transistor P6 flow through the third resistor R3. Therefore, at VIN-VOUT <V TH_P6 +V D1 When (such as Figure 5 The current limit value of linear regulator 2 is I limit It all depends on the third PMOS tube P3, the current limit value I limit It is Vr2*N / R3.

[0112] As VIN-VOUT increases until V TH_P6 +V D1 ≤(VIN-VOUT-V TH_P6 -V D1 ) / R4 OUT / M (such as Figure 5 As shown in point B in the figure, the sixth PMOS tube P6 enters the linear region. As (V IN -V OUT ) increases, the current limit value I limit Start to decrease.

[0113] As VIN-VOUT increases until I OUT / M≤(VIN-VOUT-V TH_P6 -V D1 ) / R4 (such as Figure 5 The sixth PMOS tube P6 enters the saturation region, and the drain current will not change. At this time, the drain currents of the third PMOS tube P3 and the fourth PMOS tube P4 are equal, and the drain currents of the fourth PMOS tube P4 and the fifth PMOS tube P5 are equal. OUT / N and I OUT The drain currents of the third PMOS tube P3 and the sixth PMOS tube P6 flow through the third resistor R3, and the voltage value on the third resistor R3 is equal to the voltage value of Vr2. The current limiting value I of the linear regulator 2 at this time can be calculated. limit V r2 MN / (M+N)R3.

[0114] ​Specifically, when the second acquisition module 23 includes a fifth transistor, a resistor unit 241, and a sixth transistor, the resistance value of the resistor unit 231 is adjusted to change the rate at which the current limiting value of the voltage stabilizing module 12 decreases as the voltage difference value increases when the voltage difference signal is greater than or equal to the first threshold value and less than the second threshold value. TH_P6 +V D1 ≤(VIN-VOUT-V TH_P6 -V D1 ), the sixth PMOS tube P6 begins to enter the linear region. Therefore, the resistance value of the regulating resistor unit 231 can regulate the drain current of the sixth PMOS tube P6.

[0115] In this embodiment, the first threshold value (that is, point A) is at least related to the sixth PMOS tube P6 and the diode D1, and the second threshold value is at least related to the sixth PMOS tube P6, the diode D1 and the fourth resistor. When the voltage difference between VIN and VOUT (VIN-VOUT) increases to IOUT / M=(VIN-VOUT-VTH_P6-VD1) / R4 (after the second threshold value), the current limit value no longer decreases with the increase of (VIN-VOUT), and IOUT / M is a fixed value. At this time, the increase in resistance value will lead to a decrease in slope. Therefore, the larger the resistance value of the fourth resistor R4, the slower the trend of the corresponding current limit value changing with the voltage difference value, that is, the slope between point A and point B becomes slower.

[0116] Specifically, when the conduction unit includes n diodes, the number of diodes in the conduction unit is adjusted to change the current limiting value I of the voltage stabilizing module 21. limit , due to V TH_P6 +V D1 ≤(VIN-VOUT-V TH_P6 -V D1 ), the sixth PMOS tube P6 begins to enter the linear region, so adding a diode can adjust the position of point B to the right and change the current limit value I limit The first threshold value changes with the pressure difference value and becomes larger. In this embodiment, the diode can also be short-circuited, so that the position of point A moves to the left, and the first threshold value of the current limiting value changes with the pressure difference value and becomes smaller.

[0117] In summary, the present invention provides a linear voltage stabilizer and a voltage regulation method, wherein the linear voltage stabilizer includes: a voltage stabilizing module, a first acquisition module, a second acquisition module and a comparison and control module; the voltage stabilizing module receives an input voltage signal and a control signal, and is used to stably adjust the voltage amplitude to a preset value, and adjust the current value of the voltage stabilizing module based on the control signal; the first acquisition module and the second acquisition module are used to collect current signals and pressure difference signals respectively, and output them to the comparison and control module; the comparison and control module simultaneously receives the current signal and the pressure difference signal, processes them to obtain the current limiting value of the voltage stabilizing module, and outputs the control signal based on the current limiting value. The linear voltage stabilizer of the present invention dynamically adjusts the current limiting value by detecting the loaded pressure difference signal, which not only limits the current of the linear amplifier, avoids device damage caused by excessive current and even load short circuit and overload, but also avoids the problem of heat damage of the linear amplifier due to excessive power. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0118] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A linear regulator, characterized in that: The linear voltage regulator at least includes: a voltage stabilization module, a first acquisition module, a second acquisition module and a comparison and control module; The voltage stabilizing module receives an input voltage signal and a control signal, and is used to stably adjust the voltage amplitude to a preset value and output it as an output voltage signal, and to adjust the current value of the voltage stabilizing module based on the control signal; The first acquisition module is used to acquire the current signal of the voltage stabilization module and output it to the comparison and control module; The second acquisition module is used to collect the pressure difference signal at both ends of the voltage stabilization module and output it to the comparison and control module; The comparison and regulation module simultaneously receives the current signal and the pressure difference signal and processes them to obtain the current limiting value of the voltage stabilization module, and outputs the control signal based on the current limiting value.

2. The linear regulator according to claim 1, characterized in that: The voltage stabilizing module includes a first transistor, a first resistor, a second resistor and a first amplifier; The first end of the first transistor receives the input voltage signal, the second end is connected to the reference ground via the second resistor and the first resistor in sequence and outputs the output voltage signal, and the control end is connected to the output end of the first amplifier and receives the control signal; The first input terminal of the first amplifier is connected to a connection node between the first resistor and the second resistor, and the second input terminal is connected to a first preset voltage.

3. The linear regulator according to claim 1, characterized in that: The first acquisition module includes a second transistor, a third transistor, a fourth transistor, a current source and a third resistor; A first end of the second transistor is connected to the output voltage signal, a second end is connected to a current source, and a control end is connected to the second end; The control end of the third transistor is connected to the control end of the second transistor, the first end is connected to the first end of the fourth transistor, and the second end is connected to the reference ground via the third resistor; The second terminal of the fourth transistor receives the input voltage signal, and the control terminal receives the control signal; The connection node between the third transistor and the third resistor is connected to the comparison and regulation module as the output end of the first acquisition module.

4. The linear regulator according to claim 1, characterized in that: The second acquisition module includes a fifth transistor, a resistance unit and a sixth transistor; The first end of the fifth transistor receives the input voltage signal, the control end receives the control signal, and the second end is connected to the first end of the sixth transistor via the resistor unit; The control end of the sixth transistor receives the output voltage signal, and the second end is connected to the comparison and regulation module as the output end of the second acquisition module.

5. The linear regulator according to claim 4, characterized in that: The resistance unit includes a fourth resistor.

6. The linear regulator according to claim 4, characterized in that: The second acquisition module also includes a conduction unit; the conduction unit is arranged in series between the resistance unit and the first end of the sixth transistor, and is used to adjust a first threshold value of the current limiting of the second acquisition module that changes with the voltage difference value.

7. The linear regulator according to claim 6, characterized in that: The conduction unit includes n diodes, where n is an integer greater than or equal to 1; when n=1, the anode of the diode is connected to the resistance unit, and the cathode is connected to the first end of the sixth transistor; when n≥2, the anode of the first-level diode is connected to the resistance unit, the cathode of the n-th-level diode is connected to the first end of the sixth transistor, and the anode of the i-th-level diode is connected to the cathode of the i-1-th-level diode, where i is an integer greater than or equal to 2.

8. The linear regulator according to claim 1, characterized in that: The comparison and regulation module includes a second amplifier and a seventh transistor; The first input end of the second amplifier is connected to the first acquisition module and the second acquisition module, the second input end is connected to a second preset voltage, and the output end is connected to the control end of the seventh transistor; The first end of the seventh transistor is connected to the input voltage signal, and the second end thereof outputs the control signal.

9. A voltage regulation method, implemented based on the linear voltage regulator according to any one of claims 1 to 8, characterized in that: When the pressure difference signal is less than a first threshold, the current limiting value of the voltage stabilizing module is a first preset value; When the pressure difference signal is greater than or equal to the first threshold value and less than the second threshold value, the current limiting value of the voltage stabilizing module decreases as the pressure difference value increases; When the pressure difference signal is greater than or equal to a second threshold, the current limiting value of the voltage stabilizing module is a second preset value; and the first preset value is greater than or equal to the second preset value.

10. The voltage stabilization and regulation method according to claim 9, characterized in that: When the second acquisition module includes a fifth transistor, a resistance unit and a sixth transistor, The resistance value of the resistor unit is regulated to change the rate at which the current limiting value of the voltage stabilizing module decreases as the pressure difference value increases when the pressure difference signal is greater than or equal to a first threshold value and less than a second threshold value.

11. The voltage stabilization and regulation method according to claim 10, characterized in that: When the second acquisition module further includes a conduction unit and the conduction unit includes n diodes, The number of diodes in the conduction unit is regulated to change a first threshold value at which the current limiting value of the voltage stabilizing module changes with the pressure difference value.

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