A configuration storage device of a reconfigurable array and a system and control method containing the same

Abstract

The present disclosure provides a configuration storage device of a reconfigurable array, a system containing the same, and a control method. The configuration storage device of the reconfigurable array includes: a bit input terminal; a bit output terminal; a selection unit; a bit data storage unit; in the configuration state, the selection unit is configured to receive configuration bit data from the bit input terminal, transmit the configuration bit data to the bit data storage unit, and store the configuration bit data in the bit data storage unit; and also includes a rotation state and an output state. In addition, the present disclosure also provides a configuration storage system of a reconfigurable array, and a corresponding control method of the system. Some embodiments of the present disclosure aim to solve the problems of high configuration switching time and uncertain configuration switching time in the prior art without increasing excessive complexity and area overhead.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a configuration storage device of a reconfigurable array and a system and a control method containing the same. Background Art

[0002] With the rapid development of big data and artificial intelligence, deep learning technology has been widely used. However, as the network size and complexity of deep learning algorithms gradually increase, traditional computer hardware can no longer meet the required acceleration performance. Therefore, it is particularly important to design a neural network hardware structure with superior performance and reconfigurable configuration. Reconfigurable arrays came into being in this context. They can flexibly configure hardware resources according to needs to efficiently execute various algorithms.

[0003] Therefore, an important computing architecture, Reconfigurable Array, was proposed. Reconfigurable arrays can be classified according to granularity, mainly including fine-grained reconfigurable arrays (FGRA) and coarse-grained reconfigurable arrays (CGRA). Among them, CGRA uses larger computing units as granularity, has higher computing performance and more friendly compiler support. As a more representative CGRA, it is a parallel computing mode in the airspace, which organizes computing resources of different granularities and functions with the hardware structure of the airspace. At runtime, according to the characteristics of the data flow, the configured hardware resources are interconnected to form a relatively fixed computing path, and the calculation is performed in a way close to "dedicated circuit"; when the algorithm and application change, it is reconfigured again to perform different tasks through configuration. It can allocate computing resources of different granularities and functions by changing the configuration data flow according to different needs. Nowadays, with the vigorous development of concepts and technologies such as AI, intelligent driving, and metaverse, users' demand for computing power is also increasing, so the configuration speed of reconfiguration of the configuration data flow of the reconfigurable array is becoming more and more important.

[0004] However, in the existing technology, there are significant problems with the reconfigurable array configuration storage structure. Although the configuration register chain structure is simple, the entire chain needs to be reconfigured during reconstruction, which is time-consuming and only suitable for simple or low switching demand scenarios. Although the dynamically reconfigured configuration structure can switch quickly, it is limited by the processing speed and area overhead of the additional controller, and the addressing method increases the configuration complexity. Although the hierarchical configuration storage structure is flexible, the reconstruction time varies depending on the configuration level and the scope of change, resulting in large time uncertainty and difficulty in adapting to high-speed switching application requirements. These problems jointly restrict the widespread application of reconfigurable arrays in scenarios that require efficient and fast response.

[0005] Therefore, the prior art still needs to be improved and enhanced. Summary of the invention

[0006] In order to solve at least one of the above problems and one or more of other potential problems, the present disclosure proposes a configuration storage device of a reconfigurable array. The configuration storage device and a configuration storage system including the same can solve the problems of high configuration switching time and uncertain configuration switching time in the prior art without increasing excessive complexity and area overhead.

[0007] In a first aspect of the present disclosure, a configuration storage device of a reconfigurable array is provided, the configuration storage device of the reconfigurable array comprising: a bit input terminal, configured to receive configuration bit data; a bit output terminal, configured to transmit the stored configuration bit data to the outside; a selection unit, configured to include a configuration state, a rotation state, and an output state; a bit data storage unit, configured to be connected in series by two or more bit data memories, wherein the first bit data memory is configured to be connected to the bit input terminal via the selection unit, and the last bit data memory is configured to be connected to the bit output terminal; in the configuration state, the selection unit is configured to receive the configuration bit number from the bit input terminal the configuration bit data is transmitted to the bit data storage unit, and the configuration bit data is stored in the bit data storage unit; in the rotation state, the selection unit is configured to connect the input end of the bit data storage unit with the output end of the bit data storage unit, transfer and store the configuration bit data stored in the bit data storage from the first bit data storage unit to the next bit data storage unit in sequence, and transfer and store the configuration bit data stored in the last bit data storage unit to the first bit data storage unit; in the output state, the configuration bit data in the last bit data storage unit is transmitted from the output end of the bit data storage unit to the bit output end.

[0008] Furthermore, in some embodiments, the number of the bit data storage devices is consistent with the number of switchable functions of the reconfigurable array.

[0009] Further, in some embodiments, when the above-mentioned selection unit is in the above-mentioned rotation state, within one clock cycle, the configuration bit data stored in the above-mentioned bit data memory is transferred and stored in sequence from the above-mentioned first bit data memory to the next bit data memory, and the configuration bit data stored in the above-mentioned last bit data memory is transferred and stored to the above-mentioned first bit data memory.

[0010] In a second aspect of the present disclosure, a configuration storage system of a reconfigurable array is provided, the configuration storage system of the reconfigurable array comprising: a plurality of the above-mentioned configuration storage devices, which are arranged to be connected in series, wherein a bit input terminal of one of the above-mentioned configuration storage devices is arranged to receive configuration bit data from a bit output terminal of a previous configuration storage device, and the bit output terminal of the above-mentioned configuration storage device is arranged to transmit configuration bit data to the outside of the above-mentioned configuration storage system and to the bit input terminal of the next configuration storage device; wherein the bit input terminal of the first configuration storage device among the above-mentioned multiple configuration storage devices is arranged to receive only configuration bit data from the outside of the above-mentioned configuration storage system, and wherein the bit output terminal of the last configuration storage device among the above-mentioned multiple configuration storage devices is arranged to transmit only configuration bit data to the outside of the above-mentioned configuration storage system.

[0011] Furthermore, in some embodiments, the plurality of configuration storage devices being arranged to be connected in series refers to: a first series link from a first configuration storage device to an Nth configuration storage device connected in series, where N is a positive integer.

[0012] Furthermore, in some embodiments, the configuration storage system further comprises: an additional plurality of configuration storage devices matching the plurality of configuration storage devices, wherein the additional plurality of configuration storage devices are configured to be connected in series.

[0013] Further, in some embodiments, a bit input terminal of a configuration storage device among the above-mentioned additional multiple configuration storage devices is configured to receive configuration bit data from a bit output terminal of a previous configuration storage device, and a bit output terminal of the above-mentioned configuration storage device is configured to transmit configuration bit data to the outside of the above-mentioned configuration storage system and to a bit input terminal of a next configuration storage device; wherein the bit input terminal of the first configuration storage device among the above-mentioned additional multiple configuration storage devices is configured to only receive configuration bit data from outside the above-mentioned configuration storage system, and wherein the bit output terminal of the last configuration storage device among the above-mentioned additional multiple configuration storage devices is configured to only transmit configuration bit data to the outside of the above-mentioned configuration storage system.

[0014] Further, in some embodiments, the additional plurality of configuration storage devices being arranged to be connected in series refers to: a second series link from the N+1th configuration storage device to the N+Mth configuration storage device connected in series, where M is a positive integer.

[0015] Further, in some embodiments, the bit output end of the above-mentioned Nth configuration storage device and the bit output end of the above-mentioned N+Mth configuration storage device are configured to be connected to the above-mentioned Nth bit output selection unit, so as to transmit the bit configuration data of the bit output end of the above-mentioned Nth configuration storage device or the bit output end of the above-mentioned N+Mth configuration storage device to outside the above-mentioned configuration storage system.

[0016] Further, in some embodiments, when the number of configuration storage devices in the above-mentioned second series link is N; the bit output terminal of the above-mentioned first configuration storage device and the bit output terminal of the above-mentioned N+1th configuration storage device are configured to be connected to the above-mentioned first bit output selection unit, so as to be used for transmitting the bit configuration data of the bit output terminal of the above-mentioned first configuration storage device or the bit output terminal of the above-mentioned N+1th configuration storage device to the outside of the above-mentioned configuration storage system; the bit output terminal of the above-mentioned Nth configuration storage device and the bit output terminal of the above-mentioned 2Nth configuration storage device are configured to be connected to the above-mentioned Nth bit output selection unit, so as to be used for transmitting the bit configuration data of the bit output terminal of the above-mentioned Nth configuration storage device or the bit output terminal of the above-mentioned 2Nth configuration storage device to the outside of the above-mentioned configuration storage system.

[0017] Further, in some embodiments, the configuration storage system further includes: a first serial link output state, a second serial link output state; when the configuration storage system is set to the first serial link output state, the bit configuration data from the bit output end of the first configuration storage device to the bit output end of the Nth configuration storage device is transmitted to the outside of the configuration storage system by the first bit output selection unit to the Nth bit output selection unit; when the configuration storage system is set to the second serial link output state, the bit configuration data from the bit output end of the N+1th configuration storage device to the bit output end of the 2Nth configuration storage device is transmitted to the outside of the configuration storage system by the N+1th bit output selection unit to the 2Nth bit output selection unit.

[0018] Further, in some embodiments, the above-mentioned configuration storage system also includes: a first serial link configuration state, a second serial link configuration state; when the above-mentioned configuration storage system is set to the above-mentioned first serial link configuration state, the above-mentioned 1st bit output selection unit to the above-mentioned Nth bit output selection unit receive bit configuration data from outside the above-mentioned configuration storage system, or the selection units in one or more configuration storage devices in the above-mentioned first serial link configuration are in a rotation state; when the above-mentioned configuration storage system is set to the above-mentioned second serial link output state, the above-mentioned N+1th bit output selection unit to the above-mentioned 2Nth bit output selection unit receive bit configuration data from outside the above-mentioned configuration storage system, or the selection units in one or more configuration storage devices in the above-mentioned second serial link configuration are in a rotation state.

[0019] In a third aspect of the present disclosure, a control method for a configuration storage system of a reconfigurable array is provided, the control method comprising: setting the above-mentioned configuration storage system to the above-mentioned first series link output state and the above-mentioned second series link output state; or setting the above-mentioned configuration storage system to a combination of the above-mentioned first series link output state and the above-mentioned second series link configuration state; or setting the above-mentioned configuration storage system to a combination of the above-mentioned second series link output state and the above-mentioned first series link configuration state; or setting the above-mentioned configuration storage system to a combination of the above-mentioned first series link configuration state and the above-mentioned first series link configuration state.

[0020] Compared with the prior art, the present disclosure has at least the following beneficial effects.

[0021] (1) In some embodiments, by setting the bit data storage unit to a serial structure of bit data storage, in its configuration state, the configuration bit data from the bit input end is transmitted to the bit data storage unit through the selection unit, and the configuration bit data is stored in the bit data storage unit, so as to realize the complete configuration of the bit data storage in the bit data storage unit; in its rotation state, the input end of the bit data storage unit and the output end of the bit data storage unit are connected end to end through the selection unit to form a loop, and then the configuration bit data stored in the bit data storage can be transmitted and stored from the first bit data storage to the next bit data storage in sequence, and the configuration bit data stored in the last bit data storage is transmitted and stored to the first bit data storage, so as to realize the circular transmission and storage of the configuration bit data in the loop, and form a rotation configuration; in its output state, the configuration bit data in the last bit data storage is transmitted from the output end of the bit data storage unit to the bit output end, so as to realize the continuous output of the bit data to the outside. Several commonly used configuration data can be stored in the bit data storage unit, and the configuration bit data output can be switched quickly and conveniently.

[0022] (2) Furthermore, in some embodiments, two groups of serial links are provided, namely, a first serial link and a second serial link, and the outputs of the two links are connected via corresponding bit output selection units so that the entire configuration storage system can realize that both serial links output states and select one of them for output; or realize that one of the two serial links outputs while the other serial link is configured, thereby ensuring that configuration and output can be performed simultaneously without requiring additional global configuration time or configuration switching time. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other features and advantages of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings, in which:

[0024] Figure 1A diagram showing a configuration storage device of a reconfigurable array according to some embodiments of the present disclosure;

[0025] Figure 2 A diagram showing a configuration storage system of a reconfigurable array according to some embodiments of the present disclosure;

[0026] Figure 3 A diagram of a configuration storage system of a reconfigurable array according to other embodiments of the present disclosure is shown;

[0027] Figure 4 A diagram showing a configuration storage system of a reconfigurable array according to still further embodiments of the present disclosure; and

[0028] In the various drawings, the same or corresponding reference numerals denote the same or corresponding parts. DETAILED DESCRIPTION

[0029] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0030] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0031] At present, there are mainly the following types of reconfigurable array configuration storage structures: 1) Configuration register chain structure, which uses register chains to store the configuration information of reconfigurable arrays. The structure is relatively simple, but every time the array function needs to be changed, the entire register chain needs to be reconfigured, which is very time-consuming and only suitable for application scenarios with simple functions or low switching time requirements. 2) Dynamic reconfiguration configuration structure, which pre-addresses different configurations for different functions, and then controls the address selection through an additional controller to achieve function switching. Although this configuration structure can achieve relatively fast switching logic, its speed depends on the processing speed of the additional address selection controller, and the additional controller will also require a certain area overhead. The use of addressing will also increase the complexity of configuration burning. 3) Hierarchical configuration storage structure, this configuration register structure divides the configuration registers into three levels: local configuration registers, local configuration memory, and global configuration memory. The problem with this configuration storage structure is that its reconfiguration time is uncertain. If the function configuration to be switched only needs to change one or several local configuration registers, the time taken will be relatively short. However, if the function to be switched needs to change multiple local configuration memories or even global configuration memories, the switching time will become extremely long. The uncertainty of configuration time cannot be well adapted to the application scenario of high-speed function switching.

[0032] In order to solve at least one of the above problems and one or more of other potential problems, an exemplary embodiment of the present disclosure provides a configuration storage device of a reconfigurable array, the configuration storage device of the reconfigurable array comprising a bit input terminal, a bit output terminal, a selection unit, and a bit data storage unit. The following is an expanded description in conjunction with the diagram.

[0033] Figure 1A diagram of a configuration storage device of a reconfigurable array according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the configuration storage device 100 of the reconfigurable array includes: a bit input terminal 110, which is configured to receive configuration bit data; a bit output terminal 120, which is configured to transmit the stored configuration bit data to the outside; a selection unit 130, which is configured to include a configuration state, a rotation state, and an output state; a bit data storage unit 140, which is configured to be connected in series by two or more bit data memories, wherein the first bit data memory 142 is configured to be connected to the bit input terminal 110 via the selection unit 130, and the last bit data memory 148 is configured to be connected to the bit output terminal 120; in the above configuration state, the selection unit 130 is configured to receive the above configuration bit data from the bit input terminal 110, and to transmit the above configuration bit data to the outside. The data is transmitted to the above-mentioned bit data storage unit 140, and the above-mentioned configuration bit data is stored in the above-mentioned bit data storage unit 140; in the above-mentioned rotation state, the above-mentioned selection unit 130 is configured to connect the input end of the above-mentioned bit data storage unit 140 with the output end of the above-mentioned bit data storage unit 140, transfer and store the configuration bit data stored in the above-mentioned bit data storage from the above-mentioned first bit data storage unit 142 to the next bit data storage in sequence, and transfer and store the configuration bit data stored in the above-mentioned last bit data storage unit 148 to the above-mentioned first bit data storage unit 142; in the above-mentioned output state, the configuration bit data in the above-mentioned last bit data storage unit 148 is transmitted from the output end of the above-mentioned bit data storage unit 140 to the above-mentioned bit output end 120. It should be understood that by setting the bit data storage unit to a serial structure of bit data storage, in its configuration state, the configuration bit data from the bit input end is transmitted to the bit data storage unit through the selection unit, and the configuration bit data is stored in the bit data storage unit, so as to realize the complete configuration of the bit data storage unit in the bit data storage unit; in its rotation state, the input end of the bit data storage unit and the output end of the bit data storage unit are connected end to end through the selection unit to form a loop, and then the configuration bit data stored in the bit data storage can be transferred and stored from the first bit data storage to the next bit data storage in sequence, and the configuration bit data stored in the last bit data storage is transferred and stored to the first bit data storage, so as to realize the circular transfer and storage of the configuration bit data in the loop, and form a rotation configuration; in its output state, the configuration bit data in the last bit data storage is transmitted from the output end of the bit data storage unit to the bit output end, so as to realize the continuous output of the bit data to the outside. Several commonly used configuration data can be stored in the bit data storage unit, and the configuration bit data output can be switched quickly and conveniently.

[0034] In some alternative embodiments, the number of bit data storage devices in the above embodiments is consistent with the number of switchable functions set in the reconfigurable array. Thus, by presetting the configuration data, the configuration storage device of the reconfigurable array can be quickly switched to the specified configuration mode after a short switch instead of waiting for the global configuration.

[0035] Furthermore, in some preferred embodiments, when the selection unit is in the rotation state, within one clock cycle, the configuration bit data stored in the bit data memory is sequentially transferred and stored from the first bit data memory to the next bit data memory, and the configuration bit data stored in the last bit data memory is transferred and stored to the first bit data memory. In this way, one bit can be rotated per clock cycle, and the configuration bit data stored in the bit data memory can be steadily adjusted in this way so that the configuration bit data stored in the bit data memory can be transferred to the last bit data memory for external output.

[0036] Furthermore, a plurality of the above configuration storage devices may be connected in series to form a configuration storage system of a reconfigurable array.

[0037] Figure 2 A diagram of a configuration storage system of a reconfigurable array according to some embodiments of the present disclosure is shown. In the illustrated embodiment, a configuration storage system 200 of a reconfigurable array includes: a plurality of the above-mentioned configuration storage devices, which are arranged to be connected in series, wherein a bit input terminal of a configuration storage device in the middle is arranged to receive configuration bit data from a bit output terminal of a previous configuration storage device, and a bit output terminal of the above-mentioned configuration storage device is arranged to transmit configuration bit data to the outside of the above-mentioned configuration storage system and to the bit input terminal of the next configuration storage device; in addition, a bit input terminal of the first configuration storage device 202 (shown at the far left end) is arranged to receive only configuration bit data from outside the configuration storage system 200; in addition, a bit output terminal of the last configuration storage device 208 (shown at the far right end) is arranged to transmit only configuration bit data to the outside of the above-mentioned configuration storage system 200. Thus, each of the configuration storage devices can output one bit of configuration data. It should be understood that these series links configured to connect the configuration storage devices in series may be referred to as first series links, and such a first series link is a link connecting the 1st configuration storage device to the Nth configuration storage device in series, where N is a positive integer.

[0038] Furthermore, an additional plurality of the above configuration storage devices may be connected in series to form another series link consisting of a plurality of configuration storage devices, which may be referred to as a second series link, for example.

[0039] Figure 3The configuration storage system of the reconfigurable array according to other embodiments of the present disclosure is shown in the figure. In the illustrated embodiment, the configuration storage device of a reconfigurable array of the first series link and the configuration storage device of a reconfigurable array of the second series link form a parallel circuit, and the bit configuration data of one of them is controlled to be output externally through the bit output selection unit below.

[0040] It should be understood that the second series link is similar to the first series link, wherein a bit input terminal of one of the plurality of configuration storage devices is configured to receive configuration bit data from a bit output terminal of a previous configuration storage device, and the bit output terminal of the configuration storage device is configured to transmit configuration bit data to outside the configuration storage system and to a bit input terminal of a next configuration storage device; wherein the bit input terminal of a first configuration storage device of the additional plurality of configuration storage devices is configured to receive only configuration bit data from outside the configuration storage system, and wherein the bit output terminal of a last configuration storage device of the additional plurality of configuration storage devices is configured to transmit only configuration bit data to outside the configuration storage system.

[0041] Further, the configuration storage devices of the second series link are connected in series from the N+1th configuration storage device to the N+Mth configuration storage device, where M is a positive integer. Further, in some embodiments, the bit output end of the Nth configuration storage device and the bit output end of the corresponding N+Mth configuration storage device are optionally configured to be connected to the above-mentioned Nth bit output selection unit, so as to transmit the bit configuration data of the bit output end of the Nth configuration storage device or the bit output end of the N+Mth configuration storage device to the outside of the configuration storage system. Specifically, see also Figure 4 ,exist Figure 4 , it can be seen that M is equal to N; in this case, the overall performance is: the bit output terminal of the 1st configuration storage device and the bit output terminal of the (N+1)th configuration storage device are configured to be connected to the 1st bit output selection unit 250-1, so as to be used for transmitting the bit configuration data of the bit output terminal of the 1st configuration storage device or the bit output terminal of the (N+1)th configuration storage device to the outside of the configuration storage system; the bit output terminal of the Nth configuration storage device and the bit output terminal of the 2Nth configuration storage device are configured to be connected to the Nth bit output selection unit 250-N, so as to be used for transmitting the bit configuration data of the bit output terminal of the Nth configuration storage device or the bit output terminal of the 2Nth configuration storage device to the outside of the configuration storage system.

[0042] Further, in some embodiments, when the first series link is in the output state, the second series link is in the output state; that is, when the configuration storage system is set to the first series link output state, the bit configuration data from the bit output end of the first configuration storage device to the bit output end of the Nth configuration storage device is transmitted to the outside of the configuration storage system by the first bit output selection unit to the Nth bit output selection unit; and when the configuration storage system is set to the second series link output state, the bit configuration data from the bit output end of the N+1th configuration storage device to the bit output end of the 2Nth configuration storage device is transmitted to the outside of the configuration storage system by the N+1th bit output selection unit to the 2Nth bit output selection unit. Then, in this example embodiment, the bit configuration data output of the corresponding configuration storage device in the first series link or the second series link can be selected by the corresponding bit output selection unit. Correspondingly, the configuration storage system further includes: a first serial link configuration state, a second serial link configuration state; when the configuration storage system is set to the first serial link configuration state, the first bit output selection unit to the Nth bit output selection unit receive bit configuration data from outside the configuration storage system, or the selection unit in one or more configuration storage devices in the first serial link configuration is in a reversal state; when the configuration storage system is set to the second serial link output state, the N+1th bit output selection unit to the 2Nth bit output selection unit receive bit configuration data from outside the configuration storage system, or the selection unit in one or more configuration storage devices in the second serial link configuration is in a reversal state. Subsequently, in this exemplary embodiment, the corresponding configuration storage devices in the first serial link and the second serial link can be configured simultaneously. Correspondingly, the configuration storage system also includes: the first series link is in a configuration state, and the second series link is in an output state; or the second series link is in a configuration state, and the first series link is in an output state; thereby one path is configured and the other path is output, which can avoid the entire configuration storage system being completely in a configuration state, thereby causing time uncertainty when adopting a new configuration, such as an application scenario where high-speed switching cannot be achieved (because it takes a lot of time to configure before it can run under the configuration).

[0043] In this regard, for the configuration storage system of the reconfigurable array including the first series link and the second series link, the inventor of the present disclosure also provides a corresponding control method, which includes: setting the configuration storage system to the output state of the first series link and the output state of the second series link; or setting the configuration storage system to the combination of the output state of the first series link and the configuration state of the second series link; or setting the configuration storage system to the combination of the output state of the second series link and the configuration state of the first series link; or setting the configuration storage system to the combination of the configuration state of the first series link and the configuration state of the first series link. It should be understood that the control method is for setting the control of two groups of series links (i.e., the first series link and the second series link), and the output of the two links is transmitted through the bit output selection unit so that the entire configuration storage system can realize the output state of both series links and select one of them for output; or realize that one of the two series links is output while the other series link is configured, so as to ensure that configuration and output can be performed simultaneously without requiring additional global configuration time or switching configuration time.

[0044] It should be understood that in the above embodiments, the selection unit or the bit output selection unit may be a multiplexer (MUX), or may be composed of an AND gate, a NOT gate, an OR gate, a tri-state gate, a gated clock, or other devices, as long as it can perform similar functions.

[0045] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0046] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A configuration storage device for a reconfigurable array, characterized in that: include: A bit input terminal is configured to receive configuration bit data; A bit output terminal configured to transmit the stored configuration bit data to the outside; A selection unit is configured to include a configuration state, a rotation state, and an output state; A bit data storage unit is configured to be connected in series by a plurality of bit data storages, wherein the first bit data storage is configured to be connected to the bit input terminal via the selection unit, and the last bit data storage is configured to be connected to the bit output terminal; In the configuration state, the selection unit is configured to receive the configuration bit data from the bit input terminal, transmit the configuration bit data to the bit data storage unit, and store the configuration bit data in the bit data storage unit; in the rotation state, the selection unit is configured to connect the input terminal of the bit data storage unit with the output terminal of the bit data storage unit, transfer and store the configuration bit data stored in the bit data storage from the first bit data storage unit to the next bit data storage unit in sequence, and transfer and store the configuration bit data stored in the last bit data storage unit to the first bit data storage unit; In the output state, the configuration bit data in the last bit data memory is transmitted from the output end of the bit data storage unit to the bit output end.

2. The device according to claim 1, characterized in that The number of the bit data memories is consistent with the number of switchable functions of the reconfigurable array.

3. The device according to claim 1, characterized in that When the selection unit is in the rotation state, within one clock cycle, the configuration bit data stored in the bit data memory is transferred and stored in sequence from the first bit data memory to the next bit data memory, and the configuration bit data stored in the last bit data memory is transferred and stored to the first bit data memory.

4. A configuration storage system comprising a reconfigurable array of the apparatus according to any one of claims 1 to 3, characterized in that: include: A plurality of the configuration storage devices are arranged to be connected in series, wherein a bit input terminal of one of the plurality of configuration storage devices connected in series is arranged to receive configuration bit data from a bit output terminal of a previous configuration storage device, and a bit output terminal of the configuration storage device is arranged to transmit configuration bit data to the outside of the configuration storage system and to a bit input terminal of a next configuration storage device; wherein a bit input terminal of a first configuration storage device among the plurality of configuration storage devices connected in series is arranged to receive only configuration bit data from outside the configuration storage system, and wherein a bit output terminal of a last configuration storage device among the plurality of configuration storage devices connected in series is arranged to transmit only configuration bit data to the outside of the configuration storage system.

5. The system according to claim 4, characterized in that The plurality of configuration storage devices being arranged to be connected in series means: A first series link is connected in series from a 1st configuration storage device to an Nth configuration storage device, where N is a positive integer.

6. The system according to claim 5, characterized in that The configuration storage system also includes: An additional plurality of configuration storage devices matching the plurality of configuration storage devices connected in series, the additional plurality of configuration storage devices being arranged to be connected in series.

7. The system according to claim 6, characterized in that A bit input of one of the additional plurality of configuration storage devices is configured to receive configuration bit data from a bit output of a previous configuration storage device, and a bit output of the configuration storage device is configured to transmit configuration bit data out of the configuration storage system and to a bit input of a next configuration storage device; The bit input terminal of the first configuration storage device in the additional plurality of configuration storage devices is configured to only receive configuration bit data from outside the configuration storage system, and the bit output terminal of the last configuration storage device in the additional plurality of configuration storage devices is configured to only transmit configuration bit data to outside the configuration storage system.

8. The system according to claim 6, characterized in that The additional plurality of configuration storage devices being arranged to be connected in series means: A second series link is connected in series from the N+1th configuration storage device to the N+Mth configuration storage device, where M is a positive integer.

9. The system according to claim 8, characterized in that The bit output end of the Nth configuration storage device and the bit output end of the N+Mth configuration storage device are configured to be connected to the Nth bit output selection unit for transmitting the bit configuration data of the bit output end of the Nth configuration storage device or the bit output end of the N+Mth configuration storage device to outside the configuration storage system.

10. The system according to claim 8, characterized in that When the number of configuration storage devices in the second series link is N; The bit output terminal of the first configuration storage device and the bit output terminal of the N+1th configuration storage device are configured to be connected to a first bit output selection unit, so as to transmit the bit configuration data of the bit output terminal of the first configuration storage device or the bit output terminal of the N+1th configuration storage device to outside the configuration storage system; The bit output end of the Nth configuration storage device and the bit output end of the 2Nth configuration storage device are configured to be connected to the Nth bit output selection unit to transmit the bit configuration data of the bit output end of the Nth configuration storage device or the bit output end of the 2Nth configuration storage device to outside the configuration storage system.

11. The system according to claim 10, characterized in that The configuration storage system further includes: a first serial link output state, a second serial link output state; When the configuration storage system is set to the first serial link output state, the bit configuration data from the bit output end of the first configuration storage device to the bit output end of the Nth configuration storage device is transmitted to the outside of the configuration storage system by the first bit output selection unit to the Nth bit output selection unit; When the configuration storage system is set to the second serial link output state, the bit configuration data from the bit output end of the N+1th configuration storage device to the bit output end of the 2Nth configuration storage device is transmitted to the outside of the configuration storage system by the N+1th bit output selection unit to the 2Nth bit output selection unit.

12. The system according to claim 11, characterized in that The configuration storage system further includes: a first serial link configuration state, a second serial link configuration state; When the configuration storage system is set to the first serial link configuration state, the first bit output selection unit to the Nth bit output selection unit receive bit configuration data from outside the configuration storage system, or the selection unit in one or more configuration storage devices in the first serial link configuration is in a rollover state; When the configuration storage system is set to the second serial link output state, the N+1th bit output selection unit to the 2Nth bit output selection unit receive bit configuration data from outside the configuration storage system, or the selection units in one or more configuration storage devices in the second serial link configuration are in a rotation state.

13. A method for controlling a configuration storage system of a reconfigurable array as claimed in claim 12, characterized in that: include: setting the configuration storage system to the first series link output state and the second series link output state; or setting the configuration storage system to a combination of the first series link output state and the second series link configuration state; or setting the configuration storage system to a combination of the second series link output state and the first series link configuration state; Or the configuration storage system is set to the first series link configuration state and a combination of the first series link configuration state.

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