First-in first-out control system and chip

Abstract

The invention discloses a first-in first-out control system and a chip, and relates to the technical field of first-in first-out. The system comprises a plurality of first-in-first-out buffers, a plurality of first-in-first-out buffer The input end of the control circuit is connected with the output end of an external data generation device, the first output end of the control circuit is connected with the write-in ends of the first-in-first-out buffers, and the read end of the control circuit is connected with the read-out ends of the first-in-first-out buffers. The second output end of the control circuit is connected with the input end of an external data receiving device, and the control circuit is used for determining at least one first target buffer from the first-in first-out buffers and writing to-be-written data generated by an external data generation device into the first target buffer; and determining at least one second target buffer from the plurality of first-in first-out buffers, reading data from the second target buffer, and sending the read data to an external data receiving device, the number of the first target buffers being the same as the number of the second target buffers.

Description

Technical Field

[0001] The present invention relates to the field of first-in first-out technology, and in particular to a first-in first-out control system and a chip. Background Art

[0002] FIFO (First Input First Output) is a commonly used data buffer and memory in chip design. It has the characteristics of first-in first-out. Asynchronous FIFO is usually used to store some cross-clock domain data. Reading and writing data based on first-in first-out is of great significance. Summary of the invention

[0003] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, the first object of the present invention is to provide a first-in-first-out control system to realize data reading and writing based on first-in-first-out.

[0004] The second objective of the present invention is to provide a chip.

[0005] To achieve the above-mentioned purpose, a first-in-first-out control system is proposed in an embodiment of the first aspect of the present invention, and the system includes: multiple first-in-first-out buffers; a control circuit, wherein the input end of the control circuit is connected to the output end of an external data generating device, the first output end of the control circuit is connected to the write end of the multiple first-in-first-out buffers, the read end of the control circuit is connected to the read end of the multiple first-in-first-out buffers, and the second output end of the control circuit is connected to the input end of an external data receiving device, and the control circuit is used to determine at least one first target buffer from the multiple first-in-first-out buffers, and write the data to be written generated by the external data generating device into the first target buffer; determine at least one second target buffer from the multiple first-in-first-out buffers, read data from the second target buffer, and send the read data to the external data receiving device, wherein the number of the first target buffers is the same as that of the second target buffers.

[0006] In addition, the first-in-first-out control system according to the embodiment of the present invention may also have the following additional technical features: In one embodiment of the present invention, the control circuit includes a mode control device and a write controller, the output end of the mode control device is connected to the control end of the write controller, the input end of the write controller is designed to be the input end of the control circuit, and the output end of the write controller is designed to be the first output end of the control circuit; wherein, when the mode control device controls the working mode of the write controller to be a combination mode, the write controller is used to determine that the first target buffer is all the first-in-first-out buffers, and write the data to be written into the first target buffer; when the mode control device controls the working mode of the write controller to be a split mode, the write controller is used to determine one of the first target buffers from the multiple first-in-first-out buffers according to the data type of the data to be written, and write the data to be written into the first target buffer.

[0007] In one embodiment of the present invention, the write controller includes: a plurality of first selection devices, the output ends of the plurality of first selection devices are connected one-to-one with the write ends of the plurality of first-in-first-out buffers; a write control circuit includes a plurality of output ends, the plurality of output ends of the write control circuit are connected one-to-one with the first input ends of the plurality of first selection devices, the write control circuit is used to determine the first target buffer, and output a first write enable signal to the first selection device corresponding to the first target buffer; a selector includes a plurality of output ends, the plurality of output ends of the selector are connected one-to-one with the second input ends of the plurality of first selection devices, the selector is used to determine the first target buffer, and output a second write enable signal to the first selection device corresponding to the first target buffer; wherein, when the working mode is a combination mode, the first selection device is used to send the first write enable signal to the first-in-first-out buffer, and when the working mode is a split mode, the first selection device is used to send the second write enable signal to the first-in-first-out buffer.

[0008] In one embodiment of the present invention, the control circuit further includes a write counter, which is used to generate a first counting result based on the data to be written. The write control circuit includes: multiple first enabling devices, the output ends of the multiple first enabling devices are connected to the first input ends of the multiple first selection devices in a one-to-one correspondence, the control ends of the multiple first enabling devices are all connected to the output end of the write counter, each of the first enabling devices stores a first trigger data, and the first trigger data stored in any two of the first enabling devices are different. For any one of the first enabling devices, when the first counting result is consistent with the first trigger data stored in the first enabling device, the first enabling device outputs the first write enable signal.

[0009] In one embodiment of the present invention, the control circuit further includes a read controller, the control end of the read controller is connected to the output end of the mode control device, the read end of the read controller is designed as the read end of the control circuit, the output end of the read controller is designed as the second output end of the control circuit, and the read controller is used to read data from the second target buffer; wherein, when the mode control device controls the working mode of the read controller to be a combination mode, the read controller determines that the second target buffer is all of the first-in-first-out buffers; when the mode control device controls the working mode of the read controller to be a split mode, the read controller determines one second target buffer from multiple first-in-first-out buffers.

[0010] In one embodiment of the present invention, the control circuit also includes a read counter, which is used to generate a second counting result. The read controller includes: multiple second enabling devices, the output ends of the multiple second enabling devices are connected to the read ends of the multiple first-in-first-out buffers in a one-to-one correspondence, the control ends of the multiple second enabling devices are all connected to the output end of the read counter, each of the second enabling devices stores a second trigger data, and the second trigger data stored in any two second enabling devices are different. For any second enabling device, when the second counting result is consistent with the second trigger data stored in the second enabling device, the second enabling device outputs a first read enable signal to the corresponding first-in-first-out buffer.

[0011] In one embodiment of the present invention, the read controller further includes: a plurality of second selection devices, the output ends of the plurality of second selection devices are connected one-to-one with the write ends of the plurality of first-in-first-out buffers, the first input ends of the plurality of second selection devices are connected one-to-one with the output ends of the plurality of second enable devices, and the second input ends of the plurality of second selection devices are connected one-to-one with the plurality of output ends of the reader; the reader is used to determine the second target buffer and output a second read enable signal to the first selection device corresponding to the second target buffer; wherein, when the working mode is a combination mode, the second selection device is used to send the first read enable signal to the first-in-first-out buffer, and when the working mode is a split mode, the second selection device is used to send the second read enable signal to the first-in-first-out buffer.

[0012] In one embodiment of the present invention, the read controller further includes: a third selection device, wherein multiple input terminals of the third selection device are connected one-to-one with read terminals of multiple first-in-first-out buffers, the control terminal of the third selection device is connected to the read counter, the output terminal of the third selection device is designed to be the output terminal of the read controller, and the third selection device is used to determine the second target buffer according to the second counting result, read data from the second target buffer, and send the read data to the external data receiving device.

[0013] In one embodiment of the present invention, the read controller further includes: a fourth selection device, a first input end of the fourth selection device is connected to the output end of the third selection device, a second input end of the fourth selection device is connected to the read end of a preset first-in-first-out buffer, the output end of the fourth selection device is designed to be the output end of the read controller, the control end of the fourth selection device is connected to the output end of the mode control device, and the fourth selection device is used to send the data read by the third selection device to the external data receiving device when the working mode is a combination mode, and, when the working mode is a split mode, read data from the preset first-in-first-out buffer and send the read data to the external data receiving device.

[0014] To achieve the above object, a second embodiment of the present invention provides a chip, including the above-mentioned first-in-first-out control system.

[0015] According to the first-in-first-out control system and chip of the embodiment of the present invention, a plurality of first-in-first-out buffers are provided; a control circuit, the input end of the control circuit is connected to the output end of the external data generating device, the first output end of the control circuit is connected to the write end of the plurality of first-in-first-out buffers, the read end of the control circuit is connected to the read end of the plurality of first-in-first-out buffers, the second output end of the control circuit is connected to the input end of the external data receiving device, the control circuit is used to determine at least one first target buffer from the plurality of first-in-first-out buffers, and write the to-be-written data generated by the external data generating device into the first target buffer, and determine at least one second target buffer from the plurality of first-in-first-out buffers, and read data from the second target buffer, and send the read data to the external data receiving device, wherein the number of the first target buffer and the second target buffer is the same. Through the first-in-first-out control system, it is possible to meet the requirements of depth or reading speed by adjusting the number of the first target buffer and the second target buffer, thereby achieving high-performance first-in-first-out control.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a structural block diagram of a first-in, first-out control system according to an embodiment of the present invention; Figure 2 is a structural diagram of a write controller of an example of the present invention; Figure 3 is a structural diagram of a read controller of an example of the present invention; Figure 4 is a structural diagram of a read controller according to another example of the present invention; Figure 5 It is a structural schematic diagram of a first-in first-out control system of an example of the present invention; Figure 6 It is a structural block diagram of a chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The first-in-first-out control system and chip of the embodiment of the present invention are described below with reference to the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described with reference to the accompanying drawings are exemplary and cannot be understood as limiting the present invention.

[0019] FIFO usually has a write port and a read port. Data is read according to the first-in, first-out principle. Data at a specific location cannot be read directly. The data in the previous location can only be obtained by reading out all the previous data. In order to read and write data using first-in, first-out, the following three methods can be used: First, the FIFO depth is greater than the maximum amount of data that can be stored at one time, that is, a large-depth FIFO can prevent data loss due to the FIFO being full due to the write speed being greater than the read speed. However, data is first-in-first-out and cannot be read out according to certain application rules. In some practical applications, various types of data will be stored in this FIFO, but the software only needs a certain type of data at a time, which causes the software to read all the data, filter out the data it needs, and store the unnecessary data in a section of memory for other sub-applications to read. This will consume the time for reading and transferring, the time for filtering, and the storage space of the memory.

[0020] Second, there are multiple FIFOs. Data is written into different FIFOs according to the configuration and application rules. The hardware performs data screening before writing. In this way, the data read by the software from different FIFOs can be processed immediately. The software no longer needs to do screening or data transfer. However, the disadvantage is that the depth of each FIFO is limited due to area and cost constraints. When the data is of the same type and needs to be stored in the same FIFO, and the amount of data is greater than the FIFO depth, data loss will occur and the demand cannot be met.

[0021] Third, the combination of multiple small FIFOs and one large FIFO can take into account the advantages of the first two solutions and overcome their disadvantages. However, this will increase the chip area and cost. In two different application scenarios, there is always a part of the FIFO idle and wasted.

[0022] Therefore, the present invention proposes a first-in-first-out control system.

[0023] Figure 1 Schematic diagram of the structure of a first-in, first-out control system according to an embodiment of the present invention.

[0024] like Figure 1 As shown, the first-in-first-out control system 100 includes: a plurality of first-in-first-out buffers 200; a control circuit 300, wherein the input end of the control circuit 300 is connected to the output end of an external data generating device, the first output end of the control circuit 300 is connected to the write end of the plurality of first-in-first-out buffers 200, the read end of the control circuit 300 is connected to the read-out end of the plurality of first-in-first-out buffers 200, the second output end of the control circuit 300 is connected to the input end of an external data receiving device, the control circuit 300 is used to determine at least one first target buffer from the plurality of first-in-first-out buffers 200, and write the data to be written generated by the external data generating device into the first target buffer, the control circuit 300 is also used to determine at least one second target buffer from the plurality of first-in-first-out buffers 200, read data from the second target buffer, and send the read data to the external data receiving device, wherein the number of the first target buffers is the same as the number of the second target buffers.

[0025] It should be noted that Figure 1 Only the connection relationship between the FIFO buffer 200 and the control circuit 300 is shown, and it is not shown that the control circuit 300 includes an input terminal, a first output terminal, a second output terminal and a read terminal, nor is it shown that the FIFO buffer 200 includes a write terminal and a read terminal.

[0026] Specifically, in order to use a large-depth FIFO buffer 200 and to quickly read data without increasing chip area and cost, the FIFO control system 100 described above is designed.

[0027] The FIFO control system 100 includes a control circuit 300 and a plurality of FIFO buffers 200. The control circuit 300 can determine at least one first target buffer from the plurality of FIFO buffers 200, and write the data to be written generated by the external data generating device into the first target buffer. The control circuit 300 can also determine at least one second target buffer from the plurality of FIFO buffers 200, and read data from the second target buffer.

[0028] Through this system, the depth and data reading speed of the FIFO buffer 200 can be freely adjusted according to actual needs.

[0029] Specifically, when there is a requirement for the data reading speed of the buffer, the number of the first target buffer and the second target buffer can be determined to be one. At this time, each time a data to be written is received, the first target buffer corresponding to the data to be written is determined, and the data to be written is written into the first target buffer. In this way, when it is necessary to read data, it can be determined in which first-in-first-out buffer 200 the data to be read is stored, and after determining the first-in-first-out buffer 200 where the data to be read is stored, the first-in-first-out buffer 200 where the data to be read is stored is used as the second target buffer, and the data is read from the second target buffer.

[0030] When there is a requirement for the depth of the cache, the number of first target caches and second target caches can be determined as multiple based on the actual depth requirement. At this time, the caches that can accommodate the data to be written are the multiple first target caches. Since there are multiple first target caches, a larger amount of data to be written can be accommodated, thereby realizing a high-depth cache.

[0031] Taking the case where the number of first target buffers is three as an example, it is obvious that the amount of data that can be stored in three buffers is greater than the amount of data that can be stored in one buffer, that is, when the number of first target buffers is three, the control circuit 300 can write to-be-written data whose amount is equal to the storage amount of three buffers into the first target buffer at most, thereby realizing a high-depth buffer. Moreover, the high-depth buffer can still follow the first-in-first-out rule.

[0032] Thus, a first-in-first-out control system 100 is set up, including: multiple first-in-first-out buffers 200; a control circuit 300, the input end of the control circuit 300 is connected to the output end of the external data generating device, the first output end of the control circuit 300 is connected to the write end of the multiple first-in-first-out buffers 200, the read end of the control circuit 300 is connected to the read end of the multiple first-in-first-out buffers 200, the second output end of the control circuit 300 is connected to the input end of the external data receiving device, the control circuit 300 is used to determine at least one first target buffer from the multiple first-in-first-out buffers 200, and write the to-be-written data generated by the external data generating device into the first target buffer, and determine at least one second target buffer from the multiple first-in-first-out buffers 200, read data from the second target buffer, and send the read data to the external data receiving device, wherein the number of the first target buffers is the same as the number of the second target buffers. Through the FIFO control system 100 , it is possible to meet the requirements of depth or reading speed by adjusting the number of the first target buffer and the second target buffer, thereby achieving high-performance FIFO control.

[0033] In some embodiments of the present invention, the control circuit 300 includes a mode control device and a write controller, the output end of the mode control device is connected to the control end of the write controller, the input end of the write controller is designed to be the input end of the control circuit 300, and the output end of the write controller is designed to be the first output end of the control circuit 300; wherein, when the mode control device controls the working mode of the write controller to be a combination mode, the write controller is used to determine that the first target buffer is all first-in-first-out buffers 200, and write the data to be written into the first target buffer; when the mode control device controls the working mode of the write controller to be a split mode, the write controller is used to determine a first target buffer from multiple first-in-first-out buffers 200 according to the data type of the data to be written, and write the data to be written into the first target buffer.

[0034] Specifically, in order to better adapt to the two requirements of depth and reading speed, the working mode is set to include a combination mode and a split mode. When there is a requirement for depth, the mode control device controls the working mode of the write controller to the combination mode. When there is a requirement for speed, the mode control device controls the working mode of the write controller to the split mode.

[0035] In the combined mode, the write controller determines that the first target buffer is the entire FIFO buffer 200 and writes the data to be written into the first target buffer.

[0036] Furthermore, in order to write the data to be written into the first target buffer, for each data to be written, a buffer corresponding to the data to be written may be selected from the first target buffer, and the data to be written may be written into the corresponding buffer.

[0037] That is to say, in the combined mode, the first target buffer is all first-in-first-out buffers 200. Since there are multiple first-in-first-out buffers 200, a large amount of data to be written can be accommodated. Therefore, when the data generation circuit generates data to be written, the write controller splits the data to be written into at least two data to be written, and writes the data to be written into the first-in-first-out buffer 200. As an example, assuming that there are three data to be written, namely, data to be written 1, data to be written 2, and data to be written 3, the first target buffer corresponding to data to be written 1 is the first buffer, the first target buffer corresponding to data to be written 2 is the second buffer, and the first target buffer corresponding to data to be written 3 is the third buffer, then data to be written 1 is written into the first buffer, data to be written 2 is written into the second buffer, and data to be written 3 is written into the third buffer.

[0038] It can be seen that, at this time, the above-mentioned multiple first-in-first-out buffers 200 can be regarded as a whole, so as to achieve a high depth.

[0039] In the split mode, the write controller determines a first target buffer from the plurality of FIFO buffers 200 according to the data type of the data to be written, and writes the data to be written into the first target buffer.

[0040] That is, in the split mode, after the data generation circuit generates the data to be written, the write controller determines a first target buffer from the plurality of first-in first-out buffers 200 according to the type of the data to be written, and writes the data to be written into the first target buffer. At this time, when the data to be written needs to be read, the first target buffer corresponding to the data to be written can be determined according to the type of the data to be written to be read, and the data can be read from the first target buffer, thereby realizing high-speed reading.

[0041] In some embodiments of the present invention, a write controller includes: a plurality of first selection devices, the output ends of the plurality of first selection devices are connected one-to-one with the write ends of a plurality of first-in-first-out buffers 200; a write control circuit includes a plurality of output ends, the plurality of output ends of the write control circuit are connected one-to-one with the first input ends of the plurality of first selection devices, the write control circuit is used to determine a first target buffer, and output a first write enable signal to the first selection device corresponding to the first target buffer; a selector includes a plurality of output ends, the plurality of output ends of the selector are connected one-to-one with the second input ends of the plurality of first selection devices, the selector is used to determine the first target buffer, and output a second write enable signal to the first selection device corresponding to the first target buffer; wherein, when the working mode is a combination mode, the first selection device is used to send the first write enable signal to the first-in-first-out buffer 200, and when the working mode is a split mode, the first selection device is used to send the second write enable signal to the first-in-first-out buffer 200.

[0042] Thus, by setting a write control circuit and a selector, the write control circuit is used to output the first write enable signal required in the combination mode, and the selector is used to output the second write enable signal required in the split mode, and the first selection device can determine whether the write enable signal sent to the first-in-first-out buffer 200 is the first write enable signal or the second write enable signal. Through this setting, it is possible to switch between the combination mode and the split mode by only controlling the first selection device, thereby achieving high-speed and efficient mode switching.

[0043] In some embodiments of the present invention, the control circuit 300 further includes a write counter, which is used to generate a first counting result based on the data to be written. The write control circuit includes: multiple first enabling devices, the output ends of the multiple first enabling devices are connected one-to-one with the first input ends of the multiple first selection devices, the control ends of the multiple first enabling devices are all connected to the output end of the write counter, each first enabling device stores a first trigger data, and the first trigger data stored in any two first enabling devices are different. For any first enabling device, when the first counting result is consistent with the first trigger data stored in the first enabling device, the first enabling device outputs a first write enable signal.

[0044] Specifically, the control circuit 300 is set to also include a write counter, and the write control circuit is set to include multiple first enabling devices, the write counter is used to generate a first counting result, the first comparison result is used to compare the first counting result with the first trigger data stored internally, and confirm whether to output the first write enable signal based on the comparison result.

[0045] In order to generate the first counting result, the write counter can be set to increase the first counting result by a preset value when generating a data to be written. For example, the control circuit 300 can be set to generate a write signal each time it receives a data to be written, and the write counter can increase the first counting result by one each time it receives a write signal.

[0046] After a certain FIFO buffer 200 receives the first write enable signal, the write controller can write the current data to be written into the FIFO buffer 200 .

[0047] Thus, it is possible to control which of the multiple first enabling devices outputs the first write enable signal through the first counting result generated by the write counter, so as to determine which first-in-first-out buffer 200 the current data to be written is written into according to the first counting result generated by the write counter. With this setting, it is possible to simply and accurately write the data to be written into the first-in-first-out buffer 200.

[0048] The above-mentioned write controller is explained below with reference to a specific example.

[0049] Specifically, see Figure 2 ,exist Figure 2 In the figure, 1 is a mode control device, 2 is a write controller, 3 is a first selection device, 4 is a write control circuit, 5 is a selector, 6 is a write counter, 7 is a first enabling device, 8 is a first AND gate, and 9 is a second AND gate.

[0050] The number of the first-in-first-out buffers 200 is M. Figure 2 In the write FIFO0, write FIFO1, write FIFO2, ..., write FIFOM-1, write FIFO0 means connecting to the first first-in-first-out buffer 200, write FIFO1 means connecting to the second first-in-first-out buffer 200, write FIFO2 means connecting to the third first-in-first-out buffer 200, and write FIFOM-1 means connecting to the Mth first-in-first-out buffer 200.

[0051] Figure 2 In the example, write counter = 0 means that the first trigger data stored in the first enabling device 7 is 0, write counter = 1 means that the first trigger data stored in the first enabling device 7 is 1, write counter = 2 means that the first trigger data stored in the first enabling device 7 is 2, and write counter = M means that the first trigger data stored in the first enabling device 7 is M. In this example, the initial first count result of the write counter 6 is -1. Figure 2 0, 1, 2, ..., M-1 in the selector 5 are ports connected to the first-in-first-out buffer 200.

[0052] The first control signal output by the mode control device 1 indicating that the working mode is the combination mode is a high level signal, and the write signal is a high level signal.

[0053] When the mode control device 1 controls the working mode to be the combination mode, the mode control device 1 outputs a combination mode enable signal of a high level signal, and the high level signal is output to the first AND gate 8 and to the first selection device 3. When the mode control device 1 controls the working mode to be the split mode, the mode control device 1 outputs a split mode enable signal to the first selection device 3.

[0054] When the external data generating device generates data to be written, the control circuit 300 generates a write signal, which is a high level signal.

[0055] It can be seen that in the combination mode, when the first data to be written is generated, the control circuit 300 generates a write signal, the first AND gate 8 outputs a high level, and the write counter 6 adds 1 to the first counting result from -1 to obtain 0. At this time, the first enabling device 7 whose first trigger data is 0 outputs a high-level first write enable signal. Since the write signal is a high-level signal, the corresponding second AND gate 9 will output the first write enable signal output by the first enabling device 7 whose first trigger data is 0 to the corresponding first selection device 3, and then output the first write enable signal to the write end of the first first-in-first-out buffer 200.

[0056] After the first write enable signal is output to the first FIFO buffer 200 , the write controller 2 can write the first data to be written into the first FIFO buffer 200 .

[0057] When the second data to be written is generated, the control circuit 300 generates a write signal, the first AND gate 8 outputs a high level, the write counter 6 adds 1 to the first count result from 0 to obtain 1, and at this time, the first enabling device 7 whose first trigger data is 1 outputs a high-level first write enable signal. Since the write signal is a high-level signal, the corresponding second AND gate 9 outputs the first write enable signal output by the first enabling device 7 whose first trigger data is 1 to the corresponding first selection device 3, and then outputs it to the write end of the second first-in-first-out buffer 200.

[0058] After the first write enable signal is output to the second FIFO buffer 200 , the write controller 2 can write the second data to be written into the second FIFO buffer 200 .

[0059] The above operation is continuously performed to realize that in the combined mode, the write counter 6 will add 1 when the write signal comes, and will automatically return to 0 when the count reaches M. The write controller 2 determines which FIFO buffer 200 to write the data into based on the comparison of the write counter 6 value.

[0060] In the split mode, the selector 5 in the write controller 2 writes the data into the corresponding first-in-first-out buffer 200 according to the user configuration and the characteristics of the data to be written.

[0061] For example, assuming that it is determined that the first data to be written needs to be written into the first FIFO buffer 200 according to the characteristics of the first data to be written, the selector 5 itself can control this, or according to the user configuration, a second write enable signal can be sent through port 0 on the selector 5. Since the current working mode is the split mode, the first selection device 3 will send the second write enable signal to the first FIFO buffer 200. After the first FIFO buffer 200 receives the write enable signal, the write controller 2 can write the first data to be written into the first FIFO buffer 200.

[0062] For another example, assuming that according to the characteristics of the second data to be written, it is determined that the second data to be written needs to be written into the third first-in-first-out buffer 200, the selector 5 itself can control it, or according to the user configuration, a second write enable signal is sent through the port 2 on the selector 5. Since the current working mode is the split mode, the first selection device 3 will send the second write enable signal to the third first-in-first-out buffer 200. After the third first-in-first-out buffer 200 receives the write enable signal, the write controller 2 can write the second data to be written into the third first-in-first-out buffer 200.

[0063] In some embodiments of the present invention, the control circuit 300 further includes a read controller, wherein the control end of the read controller is connected to the output end of the mode control device, the read end of the read controller is designed as the read end of the control circuit 300, and the output end of the read controller is designed as the second output end of the control circuit 300, and the read controller is used to read data from the second target buffer; wherein, when the mode control device controls the working mode of the read controller to be a combination mode, the read controller determines that the second target buffer is all first-in-first-out buffers 200; when the mode control device controls the working mode of the read controller to be a split mode, the read controller determines a second target buffer from multiple first-in-first-out buffers 200.

[0064] That is, when the read controller reads data from the FIFO buffer 200 , it also needs to determine the second target buffer according to the working mode.

[0065] When the current working mode is the combination mode, the second target buffer is all the first-in-first-out buffers 200. At this time, the write controller polls and writes the data to be written into all the first-in-first-out buffers 200, and the read controller polls and reads data from all the first-in-first-out buffers 200 when data needs to be read.

[0066] When the current working mode is the split mode, the read controller needs to determine the FIFO buffer 200 where the data to be read is located, and uses the FIFO buffer 200 as the second target buffer, and reads data from the second target buffer.

[0067] In some embodiments of the present invention, the control circuit 300 also includes a read counter, which is used to generate a second counting result, and a read controller, including: multiple second enabling devices, the output ends of the multiple second enabling devices are connected one-to-one with the reading ends of the multiple first-in-first-out buffers 200, the control ends of the multiple second enabling devices are all connected to the output end of the read counter, each second enabling device stores a second trigger data, and the second trigger data stored in any two second enabling devices are different. For any second enabling device, when the second counting result is consistent with the second trigger data stored in the second enabling device, the second enabling device outputs a first read enable signal to the corresponding first-in-first-out buffer 200.

[0068] Specifically, the control circuit 300 is configured to also include a read counter. To generate a second counting result, the read counter can be configured to increase the second counting result by a preset value each time a signal indicating data reading is received, or the second counting result can be increased by a preset value at preset intervals.

[0069] Therefore, the second counting result generated by the read counter is used to determine which second enabling device outputs the first read enable signal, thereby quickly and accurately sending the read enable signal to the first-in-first-out buffer 200 .

[0070] In some embodiments of the present invention, the read controller further includes: a plurality of second selection devices, the output ends of the plurality of second selection devices are connected one-to-one with the write ends of the plurality of first-in-first-out buffers 200, the first input ends of the plurality of second selection devices are connected one-to-one with the output ends of the plurality of second enable devices, and the second input ends of the plurality of second selection devices are connected one-to-one with the plurality of output ends of the reader; the reader is used to determine the second target buffer and output a second read enable signal to the first selection device corresponding to the second target buffer; wherein, when the working mode is the combination mode, the second selection device is used to send the first read enable signal to the first-in-first-out buffer 200, and when the working mode is the split mode, the second selection device is used to send the second read enable signal to the first-in-first-out buffer 200.

[0071] Therefore, the read controller is configured to also include a second selection device and a reader, the reader being used to output a second read enable signal, that is, the second enable device outputs the first read enable signal required in the combination mode, and the reader outputs the second read enable signal required in the split mode. At this time, different working modes can be realized by only selecting the enable signal output to the first-in-first-out buffer 200 by the second selection device, thereby realizing fast and efficient working mode switching.

[0072] In some embodiments of the present invention, the read controller further includes: a third selection device, wherein multiple input terminals of the third selection device are connected one-to-one with the read terminals of multiple first-in-first-out buffers 200, the control terminal of the third selection device is connected to the read counter, the output terminal of the third selection device is designed to be the output terminal of the read controller, and the third selection device is used to determine the second target buffer according to the second counting result and read data from the second target buffer.

[0073] Therefore, the read controller is set to also include a third selection device, and the control end of the third selection device is connected to the output end of the read counter. At this time, according to the second counting result output by the read counter, the second enabling device outputs a first read enable signal, and the third selecting device determines the second target cache, thereby realizing outputting a read enable signal to the first-in-first-out cache 200 according to the second counting result generated by the read counter, and reading data therefrom.

[0074] In some embodiments of the present invention, the read controller further includes: a fourth selection device, a first input end of the fourth selection device is connected to the output end of the third selection device, a second input end of the fourth selection device is connected to the read end of the preset first-in-first-out buffer 200, the output end of the fourth selection device is designed to be the output end of the read controller, the control end of the fourth selection device is connected to the output end of the mode control device, and the fourth selection device is used to send the data read by the third selection device to the external data receiving device when the working mode is the combination mode, and, when the working mode is the split mode, read data from the preset first-in-first-out buffer 200 and send the read data to the external data receiving device.

[0075] The above-mentioned read controller is explained below with reference to a specific example.

[0076] Specifically, see Figure 3 and Figure 4 In this example, 10 is a read controller, 11 is a read counter, 12 is a second enabling device, 13 is a second selecting device, 14 is a third selecting device, 15 is a fourth selecting device, 16 is a third AND gate, 17 is a fourth AND gate, and 18 is a fifth AND gate. 1 is a mode control device.

[0077] in, Figure 3 For the part where the read enable signal is sent in this example, Figure 4 This is the part of the example that reads the data.

[0078] The number of the first-in-first-out buffers 200 is M. Figure 3In the read FIFO0, read FIFO1, read FIFO2, ..., read FIFOM-1, read FIFO0 means connecting to the first first-in-first-out buffer 200, read FIFO1 means connecting to the second first-in-first-out buffer 200, read FIFO2 means connecting to the third first-in-first-out buffer 200, and read FIFOM-1 means connecting to the Mth first-in-first-out buffer 200.

[0079] Likewise, Figure 4 Among the FIFO0 data, FIFO1 data, FIFO2 data, ..., FIFOM-1 data, FIFO0 data means connected to the first first-in-first-out buffer 200, FIFO1 data means connected to the second first-in-first-out buffer 200, FIFO2 data means connected to the third first-in-first-out buffer 200, and FIFOM-1 data means connected to the Mth first-in-first-out buffer 200.

[0080] Figure 3 In the example, the read counter = 0 means that the second trigger data stored in the second enabling device 12 is 0, the read counter = 1 means that the second trigger data stored in the second enabling device 12 is 1, the read counter = 2 means that the second trigger data stored in the second enabling device 12 is 2, and the read counter = M means that the second trigger data stored in the second enabling device 12 is M. In this example, the initial first count result of the read counter 11 is -1.

[0081] Figure 3 In the example, read signal 0, read signal 1, read signal 2, ..., read signal M-1 are all second read enable signals output by the reader.

[0082] The first control signal output by the mode control device 1 indicating that the working mode is the combination mode is a high level signal, and the read signal 0 is a signal indicating data reading, and is also a high level signal.

[0083] When the mode control device 1 controls the working mode to be the combination mode, the mode control device 1 outputs a combination mode enable signal of a high level signal, and the high level signal is output to the fourth AND gate 17 and output to the first selection device 3. When the mode control device 1 controls the working mode to be the split mode, the mode control device 2 outputs a split mode enable signal to the first selection device 3.

[0084] It can be seen that in the combination mode, when data reading is required, the control circuit 300 generates a read signal 0, the fourth AND gate 17 outputs a high level, and the read counter 11 adds 1 to the second counting result from -1 to obtain 0. At this time, the second enabling device 12 whose second trigger data is 0 outputs a high-level first read enable signal. Since the read signal 0 is a high-level signal, the corresponding second AND gate 9 will output the first read enable signal output by the second enabling device 12 whose second trigger data is 0 to the corresponding second selection device 13, and then output the first read enable signal to the read end of the first first-in-first-out buffer 200.

[0085] After the first read enable signal is output to the first FIFO buffer 200 , the read controller 10 can read data from the first FIFO buffer 200 .

[0086] Further, the control circuit 300 generates a read signal 0, the fourth AND gate 17 outputs a high level, the read counter 11 adds 1 to the second count result from 0 to obtain 1, and at this time, the second enabling device 12 whose second trigger data is 1 outputs a high-level first read enable signal. Since the read signal 0 is a high-level signal, the corresponding second AND gate 9 outputs the first read enable signal output by the second enabling device 12 whose second trigger data is 1 to the corresponding second selection device 13, and then outputs it to the read end of the second first-in-first-out buffer 200.

[0087] After the first read enable signal is output to the second FIFO buffer 200 , the read controller 10 can read data from the second FIFO buffer 200 .

[0088] The above operation is continuously performed until all the data to be read out are read out. Through this setting, in the combined mode, the read counter 11 will add 1 when the read signal 0 acts. When the count reaches M, it automatically returns to 0. The read controller 10 compares the read counter 11, reads data from the corresponding first-in-first-out buffer 200, and the corresponding read pointer is increased by 1. The data is output to the bus through the interface, so that all the first-in-first-out buffers 200 can be read out through one interface in the first-in-first-out order. From the user's point of view, it is a large deep buffer.

[0089] In the split mode, taking the second and third FIFO buffers 200 as an example, read interface 1 accesses the second FIFO buffer 200 through read signal 1, and the data is sent to the bus by interface 1. Read interface 2 accesses the third FIFO buffer 200 through read signal 2, and the data is sent to the bus through interface 2.

[0090] For example, assuming that the data to be read is determined to be stored in the first FIFO buffer 200, a second read enable signal read signal 0 may be issued. Since the current working mode is the split mode, the second selection device 13 sends the second read enable signal to the first FIFO buffer 200. After the first FIFO buffer 200 receives the read enable signal, the read controller 10 may read data from the first FIFO buffer 200.

[0091] For another example, assuming that the data to be read is determined to be stored in the third FIFO buffer 200, a second read enable signal read signal 2 may be issued. Since the current working mode is the split mode, the second selection device 13 will send the second read enable signal to the third FIFO buffer 200. After the third FIFO buffer 200 receives the read enable signal, the read controller 10 can read data from the third FIFO buffer 200.

[0092] See below for more information Figure 4 Describes how to read data.

[0093] When the working mode is the combination mode, the mode control device 1 outputs a combination mode enable signal of a high level signal, and the high level signal is output to the fifth AND gate 18 and output to the fourth selection device 15. When the mode control device 1 controls the working mode to be the split mode, the mode control device 2 outputs a split mode enable signal to the fourth selection device 15.

[0094] It can be seen that in the combination mode, when data reading is required, the control circuit 300 generates a read signal 0, the fifth AND gate 18 outputs a high level, and the read counter 11 adds 1 to the second counting result from -1 to obtain 0. At this time, the third selection device 14 reads data from the first first-in first-out buffer 200. Since the working mode is the combination mode, the fourth selection device 15 outputs the data read by the third selection device 14 through the read interface 0.

[0095] Further, the control circuit 300 generates a read signal 0, the fifth AND gate 18 outputs a high level, and the read counter 11 adds 1 to the second counting result from -1 to obtain 1. At this time, the third selection device 14 reads data from the second first-in first-out buffer 200. Since the working mode is the combination mode, the fourth selection device 15 outputs the data read by the third selection device 14 through the read interface 0.

[0096] By continuously executing the above operations, data output in the combined mode can be achieved.

[0097] In the split mode, when the data to be read is in the first FIFO buffer 200, the read controller 10 reads the data from the first FIFO buffer 200, and the read data is output from the read interface 0 to the external data receiving device through the fourth selection device 15.

[0098] When the data to be read out is in the second FIFO buffer 200 , the read controller 10 reads the data from the second FIFO buffer 200 , and the read data is output from the read interface 1 to the external data receiving device.

[0099] When the data to be read out is in the third FIFO buffer 200 , the read controller 10 reads the data from the third FIFO buffer 200 , and the read data is output from the read interface 2 to the external data receiving device.

[0100] When the data to be read out is in the Mth FIFO buffer 200 , the read controller 10 reads the data from the Mth FIFO buffer 200 , and the read data is output from the read interface M- 1 to the external data receiving device.

[0101] Combine the following Figure 5 The example shown is used for illustration.

[0102] exist Figure 5 FIFO0 is the first FIFO buffer 200 , FIFO1 is the second FIFO buffer 200 , FIFO2 is the third FIFO buffer 200 , and FIFO (M−1) is the Mth FIFO buffer 200 . Figure 5 The "write" in FIFO refers to the write end of the FIFO buffer 200. Figure 5 The “read” in the figure means the read end of the first-in-first-out buffer 200 .

[0103] Figure 5 In the data storage example in the combined mode, it can be seen that Figure 5 The data to be written are written into each first-in-first-out buffer 200 in the order of data 0, data 1, data 2, …, data M-1, data M, data M+1, data M+2, …, data 2M+1, …, data (N-1)×M, data (N-1)×M+1, data (N-1)×M+2, …, data N×M+1.

[0104] Specifically, the write controller 2 reorganizes the data, and stores data 0 in FIFO0, data 1 in FIFO1... When FIFO (M-1) is stored, each first-in first-out buffer 200 is stored with a data, and the new data is stored in FIFO0. The data is stored in this cyclic order. The write pointer inside each first-in first-out buffer 200 does not need to increase according to the number of stored data. At this time, the read controller 10 will also read data 0 from FIFO0, data 1 from FIFO1..., and data M from FIFO0... The data will be output to the bus through the same output interface.

[0105] Of course, in the split mode, the write controller 2 will write the data to be written with different characteristics into different first-in first-out buffers 200 according to the configurable data classification method. The relationship between the first-in first-out buffers 200 is independent. At this time, the read controller 10 will read the data from the corresponding first-in first-out buffer 200 according to the different read interfaces. The data will be output to the bus through multiple output interfaces.

[0106] In summary, the first-in-first-out control system of the embodiment of the present invention is provided with a plurality of first-in-first-out buffers; a control circuit, the input end of the control circuit is connected to the output end of the external data generating device, the first output end of the control circuit is connected to the write end of the plurality of first-in-first-out buffers, the read end of the control circuit is connected to the read end of the plurality of first-in-first-out buffers, the second output end of the control circuit is connected to the input end of the external data receiving device, the control circuit is used to determine at least one first target buffer from the plurality of first-in-first-out buffers, and write the to-be-written data generated by the external data generating device into the first target buffer, and determine at least one second target buffer from the plurality of first-in-first-out buffers, and read data from the second target buffer, and send the read data to the external data receiving device, wherein the number of the first target buffer and the second target buffer is the same. Through the first-in-first-out control system, it is possible to meet the requirements of depth or reading speed by adjusting the number of the first target buffer and the second target buffer, thereby realizing high-performance first-in-first-out control.

[0107] Furthermore, the present invention provides a chip.

[0108] Figure 6 It is a structural block diagram of a chip according to an embodiment of the present invention.

[0109] like Figure 6 As shown, the chip 1000 includes the above-mentioned first-in-first-out control system 100 .

[0110] According to the chip of the embodiment of the present invention, through the above-mentioned first-in-first-out control system, multiple first-in-first-out buffers are set; the control circuit, the input end of the control circuit is connected to the output end of the external data generating device, the first output end of the control circuit is connected to the write end of the multiple first-in-first-out buffers, the read end of the control circuit is connected to the read end of the multiple first-in-first-out buffers, the second output end of the control circuit is connected to the input end of the external data receiving device, the control circuit is used to determine at least one first target buffer from the multiple first-in-first-out buffers, and write the data to be written generated by the external data generating device into the first target buffer, and determine at least one second target buffer from the multiple first-in-first-out buffers, and read data from the second target buffer, and send the read data to the external data receiving device, wherein the number of the first target buffer and the second target buffer is the same. Through this first-in-first-out control system, it can be achieved by adjusting the number of the first target buffer and the second target buffer to meet the requirements of depth or reading speed, thereby achieving high-performance first-in-first-out control.

[0111] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or equipment (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or equipment and execute instructions), or in combination with these instruction execution systems, devices or equipment. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or equipment, or in combination with these instruction execution systems, devices or equipment. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and editable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0112] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiment, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0113] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0114] In the description of this specification, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and cannot be understood as a limitation on the present invention.

[0115] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0116] In the description of this specification, unless otherwise specified, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0117] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0118] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A first-in, first-out control system, characterized in that: The system comprises: Multiple first-in, first-out buffers; A control circuit, wherein the input end of the control circuit is connected to the output end of an external data generating device, the first output end of the control circuit is connected to the write end of a plurality of the first-in-first-out buffers, the read end of the control circuit is connected to the read end of the plurality of the first-in-first-out buffers, and the second output end of the control circuit is connected to the input end of an external data receiving device, the control circuit is used to determine at least one first target buffer from the plurality of the first-in-first-out buffers, and write the to-be-written data generated by the external data generating device into the first target buffer; determine at least one second target buffer from the plurality of the first-in-first-out buffers, read data from the second target buffer, and send the read data to the external data receiving device, wherein the number of the first target buffers is the same as the number of the second target buffers.

2. The first-in, first-out control system according to claim 1, characterized in that: The control circuit includes a mode control device and a write controller, the output end of the mode control device is connected to the control end of the write controller, the input end of the write controller is designed as the input end of the control circuit, and the output end of the write controller is designed as the first output end of the control circuit; wherein, When the mode control device controls the operation mode of the write controller to be the combined mode, the write controller is used to determine that the first target buffer is all the first-in-first-out buffers, and write the data to be written into the first target buffer; When the mode control device controls the working mode of the write controller to be a split mode, the write controller is used to determine a first target buffer from multiple first-in-first-out buffers according to the data type of the data to be written, and write the data to be written into the first target buffer.

3. The first-in, first-out control system according to claim 2, characterized in that: The write controller comprises: A plurality of first selection devices, wherein the output ends of the plurality of first selection devices are connected to the write ends of the plurality of first-in-first-out buffers in a one-to-one correspondence; A write control circuit, comprising a plurality of output terminals, wherein the plurality of output terminals of the write control circuit are connected one-to-one with the first input terminals of the plurality of first selection devices, and the write control circuit is used to determine the first target buffer and output a first write enable signal to the first selection device corresponding to the first target buffer; A selector, comprising a plurality of output terminals, wherein the plurality of output terminals of the selector are connected one-to-one with the second input terminals of the plurality of first selection devices, and the selector is used to determine the first target buffer and output a second write enable signal to the first selection device corresponding to the first target buffer; Wherein, when the working mode is a combined mode, the first selection device is used to send the first write enable signal to the first-in-first-out buffer, and when the working mode is a split mode, the first selection device is used to send the second write enable signal to the first-in-first-out buffer.

4. The first-in, first-out control system according to claim 3, characterized in that: The control circuit further includes a write counter, wherein the write counter is used to generate a first counting result according to the data to be written, and the write control circuit includes: There are multiple first enabling devices, and the output ends of the multiple first enabling devices are connected to the first input ends of the multiple first selecting devices in a one-to-one correspondence. The control ends of the multiple first enabling devices are all connected to the output end of the write counter. Each of the first enabling devices stores a first trigger data, and the first trigger data stored in any two of the first enabling devices are different. For any one of the first enabling devices, when the first counting result is consistent with the first trigger data stored in the first enabling device, the first enabling device outputs the first write enable signal.

5. The first-in, first-out control system according to claim 2, characterized in that: The control circuit further includes a read controller, a control end of the read controller is connected to an output end of the mode control device, a read end of the read controller is designed as a read end of the control circuit, an output end of the read controller is designed as a second output end of the control circuit, and the read controller is used to read data from the second target buffer; wherein, When the mode control device controls the working mode of the read controller to be the combined mode, the read controller determines that the second target buffer is all the first-in-first-out buffers; When the mode control device controls the working mode of the read controller to be the split mode, the read controller determines a second target buffer from the plurality of first-in-first-out buffers.

6. The first-in, first-out control system according to claim 5, characterized in that: The control circuit further includes a read counter, the read counter is used to generate a second counting result, and the read controller includes: A plurality of second enabling devices, the output ends of the plurality of second enabling devices are connected to the read ends of the plurality of first-in-first-out buffers in a one-to-one correspondence, the control ends of the plurality of second enabling devices are all connected to the output end of the read counter, each of the second enabling devices stores a second trigger data, and the second trigger data stored in any two of the second enabling devices are different, and for any one of the second enabling devices, when the second counting result is consistent with the second trigger data stored in the second enabling device, the second enabling device outputs a first read enable signal to the corresponding first-in-first-out buffer.

7. The first-in, first-out control system according to claim 6, characterized in that: The read controller further includes: A plurality of second selection devices, wherein the output ends of the plurality of second selection devices are connected to the write ends of the plurality of first-in-first-out buffers in a one-to-one correspondence, the first input ends of the plurality of second selection devices are connected to the output ends of the plurality of second enabling devices in a one-to-one correspondence, and the second input ends of the plurality of second selection devices are connected to the plurality of output ends of the reader in a one-to-one correspondence; The reader is used to determine the second target buffer and output a second read enable signal to a first selection device corresponding to the second target buffer; Wherein, when the working mode is a combination mode, the second selection device is used to send the first read enable signal to the first-in-first-out buffer, and when the working mode is a split mode, the second selection device is used to send the second read enable signal to the first-in-first-out buffer.

8. The first-in, first-out control system according to claim 6, characterized in that: The read controller further includes: A third selection device, wherein the multiple input terminals of the third selection device are connected one-to-one with the read terminals of the multiple first-in-first-out buffers, the control terminal of the third selection device is connected to the read counter, the output terminal of the third selection device is designed to be the output terminal of the read controller, and the third selection device is used to determine the second target buffer according to the second counting result, read data from the second target buffer, and send the read data to the external data receiving device.

9. The first-in, first-out control system according to claim 8, characterized in that: The read controller further includes: A fourth selection device, wherein a first input terminal of the fourth selection device is connected to an output terminal of the third selection device, a second input terminal of the fourth selection device is connected to a read terminal of a preset first-in-first-out buffer, an output terminal of the fourth selection device is designed to be an output terminal of the read controller, a control terminal of the fourth selection device is connected to an output terminal of the mode control device, and the fourth selection device is used to send the data read by the third selection device to the external data receiving device when the working mode is a combination mode, and to read data from the preset first-in-first-out buffer and send the read data to the external data receiving device when the working mode is a split mode.

10. A chip, characterized in that: Comprising a first-in-first-out control system according to any one of claims 1-9.

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