NOR gate-based 4-2 compressor approximate adder tree circuit

Abstract

The invention discloses a 4-2 compressor approximate adder tree circuit based on a NOR gate, and belongs to the field of integrated circuit design, the circuit is formed by repeatedly arranging a plurality of 4-2 compressors on a column, each 4-2 compressor is formed by cascading a 28-tube static complementary full adder and a NOR gate, input data on the global bit line GBL and weight data on the local bit line LBL are multiplied in the digital multiplication unit, calculation results of every four digital calculation units are sent into the 4-2 compressors, and the calculation results are sent into one channel adder tree to be accumulated after being subjected to parallel calculation by the 4-2 compressors to obtain final calculation results of the digital calculation units. According to the invention, approximate logic is utilized to simplify calculation and reduce internal bandwidth, a large amount of power consumption and waste of area resources are avoided with relatively low precision cost, and the limitation of a large-scale adder tree in a calculation circuit in a digital domain memory is broken through.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit design, and in particular to a 4-2 compressor approximate adder tree circuit based on a NOR gate. Background Art

[0002] In the traditional von Neumann architecture, the storage unit and the CPU computing unit are independent of each other and can only rely on a limited bandwidth bus to move data, resulting in the separation of storage and computing. The performance of the memory restricts the further improvement of the overall performance of the system, which is also called the storage wall problem of the von Neumann architecture. In addition, for large-scale computing and processing tasks such as AI or data, it will lead to higher transmission power consumption losses and higher hardware costs. The energy consumption of memory access is often not in the same order of magnitude as the energy consumption of CPU computing. A lot of time and energy are consumed in data transfer and memory reading and writing. The processor often finds it difficult to meet the computing power and energy efficiency requirements of neural networks.

[0003] Computing-in-Memory (CIM) is a feasible way to solve the storage wall problem. The essence of the integrated storage and computing architecture is to expand the function of the memory. On the basis of being able to store data, it can also support some common multiplication and addition or logical operations in neural networks, reduce the work of moving data, greatly reduce the interaction cost, save memory access overhead, and improve energy consumption and computing power density. It is suitable for high-efficiency convolutional neural network calculations and big data processing, and is the mainstream direction of future big data computing chip architecture.

[0004] Static Random Access Memory (SRAM) is a type of volatile memory with the advantages of fast access speed, low static power consumption, and high durability. It is more suitable for scenarios with high performance, high precision, and medium to large computing power requirements. At present, SRAM-CIM can be divided into analog domain, digital domain, and time domain computing according to the computing method.

[0005] The digital domain in-memory computing circuit uses all-digital circuits to perform calculations. The calculation precision and accuracy are high, the stability is good, and it has great application potential. However, it needs to use a large-scale adder tree to perform accumulation operations, which will generate a lot of area and power consumption costs, and the energy efficiency and area efficiency will be limited. With the increase in the number of channels in the adder tree, the number of adders in the existing level and the number of levels of the adder tree need to be increased, which will cause a significant increase in power consumption. It is known that the power consumption of a 128-channel adder tree is about 9.18 times that of a 16-channel adder tree.

[0006] In addition, in the circuit design of digital storage and calculation units, in order to effectively reduce the number of bits of intermediate results and optimize circuit complexity for performing multi-bit multiplication operations, a 4-2 compressor is often used as a key component to achieve efficient compression of the output results of four parallel multiplication calculation units. However, the 4-2 compressor can effectively reduce the number of bits of intermediate results, but it also requires certain hardware resources. When a large amount of parallel data needs to be processed, the complexity and resource usage of the circuit will be significantly increased. In addition, since the 4-2 compressor needs to frequently switch logic gates during the operation process, it will generate higher power consumption. Summary of the invention

[0007] The present invention provides a 4-2 compressor approximate adder tree circuit based on NOR gates, which uses approximate logic to simplify the calculation process and reduce the demand for internal bandwidth. It significantly reduces the waste of a large amount of power consumption and area resources at the cost of sacrificing lower precision, breaks through the limitation of large-scale adder trees in digital domain in-memory calculation circuits, and makes more efficient use of hardware resources.

[0008] The embodiment of the present invention provides a 4-2 compressor approximate adder tree circuit based on a NOR gate, comprising:

[0009] A plurality of 4-2 compressors are repeatedly arranged in columns, the input end of each 4-2 compressor is connected to a digital multiplication calculation unit, the output ends of all 4-2 compressors are commonly connected to a channel adder tree, the input data on the global bit line GBL and the weight data on the local bit line LBL are multiplied in the digital multiplication unit, the digital multiplication unit generates a 1-bit operation result, and the four 1-bit operation results are sent to the 4-2 compressors, and after being operated in parallel by the plurality of 4-2 compressors, they are sent to the channel adder tree for accumulation to obtain a final operation result;

[0010] The 4-2 compressor is formed by cascading a 28-tube static complementary full adder and a NOR gate, and the output of the 28-tube static complementary full adder serves as an input of the NOR gate.

[0011] Optionally, in one embodiment of the present invention, the 28-tube static complementary full adder adopts a complementary static CMOS adder to transform the logic equation of the binary full adder into a complementary CMOS circuit. The 28-tube static complementary full adder has two binary inputs A and B and C in A carry input, after operation, the output S and the carry output C are obtained out , Carry C out The calculation involves the carry C of the previous level in and the result of the operation at the current level, the logical expression is C out =AB+BC i +AC i, the final sum is generated by the XOR logic of the three inputs, and the expression after the corresponding logical transformation is

[0012]

[0013] Optionally, in one embodiment of the present invention, every four 1-bit calculation results A0, A1, A2, and A3 of the digital multiplication calculation unit are used as inputs of the 4-2 compressor, wherein the calculation results of the three digital multiplication calculation units A1, A2, and A3 are used as three inputs of the 28-tube static complementary full adder, and the output S and A0 of the 28-tube static complementary full adder are used as two inputs of the NOR gate, and the final sum result S[0] and the carry result S[1] are obtained through the NOR gate operation.

[0014] The 4-2 compressor approximate adder tree circuit based on the NOR gate of the embodiment of the present invention is composed of multiple 4-2 compressors repeatedly arranged in columns, each 4-2 compressor is cascaded by a 28-tube static complementary full adder and a NOR gate, the input data on the global bit line GBL and the weight data on the local bit line LBL are multiplied in the digital multiplication unit, and the calculation results of every four digital calculation units are sent to the 4-2 compressor, and after the multiple 4-2 compressors are parallelly calculated, they are sent to a channel adder tree for accumulation to obtain the calculation results of the final digital calculation unit. The present invention uses approximate logic to simplify calculations and reduce internal bandwidth, avoids a large amount of power consumption and area resource waste at a relatively low precision cost, and breaks through the limitation of large-scale adder trees in digital domain memory calculation circuits.

[0015] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram of a circuit structure of a 4-2 compressor approximate adder tree based on a NOR gate in a digital domain in-memory computing circuit provided according to an embodiment of the present invention;

[0018] Figure 2 Schematic diagram of the structure of a 4-2 compressor circuit based on a NOR gate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0020] like Figure 1 and Figure 2 As shown, the 4-2 compressor approximate adder tree circuit based on NOR gates includes: multiple 4-2 compressors repeatedly arranged in columns, the input end of each 4-2 compressor is connected to a digital multiplication calculation unit, the output ends of all 4-2 compressors are commonly connected to a channel adder tree, the input data on the global bit line GBL and the weight data on the local bit line LBL are multiplied in the digital multiplication unit, the digital multiplication unit generates a 1-bit operation result, and the four 1-bit operation results are sent to the 4-2 compressor, and after parallel operation by multiple 4-2 compressors, they are sent to the channel adder tree for accumulation to obtain the final operation result; wherein, the 4-2 compressor is cascaded by a 28-tube static complementary full adder and a NOR gate, and the output sum of the 28-tube static complementary full adder is used as an input of the NOR gate.

[0021] In the embodiment of the present invention, the 28-tube static complementary full adder adopts a complementary static CMOS adder, and the logic equation of the binary full adder is transformed into a complementary CMOS circuit to reduce the number of transistors. The 28-tube static complementary full adder has two binary inputs A and B and C in A carry input, after operation, the output S and the carry output C are obtained out , Carry C out The calculation involves the carry C of the previous level in and the result of the operation at the current level, the logical expression is C out =AB+BC i +AC i , the final sum is generated by the XOR logic of the three inputs, and the expression after the corresponding logical transformation is

[0022]

[0023] In the specific implementation of the 4-2 compressor based on the NOR gate, the input data on the global bit line GBL and the weight data on the local bit line LBL are multiplied in the digital multiplication calculation unit. Each digital multiplication calculation unit generates a 1-bit operation result. Each of the four 1-bit results A0, A1, A2, and A3 are used as inputs to the 28-tube static complementary full adder to obtain the output intermediate sum value S. Next, S and A0 are used as inputs to the NOR gate NOR. After the logical operation of the NOR gate, the final output signal is the sum result S[0] and the carry result S[1].

[0024] Furthermore, the input signal of the 4-2 compressor based on the NOR gate is the 1-bit operation result generated by the digital multiplication calculation unit. The overall digital calculation unit operation process is as follows: every four columns in a 128-column weight array are divided into 32 digital multiplication calculation units as a group. The four 1-bit parallel operation results generated are sent to 32 4-2 compressors based on the NOR gate. The 32 parallel operation intermediate results obtained are sent to a channel adder tree for gradual merging and accumulation layer by layer, and finally the complete digital calculation unit operation result is obtained.

[0025] In the circuit structure of the 4-2 compressor based on the NOR gate, an adder in the traditional 4-2 compressor is replaced by a NOR gate. This approximate processing method may introduce potential errors. It can be observed from the truth table of the 4-2 compressor based on the NOR gate that when A0 is forced to be 0 or the corresponding weight bit is further forced to be 0, the full-precision result can be obtained. According to the test, the total error rate of this circuit structure is 21.875% under completely random input values ​​and weight values.

[0026] According to the 4-2 compressor approximate adder tree circuit based on NOR gates proposed in the embodiment of the present invention, approximate logic is used to simplify operations and reduce internal bandwidth, thereby minimizing the size of the adder tree. Compared with the traditional 4-2 compressor structure, the circuit uses NOR gates to replace the original half adders, reducing the output bandwidth from 3 to 2, and each level of the corresponding adder tree will reduce one adder, thereby reducing the scale of the adder tree, reducing the area, and improving the operation speed.

[0027] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0028] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "N" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

Claims

1. A 4-2 compressor approximate adder tree circuit based on NOR gate, characterized in that: include: A plurality of 4-2 compressors are repeatedly arranged in columns, the input end of each 4-2 compressor is connected to a digital multiplication calculation unit, the output ends of all 4-2 compressors are commonly connected to a channel adder tree, the input data on the global bit line GBL and the weight data on the local bit line LBL are multiplied in the digital multiplication unit, the digital multiplication unit generates a 1-bit operation result, and the four 1-bit operation results are sent to the 4-2 compressors, and after being operated in parallel by the plurality of 4-2 compressors, they are sent to the channel adder tree for accumulation to obtain a final operation result; The 4-2 compressor is formed by cascading a 28-tube static complementary full adder and a NOR gate, and the output of the 28-tube static complementary full adder serves as an input of the NOR gate.

2. The 4-2 compressor approximate adder tree circuit based on NOR gate according to claim 1, characterized in that: The 28-tube static complementary full adder adopts a complementary static CMOS adder to transform the logic equation of the binary full adder into a complementary CMOS circuit. The 28-tube static complementary full adder has two binary inputs A and B and C in A carry input, after operation, the output S and the carry output C are obtained out , Carry C out The calculation involves the carry C of the previous level in and the result of the operation at the current level, the logical expression is C out =AB+BC i +AC i , the final sum is generated by the XOR logic of the three inputs, and the expression after the corresponding logical transformation is 3. The 4-2 compressor approximate adder tree circuit based on NOR gate according to claim 1, characterized in that: Every four 1-bit calculation results A0, A1, A2, A3 of the digital multiplication calculation unit are used as the input of the 4-2 compressor, wherein the calculation results of the three digital multiplication calculation units A1, A2, A3 are used as the three inputs of the 28-tube static complementary full adder, and the output S and A0 of the 28-tube static complementary full adder are used as the two inputs of the NOR gate, and the final sum result S[0] and the carry result S[1] are obtained through the NOR gate operation.

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