Data prefetching method and device, equipment and storage medium

Abstract

The invention relates to a data prefetching method, device and equipment and a storage medium, and the method comprises the steps that a program code is subjected to static analysis through a compiler, a self-defined guide instruction is inserted into the program code according to an analysis result, and the guide instruction comprises prefetcher indication information for program code memory access; separating the guide instruction, and caching the guide instruction in a preset guide instruction queue; reading a guide instruction in the guide instruction queue, and configuring a prefetching strategy according to prefetcher indication information in the guide instruction; and performing data prefetching based on the prefetching strategy. According to the application, the prefetcher can be guided to train and quickly enter a prefetching state, so that the training delay and prefetching deviation of the prefetcher are reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data pre-fetching method, device, equipment and storage medium. Background Art

[0002] At present, data prefetching refers to loading the data to be used from the main memory to the cache in advance during the operation of the processor, so as to improve the cache hit rate, reduce the pause time of the processor to access the memory data, and improve the performance of the processor. Prefetching is divided into software prefetching and hardware prefetching.

[0003] Software prefetching is generally implemented through specific instructions or compiler options, instructing the CPU to perform data prefetching operations and obtain data in advance; hardware prefetching is generally implemented through the CPU's internal hardware logic, based on data locality relationships such as memory access mode and memory access history, to predict and load data into the cache in advance. Currently, both software and hardware data prefetching are used in processors, but due to the complexity of data applications, the accuracy of data prefetching is far from that of instruction prefetching, and there is a lot of room for improvement. Most current processors use hardware prefetching, using different prefetching strategies to adapt to different memory access characteristics. However, the prefetcher requires data training to produce good prediction results, which will cause large delays and uncertainties. Complex data applications will further interfere with the training of different prefetchers, resulting in lower prefetching rates and accuracy, and will also cause additional cache pollution, increase memory access delays, and affect processor performance. Therefore, a method is needed to solve the above problems. Summary of the invention

[0004] Based on this, the present application provides a data pre-fetching method, device, equipment and storage medium to solve the problems existing in the prior art.

[0005] In a first aspect, a data pre-fetching method is provided, the method comprising:

[0006] Performing static analysis on the program code through a compiler, and inserting a custom boot instruction into the program code according to the analysis result, wherein the boot instruction includes prefetcher indication information for accessing the program code;

[0007] Separating the guidance instruction and caching the guidance instruction in a preset guidance instruction queue;

[0008] Reading the guidance instruction in the guidance instruction queue, and configuring the prefetch strategy according to the prefetcher indication information in the guidance instruction;

[0009] Data prefetching is performed based on the prefetching strategy.

[0010] According to an achievable method in an embodiment of the present application, the program code is statically analyzed by a compiler, and a custom boot instruction is inserted into the program code according to the analysis result, wherein the boot instruction includes prefetcher indication information for accessing the program code, including:

[0011] Performing static analysis on characteristic information of program code through a compiler to determine memory access characteristics of data, wherein the characteristic information includes one or more of program characteristic information, memory access mode information, data dependency information, and custom identification information in a code writing process;

[0012] Determining prefetcher indication information corresponding to the program code according to the memory access characteristics of the data, the prefetcher indication information including recommended target prefetcher information, disabled target prefetcher information or no recommended prefetcher information;

[0013] Based on the prefetcher indication information corresponding to the program code, a custom boot instruction is inserted into the program code.

[0014] According to an achievable method in an embodiment of the present application, separating the boot instruction and caching the boot instruction in a preset boot instruction queue includes:

[0015] Presetting a corresponding instruction operation code for each instruction, wherein a first instruction operation code is set for the boot instruction, and a second instruction operation code is set for non-boot instructions other than the boot instruction;

[0016] Identify the instruction operation code corresponding to each instruction through the instruction scanning module;

[0017] Based on the instruction opcode, the boot instruction is separated from the non-boot instruction. If the first instruction opcode is identified, the corresponding boot instruction is cached in a preset boot instruction queue. If the second instruction opcode is identified, the corresponding non-boot instruction is cached in a preset non-boot instruction queue.

[0018] According to an achievable method in an embodiment of the present application, reading the guide instruction in the guide instruction queue and configuring the prefetch strategy according to the prefetcher indication information in the guide instruction includes:

[0019] Reading a guide instruction in the guide instruction queue, and determining prefetcher indication information corresponding to the program code according to the guide instruction, wherein the prefetcher indication information includes recommended target prefetcher information, disabled target prefetcher information, or no recommended prefetcher information;

[0020] If the prefetcher indication information is recommended target prefetcher information, determining an applicable first target prefetcher and configuring a first prefetching strategy for starting the first target prefetcher;

[0021] If the prefetcher indication information is information of disabling a target prefetcher, determining a second target prefetcher to be disabled and configuring a second prefetching strategy of disabling the second target prefetcher and enabling a third target prefetcher, wherein the third target prefetcher represents other prefetchers except the second target prefetcher;

[0022] If the prefetcher indication information indicates that there is no recommended prefetcher information, indicating that the memory access characteristics of the compiled and analyzed program code data are unclear, then according to the actual application requirements and preset configuration, all prefetchers are enabled to perform prefetching according to autonomous training of the memory access process, or all prefetchers are disabled and the previous training cache of each prefetcher is maintained.

[0023] According to an achievable method in an embodiment of the present application, prefetching data based on the prefetching strategy includes:

[0024] When a non-guided instruction and a guided instruction are adjacent, and the non-guided instruction is after the guided instruction, data prefetching is performed based on the prefetching strategy after the non-guided instruction arrives, wherein the non-guided instruction represents an instruction other than the guided instruction.

[0025] According to an achievable method in an embodiment of the present application, after prefetching data based on the prefetching strategy, the method further includes:

[0026] Acquire state information after the prefetcher performs data prefetching based on the prefetching strategy;

[0027] Statistics are performed on the status information of different prefetchers to obtain statistical results.

[0028] According to an achievable method in an embodiment of the present application, the boot instruction is a custom extended instruction based on the RISC-V instruction set architecture, and its encoding complies with the extended instruction encoding specification of RISC-V.

[0029] In a second aspect, a data pre-fetching device is provided, the device comprising:

[0030] Compilation module: used to perform static analysis on program code through a compiler, and insert a custom boot instruction into the program code according to the analysis result, wherein the boot instruction includes prefetcher indication information for accessing memory of the program code;

[0031] Cache module: used for separating the boot instruction and caching the boot instruction in a preset boot instruction queue;

[0032] Configuration module: used for reading the guidance instruction in the guidance instruction queue and configuring the prefetching strategy according to the prefetcher indication information in the guidance instruction;

[0033] Execution module: used for performing data pre-fetching based on the pre-fetching strategy.

[0034] In a third aspect, a computer device is provided, comprising:

[0035] at least one processor; and

[0036] a memory communicatively connected to the at least one processor; wherein,

[0037] The memory stores computer instructions that can be executed by the at least one processor, and the computer instructions are executed by the at least one processor to enable the at least one processor to perform the method involved in the first aspect above.

[0038] In a fourth aspect, a computer-readable storage medium is provided, on which computer instructions are stored, characterized in that the computer instructions are used to enable a computer to execute the method involved in the first aspect above.

[0039] According to the technical content provided in the embodiments of the present application, the present application performs static analysis on the program code through a compiler, inserts a custom boot instruction into the program code according to the analysis results, and caches the boot instruction in a boot instruction queue, further configures a prefetch strategy according to the prefetcher indication information in the boot instruction, and performs data prefetching based on the prefetch strategy. The present application can generate a custom boot instruction based on the memory access characteristics of the program code data, and can guide the configuration and use of the prefetcher based on the boot instruction during the execution of the processor, thereby reducing the prefetcher selection and training delay, and by reducing the interference of redundant data on different prefetchers, guide the prefetcher training and quickly enter the prefetch state, thereby reducing the training delay and prefetch deviation of the prefetcher. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of a flow chart of a data pre-fetching method in an embodiment;

[0041] Figure 2 is a schematic diagram of a data pre-fetching method in one embodiment;

[0042] Figure 3 A schematic diagram of guiding instruction encoding of a data prefetching method in one embodiment;

[0043] Figure 4 A system architecture diagram of a data pre-fetching method in one embodiment;

[0044] Figure 5 is a structural block diagram of a data pre-fetching device in one embodiment;

[0045] Figure 6 FIG. 4 is a schematic structural diagram of a computer device in one embodiment. DETAILED DESCRIPTION

[0046] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0047] Figure 1 A flowchart of a data pre-fetching method provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method may include the following steps:

[0048] Step 101: statically analyzing the program code through a compiler, and inserting a custom boot instruction into the program code according to the analysis result, the boot instruction including prefetcher instruction information for accessing the program code.

[0049] Specifically, Figure 1 As shown, combined with Figure 2 ,During the program compilation stage, the compiler performs static analysis on the program code to identify the memory access mode and data dependency of the program segment. According to the analysis results, custom extended instructions, namely boot instructions, are inserted into different segments of the program code. The boot instructions contain the recommended or disabled prefetcher information and some prefetch configuration parameters for memory access of a certain segment of program code.

[0050] Step 102: Separate the boot command and cache the boot command in a preset boot command queue.

[0051] Specifically, during the processor execution phase, the boot instruction is identified and separated and processed by the instruction scanning module, and is cached in a dedicated boot instruction queue.

[0052] Step 103: Read the guidance instruction in the guidance instruction queue, and configure the prefetch strategy according to the prefetcher indication information in the guidance instruction.

[0053] When there is no guidance instruction information in the guidance instruction queue module, the prefetcher of each prefetch algorithm performs predictive prefetching according to the memory access process or previous configuration. When there is guidance instruction information in the guidance instruction queue module, the prefetch configuration module immediately reads the instruction information and completes the configuration of the prefetch algorithm strategy. The prefetch configuration module reads the guidance instruction information in the queue and configures the prefetch strategy according to the guidance instruction content, including enabling or disabling specific prefetchers and their parameter settings.

[0054] Step 104: Prefetch data based on the prefetch strategy.

[0055] Specifically, the boot instruction contains the recommended or disabled prefetcher information and some prefetch configuration parameters for memory access of a certain section of program code. It will be parsed before the relevant memory access instruction to guide the subsequent memory access process to give priority to or disable a certain type of prefetch strategy to reduce the interference of redundant data on different prefetch algorithms, guide the prefetch algorithm training and quickly enter the prefetch state, and reduce the training delay and prefetch deviation of the prefetch algorithm.

[0056] It can be seen that the embodiment of the present application performs static analysis on the program code through the compiler, inserts a custom boot instruction into the program code according to the analysis result, caches the boot instruction in the boot instruction queue, further configures the prefetch strategy according to the prefetcher indication information in the boot instruction, and performs data prefetching based on the prefetch strategy. The present application can generate custom boot instructions based on the memory access characteristics of the program code data, and can guide the configuration and use of the prefetcher based on the boot instruction during the execution of the processor, thereby reducing the prefetcher selection and training delay, and guiding the prefetcher training and quickly entering the prefetch state by reducing the interference of redundant data on different prefetchers, thereby reducing the training delay and prefetching deviation of the prefetcher.

[0057] In one embodiment of the present application, a program code is statically analyzed by a compiler, and a custom boot instruction is inserted into the program code based on the analysis result, the boot instruction including prefetcher indication information for memory access of the program code, including: statically analyzing feature information of the program code by the compiler to determine memory access characteristics of the data, wherein the feature information includes one or more of program feature information, memory access mode information, data dependency information, and custom identification information in the code writing process; determining prefetcher indication information corresponding to the program code based on the memory access characteristics of the data, the prefetcher indication information including recommended target prefetcher information, disabled target prefetcher information, or no recommended prefetcher information; and inserting a custom boot instruction into the program code based on the prefetcher indication information corresponding to the program code.

[0058] Specifically, the guiding instructions in this embodiment are the compiler's analysis and inference of the data access characteristics during the static analysis of the program code based on information such as program characteristics, memory access modes, data dependencies, and custom identifiers in the code writing process, to optimize the program architecture. When the data access characteristics of a certain program segment are applicable (or not applicable) to a certain prefetch algorithm, the generated custom extension instructions can guide the configuration and use of the prefetch algorithm (prefetcher) during the execution of the processor, thereby reducing the prefetcher selection and training delays.

[0059] In one embodiment of the present application, the boot instruction is a custom extended instruction based on the RISC-V instruction set architecture, and its encoding complies with the extended instruction encoding specification of RISC-V.

[0060] Specifically, Figure 3 As shown, the boot instruction is a custom extended instruction based on RISC-V and complies with the extended instruction encoding specification of RISC-V.

[0061] The embodiments of the present application are based on the open source and flexible expansion characteristics of the RISC_V instruction set architecture, and combine program compilation, instruction extension and prefetch algorithm. Through compiler optimization and training, it is possible to analyze the memory access mode and data dependencies according to the characteristics of the program, and insert custom extension instructions into different program segments according to the characteristics of the established hardware prefetch algorithm. This can guide the configuration and use of the prefetch algorithm (prefetcher) during the execution of the processor, and reduce the delay in prefetcher selection and training.

[0062] In one embodiment of the present application, boot instructions are separated and cached in a preset boot instruction queue, including: pre-setting a corresponding instruction operation code for each instruction, wherein a first instruction operation code is set for the boot instruction, and a second instruction operation code is set for non-boot instructions other than the boot instruction; identifying the instruction operation code corresponding to each instruction through an instruction scanning module; separating the boot instruction from the non-boot instruction based on the instruction operation code, and if the first instruction operation code is identified, caching the corresponding boot instruction in the preset boot instruction queue, and if the second instruction operation code is identified, caching the corresponding non-boot instruction in the preset non-boot instruction queue.

[0063] Specifically, the system implementation of instruction execution is as follows Figure 4 As shown, Frontend represents the front end of the processor instruction pipeline, which generally includes functions such as instruction fetching, pre-decoding, and branch prediction; ID represents the decoding stage of the processor instruction pipeline; Issue represents the emission stage of the processor instruction pipeline; Ext represents the execution stage of the processor instruction pipeline; and Commit represents the submission stage of the processor instruction pipeline. In the Frontend stage, the instruction scanning module can be used to identify each instruction opcode in advance during the instruction fetching process, set the first instruction opcode for the guide instruction, and set the second instruction opcode for the non-guide instruction other than the guide instruction, so as to quickly parse the guide instruction. The guide instruction and other instructions are processed separately and cached in the Queue register group (i.e., the guide instruction queue) and the Inst_Queue cache module (i.e., the non-guide instruction queue), respectively, to achieve the decoupling of the instruction pipeline instruction fetching and decoding processing.

[0064] The embodiments of the present application do not require the use of general registers, thus eliminating the processing steps of the boot instruction in the decoding and transmission stages. After parsing, the instruction completion status can be submitted in a timely manner to complete the instruction execution closed loop and improve efficiency.

[0065] In one embodiment of the present application, a boot instruction in a boot instruction queue is read, and a prefetch strategy is configured according to prefetcher indication information in the boot instruction, including: reading a boot instruction in a boot instruction queue, determining prefetcher indication information corresponding to a program code according to the boot instruction, wherein the prefetcher indication information includes recommended target prefetcher information, disabled target prefetcher information, or no recommended prefetcher information; if the prefetcher indication information is the recommended target prefetcher information, determining an applicable first target prefetcher and configuring a first prefetch strategy for starting the first target prefetcher; if the prefetcher indication information is the recommended target prefetcher information, If the indication information is information of disabling a target prefetcher, the second target prefetcher to be disabled is determined and a second prefetch strategy is configured to disable the second target prefetcher and start the third target prefetcher, wherein the third target prefetcher represents other prefetchers except the second target prefetcher; if the prefetcher indication information is information of no recommended prefetcher, indicating that the memory access characteristics of the compiled and analyzed program code data are unclear, then according to actual application requirements and preset configurations, all prefetchers are enabled to perform prefetching according to autonomous training during the memory access process, or all prefetchers are disabled and the previous training cache of each prefetcher is maintained.

[0066] Specifically, Figure 4 As shown, when there is no guide instruction information in the Queue module, the prefetcher of each prefetch algorithm performs autonomous training according to the memory access process or completes predictive prefetching according to the previous configuration. When there is guide instruction information in the Queue module, the prefetch configuration module (Pref_Cfg) immediately reads the instruction information and completes the configuration of the prefetch algorithm strategy. It is worth noting that the prefetcher based on different prefetch algorithms is not the focus of this embodiment. This embodiment only illustrates 4 prefetchers (Prefether1~Prefether4) without indicating the actual prefetch algorithm type. In actual application, different categories and different numbers of prefetch algorithms can be used as needed, such as stream prefetch, step prefetch, offset prefetch or space prefetch. The prefetch configuration module (Pref_Cfg) reads the guide instruction in the guide instruction queue and determines the prefetcher indication information corresponding to the program code according to the guide instruction, wherein the prefetcher indication information includes recommended target prefetcher information, disabled target prefetcher information or no recommended prefetcher information.

[0067] If the prefetcher indication information is the recommended target prefetcher information, the applicable first target prefetcher is determined and the first prefetch strategy for starting the first target prefetcher is configured. Specifically, the program segment that has been compiled and analyzed may be suitable for a certain prefetcher. The Pref_Cfg module parses the boot instruction information. When the PC value of the normally transmitted instruction is adjacent to the boot instruction, the relevant prefetcher is enabled, and other prefetchers are disabled at the same time, and some parameters such as step size, offset, prefetch degree, etc. are configured until the next boot instruction arrives. Among them, the PC value is equivalent to the identification information of each instruction, and each instruction can be distinguished by the PC value.

[0068] If the prefetcher indication information is information for disabling a target prefetcher, then the second target prefetcher to be disabled is determined and a second prefetching strategy is configured to disable the second target prefetcher and enable the third target prefetcher, wherein the third target prefetcher represents other prefetchers except the second target prefetcher. Specifically, the program segment analyzed by compilation may not be clearly applicable to a certain prefetcher, but is clearly not applicable to a certain prefetcher. The Pref_Cfg module parses the boot instruction information, and when the PC value of the normally transmitted instruction is adjacent to the boot instruction, the relevant prefetcher is disabled, and other prefetchers are enabled at the same time until the next boot instruction arrives.

[0069] If the prefetcher indication information is that there is no recommended prefetcher information, indicating that the memory access characteristics of the compiled and analyzed program code data are unclear, then according to the actual application requirements and preset configuration, all prefetchers are enabled to perform prefetching according to autonomous training of the memory access process, or all prefetchers are disabled and the previous training cache of each prefetcher is maintained. Specifically, for the program segment that has been compiled and analyzed, its memory access characteristics cannot be clearly determined, and configuration information may not be recommended. The Pref_Cfg module parses the boot instruction information, and when the PC value of the normally transmitted instruction is adjacent to the boot instruction, the configuration information of the previous boot instruction is released. According to the actual application requirements or preset configuration, all prefetchers are enabled to perform prefetching according to autonomous training of the memory access process, or all prefetchers are disabled and the previous training cache of each prefetcher is maintained.

[0070] In one embodiment of the present application, data prefetching is performed based on a prefetching strategy, including: when a non-guided instruction and a guided instruction are adjacent, and the non-guided instruction is after the guided instruction, data prefetching is performed based on the prefetching strategy after the non-guided instruction arrives, wherein the non-guided instruction represents an instruction other than the guided instruction.

[0071] Specifically, the guide instruction is for a section of program. The Pref_Cfg module is based on the PC value of the normally transmitted non-guide instruction and the current guide instruction. When PC Normal>=PC Guide-4 (that is, the normally transmitted non-guide instruction and the guide instruction are adjacent, and the non-guide instruction is after the guide instruction), after the non-guide instruction arrives, data is pre-fetched based on the pre-fetch strategy, the current guide instruction configuration is enabled, and the previous guide instruction configuration is terminated. The recommended configuration of the guide instruction can directly select the pre-fetcher to quickly enter the pre-fetch state, or narrow the selection range of the pre-fetcher, reduce the impact of redundant data on non-related pre-fetchers, reduce pre-fetch training delay and deviation, and improve pre-fetch accuracy.

[0072] In an embodiment of the present application, when a non-guided instruction and a guided instruction are adjacent and the non-guided instruction follows the guided instruction, data prefetching is performed based on a prefetching strategy after the non-guided instruction arrives. By setting the conditions for the guided instruction to take effect, the impact of redundant data on non-related prefetchers can be reduced, the prefetch training delay and deviation can be reduced, and the prefetch accuracy can be improved.

[0073] In one embodiment of the present application, after prefetching data based on the prefetching strategy, it also includes: obtaining status information of the prefetcher after executing data prefetching based on the prefetching strategy; and performing information statistics on status information of different prefetchers to obtain statistical results.

[0074] Specifically, Figure 4 As shown, the prediction result of the prefetcher is output to the prefetch control module (Pref_Ctrl) to execute data prefetching. At the same time, the Pref_Ctrl module performs information statistics according to the status information of the prefetcher in each Cache to obtain the statistical result.

[0075] In one embodiment of the present application, after data prefetching is performed based on a prefetching strategy, it also includes: obtaining status information of the prefetcher after executing data prefetching based on the prefetching strategy, wherein the status information includes prefetching status information, replacement cycle information, and hit status information of the data; based on the prefetching status information, replacement cycle information, and hit status information of the data in each prefetcher, counting the prefetching coverage and accuracy of each section of program code, and obtaining the prefetching feedback information corresponding to each section of program code; sending the prefetching feedback information of each section of program code to the system layer, and optimizing the compiler's analysis of the program segment based on the feedback information.

[0076] The embodiments of the present application send the pre-fetch feedback information of each section of program code to the system layer, and optimize the compiler's analysis of the program section according to the feedback information, so as to gradually improve the adaptability of the guidance instructions and the pre-fetch algorithm, form a positive cycle, and improve the accuracy of analysis and guidance.

[0077] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in the application, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0078] Figure 5 A schematic diagram of the structure of a data pre-fetching device provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the device may include:

[0079] Compilation module 501: used to perform static analysis on program code through a compiler, and insert a custom boot instruction into the program code according to the analysis result, wherein the boot instruction includes prefetcher indication information for accessing memory of the program code;

[0080] Cache module 502: used to separate the boot instruction and cache the boot instruction in a preset boot instruction queue;

[0081] Configuration module 503: used for reading the guidance instruction in the guidance instruction queue, and configuring the prefetching strategy according to the prefetcher indication information in the guidance instruction;

[0082] Execution module 504: configured to perform data pre-fetching based on the pre-fetching strategy.

[0083] In one embodiment of the present application, the compiling module 501 is further configured to perform static analysis on characteristic information of the program code through a compiler to determine the memory access characteristics of the data, wherein the characteristic information includes one or more of program characteristic information, memory access mode information, data dependency information, and custom identification information in the code writing process;

[0084] Determining prefetcher indication information corresponding to the program code according to the memory access characteristics of the data, the prefetcher indication information including recommended target prefetcher information, disabled target prefetcher information or no recommended prefetcher information;

[0085] Based on the prefetcher indication information corresponding to the program code, a custom boot instruction is inserted into the program code.

[0086] In one embodiment of the present application, the cache module 502 is further configured to pre-set a corresponding instruction operation code for each instruction, wherein a first instruction operation code is set for the boot instruction, and a second instruction operation code is set for non-boot instructions other than the boot instruction;

[0087] Identify the instruction operation code corresponding to each instruction through the instruction scanning module;

[0088] Based on the instruction opcode, the boot instruction is separated from the non-boot instruction. If the first instruction opcode is identified, the corresponding boot instruction is cached in a preset boot instruction queue. If the second instruction opcode is identified, the corresponding non-boot instruction is cached in a preset non-boot instruction queue.

[0089] In one embodiment of the present application, the configuration module 503 is further configured to read the guide instruction in the guide instruction queue, and determine the prefetcher indication information corresponding to the program code according to the guide instruction, wherein the prefetcher indication information includes recommended target prefetcher information, disabled target prefetcher information, or no recommended prefetcher information;

[0090] If the prefetcher indication information is recommended target prefetcher information, determining an applicable first target prefetcher and configuring a first prefetching strategy for starting the first target prefetcher;

[0091] If the prefetcher indication information is information of disabling a target prefetcher, determining a second target prefetcher to be disabled and configuring a second prefetching strategy of disabling the second target prefetcher and enabling a third target prefetcher, wherein the third target prefetcher represents other prefetchers except the second target prefetcher;

[0092] If the prefetcher indication information indicates that there is no recommended prefetcher information, indicating that the memory access characteristics of the compiled and analyzed program code data are unclear, then according to the actual application requirements and preset configuration, all prefetchers are enabled to perform prefetching according to autonomous training of the memory access process, or all prefetchers are disabled and the previous training cache of each prefetcher is maintained.

[0093] In one embodiment of the present application, the execution module 504 is also used to perform data prefetching based on the prefetching strategy after the arrival of the non-guided instruction when a non-guided instruction and a guided instruction are adjacent and the non-guided instruction is after the guided instruction, wherein the non-guided instruction represents an instruction other than the guided instruction.

[0094] In one embodiment of the present application, after prefetching data based on the prefetching strategy, it also includes: obtaining status information of the prefetcher after executing data prefetching based on the prefetching strategy; and performing information statistics on the status information of different prefetchers to obtain statistical results.

[0095] In one embodiment of the present application, the boot instruction is a custom extended instruction based on the RISC-V instruction set architecture, and its encoding complies with the extended instruction encoding specification of RISC-V.

[0096] According to the specific embodiments provided by the present application, the technical solution provided by the present application can have the following advantages: static analysis of the program code is performed by the compiler, a custom boot instruction is inserted into the program code according to the analysis results, and the boot instruction is cached in the boot instruction queue, and the prefetch strategy is further configured according to the prefetcher indication information in the boot instruction, and data is prefetched based on the prefetch strategy. The present application can generate a custom boot instruction based on the memory access characteristics of the program code data, and can guide the configuration and use of the prefetcher based on the boot instruction during the execution of the processor, thereby reducing the prefetcher selection and training delay, and by reducing the interference of redundant data on different prefetchers, guide the prefetcher training and quickly enter the prefetch state, thereby reducing the training delay and prefetch deviation of the prefetcher.

[0097] The same or similar parts between the above embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0098] It should be noted that the embodiments of the present application may involve the use of user data. In actual applications, user-specific personal data can be used in the scheme described in this article within the scope permitted by applicable laws and regulations, provided that the applicable laws and regulations of the country are met (for example, the user's explicit consent, effective notification to the user, and the user's explicit authorization, etc.).

[0099] According to an embodiment of the present application, the present application also provides a computer device and a computer-readable storage medium. The present application also provides a computer device, including at least one processor and a memory connected to the at least one processor in communication; wherein the memory stores computer instructions executable by the at least one processor, and the computer instructions are executed by the at least one processor so that the at least one processor can execute the data prefetching method described in any of the above embodiments.

[0100] like Figure 6 , is a block diagram of a computer device according to an embodiment of the present application. The computer device is intended to represent various forms of digital computers or mobile devices. The digital computer may include a desktop computer, a portable computer, a workbench, a personal digital assistant, a server, a mainframe computer, and other suitable computers. The mobile device may include a tablet computer, a smart phone, a wearable device, etc.

[0101] like Figure 6As shown, the computer device 600 includes a computing unit 601, a ROM 602, a RAM 603, a bus 604, and an input / output (I / O) interface 605. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other via the bus 604. The input / output (I / O) interface 605 is also connected to the bus 604.

[0102] The computing unit 601 can perform various processes in the method embodiment of the present application according to the computer instructions stored in the read-only memory (ROM) 602 or the computer instructions loaded from the storage unit 608 to the random access memory (RAM) 603. The computing unit 601 can be various general and / or special processing components with processing and computing capabilities. The computing unit 601 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. In some embodiments, the method provided in the embodiment of the present application can be implemented as a computer software program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 608.

[0103] The RAM 606 may also store various programs and data required for the operation of the device 600. Part or all of the computer program may be loaded and / or installed on the device 600 via the ROM 602 and / or the communication unit 609.

[0104] The input unit 606, output unit 607, storage unit 608 and communication unit 609 in the computer device 600 can be connected to the I / O interface 605. The input unit 606 can be, for example, a keyboard, a mouse, a touch screen, a microphone, etc. The output unit 607 can be, for example, a display, a speaker, an indicator light, etc. The device 600 can exchange information, data, etc. with other devices through the communication unit 609.

[0105] It should be noted that the device may also include other components necessary for normal operation, or may only include components necessary for implementing the solution of the present application, rather than all the components shown in the figure.

[0106] Various implementations of the systems and techniques described herein can be realized in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof.

[0107] The computer instructions for implementing the method of the present application can be written in any combination of one or more programming languages. These computer instructions can be provided to the computing unit 601, so that when the computer instructions are executed by the computing unit 601 such as a processor, the steps involved in the method embodiment of the present application are executed.

[0108] The present application also provides a computer-readable storage medium on which computer instructions are stored, and the computer instructions are used to enable a computer to execute the data pre-fetching method described in any of the above embodiments.

[0109] The computer-readable storage medium provided in the present application may be a tangible medium that may contain or store computer instructions for executing the steps involved in the method embodiments of the present application. The computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, and other forms of storage media.

[0110] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included in the protection scope of this application.

Claims

1. A method for pre-fetching data, It is characterized in that The method includes: Performing static analysis on the program code through a compiler, and inserting a custom boot instruction into the program code according to the analysis result, wherein the boot instruction includes prefetcher indication information for accessing the program code; Separating the guidance instruction and caching the guidance instruction in a preset guidance instruction queue; Reading the guidance instruction in the guidance instruction queue, and configuring the prefetch strategy according to the prefetcher indication information in the guidance instruction; Data prefetching is performed based on the prefetching strategy.

2. The data pre-fetching method according to claim 1, It is characterized in that The method of statically analyzing the program code by a compiler and inserting a custom boot instruction into the program code according to the analysis result, wherein the boot instruction contains prefetcher instruction information for accessing the program code, including: Performing static analysis on characteristic information of program code through a compiler to determine memory access characteristics of data, wherein the characteristic information includes one or more of program characteristic information, memory access mode information, data dependency information, and custom identification information in a code writing process; Determining prefetcher indication information corresponding to the program code according to the memory access characteristics of the data, the prefetcher indication information including recommended target prefetcher information, disabled target prefetcher information or no recommended prefetcher information; Based on the prefetcher indication information corresponding to the program code, a custom boot instruction is inserted into the program code.

3. The data pre-fetching method according to claim 1, It is characterized in that The step of separating the boot instruction and caching the boot instruction in a preset boot instruction queue includes: Presetting a corresponding instruction operation code for each instruction, wherein a first instruction operation code is set for the boot instruction, and a second instruction operation code is set for non-boot instructions other than the boot instruction; Identify the instruction operation code corresponding to each instruction through the instruction scanning module; Based on the instruction opcode, the boot instruction is separated from the non-boot instruction. If the first instruction opcode is identified, the corresponding boot instruction is cached in a preset boot instruction queue. If the second instruction opcode is identified, the corresponding non-boot instruction is cached in a preset non-boot instruction queue.

4. The data pre-fetching method according to claim 2, It is characterized in that The step of reading the guide instruction in the guide instruction queue and configuring the prefetch strategy according to the prefetcher indication information in the guide instruction includes: Reading a guide instruction in the guide instruction queue, and determining prefetcher indication information corresponding to the program code according to the guide instruction, wherein the prefetcher indication information includes recommended target prefetcher information, disabled target prefetcher information, or no recommended prefetcher information; If the prefetcher indication information is recommended target prefetcher information, determining an applicable first target prefetcher and configuring a first prefetching strategy for starting the first target prefetcher; If the prefetcher indication information is information of disabling a target prefetcher, determining a second target prefetcher to be disabled and configuring a second prefetching strategy of disabling the second target prefetcher and enabling a third target prefetcher, wherein the third target prefetcher represents other prefetchers except the second target prefetcher; If the prefetcher indication information indicates that there is no recommended prefetcher information, indicating that the memory access characteristics of the compiled and analyzed program code data are unclear, then according to the actual application requirements and preset configuration, all prefetchers are enabled to perform prefetching according to autonomous training of the memory access process, or all prefetchers are disabled and the previous training cache of each prefetcher is maintained.

5. The data pre-fetching method according to claim 1, It is characterized in that The prefetching of data based on the prefetching strategy includes: When a non-guided instruction and a guided instruction are adjacent, and the non-guided instruction is after the guided instruction, data prefetching is performed based on the prefetching strategy after the non-guided instruction arrives, wherein the non-guided instruction represents an instruction other than the guided instruction.

6. The data pre-fetching method according to claim 1, It is characterized in that After prefetching data based on the prefetching strategy, the method further includes: Acquire state information after the prefetcher performs data prefetching based on the prefetching strategy; Statistics are performed on the status information of different prefetchers to obtain statistical results.

7. The data pre-fetching method according to claim 1, It is characterized in that The boot instruction is a custom extended instruction based on the RISC-V instruction set architecture, and its encoding complies with the extended instruction encoding specification of RISC-V.

8. A data pre-fetching device, It is characterized in that The device includes: Compilation module: used to perform static analysis on program code through a compiler, and insert a custom boot instruction into the program code according to the analysis result, wherein the boot instruction includes prefetcher indication information for accessing memory of the program code; Cache module: used for separating the boot instruction and caching the boot instruction in a preset boot instruction queue; Configuration module: used for reading the guidance instruction in the guidance instruction queue and configuring the prefetching strategy according to the prefetcher indication information in the guidance instruction; Execution module: used for pre-fetching data based on the pre-fetching strategy.

9. A computer device, include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores computer instructions that can be executed by the at least one processor, and the computer instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having computer instructions stored thereon, It is characterized in that The computer instructions are used to make a computer execute the method according to any one of claims 1 to 7.

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