Computing power core bad block monitoring device and method based on Chiplet architecture

Abstract

The invention discloses a Chiplet architecture-based computing power core bad block monitoring device and a Chiplet architecture-based computing power core bad block monitoring method, belongs to the technical field of chip design, and is used for solving the problems that a computing power core module in a Chiplet architecture possibly has computing block abnormity in an operation process, normal execution of a task is not facilitated, the performance and reliability of the whole Chiplet architecture are influenced, and the reliability of the whole Chiplet architecture is influenced. And effective monitoring and processing are urgently needed for the computing power core module. The device comprises a central processing unit module and a plurality of computing power core modules, the computing power core module comprises a monitor and a plurality of computing blocks; the computing block is a basic unit of the computing power core module; the monitor is used for detecting state information of the computing core module; the central processing unit module comprises a plurality of central processing units. According to the method, the state of the computing power core can be monitored in real time, bad blocks in the computing power core can be found and isolated in time, and the reliability and stability of the Chiplet architecture are improved.

Description

Technical Field

[0001] The present invention relates to the field of chip design technology, and in particular to a computing core bad block monitoring device and method based on a chiplet architecture. Background Art

[0002] As the scale of data centers continues to expand, traditional monolithic integration methods face yield and cost challenges when manufacturing large, high-performance chips. The subsequent emergence of chiplet technology provides a new solution for improving chip yield and reducing costs. Chiplet, also known as chiplet or microchip, is a design method that splits a complex chip into multiple small, independent and reusable modules. These modules can be processor cores, memory chips, sensors or other types of integrated circuits, which are interconnected through high-speed interfaces or connectors to form a complete system chip.

[0003] With the continuous development of technology and the increasing complexity of chip design, Chiplet has become an effective way to deal with chip yield and cost challenges. By splitting large chips into multiple small, independent modules, the design complexity can be significantly reduced, production efficiency can be improved, and costs can be reduced. At the same time, Chiplet is also reusable, which means that each module can be designed and produced independently, and then combined as needed to achieve flexible customized design. The emergence of this design method makes chip design more modular, similar to the way computer hardware is assembled, and different modules can be selected and combined according to different needs. This not only improves the flexibility of design, but also promotes cross-vendor and cross-domain collaborative design and optimization.

[0004] The chiplet architecture contains several Dies. A Die refers to a separate wafer area that contains a complete functional unit or a group of related functional units, which can be understood as a module with complete functions. The computing power core Die in the chiplet architecture, that is, the computing power core module, contains many computing blocks. During the operation of these computing blocks, individual computing blocks may fail or be abnormal. At this time, if there are tasks running in them, it is easy to cause task execution failure or errors, affecting the performance and reliability of the overall chiplet architecture. Therefore, there is an urgent need for an effective monitoring and processing method for the computing power core module to ensure the stability of the computing power core of the chiplet architecture. Summary of the invention

[0005] The embodiments of the present invention provide a computing core bad block monitoring device and method based on a chiplet architecture, which are used to solve the following technical problems: the computing core module in the chiplet architecture may have computing block abnormalities during operation, which is not conducive to the normal execution of tasks and affects the performance and reliability of the overall chiplet architecture. It is urgent to effectively monitor and process the computing core module.

[0006] The embodiment of the present invention adopts the following technical solutions:

[0007] On the one hand, an embodiment of the present invention provides a computing core bad block monitoring device based on a chiplet architecture, the device comprising: a central processing unit module and a plurality of computing core modules;

[0008] The computing power core module includes a monitor and a plurality of computing blocks; the computing block is a basic unit of the computing power core module;

[0009] The monitor is used to detect the status information of the computing core module;

[0010] The central processing unit module includes a plurality of central processing units.

[0011] In a feasible implementation manner, the computing power core module is connected to the central processing unit module via a D2D high-speed interface; the D2D high-speed interface is used to transmit commands and data.

[0012] In a feasible implementation manner, the monitor at least includes: an arbitrator submodule, a data packet parsing submodule, a power consumption estimation submodule, a performance estimation submodule, a resource occupancy estimation submodule, a computing block resource control submodule and a computing block status table.

[0013] In a feasible implementation manner, each of the computing power core modules further includes: a redundant computing power calculation block;

[0014] The redundant computing power calculation block is used to receive the tasks running in the bad block of the computing power core module; wherein the bad block refers to a computing block that has a fault or an abnormality.

[0015] On the other hand, an embodiment of the present invention further provides a bad block monitoring method for a computing power core based on a chiplet architecture, which is applied to the bad block monitoring device for a computing power core based on a chiplet architecture, and the method includes:

[0016] The central processing unit module collects the operation status information of the computing power core module, analyzes the operation status information, and determines the bad blocks existing in the computing power core module;

[0017] The central processing unit module transfers the tasks running in the bad block to the redundant computing power calculation block or other computing power core modules for continued operation.

[0018] In a feasible implementation manner, the central processing unit module collects the operating status information of the computing power core module, specifically including:

[0019] The central processing unit module generates a status detection command and sends it to the computing power core module;

[0020] The monitor of the computing power core module parses the status monitoring command and activates each computing block in the computing power core module through the parsed command;

[0021] Each computing block returns its own activation status information, the monitor collects and summarizes the activation status information, generates the operating status information of the computing power core module, and sends it to the central processing unit module.

[0022] In a feasible implementation manner, the central processing unit module analyzes the running status information to determine the bad blocks existing in the computing power core module, specifically including:

[0023] The central processing unit module analyzes the abnormal activation state information in the running state information, and determines the corresponding abnormal computing block according to the source of the abnormal activation state information;

[0024] The abnormal computing block is determined as a bad block in the computing power core module, and the location information of the bad block is obtained.

[0025] In a feasible implementation manner, after the central processing unit module analyzes the running status information and determines the bad blocks existing in the computing power core module, the method further includes:

[0026] The central processing unit module isolates the bad blocks determined in the computing power core module and records all abnormal activation status information in the computing power core module.

[0027] In a feasible implementation manner, the central processing unit module transfers the tasks running in the bad block to the redundant computing power calculation block or other computing power core modules for continued operation, specifically including:

[0028] The central processing unit module starts the redundant computing power calculation block in the computing power core module, and transfers the tasks running in the bad block to the redundant computing power calculation block for continued operation;

[0029] If all computing blocks in the computing power core module are occupied, the central processing unit starts unoccupied computing blocks in adjacent computing power core modules to receive tasks in the bad blocks.

[0030] In a feasible implementation manner, the method further includes:

[0031] When all computing blocks in the computing power core module are operating normally, the monitor sequentially obtains status information of each computing block, and performs power consumption estimation, performance estimation, and resource occupancy estimation on the status information to obtain evaluation information of the entire computing power core module;

[0032] The evaluation information is stored in a computing block status table, and the evaluation information is transmitted to the central processing unit module through the computing block status table.

[0033] Compared with the prior art, the device and method for monitoring bad blocks of a computing core based on a chiplet architecture provided by the embodiment of the present invention have the following beneficial effects:

[0034] Through the above technical solution, the present invention can monitor the status of the computing core in real time, promptly discover and isolate bad blocks in the computing core, and perform corresponding processing to ensure the stable operation of tasks in the bad blocks. It realizes real-time monitoring and effective processing of bad blocks in the computing core based on the chiplet architecture, and improves the reliability and stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0036] Figure 1 A schematic diagram of the architecture of a bad block monitoring device for a computing core based on a chiplet architecture provided by an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of a monitor structure provided by an embodiment of the present invention;

[0038] Figure 3 A flowchart of a bad block monitoring method for a computing core based on a chiplet architecture is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0040] First, an embodiment of the present invention provides a computing core bad block monitoring device based on a chiplet architecture. Figure 1 A schematic diagram of the architecture of a bad block monitoring device for a computing core based on a chiplet architecture provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the device includes a central processing unit module, namely Figure 1 The central processing unit Die in the , also includes multiple computing power core modules, namely Figure 1 The computing core Die.

[0041] like Figure 1 As shown, each computing core Die includes a monitor and multiple computing blocks. The computing block is the basic unit of the computing core module, and the monitor is used to detect the status information of each computing block in the computing core module.

[0042] Furthermore, the central processing unit Die includes multiple central processing units.

[0043] Furthermore, if Figure 1 As shown, the computing core Die and the central processing unit Die are connected to each other through a D2D high-speed interface. The D2D high-speed interface is used to transmit commands and data between the computing core Die and the central processing unit Die.

[0044] Figure 2 A schematic diagram of a monitor structure provided by an embodiment of the present invention, such as Figure 2 As shown, the monitor at least includes: an arbitrator submodule, a data packet parsing submodule, a power consumption estimation submodule, a performance estimation submodule, a resource occupancy estimation submodule, a computing block resource control submodule and a computing block status table.

[0045] When the chip is operating normally, the monitor obtains the status information of the computing blocks in sequence through the arbitrator. After power consumption estimation, performance estimation, and resource occupancy estimation, the evaluation information of the entire computing core Die is obtained, and the evaluation information is stored in the computing block status table, through which the information is passed to the central processing unit Die.

[0046] Furthermore, each computing power core module also includes: a redundant computing power calculation block. The redundant computing power calculation block is used to receive the tasks being run in the bad blocks of the computing power core module; wherein the bad blocks refer to the computing blocks that have failed or are abnormal.

[0047] Based on the above computing power core bad block monitoring device, the embodiment of the present invention provides a computing power core bad block monitoring method based on chiplet architecture. Figure 3 A flowchart of a method for monitoring bad blocks in a computing core based on a chiplet architecture is provided in an embodiment of the present invention. Figure 3 As shown, the bad block monitoring method of the computing core based on the chiplet architecture specifically includes steps S301-S302:

[0048] S301. The central processing unit module collects the operating status information of the computing power core module, analyzes the operating status information, and determines the bad blocks existing in the computing power core module.

[0049] Specifically, the central processing unit module generates a status detection command and sends it to the computing power core module. The monitor of the computing power core module parses the received status monitoring command and activates each computing block in the computing power core module through the parsed command.

[0050] Furthermore, each computing block returns its own activation status information, the monitor collects and summarizes the activation status information, generates the operating status information of the computing power core module, and sends it to the central processing unit module.

[0051] As a feasible implementation method, after the chip is powered on, the central processing unit Die will first send a detection command to the computing core Die through the D2D interface. After the monitor parses the command through the data packet parsing module, it distributes the instruction to the computing block in the computing core Die. The instruction will activate the computing blocks in all core computing Dies, and each computing block will return its own activation status. The monitor will collect the working status of the computing core Die, collect data specific to the specific computing block of each computing core Die, and send the collected data to the central processing unit Die through the D2D interface.

[0052] In one embodiment, Figure 1 As shown, the central processing unit Die sends a detection command to the computing core Die1. The monitor in the computing core Die1 receives and parses the detection command, and distributes the parsed command to computing blocks 1 to n to activate these computing blocks. Then computing blocks 1 to n will return their respective activation states and feed them back to the monitor. After the monitor collects the activation states of all computing blocks, it sends them to the central processing unit Die.

[0053] Furthermore, the central processing unit module analyzes the abnormal activation state information in the running state information, and determines the corresponding abnormal computing block according to the source of the abnormal activation state information, determines the abnormal computing block as a bad block in the computing power core module, and obtains the location information of the bad block.

[0054] Furthermore, the central processing unit module isolates the bad blocks identified in the computing power core module and records all abnormal activation status information in the computing power core module.

[0055] As a feasible implementation method, the central processing unit Die isolates the bad blocks in the computing core according to the situation of each computing core Die to ensure that the next task will not be assigned to the bad blocks. At the same time, the central processing unit Die will also record the bad block information to provide data support for subsequent maintenance and repair.

[0056] S302: The central processing unit module transfers the tasks currently running in the bad block to the redundant computing power calculation block or other computing power core modules for continued operation.

[0057] Specifically, the central processing unit module starts the redundant computing power calculation block in the computing power core module, and transfers the tasks running in the bad block to the redundant computing power calculation block to continue running.

[0058] If all computing blocks in the computing power core module are occupied, the central processing unit starts the unoccupied computing blocks in the adjacent computing power core module and receives the tasks in the bad blocks.

[0059] As a feasible implementation method, if during the operation, it is determined based on the collected information that a certain computing block has failed, then the central processing unit first sends instructions to the computing power core Die where the computing block is located, and starts the redundant computing power computing block. If all the computing blocks of the computing power core Die are occupied, the unoccupied computing blocks in the adjacent computing power core Die are started to prepare to receive the bad block task. At the same time, the central processing unit Die sends a dynamic task allocation instruction, and transfers the running task to the started redundant computing power computing block through the computing block resource control module in the monitor. The central processing unit Die marks the computing block of the computing power core Die as a bad block, and does not allocate computing power tasks to this computing block in the next computing task. The status of the computing power core Die can also be continuously sent to the central processing unit unit through the computing block status table, and the chip status information is stored in the external memory. These status information can be used through the deep learning algorithm to more accurately maintain the chip and ensure the stability of the chip.

[0060] Furthermore, when all computing blocks in the computing power core module are operating normally, the monitor obtains the status information of each computing block in sequence, and estimates the power consumption, performance and resource occupancy of the status information to obtain the evaluation information of the entire computing power core module. The evaluation information is stored in the computing block status table, and the evaluation information is passed to the central processing unit module through the computing block status table.

[0061] As a feasible implementation method, when the chip is operating normally, the monitor obtains the status information of the computing blocks in sequence through the arbitrator. These status information are passed through the power consumption estimation, performance estimation, and resource occupancy estimation modules to obtain the evaluation information of the entire computing core Die. The evaluation information is stored in the computing block status table, and the information is passed to the central processing unit Die through the table.

[0062] Through the above technical solution, the present invention can monitor the status of the computing core in real time, promptly discover and isolate bad blocks in the computing core, and perform corresponding processing to ensure the stable operation of tasks in the bad blocks. It realizes real-time monitoring and effective processing of bad blocks in the computing core based on the chiplet architecture, and improves the reliability and stability of the system.

[0063] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0064] For the convenience of description, the above device is described by dividing it into various units according to its functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0065] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, the embodiments of this specification may be in the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the embodiments of this specification may be in the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0066] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0067] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0068] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0069] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0070] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0071] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0072] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0073] This specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0074] Each embodiment of the present invention is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, equipment, and non-volatile computer storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0075] The above describes specific embodiments of the present invention. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0076] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention should be included in the protection scope of the present invention.

Claims

1. A computing core bad block monitoring device based on chiplet architecture, characterized in that: The device includes a central processing unit module and a plurality of computing power core modules; The computing power core module includes a monitor and a plurality of computing blocks; the computing block is a basic unit of the computing power core module; The monitor is used to detect the status information of the computing core module; The central processing unit module includes a plurality of central processing units.

2. According to claim 1, a computing core bad block monitoring device based on chiplet architecture is characterized in that: The computing power core module is connected to the central processing unit module via a D2D high-speed interface; the D2D high-speed interface is used to transmit commands and data.

3. According to the chiplet architecture-based computing core bad block monitoring device of claim 1, it is characterized in that: The monitor at least includes: an arbitrator submodule, a data packet parsing submodule, a power consumption estimation submodule, a performance estimation submodule, a resource occupancy estimation submodule, a computing block resource control submodule and a computing block status table.

4. According to the chiplet architecture-based computing core bad block monitoring device of claim 1, it is characterized in that: Each of the computing power core modules also includes: a redundant computing power calculation block; The redundant computing power calculation block is used to receive the tasks running in the bad block of the computing power core module; wherein the bad block refers to a computing block that has a fault or an abnormality.

5. A method for monitoring bad blocks of a computing core based on a chiplet architecture, applied to a device for monitoring bad blocks of a computing core based on a chiplet architecture as claimed in claim 1, characterized in that: The method comprises: The central processing unit module collects the operation status information of the computing power core module, analyzes the operation status information, and determines the bad blocks existing in the computing power core module; The central processing unit module transfers the tasks running in the bad block to the redundant computing power calculation block or other computing power core modules for continued operation.

6. According to the method for monitoring bad blocks of a computing core based on a chiplet architecture according to claim 5, it is characterized in that: The central processing unit module collects the operation status information of the computing power core module, specifically including: The central processing unit module generates a status detection command and sends it to the computing power core module; The monitor of the computing power core module parses the status monitoring command and activates each computing block in the computing power core module through the parsed command; Each computing block returns its own activation status information, the monitor collects and summarizes the activation status information, generates the operating status information of the computing power core module, and sends it to the central processing unit module.

7. According to claim 5, a method for monitoring bad blocks in a computing core based on a chiplet architecture is characterized in that: The central processing unit module analyzes the running status information to determine the bad blocks existing in the computing power core module, specifically including: The central processing unit module analyzes the abnormal activation state information in the running state information, and determines the corresponding abnormal computing block according to the source of the abnormal activation state information; The abnormal computing block is determined as a bad block in the computing power core module, and the location information of the bad block is obtained.

8. The method for monitoring bad blocks of a computing core based on a chiplet architecture according to claim 5, characterized in that: After the central processing unit module analyzes the running status information and determines the bad blocks existing in the computing power core module, the method further includes: The central processing unit module isolates the bad blocks determined in the computing power core module and records all abnormal activation status information in the computing power core module.

9. According to claim 5, a method for monitoring bad blocks in a computing core based on a chiplet architecture is characterized in that: The central processing unit module transfers the tasks running in the bad block to the redundant computing power calculation block or other computing power core modules for continued operation, specifically including: The central processing unit module starts the redundant computing power calculation block in the computing power core module, and transfers the tasks running in the bad block to the redundant computing power calculation block for continued operation; If all computing blocks in the computing power core module are occupied, the central processing unit starts unoccupied computing blocks in adjacent computing power core modules to receive tasks in the bad blocks.

10. The method for monitoring bad blocks of a computing core based on a chiplet architecture according to claim 5, characterized in that: The method further comprises: When all computing blocks in the computing power core module are operating normally, the monitor sequentially obtains status information of each computing block, and performs power consumption estimation, performance estimation, and resource occupancy estimation on the status information to obtain evaluation information of the entire computing power core module; The evaluation information is stored in a computing block status table, and the evaluation information is transmitted to the central processing unit module through the computing block status table.

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