Multi-level caching method, equipment and medium

Abstract

The invention discloses a multi-level caching method and device and a medium, and the method comprises the steps: determining a first cache and a second cache through a preset CPU, and connecting an external bus through the first cache to receive data from the external bus; an operation request corresponding to the data is judged, and the operation request comprises read operation, write operation, reset and synchronization; if the operation request is a read operation or a write operation, querying the first cache to determine a packet header storage array of the first cache, determining a hit state of the data through the packet header storage array, and performing a corresponding operation according to the hit state; and if the operation request is reset and synchronization, determining the state of the first cache so as to reset and / or synchronize the first cache and the second cache according to the state of the first cache. According to the method, the data processing efficiency and the system stability are remarkably improved, the logic is clear, the data processing speed is increased, and the flexibility and maintainability of the system are enhanced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a multi-level cache method, device and medium. Background Art

[0002] In modern computer architecture, the performance difference between the central processing unit (CPU) and main memory (RAM) is becoming increasingly significant. The CPU is known for its extremely high computing speed and can quickly process a large amount of data instructions. Although the main memory RAM has a large capacity and low cost, its access speed is relatively slow, which has become one of the bottlenecks restricting the performance of the CPU. In order to alleviate this contradiction and improve the overall performance of the system, cache technology came into being. Cache is a fast storage medium located between the CPU and the main memory. Its original design is to store data and instructions that the CPU has recently or may soon access. By reducing the number of direct accesses of the CPU to the main memory, cache technology can significantly improve data access efficiency and reduce the waiting time of the CPU, thereby enhancing the overall response speed and throughput of the system. In a multi-level cache architecture, how to ensure the consistency of data between caches at all levels and between caches and main memory is a complex issue. When the data in a cache is updated, it is necessary to ensure that the corresponding data in all other caches and main memory are also updated synchronously, otherwise it will cause data inconsistency problems and affect the correct execution of the program. Summary of the invention

[0003] In order to solve the above problems, the present application proposes a multi-level cache method, including: determining a first cache and a second cache through a pre-set CPU, and connecting an external bus through the first cache to receive data from the external bus; judging the operation request corresponding to the data, wherein the operation request includes a read operation, a write operation, a reset and a synchronization; if the operation request is a read operation or a write operation, querying the first cache to determine the packet header storage array of the first cache, determining the hit status of the data through the packet header storage array, and performing corresponding operations according to the hit status; if the operation request is a reset and synchronization, determining the status of the first cache to reset and / or synchronize the first cache and the second cache according to the status of the first cache.

[0004] In one example, the operation request is a read operation, which specifically includes: querying the first cache to determine the packet header storage array of the first cache, and determining the hit status of the data through the packet header storage array, wherein the hit status includes hit and miss; if the hit status is a hit, determining whether the first cache and the second cache are consistent; if the first cache and the second cache are consistent, reading the data through the first cache; if the first cache and the second cache are inconsistent, determining the dirty bit mark signal of the first cache, and reading the data according to the dirty bit mark signal; if the hit status is a miss, upgrading the operation request so that the operation request reaches the level of the second cache, and sending the upgraded operation request to the pipeline of the second cache to read the data through the second cache.

[0005] In one example, after reading data through the second cache, the method also includes: caching the operation request through the second cache, reading data from the cached operation request, and sending a read signal to the CPU; receiving the read signal through the CPU to obtain the read data according to the read signal, so that the CPU sends the read data through the external bus.

[0006] In one example, the operation request is a write operation, which specifically includes: querying the first cache to determine the packet header storage array of the first cache, and determining the hit status of the data through the packet header storage array, wherein the hit status includes hit and miss; if the hit status is a hit, indexing through the packet header storage array to determine the corresponding data to be written; if the hit status is a miss, upgrading the operation request so that the operation request reaches the level of the second cache, and sending the upgraded operation request to the pipeline of the second cache to write data through the second cache.

[0007] In an example, the method further includes: determining the written data through the first cache, setting a dirty bit mark according to the written data, so as to distinguish the original data of the second cache according to the dirty bit mark.

[0008] In one example, the first cache and the second cache are reset and / or synchronized according to the state of the first cache, specifically including: determining whether there is a dirty bit in the first cache according to the state of the first cache; if there is a dirty bit in the first cache, resetting the first cache and synchronizing the first cache according to the second cache; if there is no dirty bit in the first cache, resetting the first cache and the second cache.

[0009] In an example, the method further includes: receiving the data through the first cache, and forwarding the data to the CPU, so that the CPU determines the corresponding operation request according to the data.

[0010] In one example, the method also includes: determining an upgrade request through the first cache, sending the upgrade request to the CPU, so that the CPU upgrades the operation request according to the upgrade request; sending the upgraded operation request to the second cache, so that the second cache performs a corresponding operation; and returning the operated data to the CPU through the second cache, so that the CPU forwards the operated data to the first cache.

[0011] On the other hand, the present application also proposes a multi-level cache device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the multi-level cache device can execute: determining a first cache and a second cache through a pre-set CPU, and connecting an external bus through the first cache to receive data from the external bus; judging an operation request corresponding to the data, wherein the operation request includes a read operation, a write operation, a reset and a synchronization; if the operation request is a read operation or a write operation, querying the first cache to determine the packet header storage array of the first cache, determining the hit status of the data through the packet header storage array, and performing corresponding operations according to the hit status; if the operation request is a reset and synchronization, determining the status of the first cache to reset and / or synchronize the first cache and the second cache according to the status of the first cache.

[0012] On the other hand, the present application also proposes a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured to: determine a first cache and a second cache through a pre-set CPU, and connect an external bus through the first cache to receive data from the external bus; judge an operation request corresponding to the data, wherein the operation request includes a read operation, a write operation, a reset and a synchronization; if the operation request is a read operation or a write operation, query the first cache to determine a packet header storage array of the first cache, determine a hit status of the data through the packet header storage array, and perform corresponding operations according to the hit status; if the operation request is a reset and synchronization, determine the status of the first cache to reset and / or synchronize the first cache and the second cache according to the status of the first cache.

[0013] This application significantly improves data processing efficiency and system stability through fine hierarchical management and operation optimization. This application first uses the first cache directly controlled by the CPU as the outpost of data interaction, quickly responds to various operation requests such as read, write, reset and synchronization, and effectively reduces the burden on the external bus. For read operations, the data hit status is accurately judged through the packet header storage array, and the data consistency between caches is intelligently distinguished to ensure the accuracy and efficiency of data reading. In the case of a miss, it is seamlessly upgraded to the second cache for processing, ensuring the continuity of data access. It is also efficient for write operations. When it hits, the index is directly written, and when it misses, the processing is upgraded, reducing data update delays. The dirty bit marking mechanism effectively distinguishes the data status between caches and provides an accurate basis for synchronization and reset operations. The reset and synchronization process is flexibly adjusted according to the cache status, which not only ensures data consistency, but also avoids unnecessary operation overhead. In addition, this application also realizes efficient collaboration between the CPU and the cache. The CPU can dynamically adjust the operation request according to the data, and timely feedback the processing results through the first cache, enhancing the overall responsiveness of the system. The entire process is compactly designed with clear logic, which not only improves the data processing speed but also enhances the flexibility and maintainability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0015] Figure 1 A schematic diagram of a multi-level cache method in an embodiment of the present application;

[0016] Figure 2 This is a schematic diagram of the structure of a multi-level cache system based on the RISC-V architecture in an embodiment of the present application;

[0017] Figure 3 This is a schematic diagram of arbitration logic of a multi-level cache system based on RISC-V architecture in an embodiment of the present application;

[0018] Figure 4 A schematic diagram of a multi-level cache device in an embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0020] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0021] like Figure 1 As shown, in order to solve the above problems, the embodiment of the present application provides a multi-level cache method, such as Figure 2 As shown, in a multi-level cache system based on RISC-V architecture, the method includes:

[0022] S101 . Determine a first cache and a second cache through a preset CPU, and connect an external bus through the first cache to receive data from the external bus.

[0023] In the CPU under the RISC-V architecture, two levels of cache are pre-set, namely L0 cache (herein referred to as the first cache) and L1 cache (herein referred to as the second cache). The CPU is connected to the external bus system through the L0 cache, and the external bus is further branched into the L1 cache bus, the high-speed bus, and the low-speed bus. Among them, the L1 cache bus is directly connected to the L1 cache, which is used to process the system's large storage requirements or long access intervals for data temporary storage; the high-speed bus follows the AHB signal standard of the AMBA bus protocol and is connected to high-speed peripherals, such as high-speed interfaces such as PCIE; and the low-speed bus is based on the APB signal of AMBA, serving low-speed peripherals such as SPI, UART and other common low-speed serial ports. The choice of peripheral bus type is mainly based on the communication frequency of the peripheral interface.

[0024] During system operation, large amounts of data such as calculation results and pre-stored data are first stored in the L1 cache. When this data needs to be accessed, the L1 cache will send the data to the L0 cache based on the request. The L0 cache is mainly used to temporarily store data and does not have long-term storage capabilities. For data that needs to be stored for a long time, it will eventually be forwarded from the L0 cache to the L1 cache for storage.

[0025] In order to effectively manage the data in the L0 cache and L1 cache, all information is stored in the cache at each level in the form of a packet header containing address information. When data is stored in the cache, the system will record the instruction and address of the data, and determine whether the data is hit by address matching during subsequent access. If the data hits, the corresponding read or update operation is performed according to the read or write request; if the data does not hit, the request will be promoted to the L1 cache for processing. This mechanism ensures the efficiency and accuracy of data access.

[0026] S102: Determine an operation request corresponding to the data, wherein the operation request includes a read operation, a write operation, a reset, and a synchronization.

[0027] The L0 level cache structure integrates the high-speed bus (AHB) interface and the low-speed bus (APB) interface. These interfaces can simultaneously receive data from high-speed peripherals or low-speed peripherals, and can send data back to the corresponding peripherals to achieve efficient data interaction. All information entering or leaving the L0 level through the interface must pass through the bus to make an operation request to request the register for arbitration processing. Figure 3 As shown in Figure 1, the arbitration logic of the bus request register includes three basic modes: read operation, write operation, and reset and synchronization. These arbitration logics ensure the orderly transmission and processing of data on the bus.

[0028] S103: If the operation request is a read operation or a write operation, query the first cache to determine the packet header storage array of the first cache, determine the hit status of the data through the packet header storage array, and perform corresponding operations according to the hit status.

[0029] In one embodiment, for a read operation, the system first queries the packet header storage array to determine whether the data is hit.

[0030] If the data hits, the system will further check whether there is a cache consistency problem. This happens when both the L1 cache and the L0 cache contain the same data, but the data in the L0 cache has changed due to use or calculation, while the data in the L1 cache remains in its original state. This is called cache inconsistency. When the cache is inconsistent, the system will give priority to the data with a dirty bit mark in the L0 cache, and ignore the dirty bit mark in its highest bit before reading the data. Among them, the dirty bit mark means that in the L0 cache, if the data is modified, an additional 1 is set in its highest bit as a mark. This type of data has an increased number of bits and the highest bit is 1, which is called dirty data. In this way, the overhead caused by frequent reads and writes between caches is reduced, because dirty data is temporarily stored in the L0 cache and does not need to be uploaded to the L1 cache immediately.

[0031] If the data does not hit, the system will first store the packet header information in the Missing Status Register (MSHR) for recording, and then upgrade the read request and forward it to the L1 level pipeline processing. The L1 cache will respond to this request and send the data to the CPU. The CPU will eventually send the data to the corresponding high-speed or low-speed peripheral interface through the corresponding module. This process ensures the continuity and accuracy of data reading.

[0032] In one embodiment, for a write operation, the system also first queries the packet header storage array to determine whether the data is hit.

[0033] If the data hits, the system adopts the "write back + write without allocation" cache strategy. In the current storage architecture, the CPU interacts directly with the L0 cache, and the L1 cache is used as an off-chip storage to cache data that is large in size but not frequently accessed or temporarily needed. The L0 cache focuses on caching currently active data, such as single-step results in a step-by-step calculation process. Regarding write operations, there are two key concepts: write hits and write misses. When a write hit occurs, it means that the header or tag of the data packet can find the corresponding address and data in the current cache level, that is, the L0 cache, allowing it to be modified directly. On the contrary, if the write operation does not hit, that is, a write miss occurs, it means that the required data is located in the next level of cache, which is actually located in the L1 cache. At this time, the L0 cache will retain the missing header information in the miss status register (MSHR) and send a request to the L1 cache to obtain the data. After the L1 cache responds, the corresponding data is sent to the L0 cache, and the L0 cache then performs data operations. The "write back + write without allocation" strategy plays an important role in this architecture. The "write back" strategy means that in the case of a write hit, the data is only written to the L0 cache, and the data that has been modified and is inconsistent with the data in the L1 cache is marked by setting the dirty bit. The dirty bit is an additional data bit used to indicate that the data has been modified. This strategy reduces the frequent reading and writing between multi-level caches and improves the efficiency of data transfer. The "write no allocation" strategy is aimed at write misses. It stipulates that when the data is not in the current highest-level cache, that is, the L0 cache, it is directly written to the L1 cache without recording the missing packet header in the L0 cache. This avoids unnecessary data copying in the L0 cache, further improves the efficiency of data reading and writing, reduces data rewrite operations between multi-level caches, and thus improves the overall performance of the system.

[0034] The system will find the data under the corresponding index in the data storage array and modify or write new data directly in the L0 cache. These data will not be uploaded to the L1 cache immediately, but will be temporarily stored in the L0 cache. Therefore, it is necessary to mark the modified data in the L0 cache by setting the dirty bit so that necessary synchronization or write-back operations can be performed in the future. The dirty bit processing ensures that the data in the L0 cache can be distinguished from the old data that may exist in the L1 cache.

[0035] If the write operation misses, the system will promote the write request to the L1 cache, and the CPU will respond and write directly to the L1 cache. In this case, since the data does not exist in the L0 cache, there is no need to perform dirty bit processing on the data in the L1 cache. This process reflects the collaborative work between cache levels and the data consistency maintenance strategy.

[0036] S104: If the operation request is reset and synchronization, determine the state of the first cache, and reset and / or synchronize the first cache and the second cache according to the state of the first cache.

[0037] When performing data synchronization and reset operations, the system needs to check the status of the L0 cache to determine whether there is an ongoing read or write process and the existence of the dirty bit. Based on the inspection results, the system will perform corresponding cleaning and data initialization operations.

[0038] The "cleaning" process is designed to clear all existing dirty bits and ensure data consistency between the L0 cache and the L1 cache. If a dirty bit is detected, the system first performs a clean operation on the L0 cache, that is, removes the dirty bit mark and synchronizes the latest data in the L1 cache to the L0 to maintain data consistency between the two.

[0039] The "reset" operation is to initialize all data. If there is no dirty bit in the system, it means that the data status of the L0 cache is relatively consistent with that of the L1 cache. At this time, the L0 cache and the L1 cache are directly initialized to restore them to their initial state.

[0040] Through such optimization processing, the system can manage cache data more effectively and ensure high efficiency and accuracy in synchronization and reset operations.

[0041] In one embodiment, all operation requests of the system are finally summarized by the L0 cache and sent to the RISC-V interface to be passed to the CPU through the interface. The CPU is responsible for further judgment, calculation, display and other processing. The RISC-V processor is directly connected to the L1 cache. When the L0 cache needs to initiate read and write requests for the level of the L1 cache, these requests are first received and processed by the CPU of the RISC-V core. Subsequently, the CPU sends the processing results back to the L0 cache so that they can be forwarded to the corresponding interface for further operation. This design ensures the smooth transmission and efficient processing of data between cache levels.

[0042] like Figure 4 As shown, the embodiment of the present application also provides a multi-level cache device, including:

[0043] at least one processor; and,

[0044] a memory communicatively connected to at least one processor; wherein,

[0045] The memory stores instructions executable by at least one processor, and the instructions are executed by at least one processor to enable a multi-level cache device to perform:

[0046] Determine a first cache and a second cache by a preset CPU, and connect an external bus through the first cache to receive data from the external bus;

[0047] Determining an operation request corresponding to the data, wherein the operation request includes a read operation, a write operation, a reset and a synchronization;

[0048] If the operation request is a read operation or a write operation, query the first cache to determine the packet header storage array of the first cache, determine the hit status of the data through the packet header storage array, and perform a corresponding operation according to the hit status;

[0049] If the operation request is reset and synchronization, the state of the first cache is determined to reset and / or synchronize the first cache and the second cache according to the state of the first cache.

[0050] The embodiment of the present application further provides a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured as follows:

[0051] Determine a first cache and a second cache by a preset CPU, and connect an external bus through the first cache to receive data from the external bus;

[0052] Determining an operation request corresponding to the data, wherein the operation request includes a read operation, a write operation, a reset and a synchronization;

[0053] If the operation request is a read operation or a write operation, query the first cache to determine the packet header storage array of the first cache, determine the hit status of the data through the packet header storage array, and perform a corresponding operation according to the hit status;

[0054] If the operation request is reset and synchronization, the state of the first cache is determined to reset and / or synchronize the first cache and the second cache according to the state of the first cache.

[0055] In the 1990s, improvements to a technology could be clearly distinguished as hardware improvements (for example, improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the method flow). However, with the development of technology, many improvements to the method flow today can be regarded as direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement in a method flow cannot be implemented using a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask a chip manufacturer to design and produce a dedicated integrated circuit chip. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0056] The controller can be implemented in any appropriate manner, for example, the controller can take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) that can be executed by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in a purely computer-readable program code manner, the controller can be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, this controller can be considered as a hardware component, and the devices included therein for implementing various functions can also be regarded as structures within the hardware component. Or even, the devices for implementing various functions can be regarded as both software modules for implementing the method and structures within the hardware component.

[0057] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0058] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0059] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0060] The devices and media provided in the embodiments of the present application correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0061] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0062] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0063] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0064] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0065] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0066] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0067] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0068] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0069] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A multi-level caching method, It is characterized in that include: Determine a first cache and a second cache by a preset CPU, and connect an external bus through the first cache to receive data from the external bus; Determining an operation request corresponding to the data, wherein the operation request includes a read operation, a write operation, a reset and a synchronization; If the operation request is a read operation or a write operation, query the first cache to determine the packet header storage array of the first cache, determine the hit status of the data through the packet header storage array, and perform a corresponding operation according to the hit status; If the operation request is reset and synchronization, the state of the first cache is determined to reset and / or synchronize the first cache and the second cache according to the state of the first cache.

2. The method according to claim 1, It is characterized in that The operation request is a read operation, specifically including: querying the first cache to determine a packet header storage array of the first cache, and determining a hit status of the data through the packet header storage array, wherein the hit status includes a hit and a miss; If the hit status is a hit, determining whether the first cache and the second cache are consistent; If the first cache and the second cache are consistent, reading data through the first cache; If the first cache is inconsistent with the second cache, determining a dirty bit mark signal of the first cache, and reading data according to the dirty bit mark signal; If the hit status is a miss, the operation request is upgraded to make the operation request reach the level of the second cache, and the upgraded operation request is sent to the pipeline of the second cache to read data through the second cache.

3. The method according to claim 2, It is characterized in that After reading data through the second cache, the method further includes: caching the operation request through the second cache, reading data of the cached operation request, and sending a read signal to the CPU; The CPU receives the read signal to obtain the read data according to the read signal, so that the CPU sends the read data through the external bus.

4. The method according to claim 1, It is characterized in that The operation request is a write operation, specifically including: querying the first cache to determine a packet header storage array of the first cache, and determining a hit status of the data through the packet header storage array, wherein the hit status includes a hit and a miss; If the hit status is a hit, indexing is performed through the packet header storage array to determine the corresponding data for writing; If the hit status is a miss, the operation request is upgraded to make the operation request reach the level of the second cache, and the upgraded operation request is sent to the pipeline of the second cache to write data through the second cache.

5. The method according to claim 1, It is characterized in that The method further comprises: The written data is determined through the first cache, and a dirty bit mark is set according to the written data, so as to distinguish the original data of the second cache according to the dirty bit mark.

6. The method according to claim 1, It is characterized in that Resetting and / or synchronizing the first cache and the second cache according to the state of the first cache specifically includes: determining whether the first cache has a dirty bit according to the state of the first cache; If the first cache has a dirty bit, resetting the first cache and synchronizing the first cache according to the second cache; If the first cache does not have a dirty bit, the first cache and the second cache are reset.

7. The method according to claim 1, It is characterized in that The method further comprises: The data is received through the first cache, and the data is forwarded to the CPU, so that the CPU determines the corresponding operation request according to the data.

8. The method according to claim 1, It is characterized in that The method further comprises: Determine an upgrade request through the first cache, and send the upgrade request to the CPU, so that the CPU upgrades the operation request according to the upgrade request; sending the upgraded operation request to the second cache so that the second cache performs a corresponding operation; The operated data is returned to the CPU through the second cache, so that the CPU forwards the operated data to the first cache.

9. A multi-level cache device, It is characterized in that include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the multi-level cache device to execute: Determine a first cache and a second cache by a preset CPU, and connect an external bus through the first cache to receive data from the external bus; Determining an operation request corresponding to the data, wherein the operation request includes a read operation, a write operation, a reset and a synchronization; If the operation request is a read operation or a write operation, query the first cache to determine the packet header storage array of the first cache, determine the hit status of the data through the packet header storage array, and perform a corresponding operation according to the hit status; If the operation request is reset and synchronization, the state of the first cache is determined to reset and / or synchronize the first cache and the second cache according to the state of the first cache.

10. A non-volatile computer storage medium storing computer executable instructions, It is characterized in that The computer executable instructions are configured to: Determine a first cache and a second cache by a preset CPU, and connect an external bus through the first cache to receive data from the external bus; Determining an operation request corresponding to the data, wherein the operation request includes a read operation, a write operation, a reset and a synchronization; If the operation request is a read operation or a write operation, query the first cache to determine the packet header storage array of the first cache, determine the hit status of the data through the packet header storage array, and perform a corresponding operation according to the hit status; If the operation request is reset and synchronization, the state of the first cache is determined to reset and / or synchronize the first cache and the second cache according to the state of the first cache.

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