Configurable PCIe transaction to CPP bus transaction conversion method and device
Through the explicit mode extension of Bar and explicit bar configuration, the target CPP transaction is generated and executed, and the mapping problem of PCIe transactions to CPP bus is solved, full mapping and flexibility is achieved, the R&D process is simplified and multiple CPP transaction types are handled. .
Patent Information
- Application Number
- CN202410872808.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-01
- Publication Date
- 2024-12-17
AI Technical Summary
The prior art cannot fully map PCIe transactions to all transaction types in the CPP bus, especially the complex transaction type requirements in the CPP bus.
The extended Bar adopts an explicit mode, and uses explicit bar to select and configure parameter data, generate target CPP transactions, and execute the operands of PCIe write transactions in the shared cache, triggering the explicit operation of the target CPP transaction, realizing the CPP bus Full map.
It realizes full mapping from PCIe transactions to CPP bus, simplifies the R&D process, enhances flexibility and dynamic configurability, and can handle a variety of CPP transaction types, including atomic add, atomic add sat, atomic sub and atomic sub sat, etc. .
Smart Images
Figure CN119149465A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of CPP transaction conversion, and in particular to a configurable PCIe transaction to CPP bus transaction conversion method and device. Background Art
[0002] The conversion of PCIe transactions to CPP bus transactions maps the addresses and transactions of the PCIe domain to the addresses and transactions of the CPP bus. Many common conversion modules can only map PCIe read and write transactions to traditional read and write operations, or a subset of atomic operations defined in the PCIe specification. However, the transaction type of the CPP bus is determined by the combination of the action / token fields, and common conversion modules will not be able to meet all transaction types in the CPP bus. Summary of the invention
[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a configurable PCIe transaction to CPP bus transaction conversion method and device, so as to solve the above technical problems in the prior art.
[0004] To achieve the above-mentioned purpose and other related purposes, the present invention provides a configurable PCIe transaction to CPP bus transaction conversion method, the method comprising: selecting an extended bar using an explicit mode based on an input PCIe address, and selecting an explicit bar in the extended bar; wherein the explicit bar stores parameter data corresponding to the configuration of each CPP transaction; using a PCIe read transaction configured as an explicit mode to access the configuration in the selected explicit bar and generate a target CPP transaction and send it to the CPP bus, so that the target CPP obtains the operand corresponding to the target CPP transaction written by the PCIe write transaction from the corresponding shared cache, so as to trigger the explicit operation corresponding to the target CPP transaction, and the target CPP returns the modified data to the PCIe device after the operation is completed.
[0005] In one embodiment of the present invention, the step of selecting an extended bar in explicit mode based on an input PCIe address, and selecting an explicit bar in the extended bar includes: selecting a corresponding extended bar in explicit mode based on the highest 3 bits of the input valid PCIe address; wherein the extended bar includes: a plurality of explicit bars; selecting a corresponding explicit bar in the extended bar based on the highest 2 bits of the valid PCIe address except the highest 3 bits.
[0006] In one embodiment of the present invention, each explicit bar includes: a first register, a second register, a third register and a reserved fourth register; wherein the first register, the second register and the third register respectively store first parameter information, second parameter information and third parameter information corresponding to the configuration of each CPP transaction.
[0007] In one embodiment of the present invention, the first parameter information includes: Address information for providing the corresponding CPP bus address, Token information in the corresponding CPP bus, and Signaltype information corresponding to the number of responses returned by the CPP bus; the second parameter information includes: SignalRef information in the corresponding CPP bus, DataMaster information in the corresponding CPP bus, and data reference information in the corresponding CPP bus; the third parameter information includes: Target information including the target ID in the corresponding CPP bus, Action information including the ation encoding in the corresponding CPP bus, Length information in the corresponding CPP bus, Bytemask information in the corresponding CPP bus, and SignalMaster information in the corresponding CPP bus.
[0008] In an embodiment of the present invention, the method of providing the corresponding CPP bus address by using the Address information includes: generating the corresponding CPP bus address based on the PCIe address and the Address information corresponding to the CPP bus address.
[0009] In an embodiment of the present invention, the first register, the second register, the third register and the fourth register are all 32 bits.
[0010] In one embodiment of the present invention, the PCIe device encapsulates the data into a Completion TLP.
[0011] In one embodiment of the present invention, the explicit command execution state machine triggers the generation of a target CPP transaction through the PCIe read transaction and receives the modified data returned by the target CPP.
[0012] In an embodiment of the present invention, the types of the target CPP transaction include: atomic add transaction, atomic add sat transaction, atomic sub transaction and atomic sub sat transaction.
[0013] To achieve the above-mentioned purpose and other related purposes, the present invention provides a configurable PCIe transaction to CPP bus transaction conversion device, comprising: an explicit bar configuration module, used to select an extended bar using an explicit mode based on an input valid PCIe address, and select an explicit bar in the extended bar; wherein the explicit bar stores parameter data corresponding to the configuration of each CPP transaction; a CPP transaction generation module, connected to the explicit bar configuration module, used to use a PCIe read transaction configured as an explicit mode to access the data in the selected explicit bar and generate a target CPP transaction and send it to the CPP bus, so that the target CPP obtains the operand corresponding to the target CPP transaction written by the PCIe write transaction from the shared cache, so as to trigger the explicit operation corresponding to the target CPP transaction, and the target CPP returns the modified data to the PCIe device after the operation is completed.
[0014] As described above, the present invention is a configurable PCIe transaction to CPP bus transaction conversion method and device, which has the following beneficial effects: the present invention uses a flexible and configurable explicit Bar to achieve full mapping from PCIe transactions to CPP buses, that is, by using a PCIe read transaction configured as an explicit mode to access the configuration in the selected explicit bar and generate a target CPP transaction and send it to the CPP bus, so that the target CPP can obtain the operand corresponding to the target CPP transaction written by the PCIe write transaction from the shared cache to trigger the explicit operation corresponding to the target CPP transaction, and the target CPP returns the modified data to the PCIe device after the operation is completed. The design scheme of the present invention is simple to implement and shortens the research and development cycle, and has dynamic configurability and enhanced flexibility of use. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 Shown is a flow chart of a configurable PCIe transaction to CPP bus transaction conversion method in one embodiment of the present invention.
[0016] Figure 2 Shown is a schematic diagram of extended bar and explicit bar selection in one embodiment of the present invention.
[0017] Figure 3 Shown is a schematic structural diagram of a configurable PCIe transaction to CPP bus transaction conversion device in an embodiment of the present invention. DETAILED DESCRIPTION
[0018] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
[0019] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present invention. It should be understood that other embodiments may also be used, and that mechanical composition, structural, electrical and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present invention is limited only by the claims of the published patents. The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.
[0020] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a part is said to "include" a certain constituent element, unless otherwise stated, it does not exclude other constituent elements, but means that other constituent elements may be included.
[0021] The terms first, second and third mentioned herein are used to describe various parts, components, regions, layers and / or segments, but are not limited thereto. These terms are only used to distinguish a certain part, component, region, layer or segment from other parts, components, regions, layers or segments. Therefore, the first part, component, region, layer or segment described below may refer to the second part, component, region, layer or segment within the scope of the present invention.
[0022] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.
[0023] The present invention provides a configurable PCIe transaction to CPP bus transaction conversion method and device, which realizes full mapping from PCIe transaction to CPP transaction by using flexible and configurable explicit Bar, that is, by using PCIe read transaction configured as explicit mode to access the data in the selected explicit bar and generate a target CPP transaction and send it to the CPP bus, so that the target CPP can obtain the operand corresponding to the target CPP transaction written by the PCIe write transaction from the shared cache to trigger the explicit operation corresponding to the target CPP transaction, and the target CPP returns the modified data to the PCIe device after the operation is completed. The design scheme of the present invention is simple to implement and shortens the research and development cycle, and has dynamic configurability and enhanced flexibility of use.
[0024] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.
[0025] like Figure 1 A schematic flow chart showing a configurable PCIe transaction to CPP bus transaction conversion method in an embodiment of the present invention.
[0026] The method comprises:
[0027] Step S1: selecting an extended bar in explicit mode based on an input PCIe address, and selecting an explicit bar in the extended bar.
[0028] In one embodiment, if Figure 2 As shown, step S1 includes: selecting a corresponding extended bar in explicit mode based on the highest 3 bits of valid bits of the input PCIe address; wherein the extended bar is an explicit register group.
[0029] The extended bar includes: a plurality of explicit bars; based on the highest 2 bits of data except the highest 3 bits of data of the PCIe address, a corresponding explicit bar is selected in the extended bar. The explicit bar is an explicit register group.
[0030] In one embodiment, if Figure 2 As shown, each explicit bar includes: a first register reg_0, a second register reg_1, a third register reg_2 and a reserved fourth register reg_3; wherein the first register reg_0, the second register reg_1 and the third register reg_2 respectively store the first parameter information, the second parameter information and the third parameter information corresponding to the configuration of each CPP transaction.
[0031] In one embodiment, the first parameter information includes: Address information for providing the corresponding CPP bus address, Token information in the corresponding CPP bus, and Signal type information corresponding to the number of responses returned by the CPP bus; the second parameter information includes: SignalRef information in the corresponding CPP bus, DataMaster information in the corresponding CPP bus, and data reference information in the corresponding CPP bus; the third parameter information includes: Target information including the target ID in the corresponding CPP bus, Action information including the ation encoding in the corresponding CPP bus, Length information in the corresponding CPP bus, Bytemask information in the corresponding CPP bus, and SignalMaster information in the corresponding CPP bus.
[0032] In one embodiment, the first register, the second register, the third register and the fourth register are all 32 bits.
[0033] The content stored in the first register is shown in Table 1, where bits 31:30 store Signal type information, bits 29:28 store Token information, bits 27:24 store Reserved bits, and bits 23:0 store Address information.
[0034] Table 1: The first register stores the first parameter information table
[0035]
[0036] The content stored in the second register is shown in Table 2, where bit 31 stores the Reserved bit, bits 30:24 store SignalRef information, bits 23:14 store DataMaster information, and bits 13:0 store data ref information.
[0037] Table 2: The second register stores the second parameter information table
[0038] Bits Field name Access Description 31 Reserved rw Reserved 30:24 SignalRef rw Signal ref in CPP bus 23:14 DataMaster rw Data master in CPP bus 13:0 Dataref rw Data reference in CPP bus
[0039] The content stored in the third register is shown in Table 3, where 31:30 stores Target information, 27:23 stores Action information, and each CPP transaction corresponds to an Action code. 22:18 stores Length information; 17:10 stores Bytemask information. 9:0 stores SignalMaster information.
[0040] Table 3: The third register stores the third parameter information table
[0041] Bits Field name Access Description 31:28 Target rw Target ID in CPP bus 27:23 Action rw ation encoding in CPP bus 22:18 Length rw length in CPP bus 17:10 Bytemask rw Byte mask in CPP bus 9:0 SignalMaster rw Signal master in CPP bus
[0042] In one embodiment, the method of providing the corresponding CPP bus address by using the Address information includes: generating the corresponding CPP bus address based on the PCIe address and the Address information corresponding to the CPP bus address.
[0043] Specifically, the difference between the number of bits remaining after removing the previous high 5 bits of the effective PCIe address and the number of bits of the fixed address of the CPP bus address (40 bits) is calculated, and the corresponding number of bits (from high to low) is found from the Address information and combined with the number of bits remaining after removing the previous high 5 bits of the effective PCIe address. Generally speaking, it is added to the high bits of the remaining bits to obtain the final CPP bus address.
[0044] For example, if the PCIe address is 32 bits, there are 27 bits left after removing 5 bits, which is 13 bits short of the 40 bits of the complete CPP bus address. Therefore, 23:11 bits are taken out from 23:0 and placed at 39:27 bits of the address. Then 26:0 bits of the address are the remaining 27 bits after removing 5 bits of the PCIe address.
[0045] Step S2: Use a PCIe read transaction configured as explicit mode to access the data in the selected explicit bar and generate a target CPP transaction and send it to the CPP bus, so that the target CPP can obtain the operand corresponding to the target CPP transaction written by the PCIe write transaction from the shared cache to trigger the explicit operation corresponding to the target CPP transaction, and the target CPP returns the modified data to the PCIe device after the operation is completed.
[0046] In one embodiment, each explicit bar corresponds to a shared cache for storing operands of the target CPP transaction.
[0047] In one embodiment, the target CPP returns the modified data to the PCIe device.
[0048] In one embodiment, the explicit command execution state machine triggers the generation of the target CPP transaction and the reception of the modified data returned by the target CPP via the PCIe read transaction.
[0049] In one embodiment, the types of the target CPP transaction include: atomic add transaction, atomic add sat transaction, atomic sub transaction and atomic sub sat transaction.
[0050] For example, the method for implementing the conversion of atomic add transaction and atomic add sat transaction includes: first configure the maptype mode of Expansion BAR to Explicit. Then configure the parameters corresponding to the Atomic Add CPP transaction to the corresponding Explicit BAR register (action=7 corresponds to Add, action=8 corresponds to Add Sat). Use PCIe memory write transaction to write the required Add operand to the shared cache associated with explicit. Use PCIe memory read transaction to access the above prepared Explicit BAR to trigger Explicit Atomic Add or AtomicAdd Sat (add operation overflow does not flip) operation. The target CPP will return the data before and after modification, and then encapsulate it into Completion TLP and return it to the Host.
[0051] For implementing atomic sub transactions and atomic sub sat transactions, the operation is similar to Add or Add Sat (action=9 corresponds to Sub, action=10 corresponds to Sub Sat), except that the operation becomes subtraction.
[0052] It should be noted that this patent is not limited to the above-mentioned transactions, but can also realize the conversion of other similar types of transactions.
[0053] In one embodiment, for some special transactions such as Checksum, the operation process is different (action=36), and the message that needs to calculate the checksum is written into the dcache; after the message checksum is calculated by the atomic engine, it is returned to the Host.
[0054] In order to better illustrate the above configurable PCIe transaction to CPP bus transaction conversion method, the present invention provides the following specific embodiments.
[0055] Embodiment 1: A configurable PCIe transaction to CPP bus transaction conversion method. Figure 3 FIG. 1 is a flow chart of a method for converting a configurable PCIe transaction to a CPP bus transaction according to the present embodiment;
[0056] This embodiment discloses a configurable PCIe transaction to CPP bus transaction conversion mode—explicit, which implements the mapping from PCIe transactions to CPP bus transactions in a simple and flexible manner. According to the application scenario, the software can dynamically configure the hardware to convert PCIe transactions into various CPP transactions.
[0057] This design is implemented by the following process:
[0058] Expansion Bar select: Select the expansion bar based on the upper 3 bits of the PCIe address and configure the mapping type in the expansion bar to explicit.
[0059] Explicit Bar select: Select the explicit bar according to the second highest 2 bits of the PCIe address. The explicit bar consists of four groups of 32-bit registers, namely ExplicitCmdBar0~3, of which the last group of registers is reserved for future expansion of the CPP bus.
[0060] Explicit Bar program: This bar contains all the fields required by CPP. It can be configured to convert PCIe transactions into any CPP transactions. In addition, there is a SigType field that determines the number of responses returned by CPP, which can be configured to 0-2.
[0061] Use PCIe memory write transactions to write the required Add operands to the shared cache or dcache associated with the explicit.
[0062] Explicit Command execution FSM: This state machine is triggered by a PCIe message read transaction configured in explicit mode, including generating a CPP transaction and receiving CPP return data to generate a PCIe Completion transaction.
[0063] Similar to the principle of the above embodiment, the present invention provides a configurable PCIe transaction to CPP bus transaction conversion device.
[0064] The following provides specific embodiments in conjunction with the accompanying drawings:
[0065] like Figure 3 A schematic diagram of the structure of a configurable PCIe transaction to CPP bus transaction conversion device in an embodiment of the present invention is shown.
[0066] The PCIe transaction to CPP bus transaction conversion device is equivalent to a bridge between PCIe and CPP, and is used to convert PCIe transactions into CPP transactions according to the address of PCIe, and then send them to CPP for processing.
[0067] The device comprises:
[0068] An explicit bar configuration module 31 is used to select an extended bar in explicit mode based on an input PCIe address, and select an explicit bar in the extended bar; wherein the explicit bar stores parameter data corresponding to configuration of each CPP transaction;
[0069] The CPP transaction generation module 32 is connected to the explicit bar configuration module 31, and is used to use the PCIe read transaction configured in explicit mode to access the data in the selected explicit bar and generate a target CPP transaction and send it to the corresponding CPP bus, so that the CPP bus can obtain the operand corresponding to the target CPP transaction written by the PCIe write transaction from the shared cache to trigger the explicit operation corresponding to the target CPP transaction, and the CPP bus encapsulates the data after the operation is completed.
[0070] Furthermore, since the implementation principle of the configurable PCIe transaction to CPP bus transaction conversion device has been described in the aforementioned embodiment, it will not be repeated here.
[0071] In one embodiment, the method of selecting an extended bar using an explicit mode based on an input PCIe address, and selecting an explicit bar in the extended bar includes: selecting a corresponding extended bar using an explicit mode based on the highest 3 bits of the input PCIe address; wherein the extended bar includes: multiple explicit bars; selecting a corresponding explicit bar in the extended bar based on the highest 2 bits of the PCIe address except the highest 3 bits.
[0072] In one embodiment, each explicit bar includes: a first register, a second register, a third register and a reserved fourth register; wherein the first register, the second register and the third register respectively store first parameter information, second parameter information and third parameter information corresponding to the configuration of each CPP transaction.
[0073] In one embodiment, the first parameter information includes: Address information for providing the corresponding CPP bus address, Token information in the corresponding CPP bus, and Signal type information corresponding to the number of responses returned by the CPP bus; the second parameter information includes: SignalRef information in the corresponding CPP bus, DataMaster information in the corresponding CPP bus, and data reference information in the corresponding CPP bus; the third parameter information includes: Target information including the target ID in the corresponding CPP bus, Action information including the ation encoding in the corresponding CPP bus, Length information in the corresponding CPP bus, Bytemask information in the corresponding CPP bus, and SignalMaster information in the corresponding CPP bus.
[0074] In one embodiment, the method of providing the corresponding CPP bus address by using the Address information includes: generating the corresponding CPP bus address based on the PCIe address and the Address information corresponding to the CPP bus address.
[0075] In one embodiment, the first register, the second register, the third register and the fourth register are all 32 bits.
[0076] In one embodiment, the target CPP returns the modified data to the PCIe device.
[0077] In one embodiment, the explicit command execution state machine triggers the generation of the target CPP transaction and the reception of the modified data returned by the target CPP via the PCIe read transaction.
[0078] In one embodiment, the types of the target CPP transaction include: atomic add transaction, atomic add sat transaction, atomic sub transaction and atomic sub sat transaction.
[0079] In summary, the configurable PCIe transaction to CPP bus transaction conversion method and device of the present invention utilizes a flexible and configurable explicit Bar to achieve full mapping from PCIe transactions to CPP buses, that is, by using a PCIe read transaction configured in explicit mode to access the data in the selected explicit bar and generate a target CPP transaction and send it to the CPP bus, so that the target CPP can obtain the operand corresponding to the target CPP transaction written by the PCIe write transaction from the shared cache to trigger the explicit operation corresponding to the target CPP transaction, and the CPP bus returns the modified data to the PCIe device after the operation is completed. The design of the present invention is simple to implement and shortens the R&D cycle, and has dynamic configurability and enhanced flexibility of use. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
[0080] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A configurable PCIe transaction to CPP bus transaction conversion method, characterized in that: The method comprises: Selecting an extended bar in explicit mode based on an input PCIe address, and selecting an explicit bar in the extended bar; wherein the explicit bar stores parameter data corresponding to configuration of each CPP transaction; A PCIe read transaction configured as explicit mode is used to access the configuration in the selected explicit bar and generate a target CPP transaction and send it to the CPP bus, so that the target CPP can obtain the operand corresponding to the target CPP transaction written by the PCIe write transaction from the corresponding shared cache to trigger an explicit operation corresponding to the target CPP transaction, and the target CPP returns the modified data to the PCIe device after the operation is completed.
2. The configurable PCIe transaction to CPP bus transaction conversion method according to claim 1, characterized in that: The step of selecting an extended bar in explicit mode based on an input PCIe address and selecting an explicit bar in the extended bar comprises: Selecting a corresponding extended bar in explicit mode based on the highest 3 bits of the input valid PCIe address; wherein the extended bar includes: a plurality of explicit bars; A corresponding explicit bar is selected in the extended bar based on the highest 2 bits of the effective PCIe address except for the highest 3 bits of the data.
3. The configurable PCIe transaction to CPP bus transaction conversion method according to claim 1, characterized in that: Each explicit bar includes: a first register, a second register, a third register, and a fourth register as a reserved register; The first register, the second register and the third register respectively store first parameter information, second parameter information and third parameter information corresponding to configuring each CPP transaction.
4. The configurable PCIe transaction to CPP bus transaction conversion method according to claim 3, characterized in that: The first parameter information includes: Address information for providing the corresponding CPP bus address, Token information in the corresponding CPP bus, and Signal type information for the number of responses returned by the corresponding CPP bus; the second parameter information includes: SignalRef information in the corresponding CPP bus, DataMaster information in the corresponding CPP bus, and data reference information in the corresponding CPP bus; the third parameter information includes: Target information including the target ID in the corresponding CPP bus, Action information including the ation encoding in the corresponding CPP bus, Length information in the corresponding CPP bus, Bytemask information in the corresponding CPP bus, and SignalMaster information in the corresponding CPP bus.
5. The configurable PCIe transaction to CPP bus transaction conversion method according to claim 4, characterized in that: The method of providing the corresponding CPP bus address by using the Address information includes: generating the corresponding CPP bus address based on the PCIe address and the Address information corresponding to the CPP bus address.
6. The configurable PCIe transaction to CPP bus transaction conversion method according to claim 3, characterized in that: The first register, the second register, the third register and the fourth register are all 32 bits.
7. The configurable PCIe transaction to CPP bus transaction conversion method according to claim 1, characterized in that: The PCIe device encapsulates the modified data into a Completion TLP.
8. The configurable PCIe transaction to CPP bus transaction conversion method according to claim 1, characterized in that: The explicit command execution state machine triggers the generation of a target CPP transaction through the PCIe read transaction and receives the modified data returned by the target CPP.
9. The configurable PCIe transaction to CPP bus transaction conversion method according to claim 1, characterized in that: The types of the target CPP transaction include: atomic add transaction, atomic add sat transaction, atomic sub transaction and atomic sub sat transaction.
10. A configurable PCIe transaction to CPP bus transaction conversion device, characterized in that: include: An explicit bar configuration module, configured to select an extended bar in explicit mode based on an input PCIe address, and select an explicit bar in the extended bar; wherein the explicit bar stores parameter data corresponding to configuration of each CPP transaction; A CPP transaction generation module is connected to the explicit bar configuration module and is used to use a PCIe read transaction configured in explicit mode to access the data in the selected explicit bar and generate a target CPP transaction and send it to the CPP bus, so that the target CPP can obtain the operand corresponding to the target CPP transaction written by the PCIe write transaction from the shared cache to trigger the explicit operation corresponding to the target CPP transaction, and the target CPP returns the data to the PCIe device after the operation is completed.