Half-duplex inter-chip SPI register access method and system

Abstract

The invention discloses a half-duplex inter-chip SPI register access method and a half-duplex inter-chip SPI register access system in the field of information communication, the half-duplex inter-chip SPI register access method and the half-duplex inter-chip SPI register access system are used for a master-side FPGA to perform read-write operation on a slave-side FPGA, and the master-side FPGA comprises an ARM processor, a connector, a converter, a master-side register and a master-side SPI interface which are connected in sequence; the slave side FPGA comprises a slave side SPI (Serial Peripheral Interface) and a slave side register which are connected with each other; the method comprises a write state and / or a read state. In a writing state, the ARM processes and initiates a writing instruction, and the writing instruction passes through a data link, reaches the slave side FPGA through PCB routing and is finally written into a corresponding address of the slave side register; in a reading state, the ARM processor initiates a reading instruction, the reading instruction reaches the slave side FPGA through the data link and the PCB routing, finally reads data of a corresponding address of the slave side register through the data link, returns the data to the master side FPGA through the PCB routing through the reverse data link, and finally returns the data to the ARM processor through the data link; according to the invention, the function of reading and writing the register from the master side FPGA to the slave side FPGA can be realized.

Description

Technical Field

[0001] The present invention relates to the field of information communication technology, and in particular to a method and system for half-duplex inter-chip SPI access registers. Background Art

[0002] In some customized wireless communication products, due to the control of multiple peripherals, high-speed port transmission and digital intermediate frequency signal processing, from the perspective of economic cost, the use of a high-end FPGA chip equipped with ARM is often abandoned, and two low-end FPGAs are used to work together, one of which is a master FPGA equipped with ARM, and the other is a slave FPGA without ARM. The master FPGA is used to control peripherals and transmit high-speed data, while the slave FPGA is used to process digital intermediate frequency signals and develop some functions that do not require software collaboration. However, the absence of ARM means that there is no GP bus to call, so the basic function of registers cannot be realized. Registers play a pivotal role in both early debugging and later positioning problems. Therefore, on the platform where the master FPGA works in collaboration with the slave FPGA, it is particularly important to develop a register system that can meet the needs of technicians for debugging and positioning problems. Summary of the invention

[0003] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a method and system for half-duplex inter-chip SPI access to registers, which realizes the function of reading and writing registers from the master side FPGA to the slave side FPGA through a master side FPGA carrying an ARM processor to another slave side FPGA without an ARM processor through a serial universal interface SPI protocol.

[0004] To achieve the above object, the present invention is implemented by adopting the following technical solutions: In a first aspect, the present invention provides a method for half-duplex inter-chip SPI access to registers, which is used to perform read and write operations on a slave-side FPGA without an ARM processor through a master-side FPGA with an ARM processor, wherein the master-side FPGA includes an ARM processor, a connector, a converter, a master-side register, and a master-side SPI interface connected in sequence; the slave-side FPGA includes an interconnected slave-side SPI interface and a slave-side register; the method includes a write state and / or a read state; In the write state, the write data and write address output by the ARM processor are obtained, and are converted into protocol data of the AXI4 protocol via the connector in sequence, and are converted into interface data consisting of write enable, write data and write address via the converter, and are converted into predefined register data via the master-side register, and are converted into serial data of the SPI protocol via the master-side SPI interface, and are converted into predefined register data via the slave-side SPI interface, and the write enable, write address and write data are identified via the slave-side register, and the write data is stored in the write address; In the read state, the read address output by the ARM processor is obtained, and is converted into protocol data of the AXI4 protocol via the connector, converted into interface data consisting of a read enable and a read address via the converter, converted into predefined register data via the master-side register, converted into serial data of the SPI protocol via the master-side SPI interface, converted into predefined register data via the slave-side SPI interface, the read enable and the read address are identified via the slave-side register, and the read data corresponding to the read address is obtained; the read data is transmitted back to the ARM processor along the transmission path.

[0005] Optionally, in the write state, based on the handshake criteria of the AXI4 protocol: when the converter is ready, the converter sends a ready signal of the write address channel and the write data channel to the connector, indicating that the converter is ready, and the connector sends the write address and write data to the converter; when the connector is ready, the connector sends a ready signal of the write reply channel to the converter, indicating that the connector is ready, and the converter sends the write reply data to the connector; According to the protocol data of the AXI4 protocol obtained by the converter, the write address and the write data are aligned at the same time and sent to the master side register, and the write enable is sent to the master side register at the same time.

[0006] Optional, in write state, Define the SPI write enable register, including the SPI write enable address and its corresponding SPI write enable signal. The high and low levels of the SPI write enable signal indicate that the write enable is valid and invalid respectively. Define a read / write judgment register, including a read / write judgment address and its corresponding read / write judgment signal, the high and low levels of the read / write judgment signal represent the read state and the write state respectively; Define the SPI write address register, including the SPI write address and its corresponding SPI write address signal. The SPI write address signal is 16 bits, indicating that the maximum transmission bit width is 16 bits. Define the SPI write data register, including the address of the SPI write data and its corresponding SPI write data signal. The SPI write data signal is 32 bits, indicating that the maximum bit width of the data to be transmitted is 32 bits. According to the interface data consisting of write enable, write data and write address obtained by the master side register, the read / write judgment signal is set to a low level, the write address is used as the SPI write address signal, the write data is used as the SPI write data signal, and the SPI write enable signal is set to a high level.

[0007] Optionally, in the write state, when the SPI write enable signal is high, the working logic of the master side SPI interface is triggered: Set the SPI chip select signal to a low level, and at the unit clock cycle position of 10 system clocks, demultiply the connected system clock by 10 times, set the SPI clock, and use the rising edge sampling of the SPI clock. Since it is necessary to transmit a 1-bit read / write judgment signal, a 16-bit SPI write address signal, and a 32-bit SPI write data signal to the slave-side FPGA, the transmitted SPI clock needs to last for 49 SPI unit clock cycles; At the position of the unit clock cycle of 5 system clocks of the SPI chip select signal, set the setup time and hold time of the collected data to 50%, and use the shift register method to send 49 bits of read and write judgment signal, SPI write address signal, and SPI write data signal in sequence through the SPI MOSI bus. When the last 1 bit of write data signal is sent, the chip select signal is set to a high level after the hold time is met, completing the operation of slave-side FPGA transmission of write address and write data.

[0008] Optionally, in the write state, the working logic of the slave side SPI interface is: When the chip select signal is set to a low level, at the rising edge of the SPI clock, it is determined whether the received read / write determination signal is a low level. If so, the 16-bit SPI write address signal and the 32-bit SPI write data signal received through the SPI MOSI bus are cached and transmitted to the slave side register, and the write enable is output to the slave side register.

[0009] In a second aspect, the present invention provides a half-duplex inter-chip SPI access register system, which is used to perform read and write operations on a slave-side FPGA without an ARM processor through a master-side FPGA with an ARM processor, wherein the master-side FPGA includes an ARM processor, a connector, a converter, a master-side register, and a master-side SPI interface connected in sequence; the slave-side FPGA includes an interconnected slave-side SPI interface and a slave-side register; the system includes a write status execution module and / or a read status execution module; The write state execution module is used to obtain the write data and write address output by the ARM processor in the write state, convert them into protocol data of the AXI4 protocol via the connector in sequence, convert them into interface data consisting of write enable, write data and write address via the converter, convert them into predefined register data via the master side register, convert them into serial data of the SPI protocol via the master side SPI interface, convert them into predefined register data via the slave side SPI interface, identify the write enable, write address and write data via the slave side register, and store the write data in the write address; The read state execution module is used to obtain the read address output by the ARM processor in the read state, convert it into protocol data of the AXI4 protocol via a connector, convert it into interface data consisting of a read enable and a read address via a converter, convert it into predefined register data via a master side register, convert it into serial data of the SPI protocol via a master side SPI interface, convert it into predefined register data via a slave side SPI interface, identify the read enable and the read address via the slave side register, and obtain the read data corresponding to the read address; and transmit the read data back to the ARM processor along the transmission path.

[0010] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a method and system for half-duplex inter-chip SPI register access, 1) using a master-side FPGA carrying an ARM processor to another slave-side FPGA without an ARM processor through a serial universal interface SPI protocol to realize the function of the master-side FPGA to read and write registers from the slave-side FPGA, thereby avoiding the economic cost of completing all ARM functions in a high-end FPGA and reducing the development cost. 2) When realizing the transmission of data and addresses, the AXI4 protocol is used to convert to a simpler enable, address and data custom interface, and to the SPI protocol, to realize the interconnection of the AXI4 protocol and the SPI protocol, which is more flexible and gives the system the ability to adapt to more scenarios. 3) By dividing the specific modules of the master-side FPGA and the slave-side FPGA and the function implementation of the specific modules, the system logic is enhanced, and it is convenient to capture the breakpoints after problems occur during the debugging period, thereby enhancing the development efficiency. 4) Using the SPI protocol, the master FPGA realizes the register reading of the slave FPGA, which only requires simple PCB routing and does not require actual SPI devices, and can complete the register reading function, thereby reducing the complexity of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural diagram of a half-duplex inter-chip SPI access register provided by an embodiment of the present invention; Figure 2 It is a schematic diagram of a write state flow of a half-duplex inter-chip SPI access register provided by an embodiment of the present invention; Figure 3 The present invention is a flowchart of a read state of a half-duplex inter-chip SPI access register provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0012] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0013] Embodiment 1:

[0014] The embodiment of the present invention provides a half-duplex inter-chip SPI access register method for performing read and write operations on a slave FPGA without an ARM processor through a master FPGA with an ARM processor. Figure 1 As shown, the master-side FPGA includes an ARM processor, a connector, a converter, a master-side register, and a master-side SPI interface connected in sequence; the slave-side FPGA includes an interconnected slave-side SPI interface and a slave-side register.

[0015] like Figure 2 As shown, in the write state, the write data and write address output by the ARM processor are obtained, and are converted into protocol data of the AXI4 protocol via the connector in sequence, converted into interface data consisting of write enable, write data and write address via the converter, converted into predefined register data via the master side register, converted into serial data of the SPI protocol via the master side SPI interface, converted into predefined register data via the slave side SPI interface, and the write enable, write address and write data are identified via the slave side register, and the write data is stored in the write address.

[0016] In the data writing direction from the master-side FPGA to the slave-side FPGA, the required write address and write data are written to the connector through the PS. The write address and write data correspond to the logic of the master-side register controlling the master-side SPI interface, which specifically involve the SPI write enable signal, SPI read / write judgment signal, SPI write address signal and SPI write data signal. It is necessary to perform data writing operations on the master-side register at the above-mentioned specific address.

[0017] For example: On the master-side FPGA, define the base address of the master-side register as 0x0, the offset address of the SPI write enable signal as 0x20, the offset address of the read / write judgment signal as 0x21, the offset address of the SPI write address signal as 0x22, and the offset address of the write data signal as 0x23. The signal corresponding to the address 0x20 is the SPI write enable signal, which is used to trigger the logic of the master-side SPI interface. The signal corresponding to the address 0x21 is the SPI read / write judgment signal, which is used to distinguish the read / write status. The signal corresponding to the address 0x22 is the SPI write address signal, which is the 16-bit SPI write address signal that is actually written into the MOSI bus of the master-side SPI interface. The signal corresponding to the address 0x23 is the SPI write data signal, which is the 32-bit SPI write data signal that is actually written into the MOSI bus of the master-side SPI interface.

[0018] The data stream of the AXI4 protocol received by the converter from the connector is converted into interface data consisting of write enable, write address and write data, and output to the master side register. Since the data received by the converter is the data specified by the AXI4 protocol, its write logic includes a write address channel, a write data channel and a write reply channel. Therefore, according to the handshake criteria specified by the AXI4 protocol, when the converter is ready, the ready signals of the write address channel and the write data channel are sent to the connector respectively, indicating that the converter is ready. At this time, the write data valid signal and the write data signal, as well as the write address valid signal and the write address signal sent by the connector are received, and the write reply ready signal of the connector is waited for. When the write reply ready signal is captured, it indicates that the connector is ready, and the write reply valid signal and the write reply signal of the converter are sent to the connector. The write address and the write data are aligned and output at the same time, and the write enable is output at this time. At this time, the AXI4 protocol is converted into a simple interface consisting of a write enable signal, a write address signal and a write data signal, connected to the master side register, and it is output to the master side register.

[0019] In the write state, Define the SPI write enable register, including the SPI write enable address and its corresponding SPI write enable signal. The high and low levels of the SPI write enable signal indicate that the write enable is valid and invalid respectively. Define a read / write judgment register, including a read / write judgment address and its corresponding read / write judgment signal, the high and low levels of the read / write judgment signal represent the read state and the write state respectively; Define the SPI write address register, including the SPI write address and its corresponding SPI write address signal. The SPI write address signal is 16 bits, indicating that the maximum transmission bit width is 16 bits. Define the SPI write data register, including the address of the SPI write data and its corresponding SPI write data signal. The SPI write data signal is 32 bits, indicating that the maximum bit width of the data to be transmitted is 32 bits. According to the interface data composed of write enable, write data and write address obtained by the master side register, the read / write judgment signal is set to a low level, the write address is used as the SPI write address signal, the write data is used as the SPI write data signal, and the SPI write enable signal is set to a high level. Since the transmission of the read / write judgment signal, SPI write address signal and SPI write data signal specified in the SPI protocol is transmitted through the master-sender slave-receive MOSI bus, it is necessary to control the timing of SPI transmission to complete the transmission of address and data, that is, to complete the control of SPI logic by controlling the write enable signal, SPI read / write judgment bit, SPI write address signal and SPI write data signal in the master side register. First, in ARM, a low-level read / write judgment bit is sent to the address of the SPI read / write judgment signal, and then an SPI write address signal is sent to the SPI write address, and then an SPI write data signal is sent to the address of the SPI write data, and then a high-level SPI write enable signal is sent to the address of the SPI write enable, and finally a low-level SPI write enable signal is sent to the address of the SPI write enable. The above operation represents a complete process in which the master FPGA sends the write address and write data to the slave FPGA through the SPI protocol. The above operations reach the master-side register after passing through the connector and converter, and the master-side register directly outputs the SPI read / write judgment signal, SPI write address signal, SPI write data signal and write enable signal to the master-side SPI interface.

[0020] In the write state, when the SPI write enable signal is high, the working logic of the master side SPI interface is triggered: Set the SPI chip select signal to a low level, and at the unit clock cycle position of 10 system clocks, divide the connected system clock by 10 times. If the system clock is 100Mhz, the SPI clock is 10Mhz. Set the SPI clock and use the rising edge sampling of the SPI clock. Since it is necessary to transmit a 1-bit read / write judgment signal, a 16-bit SPI write address signal, and a 32-bit SPI write data signal to the slave-side FPGA, the transmitted SPI clock needs to last for 49 SPI unit clock cycles. At the unit clock cycle position of 5 system clocks of the SPI chip select signal, set the setup time and hold time of the collected data to 50%. Use the shift register method to send 49 bits of the read / write judgment signal, SPI write address signal, and SPI write data signal in sequence through the SPI MOSI bus. When the last 1-bit write data signal is sent, the chip select signal is set to a high level after the hold time is satisfied, completing the operation of the slave-side FPGA transmission of the write address and write data.

[0021] In the write state, the working logic of the slave SPI interface is: When the chip select signal is set to a low level, at the rising edge of the SPI clock, it is determined whether the received read / write judgment signal is at a low level. If so, the 16-bit SPI write address signal and 32-bit SPI write data signal received through the SPI MOSI bus are cached and transmitted to the slave register, and the write enable is output to the slave register. If the read / write judgment signal is not at a low level, no logical operation is performed.

[0022] In the slave register, the write address and write data are identified, and the write data is stored in the write address. In the slave register, the register signal to be used and its corresponding address are defined. This address and data correspond to the write instruction initiated by the ARM of the master FPGA, and correspond to the write address and write data transmitted in the slave SPI interface. When the write enable is high, the data corresponding to the address is identified and the data is stored in the data signal corresponding to the address.

[0023] like Figure 3 As shown, in the read state, the read address output by the ARM processor is obtained, and is converted into protocol data of the AXI4 protocol via the connector in sequence, converted into interface data consisting of a read enable and a read address via the converter, converted into predefined register data via the master side register, converted into serial data of the SPI protocol via the master side SPI interface, converted into predefined register data via the slave side SPI interface, the read enable and the read address are identified via the slave side register, and the read data corresponding to the read address is obtained; the read data is transmitted back to the ARM processor along the transmission path in reverse.

[0024] Reading status works similarly to writing status: In the direction of reading data from the master FPGA to the slave FPGA, the ARM processor writes the required read address to the connector and waits for the read data returned by the connector. This address and data correspond to the logic of the master register controlling the master SPI interface, which specifically involves the SPI read enable signal, SPI read / write judgment bit signal, SPI read address signal and SPI read data signal. The address of the above-mentioned specific master register needs to be written. Since the data format from the GP port of the ARM processor is AXI3, it needs to be converted from AXI3 to AXI4 through the connector.

[0025] The data of the AXI4 protocol received by the converter is converted into interface data consisting of a read enable and a read address. Since the data of the connector received by the converter is the data specified by the AXI4 protocol, and its read logic includes a read address channel and a read data channel, according to the handshake criteria specified by the AXI4 protocol, when the converter is ready, the read address channel's ready signal is sent to the connector, indicating that the converter is ready. Then the converter receives the read address valid signal and the read address signal sent by the connector. When the connector is ready to read data, it sends a ready signal to the converter and waits for the read data returned by the converter, but only when the read address passes through the complete data link, it is finally returned to the connector. The read address and its corresponding read enable are output at the same time, and the input read data and its corresponding read enable are waited for. At this time, the AXI4 protocol is converted into a simple interface connected to the master register, consisting of a read enable signal, a read address signal and a read data signal, and outputs it to the master register.

[0026] Define the SPI read / write judgment, read address and read enable in the master-side register, and send the corresponding signals to the master-side SPI module in sequence. Define the read enable register in the master-side register, the read enable signal corresponding to the read enable address, a high level indicates that the read enable is valid, and a low level indicates that the read enable is invalid; define the read / write judgment register, the read / write judgment signal corresponding to the read / write judgment address, a high level indicates a read state, and a low level indicates a write state; define the SPI read address register, the SPI read address signal, defined as 16 bits, indicating that the address with a maximum bit width of 16 bits can be transmitted; define the SPI read data register, the SPI read data signal, defined as 32 bits, indicating that the data with a maximum bit width of 32 bits can be transmitted. Since the read / write judgment signal and read address signal specified by the SPI protocol are transmitted through MOSI, and the transmission of the read data signal is transmitted through MISO, that is, it is necessary to complete the transmission of the address and data by operating the timing of SPI transmission, that is, by controlling the read enable signal, read / write judgment signal, and read address signal in the master side register to control the read address control of the SPI logic, and then complete the reading of the data of the corresponding address by receiving the read data signal returned by the master side SPI interface. First, in the ARM processor, a high-level read / write judgment bit is sent to the address of the read / write judgment signal, and then an SPI read address signal is sent to the SPI read address, and then a high-level SPI read enable signal is sent to the SPI read enable address, and finally a low-level SPI read enable signal is sent to the SPI read enable address, and then the read data signal returned by the master side SPI interface is waited, indicating a complete read data process. The above operations reach the master side register through the connector and the converter, and the master side register directly outputs the read / write judgment signal, the read address signal, and the read enable signal to the master side SPI module, and waits for the read data signal input by the master side SPI interface.

[0027] The read address received by the master SPI interface is used to convert the parallel data of the master register into the serial data of the SPI protocol, and then output to the SPI pins on the FPGA. When the SPI read enable signal is high, the logic of the master SPI interface is triggered. First, the SPI CS chip select signal is pulled low, and then the connected system clock is demultiplied at the unit clock cycle position of 10 system clocks, and the SPI clock is set, that is, the rising edge sampling of the clock is adopted. Since it is necessary to transmit a 1-bit read / write judgment signal and a 16-bit read address signal to the slave FPGA, a total of 17 bits, and it is also necessary to receive a 32-bit read data signal transmitted from the FPGA, and in the middle time slot between sending and receiving, the SPI clock needs to maintain a clock cycle of 1 unit of the SPI clock as the processing delay of the slave FPGA, so the transmitted SPI clock needs to last for 50 unit clock cycles of the SPI. Then, at the unit clock cycle position of 5 system clocks of the SPI chip select signal, set the setup time and hold time of the collected data to 50%, use the shift register method to receive the read and write judgment signal and the read address signal in turn, and receive 17 bits in turn through the SPI master-sender and slave-receiver MOSI signal. After waiting for a complete SPI clock cycle, receive the 32-bit read data transmitted vertically from the MISO of the slave FPGA. After the last 1-bit read data signal is received and the hold time is met, pull up the chip select signal, and the transmission operation of the read address and read data is completed.

[0028] In the slave side FPGA, the received SPI data is converted from SPI serial data to parallel data of the slave side register. When the chip select signal is pulled low, at the first rising edge of the SPI clock, it is first determined whether the received read / write determination signal is at a high level. If so, the serial 16-bit read address bit is cached at each rising edge of the next SPI clock, and the cached read address and the read enable indicating that the read address is valid are output to the slave side register at the same time, while waiting for the read data signal input from the slave side register; if not, no logical operation is performed.

[0029] In the slave register, the data corresponding to the read address is identified, and the read data is output to the slave SPI interface. In the slave register, the register signal to be used and its corresponding address are defined. This address and data correspond to the read instruction initiated by the ARM processor of the master FPGA, and correspond to the read address and read data transmitted in the slave SPI interface. When the read enable is high, the data corresponding to the address is identified, and the data is taken out, and the high level of the read data is output to the master SPI interface.

[0030] The data received by the master SPI interface is converted from parallel data to SPI serial data, and output to the SPI pin of the master FPGA. When the logic of the master SPI interface is carried out, the 17-bit read / write judgment signal and read address signal transmitted by the master FPGA through MOSI are received, and after waiting for a complete SPI clock cycle, the setup time and hold time of the collected data are set to 50%, and when the read enable is high at this time, the 32-bit read data is converted from high to low, from parallel data to serial data using the MSB method, and the read data is sent to the master FPGA through the master-receiver-slave-transmitter MISO bus.

[0031] On the master side FPGA, the data received by the master side SPI interface is converted from the serial data of the SPI protocol to the parallel data of the master side register, and then output to the master side register. When the logic of the master side SPI interface is carried out, 17 bits are output in sequence through the SPI master-sender and slave-receiver MOSI signals, and after waiting for a complete SPI clock cycle, the 32-bit serial read data transmitted from the MISO bus of the slave side FPGA is cached in the MSB mode. After the last 1-bit read data signal is received, and the chip select signal is pulled high after the hold time is met, the cached 32-bit parallel data and the read enable valid signal are transmitted to the master side register.

[0032] The read address and read enable received by the master register are converted into AXI4 protocol data and output to the converter. When the read data ready signal sent by the connector is high, the 32-bit parallel data received by the master register from the master SPI module and the read data valid signal are sent to the connector and finally to the ARM processor.

[0033] Embodiment 2:

[0034] Based on a method for half-duplex inter-chip SPI access to registers provided in Example 1, an embodiment of the present invention provides a system for half-duplex inter-chip SPI access to registers, which is used to perform read and write operations on a slave-side FPGA without an ARM processor through a master-side FPGA with an ARM processor, wherein the master-side FPGA includes an ARM processor, a connector, a converter, a master-side register, and a master-side SPI interface connected in sequence; the slave-side FPGA includes an interconnected slave-side SPI interface and a slave-side register; the system includes a write status execution module and / or a read status execution module; The write state execution module is used to obtain the write data and write address output by the ARM processor in the write state, convert them into protocol data of the AXI4 protocol via the connector, convert them into interface data consisting of write enable, write data and write address via the converter, convert them into predefined register data via the master side register, convert them into serial data of the SPI protocol via the master side SPI interface, convert them into predefined register data via the slave side SPI interface, identify the write enable, write address and write data via the slave side register, and store the write data in the write address; The read status execution module is used to obtain the read address output by the ARM processor in the read state, convert it into protocol data of the AXI4 protocol via the connector, convert it into interface data consisting of read enable and read address via the converter, convert it into predefined register data via the master side register, convert it into serial data of the SPI protocol via the master side SPI interface, convert it into predefined register data via the slave side SPI interface, identify the read enable and read address via the slave side register, and obtain the read data corresponding to the read address; and transmit the read data back to the ARM processor along the transmission path.

[0035] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0036] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0037] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0038] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0039] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for half-duplex inter-chip SPI access register, characterized in that: Used to perform read and write operations on a slave-side FPGA without an ARM processor through a master-side FPGA with an ARM processor, the master-side FPGA includes an ARM processor, a connector, a converter, a master-side register, and a master-side SPI interface connected in sequence; the slave-side FPGA includes an interconnected slave-side SPI interface and a slave-side register; the method includes a write state and / or a read state; In the write state, the write data and write address output by the ARM processor are obtained, and are converted into protocol data of the AXI4 protocol via the connector in sequence, and are converted into interface data consisting of write enable, write data and write address via the converter, and are converted into predefined register data via the master-side register, and are converted into serial data of the SPI protocol via the master-side SPI interface, and are converted into predefined register data via the slave-side SPI interface, and the write enable, write address and write data are identified via the slave-side register, and the write data is stored in the write address; In the read state, the read address output by the ARM processor is obtained, and is converted into protocol data of the AXI4 protocol via the connector, converted into interface data consisting of a read enable and a read address via the converter, converted into predefined register data via the master-side register, converted into serial data of the SPI protocol via the master-side SPI interface, converted into predefined register data via the slave-side SPI interface, and the read enable and the read address are identified via the slave-side register to obtain the read data corresponding to the read address; The read data is transmitted back to the ARM processor along the transmission path.

2. The method for half-duplex inter-chip SPI access register according to claim 1, characterized in that: In the write state, based on the handshake rule of the AXI4 protocol: when the converter is ready, the converter sends a ready signal of the write address channel and the write data channel to the connector, indicating that the converter is ready, and the connector sends the write address and write data to the converter; When the connector is ready, the connector sends a ready signal of the write reply channel to the converter, indicating that the connector is ready. At this time, the converter sends the write reply data to the connector; According to the protocol data of the AXI4 protocol obtained by the converter, the write address and the write data are aligned at the same time and sent to the master side register, and the write enable is sent to the master side register at the same time.

3. The method for half-duplex inter-chip SPI access register according to claim 1, characterized in that: In write state, Define the SPI write enable register, including the SPI write enable address and its corresponding SPI write enable signal. The high and low levels of the SPI write enable signal indicate whether the write enable is valid or invalid. Define a read / write judgment register, including a read / write judgment address and its corresponding read / write judgment signal. The high and low levels of the read / write judgment signal represent the read state and the write state respectively. Define the SPI write address register, including the SPI write address and its corresponding SPI write address signal. The SPI write address signal is 16 bits, indicating that the maximum transmission bit width is 16 bits. Define the SPI write data register, including the address of the SPI write data and its corresponding SPI write data signal. The SPI write data signal is 32 bits, indicating that the maximum bit width of the data to be transmitted is 32 bits. According to the interface data consisting of write enable, write data and write address obtained by the master side register, the read / write judgment signal is set to a low level, the write address is used as the SPI write address signal, the write data is used as the SPI write data signal, and the SPI write enable signal is set to a high level.

4. The method for half-duplex inter-chip SPI access register according to claim 3, characterized in that: In the write state, when the SPI write enable signal is high, the working logic of the master side SPI interface is triggered: Set the SPI chip select signal to a low level, and at the unit clock cycle position of 10 system clocks, demultiply the connected system clock by 10 times, set the SPI clock, and use the rising edge sampling of the SPI clock. Since it is necessary to transmit a 1-bit read / write judgment signal, a 16-bit SPI write address signal, and a 32-bit SPI write data signal to the slave-side FPGA, the transmitted SPI clock needs to last for 49 SPI unit clock cycles; At the position of the unit clock cycle of 5 system clocks of the SPI chip select signal, set the setup time and hold time of the collected data to 50%, and use the shift register method to send 49 bits of read and write judgment signal, SPI write address signal, and SPI write data signal in sequence through the SPI MOSI bus. When the last 1 bit of write data signal is sent, the chip select signal is set to a high level after the hold time is met, completing the operation of slave-side FPGA transmission of write address and write data.

5. The method for half-duplex inter-chip SPI access register according to claim 3, characterized in that: In the write state, the working logic of the slave SPI interface is: When the chip select signal is set to a low level, at the rising edge of the SPI clock, it is determined whether the received read / write determination signal is a low level. If so, the 16-bit SPI write address signal and the 32-bit SPI write data signal received through the SPI MOSI bus are cached and transmitted to the slave side register, and the write enable is output to the slave side register.

6. A half-duplex inter-chip SPI access register system, characterized in that: Used to perform read and write operations on a slave-side FPGA without an ARM processor through a master-side FPGA with an ARM processor, the master-side FPGA includes an ARM processor, a connector, a converter, a master-side register, and a master-side SPI interface connected in sequence; the slave-side FPGA includes an interconnected slave-side SPI interface and a slave-side register; the system includes a write status execution module and / or a read status execution module; The write state execution module is used to obtain the write data and write address output by the ARM processor in the write state, convert them into protocol data of the AXI4 protocol via the connector in sequence, convert them into interface data consisting of write enable, write data and write address via the converter, convert them into predefined register data via the master side register, convert them into serial data of the SPI protocol via the master side SPI interface, convert them into predefined register data via the slave side SPI interface, identify the write enable, write address and write data via the slave side register, and store the write data in the write address; The read state execution module is used to obtain the read address output by the ARM processor in the read state, convert it into protocol data of the AXI4 protocol via the connector, convert it into interface data consisting of a read enable and a read address via the converter, convert it into predefined register data via the master side register, convert it into serial data of the SPI protocol via the master side SPI interface, convert it into predefined register data via the slave side SPI interface, identify the read enable and the read address via the slave side register, and obtain the read data corresponding to the read address; The read data is transmitted back to the ARM processor along the transmission path.

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