In-memory computing circuit of lightning type digital / analog mixed domain
By adopting a lightning-type digital/analog hybrid domain design in the in-memory computing circuit, using a compact double word line SRAM array and a multi-period adder tree, combined with high-digit and low-bit analog unit processing, the in-memory computing circuit is solved in the neural network. The balance of energy efficiency and accuracy in calculations achieves efficient computing performance.
Patent Information
- Application Number
- CN202411179814.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2024-12-17
AI Technical Summary
When handling computing intensive tasks such as neural networks, existing in-memory computing circuits face challenges such as "memory wall" and "power wall". Digital domain computing has power consumption and area overhead, and analog domain computing requires high-precision ADC and DAC. Delay and power consumption increase, time domain calculation is greatly affected by process and temperature, and hybrid domain design is difficult to balance accuracy and energy overhead.
Design a lightning-type digital/analog hybrid domain in-memory computing circuit, using a 512×128-bit compact double word line SRAM array, input buffer, word line driver, write IO circuit, analog quantization circuit and multi-period adder Trees, through high-digit digital cells and low-digit analog cells separation processing, reduce adder tree size and power consumption, and design analog quantization circuits in the analog domain to reduce errors.
It realizes calculations that maintain high energy efficiency and inference accuracy under various cumulative lengths. It is less affected by process, voltage, and temperature, and has a fast calculation speed. It can handle visual Transformer and large CNN models. It supports INT8MAC operations of cumulative lengths from 128 to 2048, and access The time is 4.1ns.
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Figure CN119149483A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a lightning-type digital / analog hybrid domain in-memory computing circuit. Background Art
[0002] The rapid development of artificial intelligence (AI) has attracted widespread attention around the world, and various influential advances, such as the emergence of large language models such as ChatGPT and the application of convolutional neural networks such as ResNet and Yolo, have demonstrated its huge potential applications. However, the main obstacle lies in the huge computing power required. Current AI chip designs mainly follow the traditional von Neumann architecture, which encounters challenges such as "memory wall" or "power wall" when dealing with computationally intensive tasks such as neural networks. This is due to the frequent and large amount of data transfer between the processor and the memory through a bandwidth-limited bus, which severely limits the energy efficiency of such chips. To address this bottleneck, academia and industry have proposed a new computing architecture: the Computing-in-Memory (CIM) architecture. CIM not only retains the inherent storage and read / write access functions of the memory, but also facilitates various logical or matrix multiplication and addition operations. This design significantly reduces the frequent interactions between the processor and the memory and the large amount of intermediate data transfer, thereby further improving the performance of the circuit.
[0003] In-memory computing can be implemented using a variety of memory technologies, including non-volatile memories such as MRAM, RRAM, and flash memory, and volatile memories such as SRAM and DRAM. Given the advantages of static random access memory (SRAM) with fast access speed, mature manufacturing process, low static power consumption, and high durability, it is currently the most reliable choice for CIM implementation. At present, in-memory computing based on SRAM can be divided into three types according to the calculation method: analog domain, digital domain, and time domain.
[0004] Digital domain computing mainly relies on digital logic for operations, and has high computing precision and accuracy. However, the adders used in the accumulation process will cause significant power consumption and area overhead. Digital logic calculations can only achieve single-bit multiplication or addition in one operation, so high-parallel computing requires more logic circuits and connections, resulting in complex layout routing and increased area overhead. In addition, the layout design of the adder tree usually presents an inverted triangle structure, and the blank areas on both sides are often difficult to be effectively utilized, resulting in additional area waste. This design limitation makes digital domain computing face challenges in the pursuit of high-efficiency and high-density integrated circuit design. Therefore, how to optimize power consumption and area utilization while ensuring calculation accuracy has become an important issue that needs to be solved in the field of digital domain computing.
[0005] Analog domain computing converts input data and stored weights from the digital domain into analog signals such as voltage or current for processing, and then quantizes the results back to the digital domain after the calculation is completed. With the improvement of in-memory computing accuracy, the signal margin of analog signals is further compressed due to the upper limit of the circuit operating voltage, which places extremely high demands on the accuracy of analog-to-digital converters (ADC) and digital-to-analog converters (DAC). However, high-precision ADCs and DACs will bring significant delays and power consumption overheads, thereby reducing the computing power-to-energy ratio of the circuit. Therefore, in analog domain in-memory computing, there is an obvious mutual constraint between high precision and high computing power-to-energy ratio.
[0006] The mainstream solution for time domain computing usually uses an inverter chain to achieve delay, and the input and weight values control the length of the delay, which is quantized into a digital result through a time-to-digital converter (TDC). Time domain computing characterizes the calculation results by the length of the delay, breaking through the limitation of the working voltage on the calculation accuracy in the analog domain. However, time domain in-memory calculations are greatly affected by process, voltage, and temperature (PVT), and the linearity and matching of the delay unit will affect the correct quantization of TDC. In addition, TDC has a large area overhead and has high requirements for the frequency and stability of the reference clock. In order to reduce the impact of on-chip clocks, some TDC designs introduce internal delay chains or phase-locked loops, which further increase the area and power consumption.
[0007] Mixed-domain in-memory computing usually improves accuracy and energy efficiency by using digital logic for high-order bits and analog logic for low-order bits. However, mixed-domain modulus SRAM-CIM design faces the challenge of finding the best balance between inference accuracy and area / energy overhead. Summary of the invention
[0008] The present invention provides a lightning-type in-memory computing circuit in a digital / analog hybrid domain. The in-memory computing circuit is less affected by process, voltage, and temperature, has a fast computing speed, and high accuracy. It breaks through the limitation that in-memory computing is difficult for visual Transformer and large CNN models to maintain high energy efficiency and reasoning accuracy under various accumulation lengths.
[0009] An embodiment of the present invention provides a lightning-type digital / analog hybrid domain in-memory computing circuit, comprising:
[0010] 512×128-bit compact dual-wordline SRAM array, input buffer, wordline driver, write IO circuit, analog quantization circuit, multi-cycle adder tree and control circuit;
[0011] Among them, the external input data and weight data are written into the storage and calculation circuit through the write IO circuit, and the input buffer is used to temporarily store and synchronize the external input data stream; the 512×128-bit compact double-word line SRAM array is used to store and calculate the weight data and the external input data passing through the input buffer, and the word line driver is responsible for controlling the word line voltage in the SRAM storage unit of the 512×128-bit compact double-word line SRAM array, so as to select a specific SRAM storage unit for data reading and writing or calculation operations; the weight data is stored in the SRAM storage unit array, and the weight data and the external input data are multiplied and partially summed and accumulated in the digital domain or analog domain according to the position of the high-order calculation unit and the low-order calculation unit in the compact double-word line SRAM array in the structure, and the digital calculation part and result are accumulated through a multi-cycle adder tree, and the analog calculation part and result are quantized through an analog quantization circuit, so as to output the final result; the control circuit is used to coordinate and manage the timing and data flow of the entire in-memory calculation circuit.
[0012] Optionally, in one embodiment of the present invention, the compact double-word line SRAM array is composed of 4 banks, each bank includes 8 16×128-bit sub-arrays, and integrates 4 computing units: a high digital unit, a low digital unit, a high analog unit, and a low analog unit; the 4 computing units are each composed of their own local computing units, and each sub-array is combined with a computing unit to form 8 bit-by-bit multiplication and accumulation units; wherein two sub-arrays are respectively combined with the high digital unit and the low digital unit, and four sub-arrays are respectively combined with the high digital unit and the high analog unit. The remaining two sub-arrays are combined with the high analog unit and the low analog unit, the high-order calculation unit processes the high four-bit input, and the low-order calculation unit processes the low four-bit input, in the high-order calculation unit, the weight W[7:2] is calculated in the digital domain, and the weight W[1:0] is calculated in the analog domain; in the low-order calculation unit, the weight W[7:6] is calculated in the digital domain, and the weight W[5:0] is calculated in the analog domain, wherein the high-order calculation unit includes the high digital unit and the high analog unit, and the low-order calculation unit includes the low digital unit and the low analog unit.
[0013] Optionally, in one embodiment of the present invention, the memory cell array of the compact dual-word line SRAM includes multiple SRAM memory cells, local bit lines LBL, complementary local bit lines LBLB, global bit lines GBL, complementary global bit lines GBLB, lateral word lines HWL, NMOS tubes N1 and NMOS tubes N2, the weight storage nodes of the SRAM memory cells are all connected to the local bit lines LBL, and the complementary weight storage nodes of the SRAM memory cells are connected to the complementary local bit lines LBLB; the source of the NMOS tube N1 is connected to the local bit line LBL, the drain is connected to the global bit line GBL, and the gate is connected to the lateral word line HWL; the source of the NMOS tube N2 is connected to the complementary local bit line LBLB, the drain is connected to the complementary global bit line GBLB, and the gate is connected to the lateral word line HWL.
[0014] Optionally, in one embodiment of the present invention, the SRAM storage cell is a 6T-SRAM storage cell, and the 6T-SRAM storage cell includes transistor TP1, transistor TP2, transistor TN1, transistor TN2, transistor TN3 and transistor TN4; the specific connection method is as follows: the gate of transistor TP1 is respectively connected to the gate of transistor TN1, the drain of transistor TP2, the drain of transistor TN2 and the drain of transistor TN4; the gate of transistor TP2 is respectively connected to the gate of transistor TN2, the drain of transistor TP1, the drain of transistor TN1 and the drain of transistor TN3; the source of transistor TP1 and transistor TP2 are both connected to the power supply VDD; the gate of transistor TN3 and transistor TN4 are both connected to the word line, the source of transistor TN3 is connected to the input end of the inverter, and the source of transistor TN4 is connected to the bit line BLB; the source of transistor TN1 and transistor TN2 are both connected to the common end VSS, wherein transistor TP1 and transistor TP2 are PMOS transistors, and transistor TN1, transistor TN2, transistor TN3 and transistor TN4 are NMOS transistors.
[0015] Optionally, in one embodiment of the present invention, the high digital unit and the low digital unit for digital multiplication and partial sum accumulation are composed of 32 digital multiplication units and 1 partial sum adder tree group, and every four 16×1-bit 6T SRAM cell columns share one high digital unit or one low digital unit; the digital multiplication unit includes 4 NOR gates, which respectively correspond to four input data and weight data as inputs for NOR operations, and finally perform partial sum accumulation through the adder tree.
[0016] Optionally, in one embodiment of the present invention, the high analog unit and the low analog unit for analog multiplication and partial sum accumulation are composed of 128 analog multiplication units in parallel, each analog multiplication unit is composed of 2 PMOS tubes in series, and are respectively controlled by the weight value stored in the double word line 6T SRAM storage array and the input value transmitted by the global bit line.
[0017] Optionally, in one embodiment of the present invention, a multi-cycle accumulation operation formula for completing a 128-channel 3×3 convolution kernel is:
[0018]
[0019] Among them, m and t represent the valid bits of input and weight respectively, n and r represent the data position in an accumulation sequence and the position in the convolutional layer sequence;
[0020] Each operation distinguishes between high and low bits. The multi-cycle accumulation operation needs to go through four stages, each stage requires 9 cycles. The steps for implementing the multi-cycle accumulation operation are as follows: 1) Each channel completes the low-bit calculation unit processing in each cycle High-order computing unit processing 2) The 9 high-order and low-order parts generated by the operation in each stage are accumulated and added to generate a multi-cycle accumulation result of the high and low orders of 1-bit weight and 1-bit input with a cumulative length of 1152; 3) The results of step 2) are accumulated according to the weight to generate a multi-cycle accumulation result of the high and low orders of 8-bit weight and 1-bit input with a cumulative length of 1152; 4) The multi-cycle accumulation operation is repeated 4 times for iteration, and the final cumulative length of 1152 is generated after the accumulation and operation. The MAC result of 8-bit weight and 8-bit input.
[0021] Optionally, in one embodiment of the present invention, the computing circuit supports two different computing modes: fixed weight accumulation of small convolution layer and multi-cycle accumulation of large convolution layer; in the fixed weight accumulation mode of small convolution layer, the weight only needs to be loaded from the SRAM storage unit to the local bit line LBL and from the local bit line LBL to the weight data once in multiple cycles; in the multi-cycle accumulation mode of large convolution layer, the weight of each cycle will change, the local computing unit needs to be pre-charged in each cycle, and the weight data and the local bit line LBL are isolated.
[0022] The lightning-type digital / analog hybrid domain in-memory computing circuit of the embodiment of the present invention divides the digital domain part and the analog domain part in the compact double-word line SRAM memory calculation column into a lightning shape. The digital domain processing part reduces the internal bandwidth by compressing the adder tree, and further reduces the scale of the adder tree, thereby reducing the circuit area overhead and power consumption. At the same time, in order to further reduce power consumption, reduce PSUM storage overhead and alleviate the impact of error accumulation, the computing circuit designs an analog quantization circuit and a multi-channel accumulation circuit in the analog domain processing part. The present invention can realize INT8MAC operations with cumulative lengths of 128 to 2048, and the access time is 4.1ns at a voltage of 0.9V, which can realize ResNet 18 reasoning of ImageNet and Visual Transformer reasoning of ImageNet. The computing circuit of the present invention is less affected by process, voltage, and temperature, has fast computing speed and high accuracy, and overcomes the problem that in-memory computing is difficult to maintain high energy efficiency and reasoning accuracy at various cumulative lengths when processing visual Transformer and large CNN models.
[0023] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0025] Figure 1 A schematic diagram of a lightning-type digital / analog hybrid domain in-memory computing circuit structure provided according to an embodiment of the present invention;
[0026] Figure 2 A schematic diagram of the structure of a memory computing unit and its operating waveform in a lightning-type digital / analog hybrid domain memory computing circuit according to an embodiment of the present invention;
[0027] Figure 3 It is a structural schematic diagram of a digital computing unit in a lightning-type digital / analog hybrid domain in-memory computing circuit according to an embodiment of the present invention;
[0028] Figure 4 It is a schematic diagram of the structure of an analog computing unit in a lightning-type digital / analog hybrid domain in-memory computing circuit according to an embodiment of the present invention. DETAILED DESCRIPTION
[0029] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.
[0030] Figure 1 A schematic diagram of the structure of a lightning-type digital / analog hybrid in-memory computing circuit provided according to an embodiment of the present invention.
[0031] like Figure 1 As shown, the in-memory computing circuit of the lightning-type digital / analog hybrid domain includes a 512×128-bit compact double-wordline SRAM array, an input buffer, a wordline driver, a write IO circuit, an analog quantization circuit, a multi-cycle adder tree, and a control circuit;
[0032] Among them, external input data and weight data are written into the storage and calculation circuit through the write IO circuit, and the input buffer is used to temporarily store and synchronize the external input data stream; the 512×128-bit compact double-word line SRAM array is used to store and calculate the weight data and the external input data passing through the input buffer, and the word line driver is responsible for controlling the word line voltage in the SRAM storage unit of the 512×128-bit compact double-word line SRAM array, so as to select a specific SRAM storage unit for data reading and writing or calculation operations; the weight data is stored in the SRAM storage unit array, and the weight data and the external input data are multiplied and partially summed and accumulated in the digital domain or analog domain according to the position of the high-order calculation unit and the low-order calculation unit in the compact double-word line SRAM array in the structure, and the digital calculation part and result are accumulated through a multi-cycle adder tree, and the analog calculation part and result are quantized through an analog quantization circuit to output the final result; the control circuit is used to coordinate and manage the timing and data flow of the entire in-memory calculation circuit.
[0033] In an embodiment of the present invention, a compact double-word line SRAM array is composed of 4 banks, each bank includes 8 16×128-bit sub-arrays, and integrates 4 computing units: a high digital unit (HDU), a low digital unit (LDU), a high analog unit (HAU) and a low analog unit (LAU); the 4 computing units are each composed of their own local computing units (LCCs), and each sub-array is combined with a computing unit to form 8 bit-wise multiplication and accumulation units (Bit-wise MAC Units, BMAUs); among them, two sub-arrays are respectively combined with HDU and LDU, four sub-arrays are respectively combined with HDU and HAU, and the remaining two sub-arrays are combined with HAU and LAU. The high-order computing unit processes the high four-bit input, and the low-order computing unit processes the low four-bit input. In the high-order computing unit, the weight W[7:2] is calculated in the digital domain, and the weight W[1:0] is calculated in the analog domain; in the low-order computing unit, the weight W[7:6] is calculated in the digital domain, and the weight W[5:0] is calculated in the analog domain. The high-order computing unit includes a high digital unit and a high analog unit, and the low-order computing unit includes a low digital unit and a low analog unit.
[0034] like Figure 2As shown, the compact double word line SRAM memory cell array includes multiple SRAM memory cells, local bit lines LBL, complementary local bit lines LBLB, global bit lines GBL, complementary global bit lines GBLB, horizontal word lines HWL, NMOS tubes N1 and NMOS tubes N2. The weight storage nodes of the SRAM memory cells are all connected to the local bit lines LBL, and the complementary weight storage nodes of the SRAM memory cells are connected to the complementary local bit lines LBLB; the source of the NMOS tube N1 is connected to the LBL, the drain is connected to the global bit line GBL, and the gate is connected to the horizontal word line HWL; the source of the NMOS tube N2 is connected to the complementary local bit line LBLB, the drain is connected to the complementary global bit line GBLB, and the gate is connected to the horizontal word line HWL. In order to support two different computing modes of small convolution layer weight fixed accumulation WSA and large convolution layer multi-cycle accumulation MCA, to ensure that the local computing unit (LCC) has sufficient node voltage and avoid read interference problems, a precharge module is added to each 16×1-bit SRAM cell column, and a switch (SW) is set to isolate WDATA from the local bit line LBL.
[0035] The computing circuit of an embodiment of the present invention supports two different computing modes: Weight Stationary Accumulation (WSA) for small convolutional layers and Multi-cycle Accumulation (MCA) for large convolutional layers. In the WSA mode, the weight only needs to be loaded from the SRAM storage unit to the local bit line (LBL) and from the LBL to the weight data (WDATA) once in multiple cycles. Therefore, there is no need to switch WL, precharge, and isolate WDATA from LBL in each cycle, which will produce more stable data nodes and reduce power consumption. In the MCA mode, the weight of each cycle will change. Therefore, the local computing unit (LCC) needs to be precharged in each cycle to ensure that sufficient node voltage is reached and to avoid read interference problems, and WDATA and LBL also need to be isolated. Otherwise, the multiplication unit will receive data twice in one cycle: once from the bit unit and the other from the precharge, which may result in a large power overhead, which is particularly significant in the digital domain.
[0036] In an embodiment of the present invention, the SRAM storage cell is a 6T-SRAM storage cell, which includes a transistor TP1, a transistor TP2, a transistor TN1, a transistor TN2, a transistor TN3 and a transistor TN4; the specific connection mode is as follows: the gate of the transistor TP1 is respectively connected to the gate of the transistor TN1, the drain of the transistor TP2, the drain of the transistor TN2 and the drain of the transistor TN4; the gate of the transistor TP2 is respectively connected to the gate of the transistor TN2, the drain of the transistor TP1, the drain of the transistor TN1 and the drain of the transistor TN3; the source of the transistor TP1 and the transistor TP2 are both connected to the power supply VDD; the gate of the transistor TN3 and the transistor TN4 are both connected to the word line, the source of the transistor TN3 is connected to the input end of the inverter, and the source of the transistor TN4 is connected to the bit line BLB; the source of the transistor TN1 and the transistor TN2 are both connected to the common end VSS, wherein the transistor TP1 and the transistor TP2 are PMOS transistors, and the transistor TN1, the transistor TN2, the transistor TN3 and the transistor TN4 are NMOS transistors.
[0037] like Figure 3 As shown, in an embodiment of the present invention, the high digital unit and the low digital unit for digital multiplication and partial sum accumulation are composed of 32 digital multiplication units and 1 partial sum adder tree group, and every four 16×1-bit 6T SRAM cell columns share a high digital unit HDU or a low digital unit LDU; the digital multiplication unit includes 4 NOR gates, which respectively correspond to four input data and weight data as inputs for NOR operations, and finally perform partial sum accumulation through the adder tree.
[0038] like Figure 4 As shown, the high analog unit HAU and the low analog unit LAU for analog multiplication and partial sum accumulation are composed of 128 analog multiplication units in parallel, each analog multiplication unit is composed of 2 PMOS tubes in series, and are controlled by the weight value stored in the double word line 6TSRAM storage array and the input value transmitted by the global bit line (GBL / GBLB). Specifically, the double word line SRAM array is responsible for storing the weight value, and these weight values are transmitted to each analog multiplication unit through the global bit line, thereby realizing the multiplication and accumulation operations.
[0039] In an embodiment of the present invention, a multi-cycle accumulation (MCA) method is applied to the MAC operation of the visual Transformer and large CNN models. The MAC operation formula for completing a 128-channel 3×3 convolution kernel is m and t represent the valid bits of input and weight respectively, while n and r represent the data position in an accumulation sequence and the position in the convolutional layer sequence. Each operation distinguishes between high and low bits. The MAC operation needs to be completed in four stages, and each stage requires 9 cycles. The steps for implementing the MAC operation are as follows: 1) Each channel completes the low-bit calculation unit processing in each cycle The high-order computing unit processes 2) The 9 high-order and low-order partial sums (PSUM) generated by each stage operation are accumulated to generate the high-order and low-order MAC results of 1-bit weight and 1-bit input with a cumulative length of 1152. 3) The results of the previous step are accumulated by weight to generate the high-order and low-order MAC results of 8-bit weight and 1-bit input with a cumulative length of 1152. 4) This process is repeated 4 times, and the cumulative sum operation generates the final MAC result of 8-bit weight and 8-bit input with a cumulative length of 1152.
[0040] In an embodiment of the present invention, at the beginning of a calculation cycle, external input data passes through an input buffer and performs multiplication and partial sum accumulation operations in the digital domain or analog domain with weight data in 8 bit-by-bit multiplication and accumulation units. The partial sum results of digital calculations are accumulated through a multi-cycle adder tree, while the partial sum results of analog calculations are quantized through an analog quantization circuit, and the results are finally output. The invention can implement INT 8MAC operations with a length between 128 and 2048, with an access time of 4.1ns at a voltage of 0.9V, and can perform ResNet 18 reasoning on ImageNet and visual Transformer reasoning on ImageNet.
[0041] The lightning-type in-memory computing circuit of the digital / analog hybrid domain of the embodiment of the present invention supports two different computing modes: fixed accumulation of small convolutional layer weights and multi-cycle accumulation of large convolutional layer, and can implement INT8MAC operations with accumulation lengths of 128 to 2048. The present invention is less affected by process, voltage, and temperature, has fast computing speed, and high accuracy, and breaks through the limitation that in-memory computing is difficult to maintain high energy efficiency and reasoning accuracy for visual Transformer and large CNN models at various accumulation lengths.
[0042] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.
[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "N" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
Claims
1. A lightning-type digital / analog hybrid domain in-memory computing circuit, characterized in that: include: 512×128-bit compact dual-wordline SRAM array, input buffer, wordline driver, write IO circuit, analog quantization circuit, multi-cycle adder tree and control circuit; Among them, the external input data and weight data are written into the storage and calculation circuit through the write IO circuit, and the input buffer is used to temporarily store and synchronize the external input data stream; the 512×128-bit compact double-word line SRAM array is used to store and calculate the weight data and the external input data passing through the input buffer, and the word line driver is responsible for controlling the word line voltage in the SRAM storage unit of the 512×128-bit compact double-word line SRAM array, so as to select a specific SRAM storage unit for data reading and writing or calculation operations; the weight data is stored in the SRAM storage unit array, and the weight data and the external input data are multiplied and partially summed and accumulated in the digital domain or analog domain according to the position of the high-order calculation unit and the low-order calculation unit in the compact double-word line SRAM array in the structure, and the digital calculation part and result are accumulated through a multi-cycle adder tree, and the analog calculation part and result are quantized through an analog quantization circuit, so as to output the final result; the control circuit is used to coordinate and manage the timing and data flow of the entire in-memory calculation circuit.
2. The lightning-type digital / analog hybrid domain in-memory computing circuit according to claim 1, characterized in that: The compact double-word line SRAM array is composed of 4 banks, each bank includes 8 16×128-bit sub-arrays and integrates 4 computing units: a high digital unit, a low digital unit, a high analog unit and a low analog unit; the 4 computing units are each composed of their own local computing units, and each sub-array is combined with a computing unit to form 8 bit-by-bit multiplication and accumulation units; among them, two sub-arrays are respectively combined with the high digital unit and the low digital unit, four sub-arrays are respectively combined with the high digital unit and the high analog unit, and the remaining two sub-arrays are respectively combined with the high digital unit and the high analog unit. The column is combined with the high analog unit and the low analog unit, the high-order calculation unit processes the high four-bit input, and the low-order calculation unit processes the low four-bit input, in the high-order calculation unit, the weight W[7:2] is calculated in the digital domain, and the weight W[1:0] is calculated in the analog domain; in the low-order calculation unit, the weight W[7:6] is calculated in the digital domain, and the weight W[5:0] is calculated in the analog domain, wherein the high-order calculation unit includes the high digital unit and the high analog unit, and the low-order calculation unit includes the low digital unit and the low analog unit.
3. The lightning-type digital / analog hybrid domain in-memory computing circuit according to claim 1, characterized in that: The storage cell array of the compact double-word line SRAM includes multiple SRAM storage cells, local bit lines LBL, complementary local bit lines LBLB, global bit lines GBL, complementary global bit lines GBLB, lateral word lines HWL, NMOS tubes N1 and NMOS tubes N2. The weight storage nodes of the SRAM storage cells are all connected to the local bit lines LBL, and the complementary weight storage nodes of the SRAM storage cells are connected to the complementary local bit lines LBLB; the source of the NMOS tube N1 is connected to the local bit line LBL, the drain is connected to the global bit line GBL, and the gate is connected to the lateral word line HWL; the source of the NMOS tube N2 is connected to the complementary local bit line LBLB, the drain is connected to the complementary global bit line GBLB, and the gate is connected to the lateral word line HWL.
4. The lightning-type digital / analog hybrid domain in-memory computing circuit according to claim 3, characterized in that: The SRAM storage cell is a 6T-SRAM storage cell, and the 6T-SRAM storage cell includes a transistor TP1, a transistor TP2, a transistor TN1, a transistor TN2, a transistor TN3 and a transistor TN4; the specific connection mode is as follows: the gate of the transistor TP1 is connected to the gate of the transistor TN1, the drain of the transistor TP2, the drain of the transistor TN2 and the drain of the transistor TN4 respectively; The gate of transistor TP2 is connected to the gate of transistor TN2, the drain of transistor TP1, the drain of transistor TN1 and the drain of transistor TN3 respectively; The sources of transistor TP1 and transistor TP2 are both connected to the power supply VDD; The gates of transistor TN3 and transistor TN4 are both connected to the word line, the source of transistor TN3 is connected to the input end of the inverter, and the source of transistor TN4 is connected to the bit line BLB; the sources of transistor TN1 and transistor TN2 are both connected to the common end VSS, wherein transistor TP1 and transistor TP2 are PMOS transistors, and transistor TN1, transistor TN2, transistor TN3 and transistor TN4 are NMOS transistors.
5. The lightning-type digital / analog hybrid domain in-memory computing circuit according to claim 2, characterized in that: The high digital unit and the low digital unit for digital multiplication and partial sum accumulation are composed of 32 digital multiplication units and 1 partial sum adder tree group, and every four 16×1-bit 6T SRAM cell columns share one high digital unit or one low digital unit; the digital multiplication unit includes 4 NOR gates, which respectively correspond to four input data and weight data as inputs for NOR operations, and finally perform partial sum accumulation through the adder tree.
6. The lightning-type digital / analog hybrid domain in-memory computing circuit according to claim 2, characterized in that: The high analog unit and low analog unit of analog multiplication and partial sum accumulation are composed of 128 analog multiplication units in parallel, each analog multiplication unit is composed of 2 PMOS tubes in series, which are controlled by the weight value stored in the double word line 6T SRAM storage array and the input value transmitted by the global bit line.
7. The lightning-type digital / analog hybrid domain in-memory computing circuit according to claim 1, characterized in that: The multi-cycle accumulation formula for completing a 128-channel 3×3 convolution kernel is: Among them, m and t represent the valid bits of input and weight respectively, n and r represent the data position in an accumulation sequence and the position in the convolutional layer sequence; Each operation distinguishes between high and low bits. The multi-cycle accumulation operation needs to go through four stages, each stage requires 9 cycles. The steps for implementing the multi-cycle accumulation operation are as follows: 1) Each channel completes the low-bit calculation unit processing in each cycle High-order computing unit processing 2) The 9 high-order and low-order parts generated by the operation in each stage are accumulated and added to generate a multi-cycle accumulation result of the high and low orders of 1-bit weight and 1-bit input with a cumulative length of 1152; 3) The results of step 2) are accumulated according to the weight to generate a multi-cycle accumulation result of the high and low orders of 8-bit weight and 1-bit input with a cumulative length of 1152; 4) The multi-cycle accumulation operation is repeated 4 times for iteration, and the final cumulative length of 1152 is generated after the accumulation and operation. The MAC result of 8-bit weight and 8-bit input.
8. The lightning-type digital / analog hybrid domain in-memory computing circuit according to claim 3, characterized in that: The computing circuit supports two different computing modes: fixed weight accumulation of small convolution layer and multi-cycle accumulation of large convolution layer. In the fixed weight accumulation mode of small convolution layer, the weight only needs to be loaded from the SRAM storage unit to the local bit line LBL and from the local bit line LBL to the weight data once in multiple cycles. In the multi-cycle accumulation mode of large convolution layer, the weight of each cycle will change, the local computing unit needs to be precharged in each cycle, and the weight data and the local bit line LBL are isolated.