Chip layout recognition method, device, computer equipment and storage medium

Abstract

The present invention relates to a chip layout recognition method, device, computer equipment and storage medium, which include several steps to accurately identify the physical layout of a memory chip. First, multiple logical addresses are determined, and it is determined whether there are unrecognized addresses among these logical addresses. If so, one is selected as the target logical address. Then, the target logical address is repeatedly electrically stimulated, and an EMMI light radiation microscope is used to collect images to obtain a layout image of the target chip. Based on these images, the luminous position is captured and associated with the target logical address to obtain layout recognition information. This process is repeated until the recognition of all logical addresses is completed, and finally all recognition information is integrated to form a complete layout map of the chip to be tested. This method effectively overcomes the shortcomings of traditional methods in locating the physical position of the logical address by refining image processing and circuit path reconstruction.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a chip layout recognition method, device, computer equipment and storage medium. Background Art

[0002] In modern memory chips, especially DRAM-type memories, the structure inside the chip is complex and contains a large number of repeated storage cells. Each storage cell can be regarded as a logical address, and these addresses are equivalent to different storage areas in the warehouse in actual use. However, when a memory chip fails, we often need to query the specific location of these logical addresses on the physical layout of the chip in order to locate the problem. This is important for chip analysis, troubleshooting and performance optimization. But the reality is that these layout information belongs to the commercial secrets of chip manufacturers and is usually not disclosed to the public, making it impossible for outsiders to directly obtain the internal structure of the chip, thereby increasing the difficulty of maintenance and testing.

[0003] Although existing testing methods can identify whether an error has occurred in the memory, they cannot determine the specific physical location of the error. This lack of physical location information greatly increases the complexity of troubleshooting. Even when testing through external equipment such as PCBA test boards, only problems at the logical address level can be detected, and the actual location in the memory chip layout cannot be further located. Summary of the invention

[0004] The main purpose of the present invention is to provide a chip layout recognition method, device, computer equipment and storage medium to solve the technical problem that existing testing means cannot accurately locate the logical address error of the memory chip to its physical layout position.

[0005] To achieve the above-mentioned purpose, the present invention provides a method for chip layout recognition, comprising the following steps: determining multiple logical addresses of a chip to be tested; judging whether there is a logical address that has not been subjected to layout recognition among the multiple logical addresses, and if so, determining a logical address that has not been subjected to layout recognition as a target logical address; repeatedly power-on-stimulating the chip to be tested based on the target logical address, and simultaneously using an EMMI light radiation microscope lens to collect images of the chip to be tested to obtain a target chip layout image; capturing the light-emitting position of the chip to be tested based on the target chip version image, and associating the light-emitting position of the chip to be tested with the target logical address to obtain layout recognition information of the target logical address; continuing to execute the step of "judging whether there is a logical address that has not been subjected to layout recognition among the multiple logical addresses" until there is no logical address that has not been subjected to layout recognition, and integrating the version recognition information of the multiple target logical addresses into a layout map of the chip to be tested.

[0006] The present invention also provides a chip layout recognition device, comprising: a determination unit, used to determine multiple logical addresses of a chip to be tested; a judgment unit, used to judge whether there is a logical address that has not been subjected to layout recognition among the multiple logical addresses, and if so, determine a logical address that has not been subjected to layout recognition as a target logical address; a collection unit, used to repeatedly power-on stimulate the chip to be tested based on the target logical address, and simultaneously use an EMMI light radiation microscope lens to collect images of the chip to be tested to obtain a target chip layout image; an acquisition unit, used to capture the light-emitting position of the chip to be tested based on the target chip version image, and associate the light-emitting position of the chip to be tested with the target logical address to obtain layout recognition information of the target logical address; an execution unit, used to continue to execute the step of "determining whether there is a logical address that has not been subjected to layout recognition among the multiple logical addresses" until there is no logical address that has not been subjected to layout recognition, and then integrate the version recognition information of the multiple target logical addresses into a layout map of the chip to be tested.

[0007] The present invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above methods when executing the computer program.

[0008] The present invention also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of any of the above-mentioned methods are implemented.

[0009] The present invention provides a chip layout recognition method, device, computer equipment and storage medium, which have significant technical advantages in chip layout recognition. By adopting EMMI (Electro Magnetic Induced Emission) light radiation microscope technology, it can capture the weak luminescence phenomenon of the chip when it is electrically stimulated, and associate the logical address of the chip with the actual layout position. This method solves the technical bottleneck that traditional testing methods cannot accurately locate logical address errors to the physical layout, and provides a new technical path for chip fault analysis and performance optimization. Compared with the prior art, the present invention can efficiently and automatically identify the internal layout of the chip through repeated electrical stimulation and light emission position capture, greatly improving the accuracy and efficiency of layout recognition.

[0010] Secondly, in the process of logical address recognition, the present invention adopts a progressive logic judgment mechanism, that is, by judging whether there are unrecognized logical addresses, the target logical address is dynamically updated to ensure that each logical address can be accurately located in the physical layout. This mechanism not only improves the coverage of the recognition process, but also can accumulate more layout information in multiple recognition cycles, gradually generate a complete layout map, and thus provide a more comprehensive view of the physical structure of the chip.

[0011] In summary, the present invention significantly improves the automation level and recognition accuracy of chip layout recognition, effectively solves the problem of difficulty in locating chip logic address errors in the prior art, and has broad application prospects and huge technology promotion value. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a schematic diagram of the steps of a chip layout recognition method in one embodiment of the present invention;

[0013] Figure 2 It is a structural block diagram of a chip layout recognition device in one embodiment of the present invention;

[0014] Figure 3 It is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0015] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0017] Reference Figure 1 , this embodiment provides a method for chip layout recognition, comprising the following steps:

[0018] S1, determine multiple logical addresses of the chip to be tested.

[0019] S2, determining whether there is a logical address that has not been subjected to layout recognition among the multiple logical addresses, and if so, determining a logical address that has not been subjected to layout recognition as a target logical address.

[0020] S3, repeatedly power-on the chip to be tested based on the target logical address, and simultaneously use an EMMI light radiation microscope lens to collect images of the chip to be tested to obtain a layout image of the target chip.

[0021] S4, capturing the light-emitting position of the chip to be tested based on the target chip version image, and associating the light-emitting position of the chip to be tested with the target logical address to obtain layout identification information of the target logical address.

[0022] S5, continue to execute the step of "determining whether there are any logical addresses that have not been identified in the multiple logical addresses" until there are no logical addresses that have not been identified, and then integrate the version identification information of the multiple target logical addresses into the layout map of the chip to be tested.

[0023] That is, the implementation process of this technical solution mainly revolves around how to establish an association between the logical address and the physical layout of the chip, and uses advanced EMMI optical radiation microscopy technology to achieve accurate identification of the physical structure inside the chip. Its main goal is to solve the problem that the logical address and the actual layout position cannot be directly corresponded in memory chips, especially DRAM-type memories. This problem is particularly prominent when troubleshooting chip faults, because when a logical address fails, traditional methods can only detect the data error corresponding to the address, but cannot further determine the specific location of the error in the physical structure of the chip. To this end, the present invention proposes an effective layout recognition scheme, which enables testers to obtain the layout layout map of the chip through a series of systematic steps, so as to quickly and accurately locate the fault point.

[0024] First, by determining multiple logical addresses of the chip to be tested, the system can identify the addresses of each logical unit in the chip. Assume that in a DRAM memory chip, each storage unit corresponds to a logical address, and these addresses are distributed in different physical locations in the chip. In traditional methods, since the chip layout information is confidential to the manufacturer, testers usually cannot know the specific location of a logical address on the physical layout, resulting in low troubleshooting efficiency. The present invention gradually builds a layout map of the entire chip by identifying logical addresses one by one. When determining whether there are addresses that have not been identified in the layout among multiple logical addresses, the system will detect each address. If it is found that an address has not been identified, the system will determine it as the target logical address. This process is similar to checking different areas in a warehouse to find storage areas that have not been checked. Each unidentified logical address may correspond to a physical location, so identifying these logical addresses becomes a key step in building a layout map.

[0025] Subsequently, based on the target logical address, the system repeatedly powers on the chip to be tested. Power-on stimulation is a method of stimulating electronic activity inside a chip by applying voltage to the chip. The storage unit inside the chip will generate weak electromagnetic radiation when powered on, and these radiations are usually not captured by ordinary test equipment, so the present invention uses an EMMI light radiation microscope. This microscope can capture the luminescence phenomenon after the chip is powered on, thereby generating an image of the chip's physical layout. To better illustrate this point, an example can be given: assuming that a logical address "0x0001" in a DRAM memory chip fails, by repeatedly powering on the logical address, the EMMI microscope captures the luminescence phenomenon of a specific area of ​​the chip, which indicates that the actual position of the logical address "0x0001" on the chip's physical layout corresponds to the area. Through this method, testers can associate the logical address with the actual physical position, and then locate the fault point.

[0026] Next, based on the target chip version image, the system will further capture the luminous position of the chip to be tested. The EMMI optical radiation microscope can capture high-precision images of the chip's luminescence phenomenon and record the position of each luminous point. Since each power-on stimulation will cause the luminescence of the area corresponding to a specific logical address, the system can infer the position of the logical address in the physical layout based on the position of the luminous point in the image. This step is very important because it combines logical information with physical information, providing basic data for subsequent layout recognition. After that, the system will associate the captured luminous position with the target logical address. Association processing refers to the correspondence between the physical position information obtained through the EMMI microscope and the logical address information inside the chip. After each power-on stimulation, the system will capture the luminous position corresponding to different logical addresses. After repeated operations, the physical position of each logical address can be finally determined. Through this process, the system can generate layout recognition information for each logical address.

[0027] After completing the above steps, the system will continue to judge whether there are any logical addresses that have not been identified. If there are unidentified addresses, the system will repeat the above operations and continue to identify and process new target logical addresses. As more and more logical addresses are identified, the system gradually builds the physical layout of the entire chip. This process is similar to a jigsaw puzzle. By identifying different logical addresses one by one, the construction of the entire layout map is finally completed. When all logical addresses are identified, the system integrates the layout identification information of multiple target logical addresses to generate a layout map of the chip to be tested. This layout map is a complete description of the physical structure inside the chip. It corresponds all logical addresses to their corresponding physical locations one by one. This map can not only be used for fault location, but also provide important data support for chip design, optimization and performance analysis.

[0028] In summary, the present invention successfully solves the technical problem that traditional testing methods cannot accurately locate the logical address errors of memory chips to the physical layout position through a series of systematic steps. With the help of EMMI light radiation microscope and power-on stimulation method, the present invention realizes the association processing of logical addresses and physical layouts, and generates a complete chip layout map. This technical solution not only improves the efficiency of chip troubleshooting, but also has broad application prospects and can play an important role in chip design, testing and optimization.

[0029] In one example, the chip to be tested is repeatedly powered on based on the target logical address, and an EMMI optical radiation microscope lens is used to capture images of the chip to be tested to obtain a target chip layout image, including: obtaining a preset power-on voltage value corresponding to the target logical address, wherein the power-on voltage value corresponding to the target logical address is sufficient to trigger a physical response of the area corresponding to the target logical address; based on the preset power-on voltage value corresponding to the target logical address, constructing a power-on cycle corresponding to the target logical address, wherein the power-on cycle includes: power-on duration, power-on voltage value and power-off cooling time; based on the power-on cycle corresponding to the target logical address, the chip to be tested is powered on, and an EMMI optical radiation microscope lens is used to capture images of the chip to be tested to obtain a target chip layout image.

[0030] This example shows how to obtain the layout image of the target chip through repeated power-on stimulation and EMMI optical radiation microscopy technology, and provides effective operation steps for establishing the association between the logical address and the physical layout. In this process, the key step is to apply power-on stimulation to the target logical address and use the preset power-on voltage value to trigger the physical response of the area corresponding to the address, so as to determine the specific physical location of the logical address in the chip layout by observing the luminescence phenomenon inside the chip.

[0031] First, obtaining the preset power-on voltage value corresponding to the target logical address is the basis of this process. The relationship between the logical address and the physical layout is complex and cannot be directly observed. Therefore, it is necessary to control the power-on of the chip so that the current flows through the physical area corresponding to a specific logical address, thereby inducing a corresponding physical response. This physical response can be manifested as a thermal effect, an electric field effect, or even a weak light radiation. By selecting a suitable voltage value, the system can ensure that the physical area corresponding to the logical address is successfully activated and generates an observable signal. For example, if the area corresponding to the target logical address "0x001A" belongs to a cell in the memory, then the cell will flow current when powered on, causing local heating or other physical phenomena. In order to induce this response, the system sets the voltage value so that the material properties within the chip are sufficient to undergo observable changes.

[0032] Secondly, based on the preset power-on voltage value of the target logic address, the system constructs an accurate power-on cycle. The power-on cycle includes not only the voltage, but also parameters such as power-on duration and power-off cooling time. The power-on duration determines the length of time the current flows through the internal circuit of the chip, while the power-off cooling time allows the chip to return to its initial state after each power-on, avoiding physical property changes or damage caused by overheating or continuous power-on. For example, if the material properties of the area corresponding to the target logic address "0x001A" require luminescence under high voltage, the system can set the power-on duration to be long enough to ensure that the luminescence phenomenon is clearly visible. At the same time, the power-off cooling time is also very important, which allows the chip to have enough time to cool down and ensure that the results of the next power-on cycle are not interfered with by the previous experiment. Each logic address may require different power-on cycle parameters, because the materials, structures and current requirements of different areas of the chip are different, so the precise setting of the parameters is crucial.

[0033] Next, based on the set power-on cycle, the system performs power-on stimulation on the chip to be tested, and uses the EMMI light radiation microscope lens to collect images. In this process, the role of the EMMI light radiation microscope is particularly critical. The weak light radiation generated by the chip when it is powered on is usually invisible to the naked eye, and the EMMI microscope can convert it into a visual image by amplifying and capturing these tiny light signals. This image shows the physical response of the chip under specific power-on conditions, usually manifested as one or more luminous areas. For example, when the power-on stimulus is applied to the logical address "0x001A", the EMMI microscope may capture the light radiation of a tiny area in the chip, indicating that the physical location corresponding to the logical address has been successfully activated. Through repeated experiments, the system can determine the luminous behavior of each logical address at different voltages and durations, thereby gradually building a complete physical layout.

[0034] To further illustrate, a detailed example can be given. Assume that in a DRAM memory chip, the logical address "0x002B" corresponds to a specific storage unit in the chip. Through experiments, the system determined that the power-on voltage value of the logical address is 3.3V, the power-on duration is 5 milliseconds, and the power-off cooling time is 2 milliseconds. During this cycle, the EMMI microscope successfully captured the luminescence phenomenon in the logical address area, which shows that the voltage of 3.3V is sufficient to trigger the physical response of the area, and the power-on cycle with a duration of 5 milliseconds makes the luminescence phenomenon obvious enough. After each power-on, the system will wait for a cooling time of 2 milliseconds to ensure that the next power-on experiment will not be affected by the previous experiment. Through such a power-on cycle design, the system can accurately control the physical response behavior of the chip, thereby improving the quality of image acquisition.

[0035] Finally, through repeated power-on stimulation and EMMI image acquisition, the system can obtain a chip layout image corresponding to a target logical address. This image not only shows the actual location of the logical address in the physical layout of the chip, but also provides basic data for subsequent layout recognition. By integrating images of multiple logical addresses, the system can generate a physical layout of the entire chip. This layout map is of great significance for chip design, troubleshooting, and optimization because it provides a correspondence between the logical level and the physical level, allowing technicians to locate problems more quickly and make repairs or improvements.

[0036] In general, this example shows how to accurately obtain the layout information of the target chip through systematic power-on stimulation and EMMI optical radiation microscopy technology. This technical solution stimulates the physical area corresponding to the target logic address by setting the power-on voltage value and power-on cycle, and then captures the luminescence phenomenon through a microscope, combining the logic information with the physical layout information, solving the technical problem that traditional testing methods cannot accurately locate the logic address. Through this method, not only the efficiency of chip fault detection is improved, but also more intuitive data support is provided for chip design and optimization.

[0037] In one example, there are multiple target chip version images, and capturing the light-emitting position of the chip to be tested based on the target chip version images includes: performing image denoising processing on the multiple target chip layout images to obtain multiple first chip layout images; performing feature decomposition on each first chip version image respectively through a preset principal component splitting model to obtain a multi-layer feature image of each target chip layout image; performing multi-scale detail enhancement processing on the multi-layer feature images through a preset dark channel prior image enhancement model to obtain a multi-layer detail enhanced image of each target chip layout image; performing detail image fusion processing on the multi-layer detail enhanced images of the target chip layout image through a preset guided filtering fusion algorithm model to obtain a corresponding fused chip layout image; performing image decomposition processing on the fused chip layout image to obtain multiple target decomposition images, and performing sub-image superposition processing on the target decomposition image to obtain multiple target sub-images; inputting the multiple target sub-images into a preset chip layout recognition model for chip layout analysis processing to obtain the light-emitting position of the chip to be tested.

[0038] In this example, the layout image of the target chip is used to extract and analyze the light-emitting position of the chip under test. The process involves multiple steps to extract key information from multiple target chip layout images and process them in detail to obtain the physical location corresponding to each logical address. These steps include image denoising, feature decomposition, multi-scale detail enhancement, detail fusion, image disassembly, sub-image overlay, and layout analysis.

[0039] First of all, one of the basic steps is to perform image denoising on multiple target chip layout images. Chip layout images often contain noise, which may come from uneven light, equipment interference or image sensor limitations during the shooting process. The purpose of image denoising is to remove these unnecessary noises to make the image clearer and the details more accurate. This step usually smoothes the image by applying denoising algorithms such as Gaussian filtering, mean filtering or median filtering to reduce the impact of noise on subsequent processing. The denoised images are called multiple first chip layout images, which retain the main layout information but remove unnecessary interference.

[0040] Next, each first chip layout image is feature decomposed using a preset principal component splitting model. Principal component analysis (PCA) is a commonly used feature extraction technique that decomposes image data into a set of unrelated principal components, each of which corresponds to a feature layer in the image. Through feature decomposition, multi-layer feature images of each target chip layout image are obtained, which reflect the different structures and details in the chip layout. The hierarchical nature of the feature image helps to extract information at different levels inside the chip, such as the features of the circuit wiring layer and the component layer. Subsequently, the multi-layer feature image is subjected to multi-scale detail enhancement processing using a preset dark channel prior image enhancement model. Dark channel prior is an image enhancement method that enhances image details by analyzing the darkest area in the image. For chip layout images, this enhancement can significantly enhance the details, making tiny luminous areas and details more prominent. The purpose of this step is to make the details in the image more prominent and enhance the visual effect so that the luminous position can be more easily identified.

[0041] After detail enhancement, the pre-set guided filter fusion algorithm model is used to perform detail image fusion processing on the multi-layer detail enhanced images. The guided filter fusion algorithm removes redundant information and highlights key features by fusing multiple detail enhanced images. This fusion process can generate a comprehensive, clear fused chip layout image that retains all important details while reducing unnecessary noise and errors in the image. Next, the fused chip layout image is subjected to image disassembly processing. This process decomposes the image into several smaller target disassembly images. These disassembly images contain more detailed local area information, which is helpful for further analysis and processing. Each target disassembly image may represent a specific area of ​​the chip layout, which contains relevant information about the location of the light emission.

[0042] The purpose of superimposing sub-images on the target disassembly image is to integrate multiple local image information. This step is to synthesize a more comprehensive target sub-image by superimposing multiple target disassembly images together. These sub-images integrate information from different areas, which helps to obtain the overall image of the chip layout. Finally, multiple target sub-images are input into the preset chip layout recognition model for analysis and processing. The chip layout recognition model is a model based on deep learning or machine learning, which is used to analyze and identify features in the chip layout. Through model processing, the light-emitting positions of the chip can be extracted and associated with the target logical addresses. Finally, the light-emitting positions of the chip to be tested are obtained, which provides accurate data support for chip fault location and layout analysis.

[0043] For example, in actual applications, if the chip under test emits light at a specific logical address, the specific location of the light-emitting area can be clearly identified in the image through the above steps. In this way, through accurate image processing and analysis technology, the relationship between the logical address and the physical layout can be effectively mapped, thereby improving the efficiency and accuracy of chip fault detection.

[0044] In one example, the light-emitting position of the chip to be tested is associated with the target logical address to obtain layout identification information of the target logical address, including: converting the first coordinate value of the identified light-emitting position of the chip to be tested in the image coordinate system into a second coordinate value in the physical coordinate system of the chip to be tested; obtaining a pre-stored circuit diagram of the chip to be tested, and determining the circuit element of the light-emitting position on the chip to be tested in combination with the second coordinate value corresponding to the light-emitting position; and constructing the layout identification information of the target logical address based on at least the circuit element of the light-emitting position on the chip to be tested.

[0045] In this example, the goal is to associate the light-emitting position of the chip under test with the target logical address to obtain the layout recognition information of the target logical address. This process involves several key steps, converting the image data of the light-emitting position into the physical coordinate information of the chip, and combining this information with the circuit diagram to construct the layout recognition information of the target logical address. The following is a detailed explanation of each step:

[0046] First, the first coordinate value of the identified light-emitting position of the chip to be tested in the image coordinate system is converted to the second coordinate value in the physical coordinate system of the chip to be tested. This step is to convert the light-emitting point on the image from the image coordinate system (i.e., the pixel coordinate system of the image) to the actual position in the physical coordinate system of the chip. This conversion usually involves a coordinate transformation algorithm, such as an affine transformation or a perspective transformation, which needs to be adjusted according to the geometric characteristics of the image and the actual layout of the chip. The purpose of this step is to accurately map the light-emitting position on the image to the actual physical position of the chip for further analysis and processing.

[0047] Next, obtain the pre-stored circuit diagram of the chip to be tested, and determine the circuit element of the light-emitting position on the chip to be tested in combination with the second coordinate value corresponding to the light-emitting position. The circuit diagram is a detailed diagram of the chip design, which contains the layout information of all circuit elements and connections inside the chip. By combining the physical coordinates of the light-emitting position, the specific circuit element corresponding to the position can be found in the circuit diagram. For example, if the light-emitting position corresponds to a specific storage unit or logic gate on the chip, then it can be determined that the light-emitting position is associated with a specific element in the circuit diagram. The purpose of this step is to correspond the physical coordinates of the light-emitting position to the specific components in the chip circuit.

[0048] Finally, at least according to the circuit elements of the light-emitting position on the chip to be tested, the layout identification information of the target logical address is constructed. This step is to organize the circuit element information of the light-emitting position into layout identification information. This means that according to the type and position of the circuit element corresponding to the light-emitting position, a layout mapping information about the target logical address is generated. For example, if the light-emitting position corresponds to a storage unit, the specific position of the logical address in the chip layout can be determined. By performing similar processing on the light-emitting positions of multiple logical addresses, the layout identification information of the entire chip can be gradually constructed, and finally the physical layout diagram of the chip can be obtained.

[0049] For example, suppose that during the test process, the light-emitting position of the chip to be tested is identified as point (100, 150) in the image coordinate system. Through coordinate transformation, this image coordinate is converted to point (12, 30) in the chip physical coordinate system. According to the pre-stored circuit diagram of the chip, point (12, 30) may correspond to a storage unit on the chip, such as storage unit U23. It can be determined that the actual position of the target logical address X in the chip layout is associated with storage unit U23. In this way, the layout identification information of the target logical address X includes the physical position of its corresponding circuit element U23. Through such processing, the actual physical position of each logical address on the chip can be accurately identified and mapped, providing important data support for chip fault analysis and performance optimization.

[0050] In one example, the version identification information of multiple target logical addresses is integrated into a layout map of the chip to be tested, including: reconstructing the overall circuit path based on the circuit elements corresponding to the multiple target logical addresses to obtain the initial overall circuit path of the chip to be tested; identifying redundant connections in the initial overall circuit path of the chip to be tested, and identifying the target logical addresses to which the redundant connections belong; adjusting the circuit elements of the target logical addresses to which the redundant connections belong based on the redundant connections, and then superimposing the circuit elements corresponding to each target logical address one by one into the global layout to obtain the layout map of the chip to be tested.

[0051] In this example, the version identification information of multiple target logical addresses is integrated into a layout map of the chip to be tested. First, the overall circuit path reconstruction is performed based on the circuit elements corresponding to the multiple target logical addresses. The main purpose of this step is to use the circuit element information obtained from each target logical address to construct the initial overall circuit path of the chip. Specifically, for each target logical address, the position of the corresponding circuit element on the chip is known, and this information can be used to infer the electrical connection relationship between these circuit elements. This connection relationship is the circuit path. By integrating the information of all target logical addresses, the circuit path diagram of the entire chip is reconstructed, thereby obtaining the initial overall circuit path of the chip. This circuit path diagram provides basic data for subsequent layout integration.

[0052] Next, redundant connections in the initial overall circuit path are identified, and the target logical addresses to which these redundant connections belong are identified. The purpose of this step is to find redundant connections in the circuit path, that is, those unnecessary or repeated electrical connections, which may affect the actual layout and performance of the chip. By analyzing the circuit path diagram, it is identified which connections are redundant and which target logical addresses these redundant connections are associated with. This information is crucial for subsequent circuit adjustment processing because it helps us understand the specific locations and logical addresses that need to be modified in the circuit path. Then, based on the redundant connections, the circuit elements of the target logical addresses to which the redundant connections belong are adjusted. For the identified redundant connections, circuit adjustments need to be made to the target logical addresses involved to optimize the circuit path and reduce redundancy. This process may involve rearranging circuit elements, correcting the connection method, or removing unnecessary connections in the design. After adjustment, ensure that the circuit layout of each target logical address meets the actual design requirements of the chip and improve the accuracy and rationality of the overall circuit path.

[0053] Finally, the circuit elements corresponding to each target logical address are superimposed one by one on the global layout to obtain the layout map of the chip to be tested. The purpose of this step is to integrate the adjusted circuit element information into a unified layout. By superimposing the circuit element information of each target logical address on the global layout according to its actual position, a layout map of the entire chip is finally formed. This map shows the actual physical location and circuit layout of each logical address on the chip, and is a key tool for chip design and troubleshooting.

[0054] For example, suppose that during the test process, we obtained a preliminary layout diagram of the circuit elements through different logical addresses. After reconstructing the overall circuit path, we found that some connections were redundant, such as some signal lines were repeatedly connected to the same circuit element. We need to identify these redundant connections and adjust the relevant logical address circuit elements, such as removing duplicate connections or optimizing path design. After the adjustment is completed, the circuit elements of each target logical address are integrated into the global layout, and finally a detailed layout map of the chip to be tested is formed. This map not only shows the actual layout of the chip, but also helps identify potential design defects or optimization points, improving the reliability and performance of the chip.

[0055] In one example, the chip layout identification method also includes: in the event that the light-emitting position of the chip to be tested fails to be captured based on the target chip version image, determining that the target logical address is a failed logical address, and continuing to execute the step of "determining whether there are any logical addresses for which layout identification has not been performed among the multiple logical addresses" until there are no more logical addresses for which layout identification has not been performed.

[0056] That is, in the process of preliminary identification and determination of multiple logical addresses of the chip to be tested, if the light-emitting position of a certain logical address is not successfully captured during the test, then this logical address needs to be marked as a failed logical address. This step is particularly important for failure analysis because it identifies those logical addresses that behave abnormally during the layout recognition process, providing basic data for subsequent analysis. This marking not only helps researchers understand which parts of the chip have potential problems, but also provides direction for further troubleshooting.

[0057] The next step is to continue processing the logic addresses that have not been identified. The method ensures that all logic addresses have been identified by the layout by repeatedly executing the judgment steps, even if some logic addresses failed in the initial test. This iterative processing method ensures that the layout of the entire chip is fully covered, thereby improving the completeness and accuracy of the identification. In each test, the unidentified logic addresses need to be re-examined and processed in order to gradually build up the overall layout of the chip.

[0058] For example, suppose that during the test of a DRAM chip, the light-emitting positions of some logical addresses cannot be accurately captured due to the limitations of circuit characteristics or test conditions. At this time, these logical addresses will be marked as failed logical addresses. The method will continue to perform tests on other logical addresses to ensure that those logical addresses can be effectively identified. After all identifiable logical addresses are processed, the failed logical addresses are analyzed again. It may be necessary to adjust the test parameters or further optimize the test conditions to obtain accurate data.

[0059] The significance of this method is that, even in the absence of manufacturer support, it still provides an effective means to identify the layout of the chip, especially in dealing with failures and improving chip reliability. This method can not only improve the quality of the chip, but also play a role in the later maintenance and optimization of the chip. In this way, researchers and engineers can better understand the actual layout and potential problems of the chip, so as to develop targeted improvement measures.

[0060] In short, this chip layout recognition method ensures the integrity and accuracy of the entire layout recognition process by effectively processing the failed logic address. It provides a reliable technical approach for chip failure analysis and reliability improvement, allowing efficient chip maintenance and optimization even without original technical support.

[0061] In one example, after there are no more logical addresses that have not been subjected to layout identification, the chip layout identification method further includes: performing failure analysis processing on the chip to be tested based on the failed logical addresses to obtain reliability report data of the chip to be tested.

[0062] In this example, the core challenge of failure analysis based on failed logical addresses is that these logical addresses cannot be directly mapped to specific circuit elements in the chip. This means that during the layout recognition process, the light-emitting position cannot be captured for various reasons, resulting in the failure to successfully establish the mapping between the relevant logical addresses and the physical layout of the chip. Such problems may arise from a variety of complex factors, such as design anomalies, process defects, heat or voltage imbalances in the internal circuits of the chip. At this time, in order to conduct in-depth analysis of these failed logical addresses and ultimately generate a reliability report, a systematic failure analysis strategy needs to be adopted, combining analysis methods from multiple dimensions to handle them.

[0063] First, we can start with the electrical characteristics test, repeatedly stimulating these failed logic addresses through different voltage and current conditions to observe whether they exhibit abnormal electrical characteristics. Although the failed logic address has no clear physical circuit component association, it may still exhibit abnormal resistance, leakage current, or voltage response during the electrical test. These abnormal phenomena can become clues for further analysis and help narrow the scope of the problem. For example, if the failed logic address responds abnormally under certain specific voltages, this phenomenon can indicate possible circuit damage or current leakage points. By comparing the electrical response of the normal logic address, the abnormal performance of the failed logic address can be effectively distinguished.

[0064] Secondly, changes in environmental conditions can also provide more clues for failure analysis. For example, by controlling the operating temperature of the chip, simulating extreme environments such as high temperature, low temperature or humidity changes, and observing whether the performance of the failed logic address under these conditions will have further abnormalities. Generally, the electrical characteristics of the circuit will be different at different temperatures, and some failed logic addresses may show more significant abnormalities in specific environments. In this way, the reliability issues of the failed logic addresses can be further verified, and their association with certain process or physical defects can be preliminarily inferred.

[0065] Once these multi-dimensional tests and analyses are completed, the final failure analysis report will be summarized based on the performance and test results of different failed logic addresses. This report will not only contain the specific abnormal performance of the failed logic address, but also speculate and summarize the possible causes of each failed logic address, pointing out their possible failure mechanisms. For example, for some failed logic addresses, the report may point out that they exhibit significant current leakage at high temperatures, and the area shows signs of material degradation in SEM imaging, which is initially speculated to be material degradation caused by long-term thermal fatigue. This type of information can help chip designers or manufacturers make process improvements in future design and manufacturing processes, thereby improving the overall reliability of the chip.

[0066] Through these steps, although the failed logic address cannot be matched to a specific circuit element during the identification process, it can still be processed through failure analysis to obtain valuable reliability report data. This report not only helps to analyze potential problems of the chip, but also provides a basis for future improvements of the chip.

[0067] It should be noted that: for capturing the light emitting position of the chip to be tested based on the target chip version image, the embodiment of the present application provides a more detailed embodiment so that the technicians can better understand the technical solution, which is as follows:

[0068] In one example, image denoising is performed on a plurality of target chip layout images to obtain a plurality of denoised target chip layout images, including: calculating the degree values ​​of salt and pepper noise of the plurality of target chip layout images, and determining the size of a filter window according to the degree values ​​of the salt and pepper noise; sliding the filter window on the plurality of target chip layout images to determine a central pixel in the filter window and auxiliary pixels around the central pixel, and performing mean correction processing on the central pixel using the auxiliary pixels around the central pixel; and obtaining a plurality of target chip layout images processed by the filter window.

[0069] In this example, in order to improve the recognition accuracy and effect of the chip layout, multi-angle image acquisition is performed on the chip layout to be detected to obtain multiple initial chip layout images, and these images are denoised. The specific steps are as follows:

[0070] First, the salt and pepper noise degree values ​​in the multiple initial chip layout images are calculated. Salt and pepper noise is a common type of image noise, which appears as black and white dots in the image. These noises will affect the clarity and detail of the image. By analyzing the degree of salt and pepper noise in the image, the noise distribution and intensity in the image can be determined. According to the degree value of the salt and pepper noise, the size of the filter window is determined. The filter window is an area used for image denoising, and its size is adjusted according to the degree of noise. When the noise level is high, a larger filter window is required to cover more pixels for denoising; when the noise level is low, a smaller filter window can be used.

[0071] Next, the determined filter window is slid on multiple initial chip layout images. The sliding process of the filter window is to traverse each pixel in the image and determine the central pixel in the filter window and the auxiliary pixels around it at each position. The central pixel is the pixel at the center of the filter window, and the auxiliary pixels are the pixels around the central pixel. In order to remove noise, the central pixel is mean-corrected by using the auxiliary pixels around the central pixel. The specific method is to calculate the mean of the auxiliary pixels and then use this mean to replace the value of the central pixel, which can effectively smooth the salt and pepper noise in the image and retain more image detail information. Finally, multiple target chip layout images processed by the filter window are obtained. The images processed by this method not only have the noise effectively removed, but also retain more detail information, laying a good foundation for subsequent chip layout recognition.

[0072] This method of multi-angle image acquisition and image denoising effectively improves the accuracy and effect of image denoising through intelligent analysis of noise levels and adaptive adjustment of filter windows, ensures the quality of chip layout images, and provides clearer and more detailed image data for subsequent feature extraction and recognition.

[0073] In one example, a preset principal component splitting model is used to perform feature decomposition on each denoised target chip version image to obtain a multi-layer feature image of each target chip layout image, including: storing the target chip version image in a matrix form through a preset principal component splitting model to obtain an image matrix; performing mean calculation and standard deviation calculation on each pixel in the image matrix, and using the calculated mean and standard deviation to normalize the target chip version image to obtain an initial normalized image; compressing abnormal pixel values ​​in the initial normalized image to limit the abnormal pixel values ​​to a range of [-1, 1] to obtain a normalized target chip version. image; expanding the normalized target chip version image into a two-dimensional matrix, wherein each row in the two-dimensional matrix represents a pixel and each column represents a feature dimension; calculating the covariance matrix of the two-dimensional matrix, and performing feature analysis on the covariance matrix to obtain eigenvalues ​​and eigenvectors, wherein the eigenvalues ​​are the variances of the two-dimensional matrix, and the eigenvectors are the data directions of the two-dimensional matrix; selecting the first k eigenvectors with the largest features as the principal component space, and projecting the two-dimensional matrix into the principal component space to obtain the target data matrix after dimensionality reduction; reconstructing the target data matrix into an image form to obtain a multi-layer feature image of the target chip version image.

[0074] In this example, the target chip layout image is feature decomposed using a preset principal component splitting model to obtain a multi-layer feature image. The specific steps are as follows:

[0075] First, the target chip layout image is stored in a matrix form through the preset principal component splitting model to obtain an image matrix. Each element of the image matrix represents a pixel value in the image. For example, a 100x100 pixel image will be converted into a 100x100 matrix, and each matrix element represents the grayscale value or color value of a pixel. Next, the mean and standard deviation are calculated for each pixel value in the image matrix. The mean is the average value of all pixel values, and the standard deviation represents the degree of dispersion of these pixel values. The purpose of calculating the mean and standard deviation is to standardize the image data to make it more stable and consistent during the processing. The calculated mean and standard deviation are used to normalize the target chip layout image. The steps of normalization are: for each pixel value, subtract the mean and divide by the standard deviation. After this processing, all pixel values ​​will be concentrated in a smaller range, usually between [-1, 1]. The image obtained is called the initial normalized image.

[0076] Then, the abnormal pixel values ​​in the initial normalized image are compressed and limited to the range of [-1, 1]. This step ensures that all pixel values ​​are within a controllable range by truncating abnormal values ​​(usually extremely large or extremely small values), thereby reducing calculation errors and improving the stability of image processing. The result is a normalized target chip layout image. Next, the normalized target chip layout image is expanded into a two-dimensional matrix. In this two-dimensional matrix, each row represents a pixel and each column represents a feature dimension. For example, if the image size is 100x100, the expanded two-dimensional matrix will have 10,000 rows, each row representing the feature value of a pixel. Then, the covariance matrix of this two-dimensional matrix is ​​calculated. The covariance matrix is ​​used to describe the correlation between different feature dimensions. It is a square matrix, and each element of the matrix represents the covariance between two feature dimensions. By calculating the covariance matrix, we can understand the internal structure of the data and the relationship between the features.

[0077] Perform feature analysis on the covariance matrix to obtain eigenvalues ​​and eigenvectors. The eigenvalue indicates the variance of the covariance matrix, and the eigenvector indicates the main direction of data change. The result of feature analysis is that we can identify the most important feature direction in the data. After obtaining the eigenvalues ​​and eigenvectors, select the first k eigenvectors with the largest features as the principal component space. The principal component space is composed of these eigenvectors and represents the main direction and characteristics of data change. The purpose of selecting the first k eigenvectors is to retain the most important information in the data while reducing the dimension of the data, thereby simplifying the complexity of data processing. Then, the two-dimensional matrix is ​​projected into this principal component space to obtain the target data matrix after dimensionality reduction. The target data matrix after dimensionality reduction contains the most important feature information retained after principal component analysis, and removes redundant and unimportant information. Finally, the target data matrix after dimensionality reduction is reconstructed into an image form to obtain a multi-layer feature image of the target chip layout image. These multi-layer feature images contain key information in the chip layout and can be used for further image processing and recognition.

[0078] By using the above method, the target chip layout image is decomposed and processed to effectively extract key feature information from the image and improve the accuracy and efficiency of image recognition. This method combines advanced technologies of image preprocessing, feature extraction and data dimensionality reduction, providing powerful technical support for chip layout recognition.

[0079] In one example, the multi-layer feature image is subjected to multi-scale detail enhancement processing by a preset dark channel prior image enhancement model to obtain a multi-layer detail enhanced image of each target chip layout image, including: determining the resolution and detail features of the multi-layer feature image of the target chip layout image by a preset dark channel prior image enhancement model; generating a local dark channel processing window according to the resolution and the detail features, and using the local dark channel processing window to perform calculation processing on each pixel in the multi-layer feature image to obtain the dark channel value of the pixel, and using the dark channel value of each pixel to perform image combination to obtain the dark channel image of the target chip layout image; using a preset pyramid image decomposition model to perform multi-scale decomposition on the multi-layer feature image of the target chip layout image to obtain decomposed sub-images of different scales; using the dark channel image to adjust the weights of the decomposed sub-images of different scales to enhance the regional features with low dark channel values ​​to obtain the multi-layer detail enhanced image of the target chip layout image.

[0080] In this example, a multi-scale detail enhancement process is performed on the multi-layer feature image through a preset dark channel prior image enhancement model to obtain a multi-layer detail enhanced image of each target chip layout image. The specific steps are as follows: First, the resolution and detail features of the multi-level feature image of the target chip layout image are determined through a preset dark channel prior image enhancement model. Dark channel prior is an image enhancement technology that is usually used to improve the contrast and clarity of an image. In this method, we need to first determine the resolution and detail features of the image to provide a basis for subsequent processing steps. Next, a local dark channel processing window is generated based on the resolution and detail features. The local dark channel processing window is used to perform sliding calculations on the image to determine the dark channel value of each pixel. The dark channel value refers to the minimum value of each pixel of the image within the local window. Specifically, the calculation process of the dark channel value is as follows: First, within the local window, the minimum value of the three channels of R, G, and B for each pixel is selected. Secondly, among the selected minimum values, the minimum value within the entire window is selected as the dark channel value of the central pixel of the window.

[0081] In this way, the dark channel value of each pixel can be obtained, and these values ​​are combined to form a dark channel image of the target chip layout image. After that, the preset pyramid image decomposition model is used to perform multi-scale decomposition on the multi-level feature image of the target chip layout image to obtain decomposed sub-images of different scales. Pyramid image decomposition is a multi-scale image processing method. By decomposing the image at different resolutions, a series of images from low resolution to high resolution are obtained. These decomposed sub-images represent the feature information of the original image at different scales. Then, the dark channel image is used to adjust the weights of the decomposed sub-images of different scales. The dark channel value in the dark channel image can be used to guide the enhancement processing of the decomposed sub-image. The specific steps are as follows: First, for each pixel in each decomposed sub-image, the weight is adjusted according to its corresponding dark channel value. Areas with low dark channel values ​​usually correspond to details and edges in the image, and these areas need to be enhanced. Secondly, through weight adjustment, the characteristics of the areas with low dark channel values ​​are enhanced, so that these areas are more prominent in the final enhanced image.

[0082] Finally, the decomposed sub-images after weight adjustment are recombined to obtain a multi-layer detail enhanced image of the target chip layout image. The recombinant process synthesizes sub-images of different scales according to certain weights to form an enhanced image containing all scale detail features. This image not only retains the detail information of the original image, but also enhances the contrast and clarity of the image, making it more accurate and reliable in subsequent chip layout recognition. Through the above method, the target chip layout image is enhanced in detail using the dark channel prior image enhancement model and multi-scale image decomposition technology. This method not only improves the clarity and contrast of the image, but also retains and enhances key detail information, providing a better data foundation for subsequent image recognition processing.

[0083] In one example, a preset guided filtering fusion algorithm model is used to perform detail image fusion processing on multiple layers of detail enhanced images of the target chip layout image to obtain a corresponding fused chip layout image, including: selecting an image with the highest detail clarity and contrast from the multiple layers of detail enhanced images of the target chip layout image as a guide image; performing guided filtering processing on each detail enhanced image except the guide image through a preset guided filtering fusion algorithm model to obtain multiple initial guided filter sub-images; and performing weighted fusion processing on all the initial guided filter sub-images and the guide image to obtain the fused chip layout image.

[0084] In this example, the preset guided filter fusion algorithm model is used to perform detail image fusion processing on the multi-layer detail enhancement image of the target chip layout image to obtain the corresponding fused chip layout image. The specific steps are as follows:

[0085] First, the image with the highest detail clarity and contrast is selected from the multi-layer detail enhancement image of the target chip layout image as the guide image. This step is very critical because the guide image will play a reference and guiding role in the subsequent filtering and fusion processing. Select the image with the highest detail clarity and contrast to ensure that the most important detail information is retained and enhanced. Next, through the preset guided filtering fusion algorithm model, each detail enhancement image except the guide image is subjected to guided filtering processing to obtain multiple initial guided filtering sub-images. Guided filtering is a smoothing filtering method that maintains image edge details, usually by using the information in the guide image to guide the filtering process of other images. The specific steps are as follows: First, for each detail enhancement image, the pixel information of the guide image is used to calculate the weighted mean of each pixel and perform smoothing processing. Secondly, the guided filtering determines the filtering result by calculating the weighted relationship between each pixel in the input image and the corresponding pixel in the guide image. In this way, the key detail information in the guide image can be retained while smoothing other detail enhancement images.

[0086] Through the above processing, multiple initial guided filter sub-images are obtained. Each initial guided filter sub-image is smoothed while still maintaining the key details and edge information provided by the guide image. Then, all the initial guided filter sub-images and the guide image are weighted fused to obtain a fused chip layout image. The specific steps of the weighted fusion process are as follows: First, a weight is assigned to each initial guided filter sub-image and the guide image. The weight assignment can be determined based on the image's detail clarity, contrast, and other quality indicators. Secondly, all the initial guided filter sub-images and the guide image are weighted averaged according to the weights. This means that the pixel values ​​of each image will be weighted summed according to the weights to obtain the final fused pixel values.

[0087] Finally, a fused chip layout image is obtained through weighted fusion processing. The fused chip layout image combines the advantages of all detail-enhanced images, while retaining the key detail information in the guide image to the greatest extent, ensuring the overall clarity and contrast of the image. Through the above-mentioned guided filtering fusion algorithm model, the noise and unnecessary information in the detail-enhanced image are effectively removed, the key details are enhanced and retained, and finally a high-quality fused chip layout image is formed. This image has high clarity and contrast, which is suitable for subsequent chip layout recognition and analysis, and can greatly improve the accuracy and efficiency of recognition.

[0088] In one example, the fused chip layout image is subjected to image disassembly processing to obtain multiple target disassembly images, and the target disassembly image is subjected to sub-image superposition processing to obtain multiple target sub-images, including: splitting the fused chip layout image into multiple target disassembly images according to resolution and preset disassembly parameters; performing sub-image superposition processing on each target disassembly image, and determining the size of the overlapping area between each target disassembly image; determining the size proportion of the overlapping area to the total area of ​​the corresponding two target disassembly images, screening out target overlapping areas with a size proportion higher than a preset preset, and using a stitching algorithm to perform a fusion processing on the target overlapping areas; based on the fusion result, performing a stitching and superposition processing on the target disassembly images to obtain the target sub-images.

[0089] In this example, multiple target disassembly images are obtained by performing image disassembly processing on the fused chip layout image, and sub-image superposition processing is performed on these target disassembly images to generate multiple target sub-images. The specific steps are as follows:

[0090] First, the fused chip layout image is split into multiple target disassembly images according to the resolution and preset disassembly parameters. The disassembly parameters may include the size, resolution and segmentation method of the image. Through these parameters, the fused chip layout image is divided into several smaller image fragments, each of which is called a target disassembly image. The purpose of this step is to divide the large image into small pieces that are easy to process and analyze. Next, each target disassembly image is subjected to sub-image superposition processing. First, the size of the overlapping area between each target disassembly image needs to be determined. The overlapping area refers to the common part between two adjacent disassembly images, which appears in both images. By determining these overlapping areas, the continuity and consistency of the images can be guaranteed when stitching.

[0091] Then, determine the size ratio of the overlapping area to the total area of ​​the two corresponding target disassembly images. The purpose of this step is to evaluate the importance and proportion of the overlapping area in the two images. Overlapping areas with higher proportions usually contain more key information and details, so they need to be given priority in subsequent processing. Target overlapping areas with size ratios higher than the preset threshold are screened out, and these target overlapping areas are fused using a stitching algorithm. The stitching algorithm can use a variety of methods, such as weighted averaging, least squares method, etc., to ensure smooth transition and detail retention of the overlapping area. Through the fusion process, the overlapping areas of the two target disassembly images are seamlessly connected together, avoiding edge effects and faults during image stitching. Finally, based on the fusion results, the target disassembly images are stitched and superimposed to obtain the target sub-image. The stitching and superposition process forms a complete target sub-image by recombining all the processed target disassembly images in a certain order. In this process, ensure that the edges between each disassembly image are aligned and continuous, so that the final target sub-image maintains integrity and consistency.

[0092] Through the above steps, the fused chip layout image is disassembled and reassembled, which can effectively manage and process large image data and improve the accuracy and efficiency of image analysis and recognition. This method ensures the consistency of the image in details and overall, and provides a high-quality data foundation for subsequent chip layout recognition.

[0093] In one example, the multiple target sub-images are input into a preset chip layout recognition model for chip layout recognition processing to obtain recognition results of the chip layout to be detected, including: inputting the multiple target sub-images into a preset chip layout recognition model; performing convolution processing on the multiple target sub-images through the convolution kernel in each convolution layer in the preset chip layout recognition model to extract primary features of each target sub-image, and using a nonlinear activation function to introduce nonlinear features to the primary features to obtain convolution feature data of each target sub-image; performing linear changes and activation processing on the convolution feature data through multiple neurons in a fully connected layer in the preset chip layout recognition model to obtain an initial recognition result of each target sub-image; integrating the initial recognition results of each target sub-image, and outputting the recognition result of the chip layout to be detected.

[0094] In one example, multiple target sub-images are input into a preset chip layout recognition model for chip layout recognition processing to obtain a recognition result of the chip layout to be detected. The specific steps are as follows:

[0095] First, multiple target sub-images are input into a preset chip layout recognition model. This model is usually a deep learning model, such as a convolutional neural network (CNN), which has been trained to recognize and process feature information in the chip layout. Next, multiple target sub-images are convolved by the convolution kernel in each convolution layer in the preset chip layout recognition model. The convolution kernel is a small weight matrix that slides over the image and processes each part of the image to extract primary features. These primary features include information such as edges, textures, and simple shapes in the image. After the convolution process is completed, a nonlinear activation function is used to introduce nonlinear features to the primary features. Commonly used nonlinear activation functions include ReLU (Rectified Linear Unit), which sets negative input values ​​to zero and keeps positive values ​​unchanged. This step increases the expressiveness of the model, enabling it to handle more complex and nonlinear image features.

[0096] Then, the convolution feature data is linearly transformed and activated by multiple neurons in the fully connected layer in the model. The fully connected layer is an important part of the neural network, and each neuron is connected to all neurons in the previous layer. The fully connected layer linearly combines the input convolution feature data and processes it through the activation function to obtain the initial recognition results of each target sub-image. These initial recognition results contain a comprehensive judgment of different features in the image. Finally, the initial recognition results of each target sub-image are integrated. The integration process can be achieved through a variety of methods, such as weighted averaging, maximum pooling or other statistical methods. The purpose of this step is to combine the recognition results of multiple sub-images to form a complete recognition result. Finally, the recognition result of the chip layout to be tested is output. This recognition result contains a comprehensive analysis and judgment of the entire chip layout, and can effectively identify the key features and structures in the chip layout.

[0097] Through the above steps, using the deep learning model to process and identify multiple target sub-images can effectively extract and analyze the complex feature information in the chip layout, and improve the accuracy and efficiency of recognition. This method combines the advantages of convolution processing, nonlinear activation, fully connected layers and integrated processing, providing strong technical support for chip layout recognition.

[0098] Reference Figure 2 , an embodiment of the present invention provides a chip layout recognition device, comprising:

[0099] Determining unit 1, used to determine multiple logical addresses of the chip to be tested;

[0100] A judging unit 2, configured to judge whether there is a logical address that has not been subjected to layout recognition among the plurality of logical addresses, and if so, determine a logical address that has not been subjected to layout recognition as a target logical address;

[0101] An acquisition unit 3 is used to repeatedly power on the chip to be tested based on the target logical address, and simultaneously use an EMMI light radiation microscope lens to acquire an image of the chip to be tested to obtain a layout image of the target chip;

[0102] An acquisition unit 4 is used to capture the light-emitting position of the chip to be tested based on the target chip version image, and associate the light-emitting position of the chip to be tested with the target logical address to obtain layout identification information of the target logical address;

[0103] The execution unit 5 is used to continue to execute the step of "determining whether there are any logical addresses that have not been identified in the multiple logical addresses" until there are no logical addresses that have not been identified, and then integrate the version identification information of the multiple target logical addresses into the layout map of the chip to be tested.

[0104] In this embodiment, for the specific implementation of each unit in the above device embodiment, please refer to the above method embodiment, which will not be repeated here.

[0105] Reference Figure 3 In an embodiment of the present invention, a computer device is also provided. The computer device may be a server, and its internal structure may be as follows: Figure 3 As shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the processor designed by the computer is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0106] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0107] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0108] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0109] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0110] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for chip layout recognition, characterized in that: The following steps are involved: Determine multiple logical addresses of the chip to be tested; Determine whether there is a logical address that has not been subjected to layout recognition among the multiple logical addresses, and if so, determine a logical address that has not been subjected to layout recognition as a target logical address; Based on the target logical address, the chip to be tested is repeatedly electrically stimulated, and an EMMI light radiation microscope lens is used to collect images of the chip to be tested to obtain a target chip layout image; Based on the target logical address, the chip to be tested is repeatedly electrically stimulated, and an EMMI light radiation microscope lens is used to collect images of the chip to be tested to obtain a target chip layout image, including: obtaining a preset power-on voltage value corresponding to the target logical address, wherein the power-on voltage value corresponding to the target logical address is sufficient to trigger a physical response of the area corresponding to the target logical address; Based on the preset power-on voltage value corresponding to the target logical address, a power-on cycle corresponding to the target logical address is constructed, wherein the power-on cycle includes: power-on duration, power-on voltage value and power-off cooling time; Based on the power-on cycle corresponding to the target logical address, the chip to be tested is electrically stimulated, and an EMMI light radiation microscope lens is used to collect images of the chip to be tested to obtain a target chip layout image; Based on the target chip version image, the luminous position of the chip to be tested is captured, and the luminous position of the chip to be tested is associated with the target logical address to obtain the layout identification information of the target logical address; there are multiple target chip version images, and the luminous position of the chip to be tested is captured based on the target chip version image, including: performing image denoising on multiple target chip layout images to obtain multiple denoised target chip layout images; performing feature decomposition on each denoised target chip version image respectively through a preset principal component decomposition model to obtain a multi-layer feature image of each target chip layout image; performing multi-scale detail enhancement on the multi-layer feature images through a preset dark channel prior image enhancement model to obtain a multi-layer detail enhanced image of each target chip layout image; performing detail image fusion on the multi-layer detail enhanced images of the target chip layout image through a preset guided filtering fusion algorithm model to obtain Corresponding fused chip layout image; performing image disassembly processing on the fused chip layout image to obtain multiple target disassembly images, and performing sub-image superposition processing on the target disassembly image to obtain multiple target sub-images; inputting the multiple target sub-images into a preset chip layout recognition model for chip layout analysis processing to obtain the light-emitting position of the chip to be tested; associating the light-emitting position of the chip to be tested with the target logical address to obtain layout recognition information of the target logical address, including: converting the first coordinate value of the light-emitting position of the chip to be tested in the image coordinate system to a second coordinate value in the physical coordinate system of the chip to be tested; acquiring a pre-stored circuit diagram of the chip to be tested, and determining the circuit element of the light-emitting position on the chip to be tested in combination with the second coordinate value corresponding to the light-emitting position; constructing the layout recognition information of the target logical address at least according to the circuit element of the light-emitting position on the chip to be tested; Continue to execute the step of "determining whether there are any logical addresses that have not been subjected to layout identification among the multiple logical addresses" until there are no logical addresses that have not been subjected to layout identification, and then integrate the version identification information of the multiple target logical addresses into the layout layout map of the chip to be tested; integrate the version identification information of the multiple target logical addresses into the layout layout map of the chip to be tested, including: based on the circuit elements corresponding to the multiple target logical addresses, reconstructing the overall circuit path to obtain the initial overall circuit path of the chip to be tested; identifying redundant connections in the initial overall circuit path of the chip to be tested, and identifying the target logical address to which the redundant connection belongs; based on the redundant connection, adjusting the circuit elements of the target logical address to which the redundant connection belongs, and then superimposing the circuit elements corresponding to each target logical address one by one into the global layout to obtain the layout layout map of the chip to be tested.

2. The method for chip layout recognition according to claim 1, characterized in that: The chip layout recognition method further includes: In the event that the light-emitting position of the chip to be tested fails to be captured based on the target chip version image, the target logical address is determined to be a failed logical address, and the step of "determining whether there are logical addresses for which layout recognition has not been performed among the multiple logical addresses" is continued until there are no logical addresses for which layout recognition has not been performed.

3. The method for chip layout recognition according to claim 1, characterized in that: After there is no more logical address that has not been subjected to layout recognition, the chip layout recognition method further includes: Failure analysis processing is performed on the chip to be tested based on the failed logical address to obtain reliability report data of the chip to be tested.

4. A chip layout recognition device, characterized in that: include: A determination unit, used for determining a plurality of logic addresses of a chip to be tested; A judging unit, configured to judge whether there is a logic address that has not been subjected to layout recognition among the plurality of logic addresses, and if so, determine a logic address that has not been subjected to layout recognition as a target logical address; The acquisition unit is used to repeatedly power-on stimulate the chip to be tested based on the target logical address, and use the EMMI light radiation microscope lens to collect images of the chip to be tested to obtain a target chip layout image; the chip to be tested is repeatedly powered on based on the target logical address, and the image of the chip to be tested is collected using the EMMI light radiation microscope lens to obtain a target chip layout image, including: obtaining a preset power-on voltage value corresponding to the target logical address, wherein the power-on voltage value corresponding to the target logical address is sufficient to trigger a physical response of the area corresponding to the target logical address; based on the preset power-on voltage value corresponding to the target logical address, constructing a power-on cycle corresponding to the target logical address, wherein the power-on cycle includes: power-on duration, power-on voltage value and power-off cooling time; based on the power-on cycle corresponding to the target logical address, the chip to be tested is powered on, and the image of the chip to be tested is collected using the EMMI light radiation microscope lens to obtain a target chip layout image; An acquisition unit is used to capture the light-emitting position of the chip to be tested based on the target chip version image, and associate the light-emitting position of the chip to be tested with the target logical address to obtain layout identification information of the target logical address; there are multiple target chip version images, and capturing the light-emitting position of the chip to be tested based on the target chip version image includes: performing image denoising on multiple target chip layout images to obtain multiple denoised target chip layout images; performing feature decomposition on each denoised target chip version image respectively through a preset principal component decomposition model to obtain a multi-layer feature image of each target chip layout image; performing multi-scale detail enhancement on the multi-layer feature images through a preset dark channel prior image enhancement model to obtain a multi-layer detail enhanced image of each target chip layout image; performing detail image fusion on the multi-layer detail enhanced images of the target chip layout image through a preset guided filtering fusion algorithm model Processing to obtain a corresponding fused chip layout image; performing image disassembly processing on the fused chip layout image to obtain multiple target disassembly images, and performing sub-image superposition processing on the target disassembly image to obtain multiple target sub-images; inputting the multiple target sub-images into a preset chip layout recognition model for chip layout analysis processing to obtain the light-emitting position of the chip to be tested; associating the light-emitting position of the chip to be tested with the target logical address to obtain layout recognition information of the target logical address, including: converting the first coordinate value of the light-emitting position of the chip to be tested in the image coordinate system to a second coordinate value in the physical coordinate system of the chip to be tested; acquiring a pre-stored circuit diagram of the chip to be tested, and determining the circuit element of the light-emitting position on the chip to be tested in combination with the second coordinate value corresponding to the light-emitting position; constructing the layout recognition information of the target logical address at least according to the circuit element of the light-emitting position on the chip to be tested; An execution unit is used to continue to execute the step of "determining whether there are any logical addresses that have not been subjected to layout identification among the multiple logical addresses" until there are no logical addresses that have not been subjected to layout identification, and then integrate the version identification information of the multiple target logical addresses into the layout layout map of the chip to be tested; integrate the version identification information of the multiple target logical addresses into the layout layout map of the chip to be tested, including: based on the circuit elements corresponding to the multiple target logical addresses, reconstructing the overall circuit path to obtain the initial overall circuit path of the chip to be tested; identifying redundant connections in the initial overall circuit path of the chip to be tested, and identifying the target logical address to which the redundant connection belongs; adjusting the circuit elements of the target logical address to which the redundant connection belongs based on the redundant connection, and then superimposing the circuit elements corresponding to each target logical address one by one into the global layout to obtain the layout layout map of the chip to be tested.

5. A computer device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 3 are implemented.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

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