Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. Provided is a transistor that achieves both miniaturization and high reliability. One embodiment of the invention provides a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a transistor and a first insulating layer. The transistor includes first to third conductive layers, a semiconductor layer, and a second insulating layer. The first insulating layer includes a first layer and a second layer on the first layer. The first insulating layer is on the first conductive layer and includes a first opening to the first conductive layer. The second conductive layer is on the second layer. The semiconductor layer is in contact with the first conductive layer and the second conductive layer, and is in contact with a side surface of the first layer inside the first opening. The second insulating layer covers the semiconductor layer in the first opening, and the third conductive layer covers the second insulating layer in the first opening. The first insulating layer includes a second opening at a different position from the first opening. The second insulating layer is in contact with the first layer inside the second opening. The first layer includes an oxide insulating film, and the second layer includes an insulating film having oxygen barrier properties.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the same. One embodiment of the present invention relates to a transistor and a method for manufacturing the same. One embodiment of the present invention relates to a display device including a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices, input-output devices, driving methods of these devices, or manufacturing methods of these devices. Semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. Background Art

[0003] There is a demand for miniaturization of transistors. For example, in a display device, the smaller the area occupied by the transistor used for a pixel, the smaller the size of the pixel can be, so high definition can be achieved. In addition, the number of transistors that can be configured per unit area can be increased, so multiple transistors can be configured in a pixel without increasing the size of the pixel, and, for example, a correction function can be assembled in the pixel.

[0004] In recent years, the high definition of display panels has been promoted. As devices that require high-definition display panels, in addition to tablet terminals, smartphones, and watch-type terminals, for example, devices for virtual reality (VR) or augmented reality (AR) are also being actively developed. High-definition display panels mainly use light-emitting elements such as organic EL (Electro Luminescence) elements or light-emitting diodes (LEDs).

[0005] Patent Document 1 discloses a high-definition display device using an organic EL device (also referred to as an organic EL element).

[0006] [Patent Document 1] International Publication No. 2016 / 038508 Summary of the invention

[0007] Transistors are required to be miniaturized and highly reliable. In particular, when transistors are used in pixels of display devices, changes in the electrical characteristics of the transistors sometimes significantly affect the unevenness of the color and brightness of each pixel. In particular, in VR devices, there is a concern that such display defects may lead to a decrease in immersion.

[0008] One of the purposes of one embodiment of the present invention is to provide a transistor that can be miniaturized. One of the purposes of one embodiment of the present invention is to provide a semiconductor device that can configure transistors at a high density. One of the purposes of one embodiment of the present invention is to provide a transistor with good electrical characteristics. One of the purposes of one embodiment of the present invention is to provide a transistor that can allow a large current to flow. One of the purposes of one embodiment of the present invention is to provide a transistor with an extremely small channel length. One of the purposes of one embodiment of the present invention is to provide a transistor that occupies a small area. One of the purposes of one embodiment of the present invention is to provide a transistor that can achieve both miniaturization and high reliability. One of the purposes of one embodiment of the present invention is to provide a display device that can easily achieve high definition. One of the purposes of one embodiment of the present invention is to provide a transistor, semiconductor device or display device with high reliability.

[0009] One object of one embodiment of the present invention is to provide a semiconductor device, a display device, or an electronic device having a novel structure. One object of one embodiment of the present invention is to at least improve at least one of the problems of the prior art.

[0010] Note that the description of these objects does not prevent the existence of other objects. Note that one embodiment of the present invention does not necessarily achieve all of the above objects. Note that objects other than the above objects can be extracted from the description of the specification, drawings, and claims.

[0011] One embodiment of the present invention is a semiconductor device including a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer and a second insulating layer. The first insulating layer includes a first layer and a second layer on the first layer. The first insulating layer is located on the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is located on the second layer. The semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the second conductive layer, and a portion in contact with the side surface of the first layer inside the first opening. The second insulating layer covers the semiconductor layer in the first opening, and the third conductive layer covers the second insulating layer in the first opening. The first insulating layer includes a second opening at a position different from the first opening. The second insulating layer has a portion in contact with the first layer inside the second opening. The first layer includes an oxide insulating film, and the second layer includes an insulating film having oxygen barrier properties.

[0012] In addition, in the above, the second opening is preferably provided at a position not overlapping with the second conductive layer when viewed from a plane. In this case, the second opening preferably has a portion overlapping with the third conductive layer. In addition, the second opening preferably has a portion overlapping with the first conductive layer.

[0013] In any of the above, the second opening preferably passes through the second layer to reach the first layer. In this case, the first layer preferably has a recessed portion overlapping the second opening. Furthermore, the second insulating layer preferably contacts the surface of the recessed portion of the first layer inside the second opening.

[0014] In any of the above, the second opening preferably passes through the second layer and the first layer. Also, the second insulating layer preferably contacts the side surface of the first insulating layer inside the second opening.

[0015] In any of the above, the first insulating layer preferably includes a third layer located below the first layer. Also, the second opening preferably passes through the second layer and the first layer to reach the third layer.

[0016] In any of the above, the first insulating layer preferably includes a third layer located below the first layer. Also, the second opening preferably passes through the second layer, the first layer, and the third layer.

[0017] In the above, it is preferred that the first layer contains silicon oxide and the second layer contains silicon nitride or aluminum oxide.

[0018] In the above, the shortest distance between the first opening and the second opening when viewed from a plane is preferably 0.1 μm or more and 100 μm or less.

[0019] In addition, another embodiment of the present invention is a method for manufacturing a semiconductor device including the following steps. That is, a first layer and a second layer are formed on a first conductive layer, a second conductive layer is formed on a second layer, a first opening reaching the first conductive layer is formed in the first layer and the second layer, and a second opening is formed at a position away from the first opening, a semiconductor film covering the first opening and the second opening and in contact with each of the first conductive layer and the second conductive layer is formed, and then a heat treatment is performed, a portion of the semiconductor film is etched to expose the second opening, an insulating layer covering the semiconductor film and the second opening is formed, and a third conductive layer overlapping the semiconductor layer is formed on the insulating layer. Here, the first layer includes an oxide insulating film, and the second layer includes an insulating film having oxygen barrier properties.

[0020] According to one embodiment of the present invention, a transistor capable of miniaturization can be provided. According to one embodiment of the present invention, a semiconductor device capable of configuring transistors at a high density can be provided. According to one embodiment of the present invention, a transistor with good electrical characteristics can be provided. According to one embodiment of the present invention, a transistor capable of allowing a large current to flow can be provided. According to one embodiment of the present invention, a transistor with an extremely small channel length can be provided. According to one embodiment of the present invention, a transistor with a small occupied area can be provided. According to one embodiment of the present invention, a transistor capable of miniaturization and high reliability can be provided. According to one embodiment of the present invention, a display device capable of easily achieving high definition can be provided. According to one embodiment of the present invention, a transistor, semiconductor device or display device with high reliability can be provided.

[0021] According to one embodiment of the present invention, a semiconductor device, a display device, or an electronic device having a novel structure can be provided. According to one embodiment of the present invention, at least one of the problems of the prior art can be improved.

[0022] Note that the description of these effects does not prevent the existence of other effects. Note that one embodiment of the present invention does not necessarily need to have all of the above effects. Note that effects other than the above effects can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figures 1A to 1C It is an example of the structure of a semiconductor device;

[0024] Figure 2A and Figure 2B It is an example of the structure of a semiconductor device;

[0025] FIG. 3A to FIG. 3C It is an example of the structure of a semiconductor device;

[0026] FIG. 4A to FIG. 4C It is an example of the structure of a semiconductor device;

[0027] Figure 5A1 , Figure 5A2 , Figure 5B1 , Figure 5B2 , Fig.5C1 , Fig.5C2 , Fig.5D1 and Fig.5D2 It is an example of the structure of a semiconductor device;

[0028] Fig. 6A and Figure 6B It is an example of the structure of a semiconductor device;

[0029] 7A to 7C It is an example of the structure of a semiconductor device;

[0030] FIG. 8A to FIG. 8C It is an example of the structure of a semiconductor device;

[0031] 9A to 9C is a diagram illustrating a method for manufacturing a semiconductor device;

[0032] FIG. 10A to FIG. 10C is a diagram illustrating a method for manufacturing a semiconductor device;

[0033] Fig.11 It is an example of the structure of the display device;

[0034] Fig.12 It is an example of the structure of the display device;

[0035] Fig.13 It is an example of the structure of the display device;

[0036] Fig.14 It is an example of the structure of the display device;

[0037] Fig.15 It is an example of the structure of the display device;

[0038] FIG. 16A to FIG. 16F is a diagram illustrating a method for manufacturing a display device;

[0039] 17A to 17D It is an example of the structure of an electronic device;

[0040] FIG. 18A to FIG. 18F It is an example of the structure of an electronic device;

[0041] FIG. 19A to FIG. 19G It is an example of the structure of an electronic device;

[0042] Fig. 20A is an optical microscope image, Fig. 20B is a cross-sectional STEM image;

[0043] Fig.21 It is the measurement result of the electrical characteristics of the transistor. DETAILED DESCRIPTION

[0044] The following describes the embodiments with reference to the accompanying drawings. However, a person skilled in the art can easily understand that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the following embodiments.

[0045] Note that in the structure of the invention described below, the same symbols are used in common between different drawings to show the same parts or parts with the same function, and their repeated descriptions are omitted. In addition, when showing parts with the same function, the same hatching is sometimes used without special additional symbols.

[0046] Note that in each of the drawings described in this specification, the size of each component, the thickness of a layer, or a region may be exaggerated for clarity, and therefore, the present invention is not limited to the sizes in the drawings.

[0047] The ordinal numbers such as “first” and “second” used in the present specification and the like are provided to avoid confusion among constituent elements and are not intended to limit the number of constituent elements.

[0048] In addition, the functions of "source" and "drain" may be interchanged when transistors with different polarities are used or when the current direction of the circuit operation changes. Therefore, in this specification, "source" and "drain" may be interchanged.

[0049] In addition, in this specification, "electrical connection" includes connection through "an element having some kind of electrical function". Here, "an element having some kind of electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. For example, as an "element having some kind of electrical function", in addition to electrodes and wiring, it also includes switching elements such as transistors, resistor elements, coils, and other elements having various functions.

[0050] In this specification, etc., "the top surface shapes are substantially consistent" means that at least a portion of the contours of each layer in the stack overlap. For example, this includes the case where the upper layer and the lower layer are processed by using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, there are cases where the contours do not overlap and the upper layer is located inside the lower layer or the upper layer is located outside the lower layer. In this case, it can sometimes be said that "the top surface shapes are substantially consistent."

[0051] Note that in this specification, etc., the top surface shape of a certain component refers to the outline shape of the component when viewed from a plane. In addition, the plane view refers to the situation when viewed from the normal direction of the surface on which the component is formed or the surface of the support body (e.g., substrate) on which the component is formed.

[0052] Note that, in the following, the directions such as "upper" and "lower" are basically used in accordance with the directions of the drawings. However, for the sake of simplicity, the directions shown as "upper" or "lower" in the specification are sometimes inconsistent with the drawings. As an example, in the case of describing the stacking order (or formation order) of a laminate, etc., even if a surface (a formed surface, a supporting surface, an adhesive surface, a flat surface, etc.) on one side of the laminate is located on the upper side of the laminate in the drawings, there are cases where the formed surface side is indicated as lower and the laminate side is indicated as upper.

[0053] In this specification, "film" and "layer" may be interchanged. For example, "insulating layer" may be replaced with "insulating film".

[0054] In this specification, etc., a display panel which is one form of a display device refers to a panel which can display (output) an image etc. on a display surface. Therefore, a display panel is one form of an output device.

[0055] In this specification, etc., a structure in which a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) is installed on a display panel substrate, or a structure in which an IC is directly mounted on a substrate by a COG (Chip On Glass) method, etc. is sometimes referred to as a display panel module or display module, or simply as a display panel, etc.

[0056] Implementation Method 1

[0057] In this embodiment, an example of a transistor which is one embodiment of the present invention and a method for manufacturing the same will be described.

[0058] A transistor according to one embodiment of the present invention includes a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, and a second electrode. The first electrode serves as one of a source electrode and a drain electrode, and the second electrode serves as the other of the source electrode and the drain electrode.

[0059] The second electrode is disposed above the first electrode. An insulating layer serving as an interlayer insulating layer (also referred to as a spacer) is disposed between the first electrode and the second electrode. An opening that reaches the first electrode is disposed in the spacer, and the semiconductor layer is disposed in a manner of contacting the first electrode, the second electrode, and the sidewall (also referred to as the side) in the opening of the insulating layer. Furthermore, a gate insulating layer and a gate electrode are disposed in a manner of covering the semiconductor layer located in the opening.

[0060] Since the source electrode and the drain electrode are located at different heights in the transistor having the above structure, the current flowing through the semiconductor flows in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction), so the transistor of one embodiment of the present invention can also be called VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, etc. The transistor can set the source electrode, semiconductor and drain electrode overlapping each other, so the occupied area can be greatly reduced compared with the so-called planar transistor (also called lateral transistor, LFET (Lateral FET) etc.) in which the semiconductor is arranged on a plane.

[0061] When the vertical transistor is used in a display device, the area occupied by the transistor can be reduced compared to a display device using an existing lateral transistor, so that the pixel can be reduced and the aperture ratio can be improved. In addition, the number of transistors that can be configured in a pixel can be increased without increasing the area of ​​the pixel, so that the pixel can be multifunctional. As a result, a display device with higher definition, higher reliability, and lower power consumption can be realized compared to an existing display device.

[0062] As the semiconductor layer, a metal oxide (oxide semiconductor) exhibiting semiconductor properties is preferably used. Oxide semiconductors have characteristics such as higher mobility than amorphous silicon and higher production rate than crystalline silicon (polycrystalline silicon or single crystal silicon). Therefore, when oxide semiconductors are used, high-performance display devices can be realized at low cost.

[0063] The portion of the semiconductor layer in contact with the insulating layer used as a spacer is provided with a channel formation region. In order to realize a transistor with good electrical characteristics, it is preferred to sufficiently reduce oxygen vacancies in the channel formation region of the semiconductor layer. Therefore, as an insulating layer used as a spacer, an oxide insulating film that releases oxygen by heating is preferably used. Thus, oxygen released from the insulating layer due to heat in the manufacturing process of the transistor is supplied to the semiconductor layer, and oxygen vacancies in the channel formation region of the semiconductor layer can be reduced. In this way, good electrical characteristics of normally closed can be realized.

[0064] Furthermore, the insulating layer preferably has a stacked structure of an oxide insulating film that releases oxygen when heated and a blocking insulating film having oxygen blocking properties thereon, thereby preventing the following situation: oxygen in the oxide insulating film is released from its top surface to the outside due to heat during the process, thereby preventing insufficient oxygen supply to the semiconductor layer.

[0065] The more oxygen in the insulating layer, the more oxygen can be supplied to the semiconductor layer. On the other hand, when there is too much oxygen in the insulating layer, the reliability of the transistor may be reduced due to the excess oxygen between the semiconductor layer and the insulating layer. More specifically, charge accumulates at the interface between the semiconductor layer and the insulating layer, and the electrical characteristics of the transistor may change. Therefore, it is preferred to adjust the oxygen content in the insulating layer to an appropriate amount.

[0066] Therefore, in the insulating layer, a venting portion for releasing oxygen from the insulating layer to the outside during the process is provided around the opening where the transistor is provided. More specifically, an opening is provided in a portion of the blocking insulating film included in the insulating layer. Thus, since a portion of the oxygen in the oxide insulating film included in the insulating layer is released from the venting portion to the outside through heat or the like in the process, the oxygen content in the oxide insulating film can be made into an appropriate amount, and while an appropriate amount of oxygen is supplied to the semiconductor layer, excess oxygen can be prevented from remaining at the interface between the semiconductor layer and the insulating layer. Thus, a transistor with good electrical characteristics and high reliability can be realized.

[0067] A more specific example will be described below with reference to the drawings.

[0068] [Structure example]

[0069] Figure 1A is a plan view of the structure of the transistor 10 and its periphery. Figure 1B , Figure 1C They are shown corresponding to Figure 1A Schematic diagram of the cross section of the truncation lines AB and CD in FIG. Figure 1A Some components (insulating layer, etc.) are omitted.

[0070] The transistor 10 is provided on an insulating layer 12 on a substrate 11. The insulating layer 12 is used as a base insulating layer. The transistor 10 includes a semiconductor layer 21, an insulating layer 22 of which a portion is used as a gate insulating layer, a conductive layer 23 of which a portion is used as a gate electrode, a conductive layer 24 of which a portion is used as one of a source electrode and a drain electrode, and a conductive layer 25 of which a portion is used as the other of the source electrode and the drain electrode.

[0071] The conductive layer 24 is provided on the insulating layer 12, and the insulating layer 41 is provided on the conductive layer 24. The conductive layer 25 is provided on the insulating layer 41. The insulating layer 41 includes an opening 20 that reaches the conductive layer 24. In addition, here is shown an example in which the conductive layer 25 is also provided with an opening that overlaps with the opening 20. However, the conductive layer 25 does not need to include an opening, and can be provided on the insulating layer 41 and at a position near the opening 20.

[0072] The insulating layer 41 is used as a spacer for insulating the conductive layer 24 from the conductive layer 25. The insulating layer 41 has a three-layer structure in which an insulating layer 41a, an insulating layer 41b, and an insulating layer 41c are stacked in this order from the insulating layer 12 side. The top surface of the conductive layer 24 is in contact with the insulating layer 41a. The conductive layer 25 is provided on the insulating layer 41c. The insulating layer 41a, the insulating layer 41b, and the insulating layer 41c may also be referred to as an insulating film.

[0073] The semiconductor layer 21 has a portion in and near the opening 20 that contacts the top surface of the conductive layer 25, a portion that contacts the side surface of the conductive layer 25, a portion that contacts the side surface of the insulating layer 41c, a portion that contacts the side surface of the insulating layer 41b, a portion that contacts the side surface of the insulating layer 41a, and a portion that contacts the top surface of the conductive layer 24.

[0074] The insulating layer 22 is provided so as to cover the insulating layer 41, the conductive layer 25, the semiconductor layer 21, and the conductive layer 24. When focusing on the inside of the opening 20, the insulating layer 22 is provided so as to follow the concave top surface of the semiconductor layer 21.

[0075] In addition, the conductive layer 23 is provided so as to cover the insulating layer 22. When focusing on the inside of the opening 20, the conductive layer 23 is provided so as to follow the concave top surface of the insulating layer 22.

[0076] Insulating layer 41 includes opening 15a and opening 15b at positions different from opening 20. Opening 15a has a region overlapping conductive layer 23 when viewed from the plane. Opening 15b is provided in a region not overlapping conductive layer 23, conductive layer 24, and conductive layer 25 when viewed from the plane.

[0077] The openings 15a and 15b are provided so as to pass through the insulating layers 41a, 41b, and 41c to reach the insulating layer 12. Inside the openings 15a and 15b, the insulating layer 22 is provided so as to be in contact with the side surfaces of the insulating layers 41a, 41b, and 41c and the top surface of the insulating layer 12. In addition, the conductive layer 23 has a portion located inside the opening 15a.

[0078] Figure 2A 1 is a three-dimensional schematic diagram of the structure of the transistor 10 and its surroundings. Figure 2A In FIG. 1 , the outlines of the openings 15a and 15b are indicated by dotted lines. Figure 2B It is a three-dimensional schematic diagram, in which Figure 2A The insulating layer 22 and the conductive layer 23 are shown in FIG. 4 , and the outline of the insulating layer 41 is shown in dotted lines. Figure 2A As shown, a portion of the conductive layer 23 has a recessed portion embedded in the opening 15 a.

[0079] The channel length of the transistor 10 can be precisely controlled according to the thickness of the insulating layer 41, so that the non-uniformity of the channel length can be made extremely small compared with a planar transistor. In addition, by thinning the insulating layer 41, a transistor with an extremely small channel length can be manufactured. For example, a transistor with a channel length of less than 2 μm, less than 1 μm, less than 500 nm, less than 300 nm, less than 200 nm, less than 100 nm, less than 50 nm, less than 30 nm, or less than 20 nm and greater than 5 nm, greater than 7 nm, or greater than 10 nm can be manufactured. Thus, a transistor with an extremely small channel length that cannot be achieved by the existing exposure device for mass production of flat panel displays (for example, a minimum line width of about 2 μm or about 1.5 μm) can be realized. In addition, a transistor with a channel length less than 10 nm can be realized without using the very expensive exposure device used in the most advanced LSI technology.

[0080] The semiconductor layer 21 can use a variety of semiconductor materials, and it is particularly preferred to use an oxide semiconductor containing a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor having both high on-state current and extremely low off-state current can be realized at low cost. Below, unless otherwise specified, a preferred structural example of the case where an oxide semiconductor is used for the semiconductor layer 21 is described.

[0081] The conductive layer 24 and the conductive layer 25 have a structure in which their respective top surfaces are in contact with the semiconductor layer 21. Therefore, when the semiconductor layer 21 uses an oxide semiconductor, there is the following concern: the surface vicinity of the conductive layer 24 and the conductive layer 25 is oxidized due to the influence of heat during the deposition process of the semiconductor film to be the semiconductor layer 21 or after the deposition process, and an insulating oxide film is formed between the conductive layer 24 and the conductive layer 25 and the semiconductor layer 21, so the contact resistance increases. Therefore, at least the uppermost portion of the conductive layer 24 and the conductive layer 25 preferably uses an oxide conductor containing a conductive oxide. Thus, the increase in contact resistance caused by oxidation of the surface of the conductive layer 24 and the conductive layer 25 can be suppressed. The conductive layer 24 and the conductive layer 25 can be referred to as an oxide layer, a metal oxide layer, or an oxide conductor layer.

[0082] A portion of the conductive layer 24 can be used as one of the source wiring and the drain wiring. In addition, a portion of the conductive layer 25 can be used as the other of the source wiring and the drain wiring. In the case where one or both of the conductive layer 24 and the conductive layer 25 are used as wiring, the resistance is preferably low. Therefore, it is preferred to use a material with higher conductivity than the oxide conductor, such as a metal, an alloy, or their nitrides. In particular, it is preferred to use a stacked structure including a layer containing the material with high conductivity as one or both of the conductive layer 24 and the conductive layer 25, and it is preferred to use the above-mentioned oxide conductor at least at the uppermost portion.

[0083] The transistor 10 is provided at the intersection of the conductive layer 23 used as the gate wiring and the conductive layer 24 used as the source wiring or the drain wiring. Thus, the occupied area can be minimized.

[0084] The semiconductor layer 21 is arranged in a manner in contact with the inner wall of the opening 20 in the insulating layer 41b. The insulating layer 41b preferably uses an oxide insulating film. In particular, it is preferred to use an oxide insulating film that releases oxygen by heating. In addition, it is preferred to provide an insulating layer 41c having a barrier to oxygen (oxygen barrier) on the insulating layer 41b. For example, as the insulating layer 41c, it is preferred to use a film that is less likely to diffuse oxygen (the diffusion coefficient of oxygen is small) than the insulating layer 41b. Thus, it is possible to prevent most of the oxygen contained in the insulating layer 41b from diffusing to the outside and the oxygen supplied to the semiconductor layer 21 from becoming insufficient. Furthermore, the insulating layer 41b is preferably sandwiched between the insulating layer 41a and the insulating layer 41c having oxygen barrier properties. Thus, the oxygen contained in the insulating layer 41b can be enclosed in the region surrounded by the insulating layer 41a, the insulating layer 41c and the semiconductor layer 21 to prevent the oxygen in the insulating layer 41b from detaching and decreasing during the process, so that oxygen can be supplied to the semiconductor layer 21 more effectively.

[0085] Typical examples of the oxide insulating film that releases oxygen when heated include a silicon oxide film and a silicon oxynitride film.

[0086] As the insulating film having oxygen barrier properties, it is preferred to use oxides, nitrides or oxynitrides such as silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium aluminate, yttrium oxide, yttrium oxynitride, gallium oxide, gallium-zinc oxide, etc. In particular, when silicon nitride and aluminum oxide are used, a film having high oxygen barrier properties can be realized at low cost, so they are preferred.

[0087] The portion of the semiconductor layer 21 in contact with the insulating layer 41b is a region where oxygen vacancies are reduced, and can also be said to be an i-type region. On the other hand, the portion not in contact with the insulating layer 41b is preferably an n-type region with a high carrier content. For example, the portion of the semiconductor layer 21 in contact with the insulating layer 41b can be called a channel formation region, and the region outside the channel formation region can be called a low resistance region (also called a source region or a drain region).

[0088] The openings 15a and 15b in the insulating layer 41 are provided at a position at a predetermined distance from the opening 20 when viewed from a plane. By providing the openings 15a and 15b, the excess oxygen in the insulating layer 41b can be released to the outside during the process. Note that the example in which the openings 15a and 15b pass through the insulating layer 41 to the insulating layer 12 is shown here, but the present invention is not limited to this. The openings 15a and 15b may be provided at least in the insulating layer 41c in the insulating layer 41.

[0089] The openings 15a and 15b have the function of releasing excess oxygen in the insulating layer 41b to the outside by heat or the like during the process, thereby adjusting the oxygen content in the insulating layer 41b to an appropriate amount. Figure 1A and Figure 1B In FIG. 1 , the shortest distance between the opening 15a and the opening 20 and the shortest distance between the opening 15b and the opening 20 when viewed from a plane are indicated by arrows as distance d. The distance d between the opening 15a and the opening 20 is preferably substantially the same as the distance d between the opening 15b and the opening 20. Thus, the unevenness of the oxygen content in the insulating layer 41b near the semiconductor layer 21 can be suppressed.

[0090] The distance d between the opening 15a and the opening 15b and the opening 20 is preferably smaller than the diffusion length (diffusion distance) of the oxygen diffused in the insulating layer 41b. Thus, the excess oxygen in the insulating layer 41b near the semiconductor layer 21 can be released to the outside through the opening 15a and the opening 15b. The diffusion length of oxygen depends on the oxygen diffusion coefficient in the insulating layer 41b and the temperature and processing time of the heat treatment in the process. Therefore, in order to release an appropriate amount of oxygen to the outside, the opening 15a and the opening 15b can be arranged at a position away from the opening 20 by an appropriate distance d according to the film quality of the insulating layer 41b and the temperature and processing time of the heat treatment in the manufacturing process.

[0091] In addition, the diffusion coefficient of a given element of a certain film varies greatly not only depending on the deposition method of the film but also on the deposition conditions. For example, when depositing a silicon oxide film using plasma enhanced chemical vapor deposition (PECVD), the diffusion coefficient of oxygen tends to depend on the ratio of the flow rate of the deposition gas (such as silane gas) to the deposition power. The smaller the ratio (P / S) of the deposition power P to the flow rate S of the silane gas, the larger the diffusion coefficient of the film can be obtained. The difference in the diffusion coefficient can be confirmed, for example, as a difference in the wet etching rate.

[0092] Thus, the distance d between the openings 15a and 15b and the opening 20 can be set to an appropriate distance according to the film quality of the insulating layer 41b and the manufacturing process of the transistor, for example, greater than the minimum processing dimension and less than 100 μm, such as greater than 0.1 μm and less than 100 μm, preferably greater than 0.1 μm and less than 50 μm, more preferably greater than 0.1 μm and less than 30 μm, and further preferably greater than 0.1 μm and less than 20 μm. Note that when the minimum processing dimension can be set to be smaller than 0.1 μm, the distance d can also be reduced to greater than 10 nm and less than 50 nm or greater than 10 nm and less than 30 nm.

[0093] Here, the channel length, channel width, and the like of the transistor 10 are described.

[0094] like Figure 1C As shown, the channel length L of the transistor 10 can be said to be the length of the portion of the semiconductor layer 21 that contacts the insulating layer 41 on the shortest path connecting the portion of the semiconductor layer 21 that contacts the conductive layer 24 and the portion of the semiconductor layer 21 that contacts the conductive layer 25. Note that in the case where the resistance of the portion other than the portion that can be regarded as contacting the insulating layer 41b (i.e., the portion that contacts the insulating layer 41a and the insulating layer 41c, respectively) is low, the channel length L can also be the length of the portion that contacts the insulating layer 41b. When the angle (θ) of the side wall of the opening 20 of the insulating layer 41 is less than 90 degrees, that is, when the insulating layer 41 has a tapered shape, the channel length L can be made greater than the thickness of the insulating layer 41 (or the insulating layer 41b).

[0095] In addition, the channel width W (not shown) of the transistor 10 depends on the shape of the opening 20. When the outline of the opening 20 is a circle with a diameter R, the channel width W can be regarded as the circumference of the opening 20 (that is, =π×R). Here, when the angle θ of the side wall of the opening 20 of the insulating layer 41 is shifted from 90 degrees, the circumference of the opening 20 varies depending on the height. In this case, the circumference at the height (here, the lower end) when the diameter of the opening 20 is the smallest can be regarded as the channel width W. In addition, the circumference at the height of the upper end or the center of the opening 20 can also be regarded as the channel width W.

[0096] The shape of the opening 20 when viewed from a plane can typically be circular. However, the shape of the opening 20 is not limited to a circle, and various shapes can be used. For example, in addition to a circle, an ellipse, a quadrangle with an arc at the corner, etc. can also be used. In addition, regular polygons such as regular triangles, squares, regular pentagons, and polygons other than regular polygons can also be used. In addition, when a concave polygon such as a star-shaped polygon is used, in which at least one internal angle exceeds 180 degrees, the channel width can be increased. In addition, a polygon with an arc at the corner, a closed curve of a combination of straight lines and curves, etc. can be used.

[0097] The semiconductor layer 21 and the insulating layer 22 are formed along the inner wall of the opening 20 of the insulating layer 41, so the thickness of this part is sometimes thinned depending on the deposition method. For example, when using a deposition method such as sputtering or plasma CVD, there is a tendency for the thickness of a film deposited on a surface inclined or perpendicular to the substrate surface to be thinner than a film deposited on a surface parallel to the substrate surface. On the other hand, when using a deposition method such as atomic layer deposition (ALD: Atomic Layer Deposition) or thermal CVD, a film with a uniform thickness can be deposited regardless of the angle of the formed surface. For example, when the angle θ of the side wall of the opening 20 of the insulating layer 41 is greater than 75 degrees, greater than 80 degrees, or greater than 85 degrees, it is preferred to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.

[0098] [About the components]

[0099] <Substrate>

[0100] As the substrate 11 for forming the transistor, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As the insulator substrate, for example, there are glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium stabilized zirconia substrates, etc.), resin substrates, etc. As the semiconductor substrate, for example, there are semiconductor substrates made of silicon or germanium or compound semiconductor substrates composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, gallium nitride, etc. In addition, there are semiconductor substrates such as SOI (Silicon On Insulator) substrates having an insulator region inside the above-mentioned semiconductor substrates. As the conductor substrate, there are graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Alternatively, a substrate containing metal nitrides, a substrate containing metal oxides, etc. can also be used. Furthermore, there are substrates having a conductive layer or a semiconductor layer on an insulator substrate, a substrate having a conductive layer or an insulating layer on a semiconductor substrate, a substrate having a semiconductor layer or an insulating layer on a conductor substrate, etc. Alternatively, substrates having elements provided on these substrates can also be used. Elements provided over the substrate include capacitors, resistors, switching elements (including transistors), light-emitting elements, memory elements, and the like.

[0101] <Semiconductor Layer>

[0102] The semiconductor layer 21 preferably includes a metal oxide (oxide semiconductor).

[0103] Examples of the metal oxide that can be used for the semiconductor layer 21 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In, Zn, Sn, or Al, and more preferably contains In or Zn.

[0104] In addition, the metal oxide preferably contains two or three selected from In, element M and Zn. For example, In-M-Zn oxide, In-M oxide or M-Zn oxide can be used. Note that element M is a metal element or a semi-metal element having a high bonding energy with oxygen, for example, a metal element or a semi-metal element having a higher bonding energy with oxygen than indium. As element M, Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge and Sb can be cited. The metal oxide preferably contains any one or more of the above elements, and particularly preferably contains one or more selected from Al, Ga, Y and Sn. Here, in this specification, etc., "metal element" sometimes includes a semi-metal element.

[0105] The atomic ratio of In in the In-M-Zn oxide is preferably greater than the atomic ratio of M. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field effect mobility of the transistor can be increased. For example, as the atomic ratio of the metal elements of the In-M-Zn oxide, the ratio of In:M:Zn can be 1:1:1, 1:1:1.2, 2:1:3, 3:1:2, 4:2:3, 4:2:4.1, 5:1:3 and 5:1:6, and compositions near these ratios. Note that the nearby composition includes a range of ±30% of the desired atomic ratio.

[0106] In addition, the atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of M. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed. For example, as the atomic ratio of the metal elements in the In-M-Zn oxide, the ratio of In:M:Zn is 1:3:2, 1:3:3 and 1:3:4, and compositions near these ratios can be cited.

[0107] The semiconductor layer 21 may be made of, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-W oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-W-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, etc. In addition, as an oxide that does not contain In, Ga oxide, Zn oxide, Ga-Zn oxide, Ga-Sn oxide, Al-Zn oxide, Al-Sn oxide, etc. may also be used. When using a material that does not contain Zn, such as indium oxide, affinity with the manufacturing process of LSI is improved, so it is preferred. On the other hand, when using a material that contains Zn, crystallinity is easily improved, so it is preferred.

[0108] In addition, metal oxides may also replace indium or contain metal elements with a larger atomic number in addition to indium. Since there is a tendency that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide, when the metal oxide contains a metal element with a large atomic number, the field effect mobility of the transistor can sometimes be improved. For example, one or more of the metal elements belonging to the 5th period and the metal elements belonging to the 6th period can be used. Specifically, Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, Eu, etc. can be cited.

[0109] In addition, the metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field effect mobility of the transistor may be improved. For example, C, N, P, S, Se, F, Cl, Br, H, etc. may be cited.

[0110] The metal oxide can be formed by sputtering or atomic layer deposition (ALD) as appropriate. When the sputtering method is used, the impurity concentration can be reduced, so it is preferred. In addition, the ALD method is excellent in coverage, so it is preferred. Note that when the metal oxide is formed by sputtering, the composition of the deposited metal oxide is sometimes different from the composition of the target. In particular, the zinc content in the deposited metal oxide is sometimes reduced to about 50% of the zinc content in the target.

[0111] In this specification, etc., the content rate of a certain metal oxide in a metal element refers to the ratio of the number of atoms of the element to the total number of atoms of the metal element contained in the metal oxide. For example, a metal oxide contains a metal element X, a metal element Y, and a metal element Z, and the number of atoms of the metal element X, the metal element Y, and the metal element Z contained in the metal oxide is A, respectively. X , A Y , A Z When the content of metal element X is displayed as A X / (A X +A Y +A Z ). In addition, when the ratio of the number of atoms of metal element X, metal element Y, and metal element Z in the metal oxide (atomic ratio) is shown as B X :B Y :B Z When the content of metal element X is displayed as B X / (B X +B Y +B Z ).

[0112] For example, when a metal oxide containing In is used, a transistor with a large on-state current can be realized by increasing the In content.

[0113] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability for forward bias can be realized. In other words, a transistor with a small change in threshold voltage in a PBTS (Positive Bias Temperature Stress) test can be realized. In addition, when using a metal oxide containing Ga, the Ga content is preferably lower than the In content. Thus, a transistor with high mobility and high reliability can be realized.

[0114] On the other hand, by increasing the Ga content, a transistor with high reliability to light can be realized. In other words, a transistor with a small change in threshold voltage in the NBTIS (Negative Bias Temperature Illumination Stress) test can be realized. Specifically, the band gap of a metal oxide in which the atomic number of Ga is greater than the atomic number of In is larger, which can reduce the change in threshold voltage of the transistor in the NBTIS test.

[0115] In addition, by increasing the zinc content, a highly crystalline metal oxide is formed, and diffusion of impurities in the metal oxide can be suppressed. This can suppress changes in the electrical characteristics of the transistor and improve reliability.

[0116] The semiconductor layer 21 may also have a stacked structure including two or more metal oxides. The compositions of the two or more metal oxides included in the semiconductor layer 21 may also be the same or substantially the same. By adopting a stacked structure of metal oxides of the same composition, for example, the same sputtering target can be used for formation, so the manufacturing cost can be reduced. Note that a stacked structure of two or more metal oxides of different compositions can also be adopted. In addition, by utilizing the ALD method, a metal oxide whose composition changes continuously in the thickness direction can be formed. As a result, compared with the case of using a film of a fixed composition, not only the range of design options is increased, but also the interface state generated between two layers of different compositions can be prevented, thereby improving electrical properties and reliability.

[0117] In the case where the semiconductor layer 21 has a two-layer structure, the second layer, that is, the side close to the gate electrode, preferably uses a material with a higher mobility (a material with high conductivity) than the first layer. Thus, a normally closed transistor with a large on-state current can be realized. Therefore, low power consumption and high performance can be achieved at the same time. Alternatively, the first layer, that is, the side in contact with the source electrode and the drain electrode, can also use a material with a higher mobility than the second layer. Thus, the contact resistance between the semiconductor layer 21 and the source electrode or the drain electrode can be reduced, so the parasitic resistance is reduced, thereby realizing a transistor with a large on-state current.

[0118] When the semiconductor layer 21 has a three-layer structure, it is preferable that the second layer use a material having a higher mobility than the first layer and the third layer. This can realize a transistor having a large on-state current and high reliability.

[0119] The higher the content of elements such as indium that contribute to the improvement of conductivity, the higher the mobility and conductivity. As an example of a material with high mobility, for example, In:Ga:Zn=4:3:2, In:Zn=1:1, In:Zn=2:1, In:Zn=4:1, In:Sn:Zn=40:1:10, In:Sn:Zn=20:1:10, In:Sn=95:5, In:Sn=90:10 and materials with atomic ratios near the above ratios can be cited. On the other hand, as a material whose mobility is lower than that of the above materials, for example, materials with In:Ga:Zn ratios of 1:3:2, 1:3:4, 2:2:1, 1:1:1, 1:1:2 and materials with atomic ratios near the above ratios can be cited.

[0120] The semiconductor layer 21 preferably uses a crystalline metal oxide layer. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a microcrystalline (nc: nano-crystal) structure, etc. can be used. When a crystalline metal oxide layer is used for the semiconductor layer 21, the defect state density in the semiconductor layer 21 can be reduced, thereby realizing a semiconductor device with high reliability.

[0121] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 21, the lower the defect state density in the semiconductor layer 21. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0122] Compared with transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have very high field effect mobility. In addition, the leakage current between the source and drain of the OS transistor in the off state (hereinafter also referred to as off-state current) is extremely low, and the charge stored in the capacitor connected in series with the transistor can be maintained for a long period of time. In addition, by using OS transistors, the power consumption of semiconductor devices can be reduced.

[0123] A semiconductor device of one embodiment of the present invention can be applied to a display device, for example. When increasing the luminous brightness of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To this end, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Because the source-drain withstand voltage of an OS transistor is higher than that of a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Thus, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be increased to increase the luminous brightness of the light-emitting device.

[0124] When the transistor operates in the saturation region, the OS transistor can make the change in the source-drain current for the change in the gate-source voltage smaller than the Si transistor. Therefore, by using the OS transistor as the driving transistor included in the pixel circuit, the amount of current flowing through the light-emitting device can be tightly controlled. As a result, the number of grayscales of the pixel circuit can be increased. In addition, even if the electrical characteristics (such as resistance) of the light-emitting device change or the electrical characteristics are uneven, a stable current can flow.

[0125] As described above, by using an OS transistor as a driving transistor in a pixel circuit, the following effects can be obtained: "suppression of black blur", "increase in luminous brightness", "multi-grayscale", "suppression of the influence of manufacturing unevenness of light-emitting devices", etc.

[0126] OS transistors have little change in electrical characteristics due to exposure to radiation, that is, they have high tolerance to radiation, so they can be appropriately used in environments where radiation may be incident. OS transistors can also be said to have high reliability with respect to radiation. For example, OS transistors can be appropriately used as pixel circuits of flat-panel detectors for X-rays. In addition, OS transistors can be appropriately used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0127] Note that the semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, a semiconductor composed of a single element or a compound semiconductor can be used. As a semiconductor composed of a single element, Si (including single crystal, polycrystalline, microcrystalline and amorphous) or Ge can be cited. As a compound semiconductor, for example, GaAs and SiGe can be cited. As a compound semiconductor, for example, an organic semiconductor, a nitride semiconductor or an oxide semiconductor can be cited. In addition, these semiconductor materials may also contain impurities as dopants.

[0128] In addition, the semiconductor layer 21 may also use a material having a layered crystal structure. The conductivity within the layer of the material having a layered crystal structure is high. Therefore, by using such a material having a layered crystal structure in the channel formation region, a transistor with a large on-state current can be provided. For example, graphene, silicene, chalcogenides, etc. can be cited. As chalcogenides, chalcogenides of transition elements such as Mo, W, Hf or Zr can be cited. At this time, as chalcogen elements, Group 16 elements such as S, Se, Te, etc. can be cited.

[0129] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layer 21, and any of an amorphous semiconductor, a single crystal semiconductor, or a semiconductor other than a single crystal having crystallinity (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystallized region in part thereof) may be used. When a semiconductor having crystallinity is used, it is preferred because it can suppress the degradation of the characteristics of the transistor.

[0130] <Gate Insulation Layer>

[0131] The insulating layer 22 is used as a gate insulating layer of a transistor and can also be used as a dielectric layer of a capacitor. When an oxide semiconductor is used for the semiconductor layer 21, the film of the insulating layer 22 that is at least in contact with the semiconductor layer 21 preferably uses an oxide insulating film. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride and Ga-Zn oxide can be used. In addition, as the insulating layer 22, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. can also be used. In addition, the insulating layer 22 can also have a stacked structure, and can have, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0132] In this specification, etc., an oxynitride refers to a material containing more oxygen than nitrogen. An oxynitride refers to a material containing more nitrogen than oxygen.

[0133] In addition, as the insulating layer 22, it is preferred to stack an insulating material composed of a high-k material, and it is preferred to use a stacked structure of a material with a high relative dielectric constant (high-k) and a material whose dielectric strength is greater than that of the high-k material. For example, as the insulating layer 22, an insulating film (also referred to as ZAZ) stacked in sequence with zirconium oxide, aluminum oxide, and zirconium oxide can be used. In addition, an insulating film (also referred to as ZAZA) stacked in sequence with zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. In addition, an insulating film (also referred to as hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide) can be used. When an insulator with a large dielectric strength such as aluminum oxide is stacked, the dielectric strength is improved, so that the electrostatic destruction of the capacitor can be suppressed.

[0134] A material exhibiting ferroelectricity may also be used as the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and other metal oxides.

[0135] <Conductive layer>

[0136] The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. Here, when an oxide semiconductor is used as the semiconductor layer 21, when a metal that is easily oxidized, such as aluminum, is used for the portion of the conductive layer 24 or the conductive layer 25 that contacts the semiconductor layer 21, there is a concern that an insulating oxide (such as aluminum oxide) is formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, thereby hindering conduction therebetween. Therefore, it is preferred that a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, or an oxide conductive material be used for at least the portion of the conductive layer 24 or the conductive layer 25 that contacts the semiconductor layer 21.

[0137] As the conductive layer 24 and the conductive layer 25, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. The above materials are conductive materials that are not easily oxidized or materials that maintain conductivity even if oxidized, so they are preferred.

[0138] In addition, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide can be used. In particular, conductive oxides containing indium have high conductivity and are therefore preferred. Alternatively, the above-mentioned oxide materials such as In-Ga-Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0139] For example, as the conductive layer 24 and the conductive layer 25, a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are sequentially stacked, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on a tungsten film, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film, etc. can be used. Note that ruthenium is a material that is not easily etched, so the thinner the better, and for example, ruthenium having a thickness of, for example, 0.1 nm or more and 2 nm or less is preferably used.

[0140] The conductive layer 23 is used as a gate electrode, and various conductive materials can be used. As the conductive layer 23, for example, a metal element selected from Al, Cr, Cu, Ag, Pt, Ta, Ni, Ti, Mo, W, Hf, V, Nb, Mn, Mg, Zr, Be, In, Ru, Ir, Sr, La, etc., or an alloy containing the metal element as a component is preferably used. In addition, a nitride of the above metal or alloy or an oxide of the above metal or alloy can also be used. For example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. In addition, a semiconductor with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus, a silicide such as nickel silicide, etc. can also be used.

[0141] In addition, the conductive layer 23 may also use the nitride and oxide that can be used for the conductive layer 24 and the conductive layer 25 .

[0142] Since the conductive layers 23, 24 and 25 are also used as wiring, it is preferable to stack low-resistance conductive materials. For example, the low-resistance conductive material used for the conductive layer 23 may be used as the lower layer of each of the conductive layers 24 and 25.

[0143] <Insulation layer>

[0144] The insulating layer 41b can be used as an interlayer insulating film. For example, it is preferable to use a deposition method such as a sputtering method or a plasma CVD method. In particular, when the sputtering method is used, it is not necessary to use hydrogen gas as a deposition gas, so a film with a very low hydrogen content can be achieved. As a result, hydrogen can be suppressed from being supplied to the semiconductor layer 21, and the electrical characteristics of the transistor 10 can be stabilized.

[0145] Since the insulating layer 41b is in contact with the channel formation region of the semiconductor layer 21, an oxide insulating film is preferably used. In particular, an oxide insulating film that releases oxygen by heating is preferably used. As the insulating layer 41b, the oxide insulating film that can be used for the gate insulating layer can be used.

[0146] In addition, since the insulating layer 41b is used as an interlayer insulating layer, it is preferable to use a deposition method that can be deposited at a higher deposition rate than other insulating layers. For example, a TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC2H5)4) film formed by a plasma CVD method can also be used as the insulating layer 41. This can improve the yield.

[0147] The insulating layer 41a and the insulating layer 41c are preferably made of a material that is less likely to transmit oxygen than the insulating layer 41b, that is, a material having oxygen barrier properties. The insulating layer 41a and the insulating layer 41b can be made of the above-mentioned insulating film having oxygen barrier properties. In particular, silicon nitride or aluminum oxide is preferably used.

[0148] Insulating layer 41a, insulating layer 41c and insulating layer 41b may use an insulating film containing the same element (for example, silicon oxide). In this case, an insulating film having a higher density than insulating layer 41b, that is, an insulating film having a slower etching rate, may be used.

[0149] The insulating layer 41a and the insulating layer 41c are preferably made of a film that does not easily diffuse hydrogen. By sandwiching the insulating layer 41b in the vertical direction between the insulating layer 41a and the insulating layer 41c that do not easily diffuse hydrogen, hydrogen can be prevented from entering the insulating layer 41b in contact with the semiconductor layer 21 from the outside.

[0150] In particular, silicon nitride and silicon nitride oxide have the characteristics that they release a small amount of impurities (for example, water and hydrogen) and are not easily permeable to oxygen and hydrogen, and therefore are suitable for the insulating layers 41 a and 41 c .

[0151] The insulating layer 12 is used as a base insulating layer or an interlayer insulating layer. As the insulating layer 12, the insulating material that can be used for the insulating layer 41b or the insulating material that can be used for the insulating layer 41a and the insulating layer 41c can be used as appropriate.

[0152] This concludes the description of the components.

[0153] [Structural example of opening]

[0154] Figure 1A The case where the openings 15a and 15b have a horizontally long shape when viewed from a plane is shown, but the shapes of the openings 15a and 15b are not limited to this. An example different from the above is described below.

[0155] Figure 3A The example of the case where the opening 15a and the opening 15b have a circular shape when viewed from a plane is shown. The opening 15a and the opening 15b are circular with a diameter substantially the same as that of the opening 20. Figure 1A The middle opening 15a has a portion that does not overlap with the conductive layer 23. Figure 3A The opening 15 a is located inside the conductive layer 23 when viewed from a plan view.

[0156] Figure 3B This is an example of a case including four openings. Figure 3BTwo openings 15a and two openings 15b are shown. Both openings 15a partially overlap with the conductive layer 23. In this way, by increasing the number of openings, oxygen can be released from the insulating layer 41b more efficiently. For example, when a heat treatment is performed to remove oxygen, the effect of shortening the treatment time or lowering the treatment temperature can be achieved.

[0157] Figure 3C Show Figure 1A The opening 15 a and the opening 15 b shown are examples of the case where they have a curved shape. Figure 3C The opening 15a and the opening 15b shown have a portion where the shortest distance from the opening 20 is equal in a portion of their respective contours. For example, when the opening 20 is circular, there is a portion where concentric circles (indicated by dotted lines) centered on the center of the opening 20 overlap with a portion of the contours of the opening 15a and the opening 15b. In this way, the larger the area where the shortest distance from the opening 20 is equal in the opening 15a and the opening 15b, the more efficiently oxygen can be released from the insulating layer 41b.

[0158] Although the example including the opening 15 a overlapping with the conductive layer 23 is shown above, a structure including an opening overlapping with the conductive layer 24 may also be adopted. Figure 4A An example is shown in which the opening 15 is provided with a portion overlapping the conductive layer 23 and a portion overlapping the conductive layer 24. Here, an example is shown in which a portion of the outline of the opening 15 overlaps with a concentric circle (indicated by a dotted line) centered on the center of the opening 20. In this way, when the opening 15 surrounds the opening 20 by more than 180 degrees, oxygen can be released from the insulating layer 41b very efficiently.

[0159] Figure 4B , Figure 4C All show cross-sectional schematic diagrams. Figure 4C As shown, in the region where the opening 15 overlaps the conductive layer 24 , a portion of the insulating layer 22 contacts the top surface of the conductive layer 24 through the opening 15 .

[0160] Note that the configuration method of the opening 15, opening 15a and opening 15b shown here is an example, and they can be configured at various positions as long as they are in an area that does not overlap with the conductive layer 25 when viewed from a plane. In addition, there is no restriction on the number of openings, and the number of openings set for a transistor can also be one, three, or five or more. In addition, two or more transistors can also include the opening together. For example, more than one opening can be set for two transistors, or more than one opening can be set for three transistors.

[0161] [Cross-sectional shape of the opening]

[0162] Next, examples of cross-sectional shapes different from those of the opening 15a, the opening 15b, or the opening 15 are described. Note that as described above, one or more openings may be provided, and therefore, they are not distinguished and are described as the opening 15 below.

[0163] Figure 5A1 is a schematic cross-sectional view of the opening 15 and its surroundings. Figure 5A2 An example is shown in which the opening 15 overlaps with the conductive layer 24 .

[0164] exist Figure 5A1 , Figure 5A2 , an example is shown in which the opening 15 passes through the insulating layer 41c and the insulating layer 41b in the insulating layer 41 and reaches the insulating layer 41a. In addition, a portion of the insulating layer 22 is provided in contact with the top surface of the insulating layer 41a in the opening 15. By adopting such a structure, when etching is performed to form the opening 15, the insulating layer 41a can be used as an etching stop layer, so that etching controllability can be improved.

[0165] exist Figure 5B1 , Figure 5B2 In the embodiment, the opening 15 is provided in the middle of the insulating layer 41c and the insulating layer 41b in the insulating layer 41. That is, a recess is provided in a portion of the insulating layer 41b that overlaps with the opening 15.

[0166] In addition, Fig.5C1 , Fig.5C2 In the embodiment, the opening 15 is provided only in the insulating layer 41 c in the insulating layer 41 .

[0167] In this way, the opening 15 only needs to be provided in at least the insulating layer 41c in the insulating layer 41, and a structure can be adopted in which the insulating layer 41b inside the opening 15 is in contact with the insulating layer 22. The deeper the opening 15 is, the larger the surface area of ​​the insulating layer 41b inside the opening 15 is, so that oxygen can be efficiently released from the insulating layer 41b.

[0168] also, Fig.5D1 , Fig.5D2 An example is shown in which the opening 15 passes through the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a and reaches the middle of the layer constituting the surface on which the insulating layer 41a is formed. Fig.5D1 In the embodiment, the portion of the insulating layer 12 overlapping the opening 15 is provided with a recess, and the insulating layer 22 covers the recess. Fig.5D2 In the embodiment, a concave portion is provided in the portion of the conductive layer 24 overlapping with the opening 15, and the concave portion is covered by the insulating layer 22. In this way, when the opening 15 passes through the insulating layer 41a, a portion of the insulating layer 12 or the conductive layer 24 constituting the surface on which the opening 15 is formed may be etched depending on the etching conditions of the insulating layer 41a.

[0169] [Deformation example]

[0170] Hereinafter, an example in which a part of the structure is different from the above is described. Note that the following description will refer to the description of the parts repeated above and the repeated description will be omitted.

[0171] [Deformation Example 1]

[0172] exist Fig. 6A , Figure 6B In the embodiment, the opening 15 passes through not only the insulating layer 41 but also the insulating layer 22. In the region of the opening 15 that does not overlap with the conductive layer 23, the insulating layer 44 is provided in contact with the side surfaces of the insulating layer 22, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a. In the region of the opening 15 that does not overlap with any of the conductive layers 23 and 24, as shown in FIG. Fig. 6A As shown in FIG. 1 , the top surface of the insulating layer 12 is in contact with the insulating layer 44. In addition, in the region of the opening 15 overlapping with the conductive layer 24, as shown in FIG. Figure 6B As shown, the top surface of conductive layer 24 is in contact with insulating layer 44 .

[0173] In the region of opening 15 overlapping conductive layer 23 , conductive layer 23 is provided in contact with the side surfaces of insulating layer 22 , insulating layer 41 c , insulating layer 41 b , and insulating layer 41 a , and the top surface of insulating layer 12 .

[0174] The above structure can be realized by forming the opening 20 and the opening 15 in different processes. More specifically, the opening 15 is formed in the insulating layer 22 and the insulating layer 41 after the insulating layer 22 is formed and before the conductive layer 23 is formed. Note that, in the case where the opening 15 is not provided in a region overlapping with the conductive layer 23, the opening 15 may be provided in a portion not overlapping with the conductive layer 23 after the conductive layer 23 is formed and before the insulating layer 44 is formed.

[0175] [Deformation Example 2]

[0176] exist Fig. 7A , Figure 7B , Figure 7C In the example shown, the opening 15 passes through not only the insulating layer 41 but also the insulating layer 44 and the insulating layer 22. In this case, the opening 15 is preferably provided in a region that does not overlap with any of the conductive layer 23, the conductive layer 24, and the conductive layer 25. In addition, when an insulating layer is further provided on the insulating layer 44, the opening 15 may also be provided at a position overlapping with the conductive layer 24.

[0177] [Deformation Example 3]

[0178] Next, an example including a conductive layer serving as a back gate is described.

[0179] Fig. 8AThe main difference between the structure shown and the above-mentioned structural examples is that the former includes a conductive layer 26 and an insulating layer 27.

[0180] The conductive layer 26 is used as a second gate electrode (or back gate electrode). The insulating layer 27 is located between the conductive layer 26 and the semiconductor layer 21, and is used as a second gate insulating layer (or back gate insulating layer). A fixed potential or an arbitrary signal can be supplied to the conductive layer 26. By providing the conductive layer 26 and supplying an appropriate potential to the conductive layer 26, the threshold voltage of the transistor can be controlled. In addition, the potential on the back channel side of the semiconductor layer 21 can be fixed, and the unevenness of the electrical characteristics can be reduced. In addition, the conductive layer 26 can also be supplied with the same potential or signal as any of the conductive layer 24, the conductive layer 25 and the conductive layer 23.

[0181] Here, the insulating layer 41 has an example of a four-layer structure of an insulating layer 41a, an insulating layer 41b1, an insulating layer 41b2, and an insulating layer 41c. The conductive layer 26 is provided between the insulating layer 41b1 and the insulating layer 41b2.

[0182] In the opening 20, the insulating layer 27 is provided in contact with the side surfaces of the insulating layer 41a, the insulating layer 41b1, the conductive layer 26, the insulating layer 41b2, the insulating layer 41c, and the conductive layer 25. In addition, in the opening 15, the insulating layer 27 is provided in contact with the insulating layer 41a, the insulating layer 41b1, the conductive layer 26, the insulating layer 41b2, and the insulating layer 41c. In addition, the insulating layer 27 is provided in contact with the side surface of the conductive layer 25 on the side of the opening 20 and also on the side surface on the opposite side thereof.

[0183] For example, after forming the openings 20 and 15, an insulating film covering the openings is deposited by a deposition method with high coverage, and then anisotropic etching is performed to form the insulating layer 27. The insulating layer 27 may also be referred to as a sidewall insulating film.

[0184] Fig. 8A The opening 15 shown on the right side of FIG. 1 is provided in a manner that passes through the conductive layer 26. Note that Figure 8B As shown, the opening 15 may not be arranged in the portion overlapping with the conductive layer 26 .

[0185] in addition, Figure 8C An example of a case where the conductive layer 23 and the insulating layer 22 are not provided is shown. In this case, the conductive layer 26 is used as a gate electrode, and the insulating layer 27 is used as a gate insulating layer. In addition, the insulating layer 44 used as a protective layer is provided in contact with the top surface and the side surface of the semiconductor layer 21 in the opening 20. The insulating layer 44 is provided in contact with the insulating layer 27 and the insulating layer 12 in the opening 15.

[0186] exist Figure 8CIn the example shown, a structure in which the conductive layer 26 used as a gate electrode surrounds the periphery of the semiconductor layer 21 is adopted, so it can be called a GAA (Gate All Around) structure. Figures 1A to 1C The structure shown in FIG. 1 is a structure in which the semiconductor layer 21 surrounds the conductive layer 23 serving as the gate electrode, and thus it can be referred to as a CAA (Channel All Around) structure.

[0187] [Manufacturing method example]

[0188] Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention is described. Figures 1A to 1C The structure shown.

[0189] Note that thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like.

[0190] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dipping, spraying, inkjet, dispenser, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and doctor blade coating.

[0191] As a sputtering method, there are RF sputtering method using a high frequency power supply for a sputtering power supply, DC sputtering method using a direct current power supply, and pulsed DC sputtering method changing the voltage applied to an electrode in a pulsed manner. RF sputtering method is mainly used when depositing insulating films, and DC sputtering method is mainly used when depositing metal conductive films. In addition, pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides by reactive sputtering method.

[0192] The CVD method can be divided into a plasma enhanced chemical vapor deposition (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to the raw material gas used.

[0193] When using the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since the thermal CVD method does not use plasma, the plasma damage to the object being processed can be reduced. In addition, when using the thermal CVD method, no plasma damage during deposition occurs, so a film with fewer defects can be obtained.

[0194] As the ALD method, the following methods can be used: a thermal ALD method in which a precursor and a reactant react using only thermal energy; a PEALD method using a reactant excited by plasma; and the like.

[0195] The CVD method and the ALD method are different from the sputtering method. The CVD method and the ALD method are deposition methods that are not easily affected by the shape of the object to be processed and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for covering the surface of an opening with a high aspect ratio. However, the deposition rate of the ALD method is slow, so it is sometimes preferably used in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0196] When using the CVD method, a film of any composition can be deposited according to the flow ratio of the raw material gas. For example, when using the CVD method, a film whose composition continuously changes can be deposited by changing the flow ratio of the raw material gas while depositing. When deposition is performed while changing the flow ratio of the raw material gas, since the time required for conveying and adjusting the pressure is not required, the deposition time can be shortened compared to the case of using multiple deposition chambers for deposition. As a result, the production rate of semiconductor devices can sometimes be improved.

[0197] When using the ALD method, a film of any composition can be deposited by introducing multiple different precursors at the same time. In addition, when introducing multiple different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor. As with the CVD method, a film whose composition changes continuously can be deposited.

[0198] In addition, when processing the thin film constituting the semiconductor device, photolithography or the like can be used. In addition, the thin film can also be processed by nanoimprinting, sandblasting, lift-off, etc. In addition, an island-shaped thin film can be directly formed by a deposition method using a shielding mask such as a metal mask.

[0199] There are two typical methods of photolithography. One is to form a resist mask on a thin film to be processed, process the thin film by etching, etc., and remove the resist mask. The other is to deposit a photosensitive thin film, then perform exposure and development to process the thin film into a desired shape.

[0200] In the photolithography method, as the light used for exposure, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm) or a mixture of these lights can be used. In addition, ultraviolet rays, KrF lasers or ArF lasers can also be used. In addition, liquid immersion exposure technology can also be used for exposure. In addition, as the light used for exposure, extreme ultraviolet (EUV: Extreme Ultra-Violet) light and X-rays can also be used. In addition, electron beams can also be used instead of light used for exposure. When extreme ultraviolet light, X-rays or electron beams are used, extremely fine processing can be performed, so it is preferred. Note that when exposure is performed by scanning with a light beam such as an electron beam, a photomask is not required.

[0201] As the etching of the thin film, dry etching, wet etching, sandblasting, etc. can be used. The wet etching method is mainly suitable for isotropic etching. On the other hand, the dry etching method can perform both isotropic etching and anisotropic etching depending on the etching device and etching conditions.

[0202] 9A to 10C The diagram is a cross-sectional view of each step in the method for manufacturing a semiconductor device described below.

[0203] First, the substrate 11 is prepared, and the insulating layer 12 is formed on the substrate 11 .

[0204] As the substrate 11, a substrate having heat resistance at least to the extent that it can withstand the subsequent heat treatment can be used. In the case of using an insulating substrate as the substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, an organic resin substrate, etc. can be used. In addition, a semiconductor substrate such as a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium or gallium nitride, or an SOI substrate can also be used.

[0205] As the insulating layer 12, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. When depositing the insulating layer 12, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be used. When the surface on which the insulating layer 12 is formed is not flat, a flattening treatment can be performed after the insulating layer 12 is deposited so that the top surface of the insulating layer 12 is flat.

[0206] Next, a conductive film is deposited on the insulating layer 12, a resist mask is formed on the conductive film, and unnecessary portions of the conductive film are removed by etching, thereby forming the conductive layer 24. The conductive film to become the conductive layer 24 can be deposited by a deposition method such as sputtering, CVD, or ALD.

[0207] Next, insulating layers 41a, 41b, and 41c are formed on the conductive layer 24 and the insulating layer 12. The insulating layers 41a, 41b, and 41c can be formed by sputtering, CVD, MBE, PLD, ALD, etc. as appropriate. Here, as the insulating layer 41b, an insulating film having a composition or constituent elements different from those of the insulating layers 41a and 41c is preferably used.

[0208] In addition, since the thickness of the insulating layer 41a, the insulating layer 41b, and the insulating layer 41c affects the channel length of the transistor, it is important to prevent the thickness of each of the insulating layer 41a, the insulating layer 41b, and the insulating layer 41c from being uneven.

[0209] The insulating layer 41b is a film that contacts the semiconductor layer 21 later, so it is preferable to use an oxide film that contains oxygen to the extent that oxygen is released by heating and has a low hydrogen content. The insulating layer 41b can be deposited by a deposition method such as a PECVD method, a sputtering method, an ALD method, and is particularly preferably deposited by a sputtering method. In particular, by depositing in a manner that does not use a gas containing hydrogen in the deposition gas and uses a gas containing oxygen, an insulating layer 41b with a very low hydrogen content and containing excess oxygen can be deposited. By depositing the insulating layer 41b in this way, oxygen can be supplied from the insulating layer 41b to the channel formation region of the semiconductor layer 21 to reduce oxygen vacancies.

[0210] In addition, a process of supplying oxygen to the insulating layer 41b may be performed after the insulating layer 41b is deposited and before the insulating layer 41c is deposited. As a method of supplying oxygen to the insulating layer 41b, heat treatment in an oxygen atmosphere, plasma treatment in an oxygen atmosphere, etc. may be cited. In addition, oxygen may be supplied by depositing an oxide film on the insulating layer 41b by sputtering in an oxygen atmosphere. Then, the oxide film may also be removed. In addition, oxygen (including any of oxygen radicals, oxygen atoms, and oxygen ions) may be supplied by ion implantation, ion doping, or plasma immersion ion implantation.

[0211] Next, a conductive film 25f is deposited on the insulating layer 41c ( Fig. 9A ). The conductive film 25f can be deposited by a deposition method such as sputtering, CVD, MBE, PLD, or ALD.

[0212] Next, the opening 20 reaching the conductive layer 24 and the openings 15a and 15b reaching the insulating layer 12 are formed in the conductive film 25f, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a. Fig. 9B ).

[0213] When the openings 20, 15a, and 15b are formed in the insulating layers 41c, 41b, and 41a, the conductive film 25f can be used as a hard mask. At this time, an opening is first formed in the conductive film 25f using a resist mask. Then, the insulating layers 41c, 41b, and 41a are sequentially etched using the conductive film 25f as a mask to form the openings 20, 15a, and 15b. In addition, the resist mask can also be removed after etching the conductive film 25f, during etching the insulating layers 41c, 41b, and 41a, or after the openings 20, 15a, and 15b are formed.

[0214] When the conductive film 25f, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a are etched using dry etching, fine openings 20, 15a, and 15b can be formed. Note that the present invention is not limited to this, and wet etching and dry etching may be combined or wet etching may be used for processing.

[0215] When the side wall of the opening 20 has a shape that is approximately perpendicular to the top surface of the conductive layer 24, the area of ​​the opening 20 can be reduced, so it is preferred. By adopting the above structure, a transistor with a small occupation area can be manufactured. In addition, the side wall of the opening 20 may also have a tapered shape. When the side wall of the opening 20 has a tapered shape, the coverage of the film formed inside the opening 20 can be improved. In addition, the same is true for the openings 15a and 15b.

[0216] The maximum width of the opening 20 (the maximum diameter when the opening 20 is circular when viewed from a plane) is preferably as fine as possible. For example, the maximum width of the opening 20 is preferably 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 150 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less and 5 nm or more. In particular, in order to process the opening 20 extremely finely, it is preferable to use a photolithography method using short-wavelength light such as EUV light or an electron beam.

[0217] Here, the opening 20 and the openings 15a and 15b are formed simultaneously by the same process. Thus, the manufacturing process can be simplified. Note that at this time, the layers located at the bottom of the opening 20 and the openings 15a and 15b are different from each other. Therefore, depending on the etching conditions of the insulating layer 41 (more specifically, the insulating layer 41c), sometimes the upper part of either or both of the conductive layer 24 located at the bottom of the opening 20 and the insulating layer 12 located at the bottom of the openings 15a and 15b is partially etched.

[0218] Alternatively, the opening 15a, the opening 15b, and the opening 20 may be formed in different processes. Figure 5A1 , Figure 5A2, Figure 5B1 , Figure 5B2 , Fig.5C1 , Fig.5C2 , Fig.5D1 as well as Fig.5D2 Various openings 15 and 20 are shown.

[0219] Next, heat treatment may also be performed. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, when heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas is preferably set to about 20%. In addition, heat treatment may be performed under reduced pressure. In addition, in order to compensate for the oxygen that has been separated, heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher after heat treatment is performed in an atmosphere of nitrogen gas or an inert gas. By performing the above-mentioned heat treatment, impurities such as water and hydrogen in the insulating layer 41 and the like can be reduced before depositing the oxide semiconductor film that will become the semiconductor layer.

[0220] The gas used in the above-mentioned heat treatment is preferably highly purified. For example, the moisture content in the gas used in the above-mentioned heat treatment is set to 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the insulating layer 41 and the like as much as possible.

[0221] Next, a semiconductor film 21f ( 21c ) to be the semiconductor layer 21 is deposited so as to cover the conductive film 25f , the insulating layer 41c , the opening 20 , the opening 15a , the opening 15b , and the like. Fig. 9C ).

[0222] As the semiconductor film 21f, an oxide semiconductor film can be used. When depositing the oxide semiconductor film, sputtering, CVD, MBE, PLD, ALD, etc. can be appropriately used. When the side wall of the opening 20 has a tapered shape, the oxide semiconductor film can be deposited by sputtering. In addition, when the side wall of the opening 20 is substantially perpendicular to the top surface of the substrate 11 or the side wall of the opening 20 has an inverse tapered shape, when depositing the oxide semiconductor film, it is preferred to use a deposition method with good coverage, and more preferably to use a CVD method or an ALD method, etc. For example, as the oxide semiconductor film, In-Ga-Zn oxide can be deposited.

[0223] In addition, during or after the deposition of the oxide semiconductor film, microwave treatment may be performed in an oxygen-containing atmosphere to reduce the concentration of impurities in the oxide semiconductor film. In addition, as impurities, hydrogen and carbon are particularly mentioned. By performing microwave treatment, the crystallinity of the oxide semiconductor film can sometimes be improved. Here, microwave treatment refers to, for example, treatment using a device including a power supply that generates high-density plasma using microwaves.

[0224] In addition, in the case where the semiconductor layer 21 has a stacked structure, the deposition methods of each layer may be the same or different. For example, in the case where the semiconductor layer 21 has a two-layer stacked structure, the lower layer of the oxide semiconductor film is deposited by sputtering, and the upper layer of the oxide semiconductor film is deposited by ALD. The oxide semiconductor film deposited by sputtering tends to have crystallinity. Therefore, by providing a crystalline oxide semiconductor film as the lower layer of the oxide semiconductor film, the crystallinity of the upper layer of the oxide semiconductor film can be improved. In addition. Even if a pinhole or a break is formed in the lower layer of the oxide semiconductor film deposited by sputtering, the upper layer of the oxide semiconductor film deposited by ALD with good coverage can be used to fill the portion overlapping with the pinhole or break.

[0225] The semiconductor film is preferably formed by, for example, a sputtering method using a metal oxide target.

[0226] The semiconductor film is preferably a dense film with as few defects as possible. In addition, the semiconductor film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water. In particular, a crystalline metal oxide film is preferably used as the semiconductor film.

[0227] When depositing a metal oxide film, an oxygen gas and an inactive gas (e.g., helium gas, argon gas, xenon gas, etc.) may also be mixed. Note that the higher the proportion of oxygen gas in the total deposition gas when depositing the metal oxide film (hereinafter, also referred to as the oxygen flow rate ratio), the higher the crystallinity of the metal oxide film can be, and a transistor with high reliability can be realized. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and a transistor with improved on-state current can be realized.

[0228] When the substrate temperature is high during the deposition of the metal oxide film, a denser metal oxide film with higher crystallinity can be formed. On the other hand, when the substrate temperature is low, a metal oxide film with lower crystallinity and higher conductivity can be formed.

[0229] As a deposition condition of the metal oxide film, the substrate temperature can be set to be higher than room temperature and lower than 250° C., preferably higher than room temperature and lower than 200° C., and more preferably higher than room temperature and lower than 140° C. For example, the substrate temperature is preferably higher than room temperature and lower than 140° C., thereby improving productivity. When the metal oxide film is deposited at room temperature or without intentional heating, the crystallinity can be reduced.

[0230] When using the ALD method, it is preferred to use a deposition method such as a thermal ALD (Atomic Layer Deposition) method or a PEALD (Plasma Enhanced ALD) method. The thermal ALD method has extremely high step coverage, so it is preferred. In addition, the PEALD method not only has high step coverage but also allows low-temperature deposition, so it is preferred.

[0231] For example, when a metal oxide is used for the semiconductor layer 21 , it can be deposited by an ALD method using a precursor containing a metal element constituting the metal oxide and an oxidant.

[0232] For example, when depositing In-Ga-Zn oxide, three precursors including a precursor containing indium, a precursor containing gallium, and a precursor containing zinc may be used. Alternatively, two precursors including a precursor containing indium and a precursor containing gallium and zinc may be used.

[0233] As the precursor containing indium, triethylindium, tri(2,2,6,6-tetramethyl-3,5-heptanedione)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, or the like can be used.

[0234] As a precursor containing gallium, trimethylgallium, triethylgallium, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedione)gallium, dimethylgallium chloride, diethylgallium chloride, gallium(III) chloride, etc. can be used.

[0235] In addition, as a precursor containing zinc, dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptanedione) zinc, zinc chloride, or the like can be used.

[0236] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0237] As a method for controlling the composition of the obtained film, there can be cited adjustment of the flow ratio of the source gas, the time for the source gas to flow, the order in which the source gas is flowed, etc. By adjusting the above conditions, a film with a continuously changing composition can also be deposited. In addition, two or more films with different compositions can also be deposited continuously.

[0238] Next, heat treatment is performed to supply oxygen from the insulating layer 41b to the semiconductor film 21f. In addition, heat treatment can remove hydrogen in the semiconductor film 21f and water adsorbed on the surface of the semiconductor film 21f. The heat treatment method can be as described above.

[0239] Next, unnecessary portions of the semiconductor film 21f are removed by etching to form the semiconductor layer 21. Next, unnecessary portions of the conductive film 25f are removed by etching to form the conductive layer 25( Fig. 10A ). Here, an example of using the same photomask to process the semiconductor layer 21 and the conductive layer 25 is shown. This is preferred because it simplifies the manufacturing process. Note that the semiconductor layer 21 and the conductive layer 25 may also be processed using different photomasks.

[0240] After the semiconductor layer 21 is formed, the side walls of the openings 15a and 15b are exposed. More specifically, at least a portion of the insulating layer 41b is exposed. By performing a heat treatment in the above state, the excess oxygen 16 in the insulating layer 41b can be released from the openings 15a and 15b to the outside. Note that in the case where there is a high-temperature treatment (such as a deposition process) below, oxygen can also be released from the insulating layer 41b in this process, so the heat treatment at this time can be omitted. For example, as a treatment at a high temperature, the deposition process of the insulating layer 22 and the deposition process of the insulating layer 44 can be cited.

[0241] The heat treatment can be performed in an atmosphere containing a noble gas or nitrogen. Alternatively, heating can be performed in an ultra-dry air (CDA: Clean Dry Air) atmosphere. In addition, by adopting an oxygen-containing atmosphere and controlling the oxygen partial pressure in the atmosphere, the amount of oxygen released from the insulating layer 41b can be controlled. Note that it is preferred that the atmosphere of the above-mentioned heat treatment does not contain hydrogen, water, etc. as much as possible. The heat treatment can be performed using an electric furnace, an RTA (Rapid Thermal Anneal) device, etc. By using an RTA device, the heat treatment time can be shortened. By using an electric furnace, it is easy to control the partial pressure of the gas used.

[0242] The temperature and time of the heat treatment can be set according to the film quality of the insulating layer 41b, the distance between the opening 20 and the opening 15a or 15b, the amount of oxygen released, etc. The total amount of oxygen released from the insulating layer 41b increases in proportion to the treatment temperature and treatment time.

[0243] For example, when an electric furnace is used and an ultra-dry air atmosphere is adopted, the treatment time (time other than the heating time and the cooling time) is preferably 30 minutes or more and 8 hours or less, more preferably 45 minutes or more and 4 hours or less, further preferably 50 minutes or more and 2 hours or less, and typically 1 hour or less. The treatment temperature is preferably 100°C or more and 550°C or less, more preferably 200°C or more and 500°C or less, and further preferably 250°C or more and 450°C or less.

[0244] Next, the insulating layer 22 is formed to cover the semiconductor layer 21, the conductive layer 25, the insulating layer 41, the insulating layer 12, etc. When depositing the insulating layer 22, sputtering, CVD, MBE, PLD, ALD, etc. can be used as appropriate.

[0245] The insulating layer 22 is preferably provided with a thickness as uniform as possible on the side surface of the semiconductor layer 21 in the opening 20. Therefore, it is particularly preferable to form the insulating layer 22 by a deposition method that is very excellent in coverage, such as a CVD method or an ALD method. Note that, in the case where the side wall of the opening 20 has a tapered shape, the insulating layer 22 can be deposited by a deposition method such as a sputtering method.

[0246] After forming the insulating layer 22 , a heat treatment may be performed to remove oxygen from the insulating layer 41 b . In this way, excess oxygen can be released from the insulating layer 41 b through the insulating layer 22 to the outside.

[0247] Next, a conductive film is deposited so as to cover the insulating layer 22 and unnecessary portions are removed by etching to form a conductive layer 23 ( Fig. 10B ).

[0248] Through the above steps, the transistor 10 can be manufactured.

[0249] Then, the insulating layer 44 is formed so as to cover the conductive layer 23 and the insulating layer 22. Fig. 10C ). The insulating layer 44 can be formed by the same method as the insulating layer 41a or the insulating layer 41b.

[0250] After forming the insulating layer 44, a heat treatment may be performed to remove oxygen from the insulating layer 41b. In this way, excess oxygen can be released from the insulating layer 41b to the outside through the insulating layer 22 and the insulating layer 44.

[0251] The heat treatment for removing oxygen from the insulating layer 41b can be performed at any time as long as the semiconductor layer 21 is formed. In addition, the heat treatment is not limited to one time, and can also be performed multiple times. In addition, when there is a high-temperature treatment (such as a deposition process, etc.) after the semiconductor layer 21 is formed, sometimes the treatment can also serve as the above-mentioned heat treatment.

[0252] The above is the description of the example of the manufacturing method.

[0253] At least a part of the structural examples described in this embodiment mode and the drawings corresponding to the structural examples can be combined with other structural examples, drawings, and the like as appropriate.

[0254] Implementation Method 2

[0255] In this embodiment, a display device using a semiconductor device which is one embodiment of the present invention is described with reference to the drawings.

[0256] The display device of this embodiment mode may be a high-resolution display device or a large display device. Therefore, for example, the display device of this embodiment mode may be used as a display portion of the following devices: electronic devices with large screens such as television devices, desktop or notebook personal computers, displays for computers, etc., digital signage, large-scale game machines such as pinball machines, etc.; digital cameras; digital video cameras; digital photo frames; mobile phones; portable game machines; portable information terminals; and sound reproduction devices.

[0257] In addition, the display device of this embodiment can be a high-definition display device. Therefore, for example, the display device of this embodiment can be used as a display unit of information terminal devices (wearable devices) such as watch-type and bracelet-type devices, and a display unit of wearable devices that can be worn on the head such as VR devices such as head-mounted displays (HMDs) and glasses-type AR devices.

[0258] A semiconductor device of one embodiment of the present invention can be used in a display device or a module including the display device. As a module including the display device, there can be cited a module in which the display device is equipped with a connector such as a flexible printed circuit (FPC) or TCP (Tape Carrier Package), a module in which an integrated circuit (IC) is installed by a COG (Chip On Glass) method or a COF (Chip On Film) method, etc.

[0259] Fig.11 A perspective view of the display device 100A is shown.

[0260] The display device 100A has a structure in which a substrate 152 and a substrate 151 are bonded together. Fig.11 In FIG. 1 , the substrate 152 is indicated by a dotted line.

[0261] The display device 100A includes a display portion 162 , a connection portion 140 , a circuit portion 164 , wiring 165 , and the like. Fig.11 FIG. 1 shows an example in which the display device 100A is equipped with the IC 173 and the FPC 172. Fig.11 The structure shown is called a display module including the display device 100A, an IC, and an FPC.

[0262] The connection portion 140 is disposed outside the display portion 162. The connection portion 140 may be disposed along one side or multiple sides of the display portion 162. The number of the connection portions 140 may also be one or more. Fig.11 The example in which the connection portion 140 is provided so as to surround four sides of the display portion 162 is shown. In the connection portion 140, the common electrode of the display element is electrically connected to the conductive layer, and a potential can be supplied to the common electrode.

[0263] The circuit unit 164 includes, for example, a scanning line driving circuit (also referred to as a gate driver). Alternatively, the circuit unit 164 may include both a scanning line driving circuit and a signal line driving circuit (also referred to as a source driver).

[0264] The wiring 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the wiring 165 from the outside through the FPC 172 or are input to the wiring 165 from the IC 173.

[0265] Fig.11 An example of providing IC 173 on substrate 151 by COG method or COF method is shown. As IC 173, for example, an IC including one or both of a scanning line driving circuit and a signal line driving circuit can be used. Note that the display device 100A and the display module may also adopt a structure without providing an IC. In addition, the IC may also be mounted on an FPC by COF method or the like.

[0266] For example, the semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 162 and the circuit portion 164 of the display device 100A. In addition, the semiconductor device of one embodiment of the present invention can also be used for the IC 173 .

[0267] For example, when a semiconductor device of one embodiment of the present invention is used in a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced to realize a high-definition display device. In addition, for example, when a semiconductor device of one embodiment of the present invention is used in a drive circuit of a display device (for example, one or both of a gate line drive circuit and a source line drive circuit), the area occupied by the drive circuit can be reduced to realize a display device with a narrow frame. In addition, a semiconductor device of one embodiment of the present invention has good electrical characteristics, and by using the semiconductor device in a display device, the reliability of the display device can be improved.

[0268] The display portion 162 is a region in the display device 100A that displays an image, and includes a plurality of pixels 210 that are periodically arranged. Fig.11An enlarged view of one pixel 210 is shown in FIG.

[0269] There is no particular limitation on the arrangement of pixels in the display device of this embodiment, and various methods can be used. Examples of the arrangement of pixels include stripe arrangement, S-stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, and Pentile arrangement.

[0270] Fig.11 The pixel 210 shown includes a sub-pixel 210R that displays red light, a sub-pixel 210G that displays green light, and a sub-pixel 210B that displays blue light.

[0271] Various elements can be used as display elements, for example, liquid crystal elements and light-emitting elements. In addition, MEMS (Micro Electro Mechanical Systems) elements of shutter mode or light interference mode, display elements using microcapsule mode, electrophoresis mode, electrowetting mode or electronic powder fluid (registered trademark) mode, etc. can also be used. In addition, QLED (Quantum-dot LED: quantum dot light-emitting diode) using light source and color conversion technology using quantum dot materials can also be used.

[0272] Examples of the liquid crystal element include a transmissive liquid crystal element, a reflective liquid crystal element, and a semi-transmissive liquid crystal element.

[0273] Examples of the light emitting element include self-luminous light emitting elements such as LED (Light Emitting Diode), OLED (Organic LED), and semiconductor lasers. Examples of the LED include miniature LEDs and micro LEDs.

[0274] Examples of the light-emitting substance included in the light-emitting element include substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (TADF materials), and inorganic compounds (such as quantum dot materials).

[0275] The light emitting element may emit light of infrared, red, green, blue, cyan, magenta, yellow or white, etc. In addition, when the light emitting element has a microcavity structure, the color purity can be further improved.

[0276] In a pair of electrodes included in the light-emitting element, one electrode is used as an anode and the other electrode is used as a cathode. A display device according to one embodiment of the present invention may also adopt any of the following structures: a top emission type that emits light in a direction opposite to a substrate on which the light-emitting element is formed, a bottom emission type that emits light to one side of a substrate on which the light-emitting element is formed, and a dual emission type that emits light to both sides.

[0277] Fig.12 An example of a cross section of a portion of the region including the FPC 172 , a portion of the circuit portion 164 , a portion of the display portion 162 , a portion of the connection portion 140 , and a portion of the region including the end portion of the display device 100A is shown.

[0278] Fig.12 The display device 100A shown includes transistors 205D, 205R, 205G, 205B, light-emitting elements 130R, 130G, 130B, etc. between substrates 151 and 152. The light-emitting element 130R is a display element included in the sub-pixel 210R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 210G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 210B that emits blue light.

[0279] The display device 100A adopts an SBS (Side By Side) structure. The SBS structure can optimize the material and structure of each light emitting element, thereby increasing the freedom of selecting materials and structures, and making it easy to improve brightness and reliability.

[0280] The display device 100A adopts a top emission type. In the top emission type, transistors and the like can be arranged so as to overlap with the light emitting region of the light emitting element, so that the aperture ratio of the pixel can be further increased compared with the bottom emission type.

[0281] The transistors 205D, 205R, 205G, and 205B are all formed over the substrate 151. These transistors can be manufactured by the same process.

[0282] An insulating layer 110 is provided over the substrate 151, and the transistors 205D, 205R, 205G, and 205B are provided in openings in the insulating layer 110. The insulating layer 110 has a structure in which insulating layers 110a, 110b, and 110c are stacked in this order from the substrate 151 side.

[0283] This embodiment shows an example of using a transistor of one embodiment of the present invention as transistors 205D, 205R, 205G, and 205B, in which an oxide semiconductor is used as a semiconductor and parasitic capacitance is reduced. For example, transistors 205R, 205G, and 205B are used as drive transistors for controlling a current flowing through a light-emitting element. The transistor 205D provided in the circuit portion 164 is a transistor constituting a part of the drive circuit.

[0284] Specifically, the transistors 205D, 205R, 205G, and 205B all include a conductive layer 104 serving as a gate, an insulating layer 106 serving as a gate insulating layer, a conductive layer 109 serving as one of a source electrode and a drain electrode, a conductive layer 107 serving as the other of the source electrode and the drain electrode, and a semiconductor layer 108. The conductive layer 109 and the conductive layer 107 are in contact with the semiconductor layer 108. In addition, a conductive layer 112a in contact with the conductive layer 107 and a conductive layer 112b in contact with the conductive layer 109 are provided. The conductive layer 112a and the conductive layer 112b include a conductive material having a lower resistance than the conductive layer 107 and the conductive layer 109, respectively, and are used as wiring. Here, a plurality of layers obtained by processing the same film are given the same hatching.

[0285] In this way, the display device 100A includes a transistor of one embodiment of the present invention in both the display unit 162 and the circuit unit 164. By using a transistor of one embodiment of the present invention in the display unit 162, the pixel size can be reduced and high definition can be achieved. In addition, by using a transistor of one embodiment of the present invention in the circuit unit 164, the area occupied by the circuit unit 164 can be reduced and a narrow frame can be achieved. In addition, by using a transistor of one embodiment of the present invention in one or both of the display unit 162 and the circuit unit 164, the load of the wiring can be reduced, thereby realizing a display device capable of operating at high speed, a large display device, or a display device with high resolution (large number of pixels). For the transistor of one embodiment of the present invention, reference can be made to the description of the above embodiment.

[0286] In addition, an opening 206 is provided near each of the transistors 205D, 205R, 205G, and 205B. The opening 206 is provided with an opening that passes through the insulating layer 110 and reaches the conductive layer 107. Furthermore, the insulating layer 106 and the insulating layer 218 are provided so as to cover the opening 206. In the opening 206, the side surface of the insulating layer 110b is in contact with the insulating layer 106. Therefore, the reliability of the transistors 205D, 205R, 205G, and 205B can be improved.

[0287] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention. For example, the transistor of one embodiment of the present invention and a transistor of another structure may be combined.

[0288] The display device of this embodiment may include, for example, any one or more of a planar transistor, a staggered transistor, and an inversely staggered transistor. The transistor included in the display device of this embodiment may also have any structure of a top-gate type and a bottom-gate type. Alternatively, a gate may be provided above and below the semiconductor layer forming the channel.

[0289] The display device of this embodiment may also include a transistor (Si transistor) using silicon for the channel formation region. Examples of silicon include single crystal silicon, polycrystalline silicon, amorphous silicon, and the like. In particular, a transistor containing LTPS in a semiconductor layer (hereinafter also referred to as an LTPS transistor) may be used. The LTPS transistor has high field effect mobility and good frequency characteristics. In addition, since amorphous silicon can be uniformly deposited on a large area of ​​a glass substrate, the productivity of transistors containing amorphous silicon in a semiconductor layer is high.

[0290] In addition, the display device of this embodiment may also include a transistor (OS transistor) using an oxide semiconductor (OS: Oxide Semiconductor) represented by In-Ga-Zn oxide (also referred to as IGZO) for a channel formation region. For example, a display device may be used in which a transistor using silicon as a semiconductor for forming a channel and a transistor using an oxide semiconductor as a semiconductor for forming a channel are mixed.

[0291] The transistor included in the circuit portion 164 and the transistor included in the display portion 162 may have the same structure or different structures. The plurality of transistors included in the circuit portion 164 may have the same structure or two or more structures. Similarly, the plurality of transistors included in the display portion 162 may have the same structure or two or more structures.

[0292] All transistors included in the display portion 162 may be OS transistors, all transistors included in the display portion 162 may be Si transistors, some transistors included in the display portion 162 may be OS transistors and the remaining transistors may be Si transistors.

[0293] For example, by using both LTPS transistors and OS transistors in the display portion 162, a display device with low power consumption and high driving capability can be realized. In addition, a structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. As a more preferred example, a structure in which an OS transistor is used as a transistor used as a switch for controlling conduction and non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current can be cited.

[0294] For example, one of the transistors included in the display portion 162 is used as a transistor for controlling current flowing through the light emitting element and may also be referred to as a driving transistor. One of a source and a drain of the driving transistor is electrically connected to a pixel electrode of the light emitting element.

[0295] On the other hand, one of the other transistors included in the display unit 162 is used as a switch for controlling the selection and non-selection of pixels, and may also be referred to as a selection transistor. The gate of the selection transistor is electrically connected to the gate line, and one of the source and the drain is electrically connected to the source line (signal line). The selection transistor is preferably an OS transistor. Therefore, even if the frame rate is significantly reduced (for example, below 1fps), the grayscale of the pixel can be maintained, thereby reducing power consumption by stopping the driver when displaying a static image.

[0296] An insulating layer 218 is provided to cover the transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided over the insulating layer 218 .

[0297] The insulating layer 218 is preferably used as a protective layer of the transistor. The insulating layer 218 is preferably made of a material that does not easily diffuse impurities such as water and hydrogen. Thus, the insulating layer 218 can be used as a barrier layer. By adopting this structure, it is possible to effectively suppress the diffusion of impurities from the outside into the transistor, thereby improving the reliability of the display device.

[0298] The insulating layer 218 preferably includes one or more inorganic insulating films. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Specific examples of the inorganic insulating film are as described above.

[0299] The insulating layer 235 is preferably used as a planarization layer, and an organic insulating film is suitable. As materials that can be used for the organic insulating film, for example, acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimide amide resins, siloxane resins, benzocyclobutene resins, phenolic resins, and precursors of these resins can be cited. In addition, the insulating layer 235 can also adopt a laminated structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 is preferably used as an etching protection layer. As a result, when processing the pixel electrodes 111R, 111G, 111B, etc., it is possible to suppress the formation of recesses in the insulating layer 235. Alternatively, recesses can be provided in the insulating layer 235 when processing the pixel electrodes 111R, 111G, 111B, etc.

[0300] The light emitting elements 130R, 130G, and 130B are provided on the insulating layer 235 .

[0301] The light emitting element 130R includes a pixel electrode 111R on the insulating layer 235 , an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. Fig.12 The light emitting element 130R shown emits red light (R). The EL layer 113R includes a light emitting layer that emits red light.

[0302] Similarly, the light emitting element 130G includes a pixel electrode 111G, an EL layer 113G, and a common electrode 115. The light emitting element 130G emits green light (G), and the EL layer 113G includes a light emitting layer that emits green light.

[0303] Similarly, the light emitting element 130B includes a pixel electrode 111B, an EL layer 113B, and a common electrode 115. The light emitting element 130B emits blue light (B), and the EL layer 113B includes a light emitting layer that emits blue light.

[0304] Note that Fig.12 EL layers 113R, 113G, and 113B are shown as having the same thickness, but the present invention is not limited thereto. The thicknesses of the EL layers 113R, 113G, and 113B may be different. For example, the thicknesses of the EL layers 113R, 113G, and 113B are preferably set according to the optical path length of the light emitted by each layer. Thus, a microcavity structure can be realized to improve the color purity of the light emitted from each light-emitting element.

[0305] The pixel electrode 111R is electrically connected to the conductive layer 112b included in the transistor 205R through openings provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235. Similarly, the pixel electrode 111G is electrically connected to the conductive layer 112b included in the transistor 205G, and the pixel electrode 111B is electrically connected to the conductive layer 112b included in the transistor 205B.

[0306] Each end of the pixel electrodes 111R, 111G, and 111B is covered by an insulating layer 237. The insulating layer 237 is used as a partition wall (also called a bank, a dam, or a spacer). The insulating layer 237 can be set to a single-layer structure or a stacked-layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the insulating layer 237 can use a material that can be used for the insulating layer 218 and a material that can be used for the insulating layer 235. The insulating layer 237 can electrically insulate the pixel electrode from the common electrode. In addition, the insulating layer 237 can electrically insulate the light-emitting elements adjacent to each other.

[0307] The common electrode 115 is a continuous film shared by the light emitting elements 130R, 130G, and 130B. The common electrode 115 shared by the plurality of light emitting elements is electrically connected to the conductive layer 123 provided in the connection portion 140. The conductive layer 123 and the pixel electrodes 111R, 111G, and 111B are preferably formed using the same material and the same process.

[0308] In the display device of one embodiment of the present invention, a conductive film that transmits visible light is used as the electrode on the light extraction side of the pixel electrode and the common electrode. In addition, a conductive film that reflects visible light is preferably used as the electrode on the side that does not extract light.

[0309] Alternatively, the electrode on the side where light is not extracted may be a conductive film that transmits visible light. In this case, it is preferred to configure the electrode between the reflective layer and the EL layer. In other words, the light emitted by the EL layer may also be reflected by the reflective layer and extracted from the display device.

[0310] As the material of a pair of electrodes forming the light emitting element, metals, alloys, conductive compounds and mixtures thereof can be appropriately used. As the material, specifically, metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium and neodymium and alloys appropriately combined therewith can be cited. In addition, as the material, indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide) and In-W-Zn oxide can be cited. In addition, as the material, alloys (aluminum alloys) containing aluminum such as alloys of aluminum, nickel and lanthanum (Al-Ni-La), alloys of silver and magnesium (Mg-Ag) and alloys of silver, palladium and copper (Ag-Pd-Cu, also recorded as APC) and alloys containing silver can be cited. In addition, examples of the material include elements belonging to Group 1 or Group 2 of the periodic table that are not listed above (e.g., lithium, cesium, calcium, and strontium), rare earth metals such as europium and ytterbium, alloys of appropriately combined elements, and graphene.

[0311] The light-emitting element preferably adopts a microcavity resonator (microcavity) structure. Therefore, one of a pair of electrodes included in the light-emitting element is preferably an electrode having visible light transmittance and reflectivity (semi-transmitting-semi-reflecting electrode), and the other is preferably an electrode having visible light reflectivity (reflecting electrode). When the light-emitting element has a microcavity structure, the light emitted from the light-emitting layer can be resonated between the two electrodes, and the light emitted from the light-emitting element can be enhanced.

[0312] The light transmittance of the transparent electrode is 40% or more. For example, an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more is preferably used as a transparent electrode of a light-emitting element. The reflectivity of the semi-transmissive-semi-reflective electrode to visible light is 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectivity of the reflective electrode to visible light is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the resistivity of these electrodes is preferably 1×10 -2 Ωcm or less.

[0313] The EL layers 113R, 113G, and 113B are all arranged in an island shape. Fig.12 In the embodiment, the ends of the adjacent EL layers 113R overlap with the ends of the EL layers 113G, the ends of the adjacent EL layers 113G overlap with the ends of the EL layers 113B, and the ends of the adjacent EL layers 113R overlap with the ends of the EL layers 113B. Fig.12 As shown in FIG. 1 , when an island-shaped EL layer is deposited using a high-definition metal mask, the ends of adjacent EL layers may overlap each other, but the present invention is not limited to this. That is, a structure in which adjacent EL layers do not overlap each other but are separated may be adopted. In addition, a structure in which adjacent EL layers overlap each other and adjacent EL layers do not overlap each other but are separated may be adopted in the display device.

[0314] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer contains one or more light-emitting substances. As the light-emitting substance, a substance that emits light in a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. In addition, as the light-emitting substance, a substance that emits near-infrared light can also be used.

[0315] Examples of the light-emitting substance include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0316] The light-emitting layer may include one or more organic compounds (host material, auxiliary material, etc.) in addition to the light-emitting substance (guest material). As one or more organic compounds, one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) may be used. In addition, as one or more organic compounds, a bipolar substance (a substance with high electron transport properties and hole transport properties, also referred to as a bipolar material) or a TADF material may also be used.

[0317] For example, the light-emitting layer preferably includes a combination of a phosphorescent material, a hole transport material that easily forms an exciplex, and an electron transport material. By adopting such a structure, light emission by ExTET (Exciplex-Triplet Energy Transfer) utilizing energy transfer from the exciplex to the luminescent substance (phosphorescent material) can be efficiently obtained. In addition, by selecting a combination of exciplexes that form light emitting light with a wavelength overlapping with the absorption band on the lowest energy side of the luminescent substance, energy transfer can be smoothed, thereby efficiently obtaining light emission. By adopting the above structure, high efficiency, low voltage drive, and long life of the light-emitting element can be achieved at the same time.

[0318] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a substance with high electron blocking properties (electron blocking layer), a layer containing a substance with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a substance with high hole blocking properties (hole blocking layer). In addition, the EL layer may also include one or both of a bipolar material and a TADF material.

[0319] The light emitting element may use a low molecular weight compound or a high molecular weight compound, and may further contain an inorganic compound. The layers constituting the light emitting element may be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, inkjet, or coating.

[0320] The light-emitting element may adopt a single structure (including a structure with only one light-emitting unit) or a series structure (including a structure with multiple light-emitting units). The light-emitting unit includes at least one light-emitting layer. The series structure has a structure in which multiple light-emitting units are connected in series through a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and injecting holes into the other when a voltage is applied between a pair of electrodes. By adopting a series structure, a light-emitting element capable of emitting light with high brightness can be realized. In addition, the series structure can improve reliability because the current required to obtain the same brightness can be reduced compared to the single structure. In addition, the series structure can also be referred to as a stacked structure.

[0321] exist Fig.12 When a tandem-structured light-emitting element is used, it is preferred that the EL layer 113R include a plurality of light-emitting units emitting red light, the EL layer 113G include a plurality of light-emitting units emitting green light, and the EL layer 113B include a plurality of light-emitting units emitting blue light.

[0322] A protective layer 131 is provided on the light emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded by an adhesive layer 142. The substrate 152 is provided with a light shielding layer 117. As a seal for the light emitting element, for example, a solid sealing structure or a hollow sealing structure can be adopted. Fig.12 In the embodiment, the space between the substrate 152 and the substrate 151 is filled with the adhesive layer 142, that is, a solid sealing structure is adopted. Alternatively, a hollow sealing structure in which the space is filled with an inert gas (nitrogen or argon, etc.) can also be adopted. In this case, the adhesive layer 142 can also be arranged in a manner that does not overlap with the light-emitting element. In addition, a resin different from the adhesive layer 142 arranged in a frame shape can also be used to fill the space.

[0323] The protective layer 131 is provided at least in the display portion 162, and is preferably provided in a manner covering the entire display portion 162. By providing the protective layer 131 on the light-emitting elements 130R, 130G, and 130B, the reliability of the light-emitting elements can be improved. The protective layer 131 is preferably provided in a manner covering the connection portion 140 and the circuit portion 164 in addition to the display portion 162. In addition, the protective layer 131 is preferably provided in a manner extending to the end of the display device 100A. On the other hand, in order to electrically connect the FPC 172 to the conductive layer 166, there is a portion in the connection portion 204 where the protective layer 131 is not provided.

[0324] The protective layer 131 may be a single-layer structure or a stacked structure of two or more layers. In addition, there is no restriction on the conductivity of the protective layer 131. As the protective layer 131, at least one of an insulating film, a semiconductor film and a conductive film may be used. When the protective layer 131 includes an inorganic film, the degradation of the light-emitting element may be suppressed, such as preventing oxidation of the common electrode 115, suppressing impurities (moisture, oxygen, etc.) from entering the light-emitting element, etc., thereby improving the reliability of the display device. As the protective layer 131, for example, inorganic insulating films such as oxide insulating films, nitride insulating films, oxynitride insulating films and nitride oxide insulating films may be used. Specific examples of these inorganic insulating films are as described above. In particular, the protective layer 131 preferably includes a nitride insulating film or a nitride oxide insulating film, and more preferably includes a nitride insulating film.

[0325] Alternatively, an inorganic film including ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or IGZO may be used as the protective layer 131. The inorganic film preferably has a high resistance, and more specifically, the inorganic film preferably has a resistance higher than that of the common electrode 115. The inorganic film may further include nitrogen.

[0326] When light emitted from the light emitting element is extracted through the protective layer 131, the protective layer 131 preferably has high visible light transmittance. For example, ITO, IGZO, and alumina are inorganic materials with high visible light transmittance and are therefore preferred.

[0327] As the protective layer 131, for example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used. By using this stacked structure, impurities (water, oxygen, etc.) can be suppressed from entering the EL layer.

[0328] Furthermore, the protective layer 131 may include an organic film. For example, the protective layer 131 may include both an organic film and an inorganic film. Examples of the organic film that can be used for the protective layer 131 include an organic insulating film that can be used for the insulating layer 235 .

[0329] A connection portion 204 is provided in a region of the substrate 151 that does not overlap with the substrate 152. In the connection portion 204, the wiring 165 is electrically connected to the FPC 172 through the conductive layer 166 and the connection layer 242. Here, an example is shown in which the wiring 165 adopts a single-layer structure of a conductive layer obtained by processing the same conductive film as the conductive layer 112b. Here, an example is shown in which the conductive layer 166 adopts a single-layer structure of a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B. The conductive layer 166 is exposed on the top surface of the connection portion 204. Therefore, the connection portion 204 can be electrically connected to the FPC 172 through the connection layer 242.

[0330] The display device 100A is a top emission type. Light emitted by the light emitting element is emitted to the substrate 152 side. The substrate 152 is preferably made of a material with high visible light transmittance. The pixel electrodes 111R, 111G, and 111B are made of a material that reflects visible light, and the counter electrode (common electrode 115) is made of a material that transmits visible light.

[0331] A light shielding layer 117 is preferably provided on a surface of the substrate 152 on the substrate 151 side. The light shielding layer 117 can be provided between adjacent light emitting elements, in the connection portion 140, the circuit portion 164, and the like.

[0332] Alternatively, a coloring layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When the color filter is provided so as to overlap with the light-emitting element, the color purity of light emitted from the pixel can be improved.

[0333] In addition, various optical components can be arranged on the outside of the substrate 152 (the surface on the opposite side of the substrate 151). As optical components, for example, polarizers, phase difference plates, light diffusion layers (diffusion films, etc.), anti-reflection layers, and light-focusing films (condensing films) can be cited. In addition, surface protective layers such as antistatic films that inhibit the adhesion of dust, water-repellent films that are not easily soiled, hard coatings that inhibit damage during use, and impact-absorbing layers can also be arranged on the outside of the substrate 152. For example, by providing a glass layer or a silicon dioxide layer (SiO x Layer), which can prevent the surface from being dirty or damaged, is preferred. In addition, DLC (diamond-like carbon), aluminum oxide (AlO x ), polyester materials or polycarbonate materials, etc. In addition, as the surface protection layer, it is preferred to use a material with high transmittance to visible light. In addition, the surface protection layer is preferably made of a material with high hardness.

[0334] Glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, etc. can be used for the substrate 151 and the substrate 152, respectively. A material that allows the light to pass through is used for the substrate on the side where the light is taken out from the light-emitting element. By using a flexible material for the substrate 151 and the substrate 152, the flexibility of the display device can be improved, thereby realizing a flexible display. A polarizing plate can also be used as at least one of the substrate 151 and the substrate 152.

[0335] As the substrate 151 and the substrate 152, the following materials can be used respectively: polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyether sulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamide-imide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. As at least one of the substrate 151 and the substrate 152, glass having a thickness sufficient to be flexible can also be used.

[0336] When a circular polarizer is overlapped on a display device, it is preferred to use a substrate with high optical isotropy as the substrate included in the display device. The substrate with high optical isotropy has low birefringence (it can also be said that the amount of birefringence is small). As films with high optical isotropy, triacetyl cellulose (TAC, also called triacetyl cellulose) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic resin films can be cited.

[0337] As the adhesive layer 142, various curing adhesives such as light curing adhesives such as ultraviolet curing adhesives, reaction curing adhesives, heat curing adhesives, anaerobic adhesives, etc. can be used. As these adhesives, epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, EVA (ethylene-vinyl acetate) resins, etc. can be cited. In particular, it is preferred to use materials with low moisture permeability such as epoxy resins. In addition, two-liquid mixed resins can also be used. In addition, adhesive sheets, etc. can also be used.

[0338] As the connection layer 242 , an anisotropic conductive film (ACF: Anisotropic Conductive Film), anisotropic conductive paste (ACP: Anisotropic Conductive Paste), or the like can be used.

[0339] [Display device 100B]

[0340] Fig.13 The main difference between the display device 100B shown and the display device 100A is that the former uses a light-emitting element and a coloring layer (color filter, etc.) having an EL layer 113 common to sub-pixels of each color and is a bottom emission type display device. Note that in the following description of the display device, the description of the same parts as the previously described display device is sometimes omitted.

[0341] Light emitted by the light emitting element is emitted toward the substrate 151. A material having high visible light transmittance is preferably used for the substrate 151. On the other hand, there is no limitation on the light transmittance of the material used for the substrate 152.

[0342] Fig.13 The display device 100B shown includes transistors 205D, 205R, 205G, 205B (not shown), light-emitting elements 130R, 130G, 130B, a coloring layer 132R that transmits red light, a coloring layer 132G that transmits green light, and a coloring layer 132B that transmits blue light, etc. between the substrate 151 and the substrate 152.

[0343] The light emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. Light emitted by the light emitting element 130R is extracted as red light to the outside of the display device 100B through the coloring layer 132R.

[0344] The light emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. Light emitted by the light emitting element 130G is extracted as green light to the outside of the display device 100B through the coloring layer 132G.

[0345] The light emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. Light emitted by the light emitting element 130B is extracted as blue light to the outside of the display device 100B through the coloring layer 132B.

[0346] The light emitting elements 130R, 130G, and 130B share the EL layer 113 and the common electrode 115. Compared with a structure in which each sub-pixel of each color is provided with a different EL layer, a structure in which each sub-pixel of each color shares the EL layer 113 can reduce the number of manufacturing steps.

[0347] For example, Fig.13 The light emitting elements 130R, 130G, and 130B shown emit white light. The white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0348] A light shielding layer 117 is preferably formed between the substrate 151 and the transistor. Fig.13 The example in which the light shielding layer 117 is provided on the substrate 151, the insulating layer 153 is provided on the light shielding layer 117, and the transistors 205D, 205R, 205G, and 205B (not shown) are provided on the insulating layer 153. In addition, the coloring layers 132R, 132G, and 132B are provided on the insulating layer 218, and the insulating layer 235 is provided on the coloring layers 132R, 132G, and 132B.

[0349] The pixel electrodes 111R, 111G, and 111B are each made of a material having high visible light transmittance. The common electrode 115 is preferably made of a material that reflects visible light. Since a metal with low resistance can be used for the common electrode 115 in a bottom emission display device, a voltage drop caused by the resistance of the common electrode 115 can be suppressed, and high display quality can be achieved.

[0350] A transistor according to one embodiment of the present invention can be miniaturized and its occupied area can be reduced, so that the aperture ratio of a pixel can be increased or the size of a pixel can be reduced in a bottom emission display device.

[0351] When the light-emitting elements 130R, 130G, and 130B use microcavities, they each emit light having a specific wavelength enhanced among the white light emitted by the EL layer 113. Here, even if the light-emitting element using the microcavity described above uses an EL layer that emits white light, it is also referred to as a light-emitting element that emits white light.

[0352] The white light-emitting element preferably includes two or more light-emitting layers. In the case of using two light-emitting layers to obtain white light, the light-emitting layers are selected in such a way that the light-emitting colors of the two light-emitting layers are in a complementary color relationship. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer in a complementary color relationship, a structure in which the light-emitting element as a whole emits white light can be obtained. In addition, in the case of using three or more light-emitting layers to obtain white light, a structure in which the light-emitting element as a whole emits white light can be obtained by combining the light-emitting colors of the three or more light-emitting layers.

[0353] The EL layer 113 preferably includes, for example, a light-emitting layer containing a light-emitting substance that emits blue light and a light-emitting layer containing a light-emitting substance that emits visible light having a longer wavelength than blue. The EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0354] The light-emitting element emitting white light preferably adopts a series structure. Specifically, it can adopt: a two-stage series structure including a light-emitting unit emitting yellow light and a light-emitting unit emitting blue light; a two-stage series structure including a light-emitting unit emitting red light and green light and a light-emitting unit emitting blue light; a three-stage series structure including a light-emitting unit emitting blue light, a light-emitting unit emitting yellow light, yellow-green light or green light, and a light-emitting unit emitting blue light in sequence; or a three-stage series structure including a light-emitting unit emitting blue light, a light-emitting unit emitting yellow light, yellow-green light or green light and red light, and a light-emitting unit emitting blue light in sequence, etc. For example, as the number of layers and color sequence of the light-emitting unit, there can be cited a two-stage structure in which B and Y are stacked from the anode side, a two-stage structure in which B and the light-emitting unit X are stacked, a three-stage structure in which B, Y and B are stacked, and a three-stage structure in which B, X and B are stacked. As the number of layers and color sequence of the light-emitting layer in the light-emitting unit X, there can be adopted a two-stage structure in which R and Y are stacked from the anode side, a two-stage structure in which R and G are stacked, a two-stage structure in which G and R are stacked, a three-stage structure in which G, R and G are stacked, or a three-stage structure in which R, G and R are stacked. In addition, a structure in which another layer is provided between two light-emitting layers can also be adopted.

[0355] Or, for example, Fig.13The light-emitting elements 130R, 130G, and 130B shown can also emit blue light. In this case, the EL layer 113 includes one or more light-emitting layers that emit blue light. In the sub-pixel 210B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. In addition, in the sub-pixel 210R that emits red light and the sub-pixel 210G that emits green light, by providing a color conversion layer between the light-emitting element 130R or the light-emitting element 130G and the substrate 151, the blue light emitted by the light-emitting element 130R or 130G is converted into light with a longer wavelength, thereby extracting red light or green light. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 151 on the optical path of light emitted by the light-emitting element 130R, and to provide a coloring layer 132G between the color conversion layer and the substrate 151 on the optical path of light emitted by the light-emitting element 130G. A part of the light emitted by the light-emitting element may be transmitted without being converted by the color conversion layer. By extracting the light transmitted through the color conversion layer through the coloring layer, the coloring layer can absorb light other than the desired color light, thereby improving the color purity of the light presented by the sub-pixel.

[0356] [Display device 100C]

[0357] Fig.14 The display device 100C shown is an example of a display device using an MML (Metal Mask Less) structure. That is, the display device 100C includes a light-emitting element that is manufactured without using a high-definition metal mask. Note that the stacked structure from the substrate 151 to the insulating layer 235 and the stacked structure from the protective layer 131 to the substrate 152 are the same as those of the display device 100A, so the description thereof is omitted.

[0358] exist Fig.14 In the embodiment, light emitting elements 130R, 130G, and 130B are disposed on the insulating layer 235 .

[0359] The light emitting element 130R includes a conductive layer 124R on the insulating layer 235 , a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114 . Fig.14 The light emitting element 130R shown emits red light (R). The layer 133R includes a light emitting layer that emits red light. In the light emitting element 130R, the layer 133R and the common layer 114 may be collectively referred to as an EL layer. One or both of the conductive layer 124R and the conductive layer 126R may be referred to as a pixel electrode.

[0360] Likewise, the light emitting element 130G includes a conductive layer 124G on the insulating layer 235 , a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114 . Fig.14 The light emitting element 130G shown emits green light (G). Layer 133G includes a light emitting layer that emits green light.

[0361] Likewise, the light emitting element 130B includes a conductive layer 124B on the insulating layer 235 , a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114 . Fig.14 The light emitting element 130B shown emits blue light (B). Layer 133B includes a light emitting layer that emits blue light.

[0362] In this specification and the like, an island-shaped layer provided for each light-emitting element in the EL layer included in the light-emitting element is referred to as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is referred to as a common layer 114. In addition, in this specification and the like, layer 133R, layer 133G, and layer 133B not including the common layer 114 are sometimes referred to as an island-shaped EL layer, an EL layer formed in an island shape, or the like.

[0363] Layer 133R, layer 133G, and layer 133B are separated from each other. By providing an island-shaped EL layer in each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. Therefore, crosstalk caused by unintentional light emission can be suppressed, thereby realizing a display device with very high contrast.

[0364] Note that Fig.14 In the figure, the layers 133R, 133G, and 133B are shown to have the same thickness, but the present invention is not limited thereto. The thicknesses of the layers 133R, 133G, and 133B may be different.

[0365] Conductive layer 124R is electrically connected to conductive layer 112b included in transistor 205R through openings provided in insulating layer 106, insulating layer 218, and insulating layer 235. Similarly, conductive layer 124G is electrically connected to conductive layer 112b included in transistor 205G, and conductive layer 124B is electrically connected to conductive layer 112b included in transistor 205B.

[0366] Conductive layers 124R, 124G, and 124B are formed to cover the openings provided in insulating layer 235. Concave portions of conductive layers 124R, 124G, and 124B are filled with layer 128, respectively.

[0367] Layer 128 has the function of flattening the concave portions of conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B electrically connected to conductive layers 124R, 124G, and 124B are provided on conductive layers 124R, 124G, and 124B and layer 128. Therefore, the region overlapping the concave portions of conductive layers 124R, 124G, and 124B can also be used as a light-emitting region, thereby increasing the aperture ratio of the pixel. Conductive layers 124R and 126R are preferably conductive layers used as reflective electrodes.

[0368] Layer 128 may be an insulating layer or a conductive layer. Layer 128 may be formed of various inorganic insulating materials, organic insulating materials, and conductive materials as appropriate. In particular, layer 128 is preferably formed of an insulating material, and is particularly preferably formed of an organic insulating material. For example, an organic insulating material that can be used for the above-mentioned insulating layer 237 can be used as layer 128.

[0369] Although Fig.14 2 shows an example in which the top surface of the layer 128 has a flat portion, but there is no particular limitation on the shape of the layer 128. The top surface of the layer 128 may have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0370] In addition, the height of the top surface of layer 128 may be the same or substantially the same as the height of the top surface of conductive layer 124R, or may be different from each other. For example, the height of the top surface of layer 128 may be lower or higher than the height of the top surface of conductive layer 124R.

[0371] The end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or may cover the side of the end of the conductive layer 124R. Each end of the conductive layer 124R and the conductive layer 126R preferably has a tapered shape. Specifically, each end of the conductive layer 124R and the conductive layer 126R preferably has a tapered shape with a taper angle less than 90°. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side of the pixel electrode has an inclined portion. By making the side of the pixel electrode have a tapered shape, the coverage of the EL layer provided along the side of the pixel electrode can be improved.

[0372] Since the conductive layers 124G and 126G and the conductive layers 124B and 126B are the same as the conductive layers 124R and 126R, detailed descriptions thereof will be omitted.

[0373] The top surface and side surfaces of the conductive layer 126R are covered by the layer 133R. Similarly, the top surface and side surfaces of the conductive layer 126G are covered by the layer 133G, and the top surface and side surfaces of the conductive layer 126B are covered by the layer 133B. Therefore, the entire region where the conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting region of the light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.

[0374] Part of the top surface and side surfaces of the layers 133R, 133G, and 133B are covered by insulating layers 125 and 127. A common layer 114 is provided on the layers 133R, 133G, 133B, and the insulating layers 125 and 127, and a common electrode 115 is provided on the common layer 114. Both the common layer 114 and the common electrode 115 are continuous films shared by a plurality of light-emitting elements.

[0375] exist Fig.14 There is no arrangement between the conductive layer 126R and the layer 133R. Fig.12 In other words, the display device 100C does not have an insulating layer (also referred to as a partition wall, a dam, a spacer, etc.) that contacts the pixel electrode and covers the top surface end of the pixel electrode. Therefore, the interval between adjacent light-emitting elements can be made very small. Therefore, a high-definition or high-resolution display device can be realized. In addition, there is no need for a mask for forming the insulating layer, thereby reducing the manufacturing cost of the display device.

[0376] As described above, layer 133R, layer 133G, and layer 133B all include a light-emitting layer. Layer 133R, layer 133G, and layer 133B preferably include a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. In addition, layer 133R, layer 133G, and layer 133B preferably include a light-emitting layer and a carrier blocking layer (hole blocking layer or electron blocking layer) on the light-emitting layer. In addition, layer 133R, layer 133G, and layer 133B may also include a light-emitting layer, a carrier blocking layer on the light-emitting layer, and a carrier transport layer on the carrier blocking layer. The surfaces of layer 133R, layer 133G, and layer 133B are exposed in the manufacturing process of the display device, so by providing one or both of the carrier transport layer and the carrier blocking layer on the light-emitting layer, the light-emitting layer can be prevented from being exposed to the outermost surface and the damage to the light-emitting layer can be reduced. As a result, the reliability of the light-emitting element can be improved.

[0377] The common layer 114 includes, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The light emitting elements 130R, 130G, and 130B share the common layer 114.

[0378] The side surfaces of the layers 133R, 133G, and 133B are covered with the insulating layer 125. The insulating layer 127 covers the side surfaces of the layers 133R, 133G, and 133B via the insulating layer 125.

[0379] By covering the side surfaces of the layers 133R, 133G, and 133B (or even covering a portion of the top surfaces thereof) with at least one of the insulating layer 125 and the insulating layer 127, the common layer 114 (or the common electrode 115) can be prevented from contacting the pixel electrode and the side surfaces of the layers 133R, 133G, and 133B, thereby preventing the light-emitting element from being short-circuited. Thus, the reliability of the light-emitting element can be improved.

[0380] The insulating layer 125 is preferably in contact with the side surfaces of the layers 133R, 133G, and 133B. By adopting a structure in which the insulating layer 125 is in contact with the layers 133R, 133G, and 133B, film peeling of the layers 133R, 133G, and 133B can be prevented, thereby improving the reliability of the light-emitting element.

[0381] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recessed portion of the insulating layer 125. The insulating layer 127 preferably covers at least a part of the side surface of the insulating layer 125.

[0382] By providing the insulating layer 125 and the insulating layer 127, the adjacent island-shaped layers can be buried, so that the unevenness of the formed surface of the layer (for example, the carrier injection layer, the common electrode, etc.) provided on the island-shaped layer can be reduced and further flattened. Therefore, the coverage of the carrier injection layer and the common electrode, etc. can be improved.

[0383] The common layer 114 and the common electrode 115 are arranged on the layer 133R, the layer 133G, the layer 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are arranged, steps are generated due to the area where the pixel electrode and the island EL layer are arranged and the area where the pixel electrode and the island EL layer are not arranged (the area between the light-emitting elements). The display device of one embodiment of the present invention can flatten the step by including the insulating layer 125 and the insulating layer 127, thereby improving the coverage of the common layer 114 and the common electrode 115. Therefore, poor connection caused by disconnection can be suppressed. Alternatively, the resistance increase caused by the local thin filmization of the common electrode 115 due to the step can be suppressed.

[0384] The top surface of the insulating layer 127 preferably has a highly flat shape. The top surface of the insulating layer 127 may also have at least one of a flat surface, a convex curved surface, and a concave curved surface. For example, the top surface of the insulating layer 127 preferably has a highly flat and smooth convex curved surface shape.

[0385] The insulating layer 125 may be an insulating layer containing an inorganic material. As the insulating layer 125, for example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film may be used. Specific examples of these inorganic insulating films are as described above. The insulating layer 125 may be a single-layer structure or a stacked-layer structure. In particular, the selectivity of aluminum oxide to the EL layer is high in etching, and it has a function of protecting the EL layer in the formation of the insulating layer 127, so it is preferred. In particular, by using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by the ALD method for the insulating layer 125, an insulating layer 125 with fewer pinholes and a good function of protecting the EL layer can be formed. In addition, the insulating layer 125 may also have a stacked-layer structure of a film formed by the ALD method and a film formed by the sputtering method. The insulating layer 125 may, for example, have a stacked-layer structure of an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.

[0386] The insulating layer 125 preferably has a function of a blocking insulating layer with respect to at least one of water and oxygen. In addition, the insulating layer 125 preferably has a function of suppressing the diffusion of at least one of water and oxygen. In addition, the insulating layer 125 preferably has a function of capturing or fixing (also referred to as doping) at least one of water and oxygen.

[0387] In this specification, etc., a blocking insulating layer refers to an insulating layer having a barrier property. In addition, in this specification, etc., a barrier property refers to a function of suppressing the diffusion of a corresponding substance (it can also be said that the permeability is low). Alternatively, it refers to a function of capturing or fixing a corresponding substance (also called doping).

[0388] When the insulating layer 125 is used as a blocking insulating layer or has an impurity gettering function, it can have a structure that suppresses the entry of impurities (typically, at least one of water and oxygen) that may diffuse from the outside into each light-emitting element. By adopting this structure, a light-emitting element with high reliability can be provided, and a display device with high reliability can be provided.

[0389] In addition, the impurity concentration of the insulating layer 125 is preferably low. This can prevent impurities from being mixed into the EL layer from the insulating layer 125 and deteriorating the EL layer. In addition, by reducing the impurity concentration in the insulating layer 125, the barrier property against at least one of water and oxygen can be improved. For example, it is preferable that one of the hydrogen concentration and the carbon concentration in the insulating layer 125 is sufficiently low, and it is preferable that both the hydrogen concentration and the carbon concentration are sufficiently low.

[0390] The insulating layer 127 provided on the insulating layer 125 has the function of flattening the large unevenness of the insulating layer 125 formed between adjacent light emitting elements. In other words, the insulating layer 127 improves the flatness of the surface on which the common electrode 115 is formed.

[0391] As the insulating layer 127, an insulating layer containing an organic material can be used as appropriate. As the organic material, a photosensitive organic resin is preferably used, for example, a photosensitive resin composition containing an acrylic resin is preferably used. Note that in this specification, etc., acrylic resin does not refer to only polymethacrylate or methacrylic resin, and sometimes refers to acrylic polymers in a broad sense as a whole.

[0392] In addition, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin and precursors of the above resins can also be used as the insulating layer 127. In addition, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose or alcohol-soluble polyamide resin can also be used as the insulating layer 127. In addition, photoresist can also be used as a photosensitive organic resin. As a photosensitive organic resin, a positive material or a negative material can be used.

[0393] A material that absorbs visible light may also be used as the insulating layer 127. By absorbing the light emitted from the light-emitting element by the insulating layer 127, it is possible to suppress the leakage of light from the light-emitting element through the insulating layer 127 to the adjacent light-emitting element (stray light). Therefore, the display quality of the display device can be improved. In addition, the display quality can be improved even if a polarizing plate is not used in the display device, so the display device can be made lighter and thinner.

[0394] As materials that absorb visible light, materials including pigments such as black, materials including dyes, resin materials having light absorption (e.g., polyimide, etc.), and resin materials that can be used for color filters (color filter materials) can be cited. In particular, when using a resin material formed by stacking or mixing two or more colors of color filter materials, the effect of shielding visible light can be improved, so it is preferred. In particular, by mixing three or more colors of color filter materials, a black or nearly black resin layer can be achieved.

[0395] [Display device 100D]

[0396] An example in which a light-emitting element is used as a display element is shown above, and a liquid crystal display device in which a liquid crystal element is used as a display element is described below.

[0397] As the liquid crystal element included in the display device, elements of various structures can be used. Typically, a transmissive liquid crystal element using a VA (Vertical Alignment) mode, an FFS (Fringe Field Switching) mode, or an IPS (In-Plane-Switching) mode can be used. In addition, the liquid crystal element can use not only a transmissive liquid crystal element but also a reflective or semi-transmissive liquid crystal element. In addition, the display device is preferably a normally black liquid crystal display device.

[0398] For example, as the VA mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, or the like can be used.

[0399] In addition, as the liquid crystal element, liquid crystal elements using various modes can be used. For example, in addition to the VA mode, FFS mode, and IPS mode, liquid crystal elements using the TN (Twisted Nematic) mode, the ASM (Axially Symmetric aligned Micro-cell) mode, the OCB (Optically Compensated Birefringence) mode, the FLC (Ferroelectric Liquid Crystal) mode, the AFLC (AntiFerroelectric Liquid Crystal) mode, the ECB (Electrically Controlled Birefringence) mode, the guest-host mode, and the like can be used.

[0400] Here, the liquid crystal display device is a display device that uses polarized light and the optical modulation effect of liquid crystal to control the transmission or non-transmission of light. The optical modulation effect of liquid crystal is controlled by the electric field (horizontal electric field, vertical electric field or inclined electric field) applied to the liquid crystal. As liquid crystals that can be used for liquid crystal elements, thermotropic liquid crystals, low molecular liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC: Polymer Dispersed Liquid Crystal: polymer dispersed liquid crystal), polymer network liquid crystals (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. The above-mentioned liquid crystal materials present cholesteric phases, smectic phases, cubic phases, chiral nematic phases, homogeneous phases, etc. depending on the conditions. In addition, as a liquid crystal material, any of positive liquid crystals and negative liquid crystals can be used, and appropriate liquid crystal materials can be used according to the mode or design used.

[0401] Fig.15 The display device 100D shown is a liquid crystal display device in the FFS mode.

[0402] The substrate 151 and the substrate 152 are attached to each other using the adhesive layer 144. In addition, a liquid crystal 262 is sealed in a region surrounded by the substrate 151, the substrate 152, and the adhesive layer 144. The polarizing plate 260a is located on the outer surface of the substrate 152, and the polarizing plate 260b is located on the outer surface of the substrate 151. In addition, although not shown in the figure, a backlight may be provided on the outer side of the polarizing plate 260a or the outer side of the polarizing plate 260b.

[0403] The substrate 151 is provided with transistors 205D, 205R, 205G, and 205B (not shown), a connection portion 204 , a spacer 224 , etc. The conductive layer 112 b included in the transistors 205R and 205G is electrically connected to the pixel electrode 111 of the liquid crystal element 60 .

[0404] The substrate 152 is provided with coloring layers 132R and 132G, a light shielding layer 117, an insulating layer 225, and the like.

[0405] The sub-pixels included in the display unit 162 include transistors, a liquid crystal element 60, and a coloring layer. For example, a sub-pixel that presents red light includes a transistor 205R, a liquid crystal element 60, and a coloring layer 132R that transmits red light. In addition, a sub-pixel that presents green light includes a transistor 205G, a liquid crystal element 60, and a coloring layer 132G that transmits green light. Although not shown, a sub-pixel that presents blue light also includes a transistor, a liquid crystal element 60, and a coloring layer that transmits blue light.

[0406] The liquid crystal element 60 includes a common electrode 115, a pixel electrode 111, and a liquid crystal 262. The common electrode 115 is disposed on the insulating layer 218, and the insulating layer 214 is disposed on the common electrode 115. In addition, the pixel electrode 111 is disposed on the insulating layer 214.

[0407] The pixel electrode 111 and the common electrode 115 allow visible light to pass through. That is, the liquid crystal element 60 can be a transmissive liquid crystal element. For example, when the backlight source is arranged on one side of the substrate 151, the light from the backlight source polarized by the polarizer 260b passes through the substrate 151, the liquid crystal element 60 and the substrate 152 to reach the polarizer 260a. At this time, the orientation of the liquid crystal 262 can be controlled by the voltage applied between the pixel electrode 111 and the common electrode 115, thereby controlling the optical modulation of the light. In other words, the intensity of the light emitted through the polarizer 260a can be controlled. In addition, because the light outside the specified wavelength region of the incident light is absorbed by the coloring layer, the extracted light becomes, for example, red light.

[0408] Here, as the polarizer 260a, a linear polarizer or a circular polarizer can be used. As the circular polarizer, for example, a polarizer formed by laminating a linear polarizer and a quarter-wave phase difference plate can be used. By using a circular polarizer as the polarizer 260a, external light reflection can be suppressed.

[0409] In addition, when a circular polarizer is used as the polarizer 260a, a circular polarizer or a general linear polarizer may be used as the polarizer 260b. The desired contrast ratio can be achieved by adjusting the cell gap, orientation, and driving voltage of the liquid crystal element used in the liquid crystal element 60 according to the types of polarizers used for the polarizers 260a and 260b.

[0410] A connection portion 204 is provided in a region near the end of the substrate 151. In the connection portion 204, the wiring 165 is electrically connected to the FPC 172 through the conductive layer 166 and the connection layer 242. The wiring 165 is connected to the wiring 165 through an opening provided in the insulating layer 110. Fig.15 In the illustrated structure, an example is shown in which the wiring 165 is formed using the same material and process as those of the conductive layer 112a and the conductive layer 107, and the conductive layer 166 is formed using the same material and process as those of the conductive layer 112b.

[0411] The pixel electrode 111 has a comb-teeth shape or a shape provided with slits in a plan view. The pixel electrode 111 overlaps with the common electrode 115. In addition, there is a portion on the common electrode 115 where the pixel electrode 111 is not arranged in the region overlapping with the colored layer.

[0412] In addition, in the liquid crystal element 60, both the pixel electrode 111 and the common electrode 115 can have a comb-tooth-shaped top surface shape. On the other hand, as shown in the display device 100D, in the liquid crystal element 60, by making only one of the pixel electrode 111 and the common electrode 115 have a comb-tooth-shaped top surface shape, a structure in which the pixel electrode 111 and the common electrode 115 partially overlap can be formed. As a result, the capacitance between the pixel electrode 111 and the common electrode 115 can be used as a storage capacitor, and there is no need to provide a capacitor separately, so that the aperture ratio of the display device can be improved.

[0413] An insulating layer 225 is provided on the substrate 152 side so as to cover the coloring layers 132R, 132G and the light shielding layer 117. The insulating layer 225 is used as a protective layer to prevent components included in the coloring layers 132R, 132G, etc. from diffusing into the liquid crystal 262. The insulating layer 225 can also be used as a planarization film. The insulating layer 225 can be formed using a light-transmitting organic resin.

[0414] In addition, an alignment film for controlling the alignment of the liquid crystal 262 may be provided on the surface of the pixel electrode 111 , the insulating layer 214 , the insulating layer 225 , and the like that is in contact with the liquid crystal 262 .

[0415] The configuration examples of the display device have been described above.

[0416] [Example of a method for manufacturing a display device]

[0417] Next, a method for manufacturing a display device using an MML (Metal Mask Less) structure is described. Here, a process for manufacturing a light-emitting element without using a high-definition metal mask is described in detail. FIG. 16A to FIG. 16F The cross-sectional views of three light-emitting elements and the connection portion 140 included in the display portion 162 in each process are shown.

[0418] When manufacturing a light-emitting element, a vacuum process such as evaporation and a solution process such as spin coating and inkjet can be used. As an evaporation method, physical evaporation methods (PVD methods) such as sputtering, ion plating, ion beam evaporation, molecular beam evaporation, vacuum evaporation, and chemical evaporation (CVD methods) can be cited. In particular, a functional layer (hole injection layer, hole transport layer, hole blocking layer, light-emitting layer, electron blocking layer, electron transport layer, electron injection layer, charge generation layer, etc.) included in the EL layer can be formed using evaporation (vacuum evaporation), coating (dip coating, dye coating, rod coating, spin coating, spray coating), printing (inkjet, screen printing (porcelain printing), offset printing (lithography), flexographic printing (relief printing), gravure printing or micro-contact printing, etc.) and other methods.

[0419] The island-shaped layer (including the light-emitting layer) manufactured by the manufacturing method of the display device described below is not formed using a high-precision metal mask, but is formed by processing by photolithography after the light-emitting layer is deposited on the entire surface. Therefore, a high-definition display device or a display device with a high aperture ratio that has been difficult to achieve so far can be realized. Furthermore, since the light-emitting layer can be formed separately for each color, a display device with extremely clear, high contrast and high display quality can be realized. In addition, by providing a sacrificial layer on the light-emitting layer, the damage to the light-emitting layer during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved.

[0420] For example, when a display device is composed of three light-emitting elements: a light-emitting element emitting blue light, a light-emitting element emitting green light, and a light-emitting element emitting red light, three island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer three times and processing using photolithography.

[0421] First, pixel electrodes 111R, 111G, 111B and a conductive layer 123 are formed on a substrate 151 provided with transistors 205R, 205G, 205B, etc. (not shown). Fig.16A ).

[0422] When forming the conductive film to be the pixel electrode, for example, a sputtering method or a vacuum evaporation method may be used. By forming a resist mask on the conductive film by a photolithography process and then processing the conductive film, the pixel electrodes 111R, 111G, 111B and the conductive layer 123 can be formed. The conductive film can be processed by one or both of a wet etching method and a dry etching method.

[0423] Next, a film 133Bf (which will later become a layer 133B) is formed on the pixel electrodes 111R, 111G, and 111B. Fig.16A ). The film 133Bf (latter layer 133B) includes a light-emitting layer that emits blue light.

[0424] This embodiment shows an example in which an island-shaped EL layer is first formed in a light-emitting element that emits blue light, and then an island-shaped EL layer is formed in a light-emitting element that emits light of other colors.

[0425] In the process of forming the island-shaped EL layer, the pixel electrodes in the light-emitting elements of the colors formed second and later may be damaged in the previous process. Therefore, the driving voltage of the light-emitting elements of the colors formed second and later may become high.

[0426] Therefore, when manufacturing a display device according to one embodiment of the present invention, it is preferred to start manufacturing from the island EL layer of the light-emitting element (e.g., the blue light-emitting element) that emits the shortest wavelength of light. For example, it is preferred to manufacture the island EL layer in the order of blue, green, red, or blue, red, green.

[0427] Thus, the state of the interface between the pixel electrode and the EL layer in the blue light-emitting element can be well maintained, thereby suppressing the driving voltage of the blue light-emitting element from becoming higher. In addition, the life of the blue light-emitting element can be extended and the reliability can be improved. Note that compared with the blue light-emitting element, the driving voltage rise of the red and green light-emitting elements is less affected, so the driving voltage can be reduced and the reliability can be improved as a whole display device.

[0428] Note that the order of manufacturing the island-shaped EL layers is not limited to the above order, and for example, the order of red, green, and blue may be adopted.

[0429] like Fig.16A As shown, the film 133Bf is not formed on the conductive layer 123. For example, the film 133Bf can be deposited only in a desired region using a range mask. By adopting a deposition process using a range mask and a processing process using a resist mask, a light emitting element can be manufactured with a relatively simple process.

[0430] The heat-resistant temperature of the compound contained in the film 133Bf is preferably 100°C or more and 180°C or less, more preferably 120°C or more and 180°C or less, and further preferably 140°C or more and 180°C or less. Thus, the reliability of the light-emitting element can be improved. In addition, the upper limit of the temperature allowed in the manufacturing process of the display device can be increased. Therefore, the range of selection of materials and formation methods for the display device can be expanded, thereby achieving an increase in yield and an increase in reliability.

[0431] As the heat-resistant temperature, for example, any of the glass transition point, softening point, melting point, thermal decomposition temperature and 5% weight loss temperature may be used, and the lowest temperature among the above temperatures is preferably used.

[0432] The film 133Bf can be formed by, for example, a vapor deposition method, specifically, a vacuum vapor deposition method. Alternatively, the film 133Bf can be formed by a transfer method, a printing method, an inkjet method, a coating method, or the like.

[0433] Next, a sacrificial layer 118B is formed on the film 133Bf and the conductive layer 123 ( Fig.16A ). The sacrificial layer 118B can be formed by forming a resist mask on the film to be the sacrificial layer 118B by a photolithography process and then processing the film.

[0434] By providing the sacrificial layer 118B on the film 133Bf, damage to the film 133Bf during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved.

[0435] The sacrificial layer 118B is preferably provided in a manner covering each end of the pixel electrodes 111R, 111G, and 111B. Thus, the end of the layer 133B formed in the subsequent process is located outside the end of the pixel electrode 111B. Since the entire top surface of the pixel electrode 111B can be used as a light-emitting area, the aperture ratio of the pixel can be increased. In addition, the end of the layer 133B may be damaged in the process after the layer 133B is formed, so it is preferably located outside the end of the pixel electrode 111B, that is, it is preferably not used as a light-emitting area. Thus, the uneven characteristics of the light-emitting element can be suppressed, and the reliability can be improved.

[0436] In addition, by covering the top surface and side surfaces of the pixel electrode 111B with the layer 133B, each process after forming the layer 133B can be performed without exposing the pixel electrode 111B. When the end of the pixel electrode 111B is exposed, corrosion may occur in an etching process, etc. By suppressing the corrosion of the pixel electrode 111B, the yield and characteristics of the light-emitting element can be improved.

[0437] Furthermore, it is preferable that the sacrificial layer 118B is further provided at a position overlapping with the conductive layer 123. Thus, the conductive layer 123 can be prevented from being damaged during the manufacturing process of the display device.

[0438] The sacrificial layer 118B is made of a film that is highly resistant to the processing conditions of the film 133Bf, and more specifically, a film that can increase the etching selectivity ratio with the film 133Bf.

[0439] The sacrificial layer 118B is formed at a temperature lower than the heat resistance temperature of each compound included in the film 133Bf. The substrate temperature when forming the sacrificial layer 118B is typically 200°C or less, preferably 150°C or less, more preferably 120°C or less, further preferably 100°C or less, and further preferably 80°C or less.

[0440] When the heat-resistant temperature of the compound contained in the film 133Bf is high, the deposition temperature of the sacrificial layer 118B can be increased, so it is preferred. For example, the substrate temperature when forming the sacrificial layer 118B can also be set to above 100°C, above 120°C, or above 140°C. The higher the deposition temperature, the denser and more barrier-resistant inorganic insulating film can be formed. Therefore, by depositing the sacrificial layer at the above temperature, the damage to the film 133Bf can be further reduced, thereby improving the reliability of the light-emitting element.

[0441] The deposition temperature of other layers (eg, insulating film 125f) formed on the film 133Bf is the same as described above.

[0442] The sacrificial layer 118B can be formed by, for example, sputtering, ALD (including thermal ALD and PEALD), CVD, or vacuum evaporation. Alternatively, the sacrificial layer 118B can be formed by the above-mentioned wet deposition method.

[0443] The sacrificial layer 118B (a layer provided in contact with the film 133Bf when the sacrificial layer 118B has a stacked structure) is preferably formed by a formation method that causes less damage to the film 133Bf. For example, ALD or vacuum evaporation is more preferable than sputtering.

[0444] The sacrificial layer 118B can be processed by wet etching or dry etching. The sacrificial layer 118B is preferably processed by anisotropic etching.

[0445] By using the wet etching method, the damage to the film 133Bf during the processing of the sacrificial layer 118B can be reduced compared to the dry etching method. When the wet etching method is used, for example, it is preferred to use a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixed solution containing two or more of the above. In addition, when the wet etching method is used, a mixed acid solution containing water, phosphoric acid, dilute hydrofluoric acid, and nitric acid can also be used. Note that the solution used for the wet etching process can be alkaline or acidic.

[0446] As the sacrificial layer 118B, for example, one or more of a metal film, an alloy film, a metal oxide film, a semiconductor film, an inorganic insulating film, and an organic insulating film can be used.

[0447] As the sacrificial layer 118B, for example, a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium, and tantalum, or an alloy material containing the metal material can be used.

[0448] The sacrificial layer 118B can use metal oxides such as In-Ga-Zn oxide, indium oxide, In-Zn oxide, In-Sn oxide, indium titanium oxide (In-Ti oxide), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), and indium tin oxide containing silicon.

[0449] Note that element M (M is one or more selected from aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium) may be used instead of the above-mentioned gallium.

[0450] For example, as a material with high affinity to the manufacturing process of the semiconductor, a semiconductor material such as silicon or germanium is preferably used. In addition, oxides or nitrides of the above semiconductor materials can be used. In addition, non-metallic materials such as carbon or their compounds can be used. In addition, metals such as titanium, tantalum, tungsten, chromium, aluminum, or alloys containing one or more of them can be used. In addition, oxides of the above metals such as titanium oxide or chromium oxide, or nitrides such as titanium nitride, chromium nitride, or tantalum nitride can be used.

[0451] In addition, various inorganic insulating films that can be used for the protective layer 131 can be used as the sacrificial layer 118B. In particular, the adhesion between the oxide insulating film and the film 133Bf is higher than the adhesion between the nitride insulating film and the film 133Bf, so it is preferred. For example, inorganic insulating materials such as aluminum oxide, hafnium oxide and silicon oxide can be used for the sacrificial layer 118B. As the sacrificial layer 118B, for example, an aluminum oxide film can be formed by the ALD method. By using the ALD method, damage to the substrate (especially the film 133Bf) can be reduced, so it is preferred.

[0452] For example, the sacrificial layer 118B may have a stacked structure of an inorganic insulating film (eg, an aluminum oxide film) formed by ALD and an inorganic film (eg, an In—Ga—Zn oxide film, a silicon film, or a tungsten film) formed by sputtering.

[0453] In addition, the same inorganic insulating film can be used for both the sacrificial layer 118B and the insulating layer 125 formed later. For example, an aluminum oxide film formed using the ALD method can be used for both the sacrificial layer 118B and the insulating layer 125. Here, the sacrificial layer 118B and the insulating layer 125 can use the same deposition conditions or different deposition conditions. For example, by depositing the sacrificial layer 118B under the same conditions as the insulating layer 125, the sacrificial layer 118B can be formed as an insulating layer with high barrier properties to at least one of water and oxygen. On the other hand, the sacrificial layer 118B is a layer that is mostly or entirely removed in a subsequent process, so it is preferably easy to process. Therefore, the sacrificial layer 118B is preferably deposited under conditions where the substrate temperature is lower than that of the insulating layer 125 during deposition.

[0454] An organic material may also be used as the sacrificial layer 118B. For example, a material that is soluble in a solvent that is chemically stable to at least the film located at the uppermost portion of the film 133Bf may also be used as the organic material. In particular, a material that is soluble in water or alcohol may be used appropriately. When depositing the above-mentioned material, it is preferred that the material is applied by the above-mentioned wet deposition method in a state where the material is dissolved in a solvent such as water or alcohol, and then a heating treatment is performed to evaporate the solvent. At this time, by performing the heating treatment in a reduced pressure atmosphere, the solvent can be removed at a low temperature and in a short time, and thermal damage to the film 133Bf can be reduced, which is preferred.

[0455] The sacrificial layer 118B may be made of an organic resin such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, polyamide resin soluble in alcohol, or fluororesin such as perfluoropolymer.

[0456] For example, the sacrificial layer 118B may have a stacked structure of an organic film (eg, a PVA film) formed by evaporation or any of the above-described wet deposition methods and an inorganic film (eg, a silicon nitride film) formed by sputtering.

[0457] Note that a part of the sacrificial film may remain as a sacrificial layer in the display device of one embodiment of the present invention.

[0458] Next, the sacrificial layer 118B is used as a hard mask processing film 133Bf to form a layer 133B ( Fig. 16B ).

[0459] Therefore, if Fig. 16B As shown, the stacked structure of the layer 133B and the sacrificial layer 118B remains on the pixel electrode 111B. In addition, the pixel electrode 111R and the pixel electrode 111G are exposed. In addition, the sacrificial layer 118B remains on the conductive layer 123 in the region corresponding to the connection portion 140.

[0460] The film 133Bf is preferably processed by anisotropic etching. Anisotropic dry etching is particularly preferred. Alternatively, wet etching may also be used.

[0461] Then, at least the light-emitting material is changed and the same steps as the film 133Bf formation step, the sacrificial layer 118B formation step, and the layer 133B formation step are repeated twice, thereby forming a stacked structure of the layer 133R and the sacrificial layer 118R on the pixel electrode 111R and a stacked structure of the layer 133G and the sacrificial layer 118G on the pixel electrode 111G ( Fig. 16C Specifically, the layer 133R is formed to include a light-emitting layer that emits red light, and the layer 133G is formed to include a light-emitting layer that emits green light. The sacrificial layers 118R and 118G may use the same material as that used for the sacrificial layer 118B, and may use different materials.

[0462] Note that the side surfaces of the layers 133B, 133G, and 133R are preferably perpendicular or substantially perpendicular to the formed surface. For example, the angle between the formed surface and these side surfaces is preferably not less than 60 degrees and not more than 90 degrees.

[0463] As described above, the distance between two adjacent layers among the layers 133B, 133G, and 133R formed by photolithography can be reduced to 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, or 1 μm or less. Here, the distance can be defined, for example, by the distance between two adjacent opposite ends of the layers 133B, 133G, and 133R. By reducing the distance between the island-shaped EL layers as described above, a display device with high definition and high aperture ratio can be provided.

[0464] Next, an insulating film 125f, which will later become the insulating layer 125, is formed to cover the pixel electrode, the layer 133B, the layer 133G, the layer 133R, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R, and an insulating layer 127 ( Fig.16D ).

[0465] As the insulating film 125f, it is preferable to form an insulating film with a thickness of 3 nm or more, 5 nm or more, or 10 nm or more and 200 nm or less, 150 nm or less, 100 nm or less, or 50 nm or less.

[0466] The insulating film 125f is preferably formed by, for example, the ALD method. The ALD method is preferred because deposition damage can be reduced and a film with high coverage can be deposited. As the insulating film 125f, for example, an aluminum oxide film is preferably formed by the ALD method.

[0467] Alternatively, the insulating film 125f may be formed by sputtering, CVD, or plasma CVD, which has a deposition rate faster than that of the ALD method. Thus, a display device with high reliability can be manufactured with high productivity.

[0468] The insulating film to be the insulating layer 127 is preferably formed by the above-mentioned wet deposition method (e.g., spin coating) using a photosensitive resin composition containing an acrylic resin, for example. Preferably, a heat treatment (also called pre-baking) is performed after deposition to remove the solvent in the insulating film. Next, visible light or ultraviolet light is irradiated to a portion of the insulating film to make the portion of the insulating film photosensitive. Next, development is performed to remove the exposed area in the insulating film. Next, a heat treatment (also called post-baking) is performed. In this way, a Fig.16D The insulating layer 127 is shown. Note that the shape of the insulating layer 127 is not limited to Fig.16D For example, the top surface of the insulating layer 127 may have one or more of a convex curved surface, a concave curved surface, and a flat surface. In addition, the insulating layer 127 may also cover the side surface of at least one end of the insulating layer 125, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R.

[0469] Then, if Fig.16EAs shown in FIG. 1 , the insulating layer 127 is used as a mask to perform etching to remove the insulating film 125f and a portion of the sacrificial layers 118B, 118G, and 118R. As a result, openings are formed in the sacrificial layers 118B, 118G, and 118R, respectively, and the top surfaces of the layers 133B, 133G, and 133R and the conductive layer 123 are exposed. Note that a portion of the sacrificial layers 118B, 118G, and 118R may remain at a position overlapping with the insulating layer 127 and the insulating layer 125 (see the sacrificial layers 119B, 119G, and 119R).

[0470] The etching process can be performed by dry etching or wet etching. In addition, when the insulating film 125f is deposited using the same material as the sacrificial layers 118B, 118G, and 118R, the etching process can be performed at one time, which is preferable.

[0471] As described above, by providing the insulating layer 127, the insulating layer 125, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R, it is possible to suppress the occurrence of poor connection due to disconnected portions and increased resistance due to locally thin portions in the common layer 114 and the common electrode 115 between the light-emitting elements. Thus, the display quality of the display device of one embodiment of the present invention can be improved.

[0472] Next, a common layer 114 and a common electrode 115 are sequentially formed on the insulating layer 127, the layer 133B, the layer 133G, and the layer 133R ( Fig.16F ).

[0473] The common layer 114 can be formed by a method such as evaporation (including vacuum evaporation), transfer, printing, inkjet, or coating.

[0474] The common electrode 115 can be formed by, for example, sputtering or vacuum deposition. Alternatively, a film formed by deposition and a film formed by sputtering may be stacked.

[0475] As described above, in a method for manufacturing a display device of one embodiment of the present invention, the island-shaped layer 133B, the island-shaped layer 133G, and the island-shaped layer 133R are not formed using a high-precision metal mask, but are formed by processing after depositing a film on one surface, so that the island-shaped layer can be formed with a uniform thickness. In addition, a high-definition display device or a display device with a high aperture ratio can be realized. In addition, even if the clarity or aperture ratio is high and the distance between sub-pixels is extremely small, the contact between the layers 133B, 133G, and 133R in adjacent sub-pixels can be suppressed. Thus, the leakage current between sub-pixels can be suppressed. Therefore, the crosstalk caused by unintentional light emission can be suppressed, so that a display device with a very high contrast ratio can be realized.

[0476] In addition, by providing the insulating layer 127 having a tapered end between adjacent island-shaped EL layers, disconnection can be suppressed when forming the common electrode 115, and a locally thin portion can be prevented from being formed in the common electrode 115. Thus, poor connection due to disconnected portions and increased resistance due to locally thin portions can be suppressed in the common layer 114 and the common electrode 115. Thus, a display device according to one embodiment of the present invention can achieve both high definition and high display quality.

[0477] The above is the description of the example of the method for manufacturing the display device.

[0478] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0479] Implementation 3

[0480] In this embodiment, using FIG. 17A to FIG. 19G An electronic device according to one embodiment of the present invention will be described.

[0481] The electronic device of this embodiment includes a display device of one embodiment of the present invention in a display portion. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, it can be used in the display portion of various electronic devices.

[0482] In addition, the semiconductor device of one embodiment of the present invention can be used in parts other than the display part of the electronic device. For example, when the semiconductor device of one embodiment of the present invention is used in the control part of the electronic device, it can achieve low power consumption, which is preferable.

[0483] Electronic devices include, for example, television sets, desktop or notebook personal computers, displays for computers, etc., digital signage, large-scale game consoles such as pinball machines, and other electronic devices with larger screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, sound reproduction devices, and the like.

[0484] In particular, since the display device of one embodiment of the present invention can improve the clarity, it can be suitably used in electronic devices including a smaller display unit. Examples of such electronic devices include watch-type and bracelet-type information terminal devices (wearable devices), wearable devices that can be worn on the head, VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.

[0485] A display device according to one embodiment of the present invention preferably has an extremely high resolution such as HD (pixel count of 1280×720), FHD (pixel count of 1920×1080), WQHD (pixel count of 2560×1440), WQXGA (pixel count of 2560×1600), 4K (pixel count of 3840×2160), 8K (pixel count of 7680×4320), etc. In particular, it is preferably set to a resolution of 4K, 8K or above. In addition, the pixel density (definition) in a display device according to one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and further preferably 7000 ppi or more. By using a display device having one or both of the above-mentioned high resolution and high definition, the sense of reality and depth can be further improved. In addition, the screen ratio (aspect ratio) of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can adapt to various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, etc.

[0486] The electronic device of this embodiment may also include a sensor (the sensor has the function of detecting, detecting or measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared).

[0487] The electronic device of this embodiment may have various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of executing various software (programs); a function of wireless communication; a function of reading programs or data stored in a storage medium; etc.

[0488] use 17A to 17D An example of a wearable device that can be worn on the head is described. These wearable devices have at least one of a function of displaying AR content, a function of displaying VR content, a function of displaying SR content, and a function of displaying MR content. When an electronic device has a function of displaying at least one of AR, VR, SR, MR, etc., the user's sense of immersion can be improved.

[0489] Fig.17A The electronic device 700A shown and Fig. 17BThe electronic devices 700B shown include a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical components 753, glasses frames 757 and a pair of nose pads 758.

[0490] The display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of performing extremely high-definition display can be realized.

[0491] Both the electronic device 700A and the electronic device 700B can project the image displayed by the display panel 751 onto the display area 756 in the optical member 753. Since the optical member 753 is light-transmissive, the user can see the image displayed in the display area overlapping the transmitted image seen through the optical member 753. Therefore, both the electronic device 700A and the electronic device 700B are electronic devices capable of AR display.

[0492] The electronic device 700A and the electronic device 700B may also be provided with a camera capable of photographing the front as an imaging unit. In addition, by providing an acceleration sensor such as a gyro sensor in the electronic device 700A and the electronic device 700B, the user's head orientation can be detected and an image corresponding to the direction can be displayed on the display area 756.

[0493] The communication unit includes a wireless communication device, through which a video signal etc. can be supplied. In addition to or in place of the wireless communication device, a connector to which a cable for supplying a video signal and a power supply potential can be connected may be included.

[0494] Electronic device 700A and electronic device 700B are provided with batteries, and can be charged wirelessly or by wire, or both.

[0495] The housing 721 may also be provided with a touch sensor module. The touch sensor module has a function of detecting whether the outer surface of the housing 721 is touched. Through the touch sensor module, various processes can be performed by detecting a user's tapping operation or sliding operation. For example, a process such as temporarily stopping or restarting a dynamic image can be performed through a tapping operation, and a process such as fast forwarding or rewinding can be performed through a sliding operation. In addition, by providing a touch sensor module on each of the two housings 721, the operating range can be expanded.

[0496] As the touch sensor module, various touch sensors can be used. For example, various methods such as electrostatic capacitance, resistance film, infrared, electromagnetic induction, surface acoustic wave, and optical can be used. In particular, it is preferred to use electrostatic capacitance or optical sensors in the touch sensor module.

[0497] When an optical touch sensor is used, a photoelectric conversion element may be used as a light receiving element. Inorganic semiconductors and organic semiconductors may be used for the active layer of the photoelectric conversion element, or both.

[0498] Fig. 17C The electronic device 800A shown and Fig.17D The electronic devices 800B shown each include a pair of display portions 820 , a housing 821 , a communication portion 822 , a pair of mounting portions 823 , a control portion 824 , a pair of imaging portions 825 , and a pair of lenses 832 .

[0499] The display unit 820 may be a display device according to one embodiment of the present invention. Therefore, an electronic device capable of displaying with extremely high definition may be realized, thereby allowing the user to experience a high sense of immersion.

[0500] The display unit 820 is provided at a position visible through the lens 832 inside the housing 821. In addition, by displaying different images on the pair of display units 820, three-dimensional display using parallax can be performed.

[0501] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user who wears the electronic device 800A or the electronic device 800B can see the image displayed on the display unit 820 through the lens 832 .

[0502] The electronic device 800A and the electronic device 800B preferably have a mechanism in which the left and right positions of the lens 832 and the display unit 820 can be adjusted so that the lens 832 and the display unit 820 are located at the most suitable position according to the position of the user's eyes. In addition, it is preferred to have a mechanism in which the focus is adjusted by changing the distance between the lens 832 and the display unit 820.

[0503] The user can use the mounting portion 823 to mount the electronic device 800A or the electronic device 800B on the head. Fig. 17C In the embodiment of the present invention, the mounting portion 823 is shown to have an example of a shape such as the temples of glasses (also referred to as temples), but the present invention is not limited thereto. As long as the user can wear it, the mounting portion 823 may also have a helmet-type or belt-type shape.

[0504] The imaging unit 825 has a function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, a plurality of cameras can be provided to be able to cope with various viewing angles such as telephoto and wide angle.

[0505] Note that the example including the imaging unit 825 is shown here, and a distance measuring sensor (hereinafter, also referred to as a detection unit) capable of measuring the distance to the object may be provided. In other words, the imaging unit 825 is a form of a detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as a laser radar (LIDAR: Light Detection and Ranging) may be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be obtained, and a more accurate gesture operation can be achieved.

[0506] The electronic device 800A may also include a vibration mechanism for use as a bone conduction headset. For example, any one or more of the display unit 820, the housing 821, and the mounting unit 823 may be configured to include the vibration mechanism. Thus, there is no need to separately provide audio equipment such as headphones, earphones, or speakers, and the user can enjoy images and sounds by simply installing the electronic device 800A.

[0507] Electronic device 800A and electronic device 800B may both include input terminals. Cables for supplying video signals from a video output device or the like, power for charging a battery provided in the electronic device, and the like may be connected to the input terminals.

[0508] An electronic device according to one embodiment of the present invention may also have a function of wirelessly communicating with earphone 750. Earphone 750 includes a communication unit (not shown) and has a wireless communication function. Earphone 750 can receive information (such as sound data) from the electronic device through the wireless communication function. For example, Fig.17A The electronic device 700A shown has a function of transmitting information to the headset 750 through a wireless communication function. In addition, for example Fig. 17C The electronic device 800A shown has a function of transmitting information to the headset 750 through a wireless communication function.

[0509] The electronic device may also include an earphone unit. Fig. 17B The electronic device 700B shown includes an earphone unit 727. For example, a structure in which the earphone unit 727 and the control unit are connected in a wired manner may be adopted. A part of the wiring connecting the earphone unit 727 and the control unit may also be arranged inside the housing 721 or the mounting portion 723.

[0510] same, Fig.17DThe electronic device 800B shown includes an earphone unit 827. For example, a structure in which the earphone unit 827 and the control unit 824 are connected in a wired manner may be adopted. A part of the wiring connecting the earphone unit 827 and the control unit 824 may also be arranged inside the housing 821 or the mounting portion 823. In addition, the earphone unit 827 and the mounting portion 823 may also include magnets. Thus, the earphone unit 827 can be fixed to the mounting portion 823 by magnetic force, and storage becomes easy, which is preferred.

[0511] The electronic device may also include a sound output terminal that can be connected to earphones or headphones. In addition, the electronic device may also include one or both of a sound input terminal and a sound input mechanism. As the sound input mechanism, for example, a sound receiving device such as a microphone may be used. By including the sound input mechanism in the electronic device, the electronic device can have the so-called earphone function.

[0512] As described above, as electronic devices according to one embodiment of the present invention, both glasses-type (electronic devices 700A and 700B, etc.) and goggles-type (electronic devices 800A and 800B, etc.) are preferable.

[0513] An electronic device according to one embodiment of the present invention can transmit information to the headset in a wired or wireless manner.

[0514] Fig.18A The electronic device 6500 shown is a portable information terminal device that can be used as a smartphone.

[0515] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

[0516] As the display portion 6502 , a display device which is one embodiment of the present invention can be used.

[0517] Fig.18B 65 is a schematic cross-sectional view of an end portion of a housing 6501 on one side of a microphone 6506 .

[0518] A light-transmitting protective component 6510 is provided on one side of the display surface of the housing 6501, and a display panel 6511, an optical component 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are provided in the space surrounded by the housing 6501 and the protective component 6510.

[0519] The display panel 6511 , the optical member 6512 , and the touch sensor panel 6513 are fixed to the protective member 6510 using an adhesive layer (not shown).

[0520] In a region outside the display portion 6502, a portion of the display panel 6511 is folded, and the folded portion is connected to an FPC 6515. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0521] The display panel 6511 can use a display device of one embodiment of the present invention. Thus, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while suppressing the thickness of the electronic device. In addition, by folding a portion of the display panel 6511 to provide a connection portion with the FPC 6515 on the back of the pixel portion, an electronic device with a narrow frame can be realized.

[0522] Fig. 18C 100 shows an example of a television set. In a television set 7100, a display portion 7000 is incorporated in a housing 7101. Here, a structure in which the housing 7101 is supported by a stand 7103 is shown.

[0523] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0524] The operation can be performed by using the operation switch provided in the housing 7101 and the remote control operation machine 7111 provided separately. Fig. 18C In addition, the display unit 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display unit 7000 with a finger or the like. In addition, the remote control unit 7111 may be provided with a display unit that displays information output from the remote control unit 7111. By using the operation keys or the touch panel provided in the remote control unit 7111, the channel and volume can be operated, and the image displayed on the display unit 7000 can be operated.

[0525] In addition, the television device 7100 includes a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, the modem can be connected to a wired or wireless communication network to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers, etc.) information communication.

[0526] Fig.18D 1 shows an example of a notebook personal computer. The notebook personal computer 7200 includes a housing 7211 , a keyboard 7212 , a pointing device 7213 , an external connection port 7214 , and the like. A display portion 7000 is incorporated in the housing 7211 .

[0527] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0528] Fig.18E and Fig.18F An example of digital signage is shown.

[0529] Fig.18E The digital signage 7300 shown includes a housing 7301, a display unit 7000, a speaker 7303, etc. In addition, an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, etc. may be included.

[0530] Fig.18F The digital signage 7400 is shown to be disposed on a cylindrical pillar 7401. The digital signage 7400 includes a display unit 7000 disposed along a curved surface of the pillar 7401.

[0531] exist Fig.18E and Fig.18F In the embodiment of the present invention, the display device can be used for the display portion 7000.

[0532] The larger the display unit 7000 is, the more information can be provided at one time. The larger the display unit 7000 is, the easier it is to attract people's attention, for example, the advertising effect can be improved.

[0533] By using a touch panel for the display unit 7000, not only can a static image or a dynamic image be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferred. In addition, when used for providing information such as route information or traffic information, the ease of use can be improved through intuitive operation.

[0534] like Fig.18E and Fig.18F As shown, the digital signage 7300 or the digital signage 7400 can preferably be linked with the information terminal device 7311 or the information terminal device 7411 such as a smartphone carried by the user through wireless communication. For example, the advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal device 7311 or the information terminal device 7411. In addition, by operating the information terminal device 7311 or the information terminal device 7411, the display of the display unit 7000 can be switched.

[0535] The game can be executed on the digital signage 7300 or the digital signage 7400 using the screen of the information terminal device 7311 or the information terminal device 7411 as an operation unit (controller). Thus, an unspecified number of users can participate in the game at the same time and enjoy the game.

[0536] FIG. 19A to FIG. 19GThe electronic device shown includes a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connecting terminal 9006, a sensor 9007 (the sensor has the function of detecting, detecting or measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared), a microphone 9008, etc.

[0537] exist FIG. 19A to FIG. 19G In the embodiment of the present invention, the display device can be used for the display portion 9001.

[0538] FIG. 19A to FIG. 19G The electronic device shown has various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of controlling processing by using various software (programs); a function of wireless communication; a function of reading out a program or data stored in a storage medium and processing it; etc. Note that the functions of the electronic device are not limited to the above functions, but may have various functions. The electronic device may also include multiple display units. In addition, a camera or the like may be provided in the electronic device so that it has the following functions: a function of taking a static image or a dynamic image, and storing the taken image in a storage medium (an external storage medium or a storage medium built into the camera); a function of displaying the taken image on a display unit; etc.

[0539] Below, we explain in detail FIG. 19A to FIG. 19G Electronic equipment shown.

[0540] Fig.19A 9101 is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used as a smart phone, for example. Note that a speaker 9003, a connection terminal 9006, a sensor 9007, etc. can also be provided in the portable information terminal 9101. In addition, as the portable information terminal 9101, text or image information can be displayed on multiple surfaces. Fig.19A 9050. In addition, information 9051 indicated by a dotted rectangle may be displayed on another surface of the display unit 9001. Examples of information 9051 include information indicating that an email, SNS, or phone call has been received; a title of the email or SNS; a sender's name of the email or SNS; a date; a time; a remaining battery level; and radio wave strength. Alternatively, icon 9050 may be displayed at a location where information 9051 is displayed.

[0541] Fig.19B 9102 is a three-dimensional diagram showing a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, when the portable information terminal 9102 is placed in a jacket pocket, the user can confirm the information 9053 displayed at a position viewed from above the portable information terminal 9102. For example, the user can confirm the display without taking the portable information terminal 9102 out of the pocket, thereby determining whether to answer a call.

[0542] Fig.19C 9103. The tablet terminal 9103 can execute various application software such as mobile phone, reading and editing of e-mails and articles, playing music, network communication, computer games, etc. The tablet terminal 9103 includes a display portion 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the housing 9000, an operation key 9005 used as a button for operation on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

[0543] Fig.19D 9001 is a three-dimensional diagram showing a watch-type portable information terminal 9200. The portable information terminal 9200 can be used, for example, as a smart watch (registered trademark). In addition, the display surface of the display unit 9001 is curved, and a display can be performed along its curved display surface. In addition, the portable information terminal 9200 can perform hands-free calls, for example, by communicating with a headset capable of wireless communication. In addition, by using the connection terminal 9006, the portable information terminal 9200 can perform data transmission and charging with other information terminals. Charging can also be performed by wireless power supply.

[0544] FIG. 19E to FIG. 19G 9201 is a perspective view showing a foldable portable information terminal. Fig.19E is a perspective view of the portable information terminal 9201 in an unfolded state. Figure 19G This is a three-dimensional diagram of the folded state. Fig.19F is from Fig.19E Status and Figure 19G The portable information terminal 9201 is easy to carry in the folded state, and has a large display area that is seamlessly spliced ​​in the unfolded state, so the display is easy to browse. The display unit 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by hinges 9055. The display unit 9001 can be bent within a range of a curvature radius of 0.1 mm or more and 150 mm or less, for example.

[0545] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0546] Example

[0547] Next, the results of manufacturing a transistor according to one embodiment of the present invention, observing its cross section, and evaluating its electrical characteristics and reliability are described.

[0548] In this embodiment, the manufacturing method shown above is used to manufacture the embodiment 1. Figures 1A to 1C The transistor shown.

[0549] As the insulating layer 12, a silicon nitride film with a thickness of about 30 nm formed by a plasma CVD method is used. As the conductive layer 24, a stacked film of an ITSO film with a thickness of about 10 nm, a copper film with a thickness of about 300 nm, and an ITSO film with a thickness of about 100 nm formed by a sputtering method is used. As the insulating layer 41, a stacked film of a silicon nitride film with a thickness of about 100 nm, a silicon oxynitride film with a thickness of about 500 nm, and a silicon nitride film with a thickness of about 150 nm, respectively, formed by a plasma CVD method, is used. As the conductive layer 25, an ITSO film with a thickness of about 100 nm formed by a sputtering method is used. An opening (opening 20, openings 15a, 15b) reaching the insulating layer 12 is formed in the insulating layer 41, and then an In-Ga-Zn oxide film with a thickness of about 35 nm is formed as the semiconductor layer 21 by a sputtering method, and then a heat treatment is performed at 350° C. for 1 hour in an ultra-dry air atmosphere using an electric furnace. Then, the semiconductor layer 21 is processed. As the insulating layer 22, a silicon oxynitride film having a thickness of about 50 nm formed by a plasma CVD method at a substrate temperature of 350° C. was used. As the conductive layer 23, a stacked film of a titanium film having a thickness of about 50 nm, an aluminum film having a thickness of about 200 nm, and a titanium film having a thickness of about 50 nm formed by a sputtering method was used. As the insulating layer 44, a silicon oxynitride film having a thickness of about 300 nm formed by a plasma CVD method at a substrate temperature of 350° C. was used. After the insulating layer 44 was formed, a heat treatment was performed at 300° C. for 1 hour in an ultra-dry air atmosphere using an electric furnace.

[0550] Thus, a transistor is manufactured.

[0551] Fig. 20A This is an optical microscope image of the manufactured transistor and its surroundings. The opening 20 is located in the center, and the openings 15a and 15b are located on the left and right sides of the opening 20. A portion of the opening 15a overlaps with the conductive layer 23. The diameter of the opening 20 is about 2 μm.

[0552] Fig. 20B It is along Fig. 20A The distance from the side wall of the opening 20 to the side wall of the opening 15b (the width of the insulating layer 41) is about 1.3 μm.

[0553] Fig.21 The Id-Vg characteristics of the transistor are shown. The vertical axis represents the source-drain current (Id) in a logarithmic axis, and the horizontal axis represents the source-gate voltage (Vg). Fig.21 The characteristics when the source-drain voltage (Vd) is 1V and 10V are shown. Fig.21 As shown, good electrical characteristics of normally-off can be confirmed.

[0554] In addition, the above transistor was subjected to PBTS test. The stress voltage (Vg) was 10V, the temperature was 60°C, and the test time was 1 hour. As a result, the initial threshold voltage was 0.49V and the variation of the threshold voltage was about 0.20V. From the above results, it can be seen that the reliability of the transistor is extremely high.

[0555] According to this example, it was confirmed that the transistor of one embodiment of the present invention has good electrical characteristics and high reliability.

Claims

1. A semiconductor device, include: transistor; as well as The first insulating layer, The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer and a second insulating layer. The first insulating layer includes a first layer and a second layer on the first layer, The first insulating layer is located on the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is located on the second layer, The semiconductor layer has a portion in contact with the first conductive layer, a portion in contact with the second conductive layer, and a portion in contact with a side surface of the first layer in the first opening. The second insulating layer covers the semiconductor layer in the first opening, The third conductive layer covers the second insulating layer in the first opening, The first insulating layer includes a second opening at a position different from the first opening, The second insulating layer has a portion in contact with the first layer within the second opening, The first layer includes an oxide insulating film, Furthermore, the second layer includes an insulating film having oxygen barrier properties.

2. The semiconductor device according to claim 1, The second opening is located at a position that does not overlap with the second conductive layer when viewed from a plane.

3. The semiconductor device according to claim 2, The second opening has a portion overlapping the third conductive layer.

4. The semiconductor device according to claim 2, The second opening has a portion overlapping the first conductive layer.

5. The semiconductor device according to claim 1, The second opening passes through the second layer to reach the first layer.

6. The semiconductor device according to claim 5, wherein the first layer has a recess overlapping the second opening, And the second insulating layer contacts a surface of the recessed portion of the first layer within the second opening.

7. The semiconductor device according to claim 1, wherein the second opening passes through the second layer and the first layer, And the second insulating layer contacts the side surface of the first insulating layer in the second opening.

8. The semiconductor device according to claim 1, wherein the first insulating layer includes a third layer located below the first layer, And the second opening passes through the second layer and the first layer to reach the third layer.

9. The semiconductor device according to claim 1, wherein the first insulating layer includes a third layer located below the first layer, And the second opening passes through the second layer, the first layer and the third layer.

10. The semiconductor device according to claim 1, wherein the first layer comprises silicon oxide, And the second layer includes silicon nitride or aluminum oxide.

11. The semiconductor device according to claim 1, The shortest distance between the first opening and the second opening is greater than or equal to 0.1 μm and less than or equal to 100 μm.

12. A method for manufacturing a semiconductor device, comprising the following steps: forming a first layer and a second layer on the first conductive layer; forming a second conductive layer on the second layer; forming a first opening reaching the first conductive layer and a second opening at a position separated from the first opening in the first layer and the second layer; performing a heat treatment after forming a semiconductor film covering the first opening and the second opening and contacting each of the first conductive layer and the second conductive layer; etching a portion of the semiconductor film to expose the second opening; forming an insulating layer covering the semiconductor film and the second opening; as well as forming a third conductive layer on the insulating layer and overlapping the semiconductor layer; wherein the first layer comprises an oxide insulating film, Furthermore, the second layer includes an insulating film having oxygen barrier properties.

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