Semiconductor device and manufacturing method of semiconductor device

Abstract

The invention provides a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a substrate structure; the groove gate parts are sequentially distributed in a preset direction and located in the substrate structure, and the preset direction is perpendicular to the thickness direction of the substrate structure; the insulating layer is located on part of the surface of one side of the substrate structure, an accommodating cavity is formed between the insulating layer and the substrate structure, and the orthographic projection of the insulating layer on the substrate structure and the orthographic projection of the trench gate part on the substrate structure are at least partially overlapped; the plurality of conductive parts are one of source metal parts or drain metal parts, at least one of the plurality of conductive parts is used for inputting signals, and at least two of the plurality of conductive parts are used for outputting signals; and at least one trench gate part is arranged between the conductive part for inputting the signal and the conductive part for outputting the signal in the preset direction. The technical problem of how to meet the requirement of secondary wiring of a semiconductor device in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] The chip scale package (CSP) itself has a high degree of integration, so it is required to realize the functional layout and adjustment of the device in terms of signal transmission in an integrated manner during packaging. The secondary wiring redistributes the first metal layer into new contact areas according to the functions and application needs. When the chip pads are redistributed, the plating channels of the redistributed pads are also formed to adapt to the new contact holes or pads, which reduces the difficulty of functional layout and routing during packaging and improves the functionality and integration of the chip.

[0003] Therefore, there is an urgent need for a semiconductor device that can meet the needs of secondary wiring. Summary of the invention

[0004] The main purpose of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, so as to solve the problem in the prior art of how the semiconductor device can meet the demand for secondary wiring.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a semiconductor device is provided, comprising: a substrate structure; a plurality of trench gate portions distributed in sequence in a preset direction, located in the substrate structure, the preset direction being perpendicular to the thickness direction of the substrate structure; an insulating layer, located on a partial surface of one side of the substrate structure, a receiving cavity being provided between the insulating layer and the substrate structure, the orthographic projection of the insulating layer on the substrate structure at least partially overlapping with the orthographic projection of the trench gate portion on the substrate structure; a plurality of conductive portions, located in the receiving cavity, on the surface of the insulating layer away from the substrate structure, and on the surface of one side of the substrate structure, the conductive portion being one of a source metal portion or a drain metal portion, at least one of the plurality of conductive portions being used for inputting signals, at least two of the plurality of conductive portions being used for outputting signals, and at least one of the trench gate portions being provided between the conductive portion for inputting signals and the conductive portion for outputting signals in the preset direction.

[0006] Furthermore, the semiconductor device further includes: a first doped region located on a surface of the trench gate portion close to a side of the substrate structure.

[0007] Further, the base structure includes: a substrate; a first sub-doping layer, located on the surface of one side of the substrate, the first sub-doping layer is in contact with the side walls of each of the trench gate portions and the surface of the first doping region close to the substrate, and the doping type of the first sub-doping layer is different from the doping type of the first doping region; a second sub-doping layer, located on the partial surface of the first sub-doping layer away from the substrate side and between two adjacent trench gate portions, the doping type of the second sub-doping layer is the same as the doping type of the first doping region; a third sub-doping layer, located on the partial surface of the first sub-doping layer away from the substrate side and on the surface of the second sub-doping layer away from the substrate side, the third sub-doping layer includes a plurality of second doping regions and third doping regions alternately arranged along a first direction, the doping type of the second doping region is different from the doping type of the third doping region, and the first direction is perpendicular to the thickness direction of the semiconductor device.

[0008] Furthermore, the doping concentration of the first doping region is greater than the doping concentration of the second sub-doping layer.

[0009] Furthermore, at least one of the second doping region or the third doping region is located on a side of the trench gate portion close to an edge of the semiconductor device.

[0010] Furthermore, at least one of the second doping region or the third doping region is located on a side of the trench gate portion close to an edge of the semiconductor device.

[0011] Furthermore, the length of the surface of the trench gate portion close to the substrate side from the predetermined surface is a first length, the length of the surface of the second sub-doping layer close to the substrate side from the predetermined surface is a second length, the second length is greater than the first length, and the predetermined surface is the surface of the base structure away from the insulating layer.

[0012] Furthermore, the length of the surface of the second sub-doped layer away from the substrate side from the predetermined surface is a third length, the length of the surface of the trench gate portion away from the substrate side from the predetermined surface is a fourth length, the fourth length is greater than the third length, and the predetermined surface is the surface of the base structure away from the insulating layer.

[0013] Furthermore, the trench gate portion includes: a polysilicon layer located in the base structure; and a gate oxide layer located on the sidewall of the polysilicon layer and on the surface of the polysilicon layer on a side close to the base structure.

[0014] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate structure, the substrate structure having a plurality of grooves; forming a trench gate portion in each of the grooves; forming an insulating layer on the surface of the trench gate portion and on a part of the surface of the substrate structure, with a receiving cavity between the insulating layer and the substrate structure; forming a conductive portion in the receiving cavity, on a surface of the insulating layer away from the substrate structure, and on the surface of the substrate structure, the conductive portion being one of a source metal portion or a drain metal portion, at least one of the plurality of conductive portions being used for inputting a signal, at least two of the plurality of conductive portions being used for outputting a signal, and at least one of the trench gate portions being provided between the conductive portion for inputting a signal and the conductive portion for outputting a signal in a preset direction, and the preset direction being perpendicular to the thickness direction of the substrate structure.

[0015] Applying the technical solution of the present invention, a semiconductor device is provided, comprising a substrate structure; a plurality of trench gate portions distributed in sequence in a preset direction, located in the substrate structure, the preset direction being perpendicular to the thickness direction of the substrate structure; an insulating layer, located on a partial surface of one side of the substrate structure, a receiving cavity being provided between the insulating layer and the substrate structure, the orthographic projection of the insulating layer on the substrate structure at least partially overlapping with the orthographic projection of the trench gate portion on the substrate structure; a plurality of conductive portions, located in the receiving cavity, on the surface of the insulating layer away from the substrate structure, and on the surface of one side of the substrate structure, the conductive portion being one of a source metal portion or a drain metal portion, at least one of the plurality of conductive portions being used for inputting signals, at least two of the plurality of conductive portions being used for outputting signals, and at least one trench gate portion being provided between the conductive portion for inputting signals and the conductive portion for outputting signals in the preset direction. By arranging both the source metal part and the drain metal part on the surface of the device, and a part of the conductive part is located on the side of the insulating layer away from the substrate structure, and the other part of the conductive part is located on the side of the insulating layer close to the substrate structure, that is, the conductive part is divided into two layers, electrical isolation and pad redistribution between conductive parts with different functions can be achieved, thereby realizing the functional layout and adjustment of the device in signal transmission, meeting the requirements of secondary wiring, and solving the technical problem of how semiconductor devices in the prior art meet the requirements of secondary wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0017] Figure 1 A schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention is shown;

[0018] Figure 2 A schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention is shown;

[0019] Figure 3 A schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention is shown;

[0020] Figure 4 A schematic structural diagram of another semiconductor device provided according to an embodiment of the present invention is shown;

[0021] Figure 5 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;

[0022] Figure 6 A schematic structural diagram of a substrate structure provided according to an embodiment of the present invention is shown;

[0023] Figure 7 Shown in Figure 6 A schematic diagram of a structure in which a trench gate portion is formed on the basis of

[0024] Figure 8 Shown in Figure 7 Schematic diagram of the structure of forming an insulating layer on the basis of.

[0025] The above drawings include the following reference numerals:

[0026] 100, base structure; 101, trench gate portion; 102, insulating layer; 103, conductive portion; 104, first doped region; 105, substrate; 106, first sub-doped layer; 107, second sub-doped layer; 108, third sub-doped layer; 109, second doped region; 110, third doped region; L1, first length; L2, second length; L3, third length; L4, fourth length; 111, polysilicon layer; 112, gate oxide layer; 113, groove; 114, accommodating cavity. DETAILED DESCRIPTION

[0027] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0028] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] As introduced in the background technology, the prior art lacks semiconductor devices that meet the requirements of secondary wiring. To solve the above problem, the embodiments of the present application provide a semiconductor device and a method for manufacturing the semiconductor device.

[0031] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0032] Figure 1 is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present application. Figure 1 As shown, the semiconductor device includes:

[0033] Base structure 100;

[0034] Specifically, the material of the substrate structure may be silicon or silicon carbide.

[0035] A plurality of trench gate portions 101 sequentially distributed in a preset direction are located in the substrate structure 100 , and the preset direction is perpendicular to the thickness direction of the substrate structure 100 ;

[0036] Specifically, the spacings between the plurality of trench gate portions may be the same or different. Furthermore, the depths of the plurality of trench gate portions may be the same or different. The number of the trench gate portions may be as follows: Figure 1 The two shown may also be more than two, and continue to be arranged along the preset direction.

[0037] An insulating layer 102 is located on a portion of the surface of one side of the substrate structure 100, a receiving cavity is provided between the insulating layer 102 and the substrate structure 100, and an orthographic projection of the insulating layer 102 on the substrate structure 100 at least partially overlaps with an orthographic projection of the trench gate portion 101 on the substrate structure 100;

[0038] In practical applications, the orthographic projection of the trench gate portion on the substrate structure is located in the orthographic projection of the insulating layer on the substrate structure.

[0039] A plurality of conductive parts 103 are located in the accommodating cavity, on the surface of the insulating layer 102 away from the substrate structure 100, and on the surface of one side of the substrate structure 100. The conductive part 103 is a source metal part or a drain metal part. At least one of the plurality of conductive parts 103 is used for inputting signals, and at least two of the plurality of conductive parts 103 are used for outputting signals. At least one trench gate part 101 is provided between the conductive part 103 for inputting signals and the conductive part 103 for outputting signals in the preset direction.

[0040] Specifically, the insulating layer is used to protect the conductive part and to achieve insulation between the conductive parts. In a preset direction, the insulating layer can be used to insulate two adjacent conductive parts. In the thickness direction of the semiconductor device, the insulating layer can also be used to insulate two different conductive parts. When the number of trench gate parts is more than two, the insulating layer and the conductive part can continue to be arranged alternately along the preset direction. Structurally, the signal input terminal and the signal output terminal are separated by at least one trench gate to ensure that the power line passes through the bottom of the trench gate, achieves vertical withstand voltage, and makes full use of the structural thickness in the vertical direction.

[0041] Through this embodiment, a semiconductor device is provided, including a substrate structure; a plurality of trench gate portions distributed in sequence in a preset direction, located in the substrate structure, the preset direction being perpendicular to the thickness direction of the substrate structure; an insulating layer, located on a portion of the surface on one side of the substrate structure, a receiving cavity being provided between the insulating layer and the substrate structure, the orthographic projection of the insulating layer on the substrate structure at least partially overlapping with the orthographic projection of the trench gate portion on the substrate structure; a plurality of conductive portions, located in the receiving cavity, on the surface of the insulating layer away from the substrate structure, and on the surface of one side of the substrate structure, the conductive portion being one of a source metal portion or a drain metal portion, at least one of the plurality of conductive portions being used for inputting signals, at least two of the plurality of conductive portions being used for outputting signals, and at least one trench gate portion being provided between the conductive portion for inputting signals and the conductive portion for outputting signals in the preset direction. By arranging both the source metal part and the drain metal part on the surface of the device, and a part of the conductive part is located on the side of the insulating layer away from the substrate structure, and the other part of the conductive part is located on the side of the insulating layer close to the substrate structure, that is, the conductive part is divided into two layers, electrical isolation and pad redistribution between conductive parts with different functions can be achieved, thereby realizing the functional layout and adjustment of the device in signal transmission, meeting the requirements of secondary wiring, and solving the technical problem of how semiconductor devices in the prior art meet the requirements of secondary wiring.

[0042] In one embodiment, if Figure 2 As shown, the semiconductor device further includes: a first doping region 104, which is located on the surface of the trench gate portion 101 close to the substrate structure 100. The positions of the insulating layer 102 and the conductive portion 103 are arranged similar to Figure 1 The above-mentioned configuration of the first doping region can further reduce the risk of the bottom of the gate structure being broken down.

[0043] Specifically, during the manufacturing process of the trench gate, the voltage resistance at the bottom of the trench gate portion is reduced due to unreasonable structural design or improper material selection, or improper processing or assembly. Forming a highly doped first doping region at the bottom of the trench can increase the voltage resistance at the bottom of the trench gate portion, further avoiding the occurrence of breakdown, thereby ensuring the normal operation of the device. The first doping region can be set between each of the above-mentioned trench gate portions and the substrate structure, or the first doping region can be set between only a portion of the trench gate portions and the substrate structure.

[0044] In other embodiments, Figure 3 As shown, the substrate structure 100 includes: a substrate 105; a first sub-doping layer 106, which is located on the surface of one side of the substrate 105, the first sub-doping layer 106 is in contact with the sidewalls of each of the trench gate portions 101 and the surface of the first doping region 104 close to the substrate 105, and the doping type of the first sub-doping layer 106 is different from the doping type of the first doping region 104; a second sub-doping layer 107, which is located on a portion of the surface of the first sub-doping layer 106 away from the substrate 105 and located between two adjacent trench gate portions 101. 1, the doping type of the second sub-doping layer 107 is the same as the doping type of the first doping region 104; the third sub-doping layer 108 is located on the surface of the first sub-doping layer 106 on the side away from the substrate 105 and the surface of the second sub-doping layer 107 on the side away from the substrate 105, the third sub-doping layer 108 includes a plurality of second doping regions and third doping regions arranged alternately along a first direction, the doping type of the second doping region is different from the doping type of the third doping region, and the first direction is perpendicular to the thickness direction of the semiconductor device. The conductive portion 103 is arranged at a position similar to Figure 2 The doping type and position setting of the first sub-doping layer, the second sub-doping layer and the third sub-doping layer can further improve the voltage resistance performance of the semiconductor device.

[0045] Specifically, the material of the substrate may be silicon or silicon carbide. Any of the second sub-doped layers may form a PN junction with the first sub-doped layer, thereby increasing the breakdown voltage of the semiconductor device. When the semiconductor device is subjected to a high voltage, the charges in the second sub-doped layer and the first sub-doped layer will generate an electric field, preventing the charges from flowing in the semiconductor device, thereby improving the withstand voltage performance of the device. In addition, the second sub-doped layer and the first sub-doped layer may also increase the junction capacitance of the device, reduce the electric field strength, thereby reducing the possibility of breakdown, and further improving the withstand voltage performance of the semiconductor device.

[0046] In order to further improve the voltage resistance performance of the semiconductor device, in some embodiments, the doping concentration of the first doping region is greater than the doping concentration of the second sub-doping layer.

[0047] Specifically, forming a highly doped first doping region at the bottom of the trench can increase the voltage resistance at the bottom of the trench gate portion, further avoiding the occurrence of breakdown, thereby ensuring the normal operation of the device. In addition, the doping concentration of the first doping region should not be too large, and the doping type of the first doping region is the same as the doping type of the second sub-doping layer.

[0048] In another embodiment, Figure 3 As shown, at least one of the second doping region 109 or the third doping region 110 is located on the edge of the semiconductor device near the trench gate portion 101. The above arrangement can improve the contact resistance and electrical performance of the edge region of the semiconductor device, and further improve the performance and stability of the semiconductor device.

[0049] In practical applications, the second doped region can be formed by ion implantation and annealing activation. Ion implantation can change the material properties of the contact area, improve the electron transfer efficiency, and reduce the contact resistance; while annealing activation can promote the diffusion and activation of the implanted ions in the material, further improving the electrical properties of the contact area. These steps can help improve the performance of semiconductor devices, reduce power consumption, extend service life, and improve stability. The second doped region or the third doped region located at the edge of the semiconductor device can contact the conductive portion. The orthographic projection of the conductive portion on the substrate structure at least partially overlaps with the orthographic projection of the second doped region or the third doped region on the substrate structure.

[0050] In some specific embodiments, such as Figure 3 As shown, at least one of the second doping region 109 and the third doping region 110 is located between two adjacent trench gate portions 101. The above arrangement can improve the contact resistance and electrical performance of the middle region of the semiconductor device, and further improve the performance and stability of the semiconductor device.

[0051] Specifically, the second doping region and the third doping region located between two adjacent trench gate portions may contact the conductive portion. The orthographic projection of the conductive portion on the substrate structure at least partially overlaps with the orthographic projection of the second doping region on the substrate structure. The orthographic projection of the conductive portion on the substrate structure at least partially overlaps with the orthographic projection of the third doping region on the substrate structure.

[0052] In another embodiment, Figure 3 As shown, the length of the surface of the trench gate portion 101 close to the substrate 105 side from the predetermined surface is a first length L1, the length of the surface of the second sub-doped layer 107 close to the substrate 105 side from the predetermined surface is a second length L2, the second length L2 is greater than the first length L1, and the predetermined surface is the surface of the base structure 100 away from the insulating layer 102. The above arrangement can further ensure the stability and safety of the trench gate portion.

[0053] Specifically, if L2 is less than L1, that is, the depth of the second sub-doping layer exceeds the depth of the trench gate portion, it may cause the trench gate structure to collapse or become unstable, seriously affecting the stability and safety of the trench gate portion. Therefore, in order to avoid this situation, the second length L2 is greater than the first length L1.

[0054] In some other embodiments, Figure 3 As shown, the length of the surface of the second sub-doped layer 107 away from the substrate 105 is a third length L3 from the predetermined surface, the length of the surface of the trench gate portion 101 away from the substrate 105 is a fourth length L4 from the predetermined surface, the fourth length L4 is greater than the third length L3, and the predetermined surface is the surface of the base structure 100 away from the insulating layer 102. The above arrangement can further ensure the stable operation of the semiconductor device.

[0055] Specifically, there is a PN junction between the top of the second sub-doped layer and the top of the trench structure. If the top of the second sub-doped layer exceeds the top of the trench structure, the PN junction will be broken down, thereby affecting the normal operation of the device. Therefore, in order to ensure the normal operation and stability of the device, the top of the second sub-doped layer shall not exceed the top of the trench structure.

[0056] In other embodiments, Figure 4As shown, the trench gate portion 101 includes: a polysilicon layer 111, located in the substrate structure 100; a gate oxide layer 112, located on the sidewalls of the polysilicon layer 111 and on the surface of the polysilicon layer 111 close to the substrate structure 100. The remaining insulating layer 102, the conductive portion 103, the first doping region 104, the substrate 105, the first sub-doping layer 106, the second sub-doping layer 107, the third sub-doping layer 108, the second doping region 109 and the third doping region 110 are located at the same position as the substrate structure 100. Figure 3 The above structure can further reduce the manufacturing cost of semiconductor devices.

[0057] In practical applications, the manufacturing process of polysilicon gate is relatively simple, low-cost, and suitable for large-scale production. In addition, polysilicon gate performs excellently in terms of photoelectric conversion efficiency. Polysilicon gate also has good stability and reliability and can work stably for a long time.

[0058] The present application also provides a method for manufacturing a semiconductor device. Figure 5 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application. Figure 5 As shown, the method includes:

[0059] Step S201, providing a substrate structure, wherein the substrate structure 100 has a plurality of grooves 113, and obtaining Figure 6 The structure shown;

[0060] Specifically, the material of the substrate structure may be silicon or silicon carbide. The spacings between the multiple grooves may be the same or different. Furthermore, the depths of the multiple grooves may be the same or different.

[0061] Step S202, forming a trench gate portion 101 in each of the above grooves 113, and obtaining Figure 7 The structure shown;

[0062] Specifically, the intervals between the plurality of trench gate portions may be the same or different, and the depths of the plurality of trench gate portions may be the same or different.

[0063] Step S203, forming an insulating layer 102 on the surface of the trench gate portion 101 and on a portion of the surface of the substrate structure 100, with a receiving cavity 114 between the insulating layer 102 and the substrate structure 100, to obtain Figure 8 The structure shown;

[0064] Specifically, in the process of forming the above-mentioned insulating layer, it can be achieved through multiple steps. First, a plurality of insulating parts with intervals are formed on the surface of the trench gate part and on part of the surface of the above-mentioned base structure. Then, a top insulating layer is formed on part of the surface of each insulating part away from the trench gate part. The two-layer structure of the top insulating layer and the plurality of insulating parts together form the above-mentioned insulating layer.

[0065] Step S204, forming a conductive portion 103 in the accommodating cavity 114, on the surface of the insulating layer 102 away from the substrate structure 100, and on the surface of the substrate structure 100, wherein the conductive portion 103 is one of a source metal portion or a drain metal portion, at least one of the plurality of conductive portions 103 is used for inputting signals, and at least two of the plurality of conductive portions 103 are used for outputting signals, and at least one trench gate portion 101 is provided between the conductive portion 103 for inputting signals and the conductive portion 103 for outputting signals in a preset direction, wherein the preset direction is perpendicular to the thickness direction of the substrate structure, and the following is obtained: Figure 1 The structure shown.

[0066] Specifically, the conductive part in the accommodating cavity can be deposited after forming a plurality of insulating parts with intervals. The insulating layer is away from the surface of the substrate structure and the conductive part on the surface of the substrate structure can be deposited after the top insulating layer is formed. The structure ensures that the signal input end and the signal output end are separated by at least one trench gate to ensure that the power line passes through the bottom of the trench gate, realizes vertical withstand voltage, and fully utilizes the structural thickness in the vertical direction.

[0067] Through this embodiment, a method for manufacturing a semiconductor device is provided, first, a substrate structure is provided, the above-mentioned substrate structure has a plurality of grooves; a trench gate portion is formed in each of the above-mentioned grooves; then, an insulating layer is formed on the surface of the above-mentioned trench gate portion and on a part of the surface of the above-mentioned substrate structure, and a receiving cavity is provided between the above-mentioned insulating layer and the above-mentioned substrate structure; finally, a conductive portion is formed in the above-mentioned receiving cavity, on the surface of the above-mentioned insulating layer away from the above-mentioned substrate structure, and on the surface of the above-mentioned substrate structure, the above-mentioned conductive portion is one of a source metal portion or a drain metal portion, at least one of the multiple conductive portions is used for inputting signals, at least two of the multiple conductive portions are used for outputting signals, and at least one trench gate portion is provided between the conductive portion for inputting signals and the conductive portion for outputting signals in a preset direction. By arranging both the source metal part and the drain metal part on the surface of the device, and a part of the conductive part is located on the side of the insulating layer away from the substrate structure, and the other part of the conductive part is located on the side of the insulating layer close to the substrate structure, that is, the conductive part is divided into two layers, electrical isolation and pad redistribution between conductive parts with different functions can be achieved, thereby realizing the functional layout and adjustment of the device in signal transmission, meeting the requirements of secondary wiring, and solving the technical problem of how semiconductor devices in the prior art meet the requirements of secondary wiring.

[0068] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0069] 1) The semiconductor device of the present application comprises a substrate structure; a plurality of trench gate portions distributed in sequence in a preset direction, located in the substrate structure, the preset direction being perpendicular to the thickness direction of the substrate structure; an insulating layer, located on a partial surface of one side of the substrate structure, a receiving cavity being provided between the insulating layer and the substrate structure, the orthographic projection of the insulating layer on the substrate structure at least partially overlapping with the orthographic projection of the trench gate portion on the substrate structure; a plurality of conductive portions, located in the receiving cavity, on the surface of the insulating layer away from the substrate structure, and on the surface of one side of the substrate structure, the conductive portion being one of a source metal portion or a drain metal portion, at least one of the plurality of conductive portions being used for inputting signals, at least two of the plurality of conductive portions being used for outputting signals, and at least one trench gate portion being provided between the conductive portion for inputting signals and the conductive portion for outputting signals in the preset direction. By arranging both the source metal part and the drain metal part on the surface of the device, and a part of the conductive part is located on the side of the insulating layer away from the substrate structure, and the other part of the conductive part is located on the side of the insulating layer close to the substrate structure, that is, the conductive part is divided into two layers, electrical isolation and pad redistribution between conductive parts with different functions can be achieved, thereby realizing the functional layout and adjustment of the device in signal transmission, meeting the requirements of secondary wiring, and solving the technical problem of how semiconductor devices in the prior art meet the requirements of secondary wiring.

[0070] 2) A method for manufacturing a semiconductor device of the present application comprises the following steps: first, providing a substrate structure, wherein the substrate structure has a plurality of grooves; forming a trench gate portion in each of the grooves; then, forming an insulating layer on the surface of the trench gate portion and on a portion of the surface of the substrate structure, wherein a receiving cavity is provided between the insulating layer and the substrate structure; finally, forming a conductive portion in the receiving cavity, on a surface of the insulating layer away from the substrate structure, and on a surface of the substrate structure, wherein the conductive portion is a source metal portion or a drain metal portion, wherein at least one of the plurality of conductive portions is used for inputting a signal, and at least two of the plurality of conductive portions are used for outputting a signal, and wherein at least one trench gate portion is provided between the conductive portion for inputting a signal and the conductive portion for outputting a signal in a preset direction. By arranging both the source metal part and the drain metal part on the surface of the device, and a part of the conductive part is located on the side of the insulating layer away from the substrate structure, and the other part of the conductive part is located on the side of the insulating layer close to the substrate structure, that is, the conductive part is divided into two layers, electrical isolation and pad redistribution between conductive parts with different functions can be achieved, thereby realizing the functional layout and adjustment of the device in signal transmission, meeting the requirements of secondary wiring, and solving the technical problem of how semiconductor devices in the prior art meet the requirements of secondary wiring.

[0071] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: Base structure; A plurality of trench gate portions sequentially distributed in a preset direction are located in the base structure, wherein the preset direction is perpendicular to a thickness direction of the base structure; an insulating layer, located on a portion of the surface of one side of the base structure, a receiving cavity being provided between the insulating layer and the base structure, and an orthographic projection of the insulating layer on the base structure at least partially overlapping with an orthographic projection of the trench gate portion on the base structure; A plurality of conductive parts are located in the accommodating cavity, on the surface of the insulating layer away from the base structure, and on the surface of one side of the base structure, the conductive part is a source metal part or a drain metal part, at least one of the plurality of conductive parts is used for inputting signals, at least two of the plurality of conductive parts are used for outputting signals, and at least one trench gate part is provided between the conductive part for inputting signals and the conductive part for outputting signals in the preset direction.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: The first doping region is located on the surface of the trench gate portion close to the substrate structure.

3. The semiconductor device according to claim 2, characterized in that The base structure comprises: substrate; A first sub-doping layer is located on a surface of one side of the substrate, the first sub-doping layer is in contact with the sidewalls of each of the trench gate portions and the surface of the first doping region close to the substrate, and the doping type of the first sub-doping layer is different from the doping type of the first doping region; A second sub-doping layer is located on a portion of the surface of the first sub-doping layer away from the substrate and between two adjacent trench gate portions, and the doping type of the second sub-doping layer is the same as the doping type of the first doping region; A third sub-doping layer is located on a partial surface of the first sub-doping layer away from the substrate and on a surface of the second sub-doping layer away from the substrate, the third sub-doping layer includes a plurality of second doping regions and third doping regions alternately arranged along a first direction, the doping type of the second doping region is different from the doping type of the third doping region, and the first direction is perpendicular to the thickness direction of the semiconductor device.

4. The semiconductor device according to claim 3, characterized in that The doping concentration of the first doping region is greater than the doping concentration of the second sub-doping layer.

5. The semiconductor device according to claim 3, characterized in that At least one of the second doping region or the third doping region is located on a side of the trench gate portion close to an edge of the semiconductor device.

6. The semiconductor device according to claim 3, characterized in that At least one of the second doping region and the third doping region is located between two adjacent trench gate portions.

7. The semiconductor device according to claim 3, characterized in that The length of the surface of the trench gate portion close to the substrate side from the predetermined surface is a first length, the length of the surface of the second sub-doping layer close to the substrate side from the predetermined surface is a second length, the second length is greater than the first length, and the predetermined surface is the surface of the base structure away from the insulating layer.

8. The semiconductor device according to claim 3, characterized in that The length of the surface of the second sub-doped layer away from the substrate side from the predetermined surface is a third length, the length of the surface of the trench gate portion away from the substrate side from the predetermined surface is a fourth length, the fourth length is greater than the third length, and the predetermined surface is the surface of the base structure away from the insulating layer.

9. The semiconductor device according to claim 1, wherein: The trench gate portion includes: A polysilicon layer, located in the base structure; The gate oxide layer is located on the sidewall of the polysilicon layer and on the surface of the polysilicon layer close to the substrate structure.

10. A method for manufacturing a semiconductor device, characterized in that: include: Providing a base structure, the base structure having a plurality of grooves; forming a trench gate portion in each of the grooves; forming an insulating layer on the surface of the trench gate portion and on a portion of the surface of the base structure, wherein a receiving cavity is provided between the insulating layer and the base structure; A conductive part is formed in the accommodating cavity, on the surface of the insulating layer away from the base structure, and on the surface of the base structure. The conductive part is one of a source metal part or a drain metal part. At least one of the multiple conductive parts is used for inputting signals, and at least two of the multiple conductive parts are used for outputting signals. There is at least one trench gate part between the conductive part for inputting signals and the conductive part for outputting signals in a preset direction, and the preset direction is perpendicular to the thickness direction of the base structure.

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