Light emitting diode chip and preparation method thereof

Abstract

The invention provides a light emitting diode chip and a preparation method thereof, and belongs to the technical field of semiconductor preparation. The light-emitting diode chip comprises an epitaxial layer and a bonding pad layer, the bonding pad layer is located on one side of the epitaxial layer and electrically connected with the epitaxial layer, the bonding pad layer comprises at least two layers of sub-bonding pads, the sub-bonding pads are sequentially stacked in the growth direction of the epitaxial layer, the orthographic projection of the sub-bonding pad closest to the epitaxial layer on the plane where the epitaxial layer is located is the reference projection, and the orthographic projection of the sub-bonding pads on the plane where the epitaxial layer is located is the reference projection. All are located in the reference projection. According to the invention, the morphology consistency of the bonding pad layer can be ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a light emitting diode chip and a manufacturing method thereof. Background Art

[0002] Mini LED (Mini Light Emitting Diode) is a new type of light-emitting diode. Due to its very small size, when it is used in displays, it can be arranged more densely, thereby greatly improving the resolution of the display.

[0003] The light emitting diode chip is an important component of the light emitting diode, which includes a pad layer, and the pad layer is used for welding gold wires.

[0004] However, since the size of the micro-LED is very small, the size of the pad layer is also very small, making it difficult to ensure the consistency of its morphology. Summary of the invention

[0005] The embodiment of the present disclosure provides a light-emitting diode chip and a method for manufacturing the same, which can ensure the morphology consistency of the pad layer. The technical solution is as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a light-emitting diode chip, comprising: an epitaxial layer and a pad layer;

[0007] The pad layer is located on one side of the epitaxial layer and is electrically connected to the epitaxial layer. The pad layer includes at least two layers of sub-pads, and each of the sub-pads is stacked in sequence along the growth direction of the epitaxial layer. The orthographic projection of the sub-pad closest to the epitaxial layer on the plane where the epitaxial layer is located is the reference projection, and the orthographic projections of each of the sub-pads on the plane where the epitaxial layer is located are all located within the reference projection.

[0008] In an implementation of the present disclosure, the thickness of each of the sub-pads is no greater than 0.5 μm.

[0009] In an implementation of the present disclosure, the sub-pad closest to the epitaxial layer includes: a Cr layer, an Al layer, a Ti layer, a Ni layer, and an Au layer stacked in sequence.

[0010] In an implementation of the present disclosure, the sub-pad farthest from the epitaxial layer includes: a Ti layer and an Au layer stacked in sequence.

[0011] In an implementation of the present disclosure, each of the sub-pads located between a sub-pad closest to the epitaxial layer and a sub-pad farthest from the epitaxial layer includes: a Ti layer, a Ni layer, and an Au layer stacked in sequence.

[0012] In a second aspect, an embodiment of the present disclosure provides a method for preparing a light-emitting diode chip, which is used to prepare the light-emitting diode chip described in the second aspect, and the preparation method includes:

[0013] preparing an epitaxial layer;

[0014] Along the growth direction of the epitaxial layer, at least two layers of sub-pads are prepared in sequence on one side of the epitaxial layer, so that the orthographic projection of each sub-pad on the plane where the epitaxial layer is located is located within the reference projection, and the reference projection is the orthographic projection of a sub-pad closest to the epitaxial layer on the plane where the epitaxial layer is located, and each sub-pad forms a pad layer.

[0015] In an implementation of the present disclosure, the thickness of each of the sub-pads is set to be no greater than 0.5 μm.

[0016] In one implementation of the present disclosure, preparing a sub-pad closest to the epitaxial layer includes:

[0017] The Cr layer, Al layer, Ti layer, Ni layer and Au layer are prepared in sequence.

[0018] In one implementation of the present disclosure, preparing a sub-pad farthest from the epitaxial layer includes:

[0019] The Ti layer and the Au layer are prepared in sequence.

[0020] In an implementation of the present disclosure, preparing each of the sub-pads located between a sub-pad closest to the epitaxial layer and a sub-pad farthest from the epitaxial layer includes:

[0021] The Ti layer, the Ni layer and the Au layer are prepared in sequence.

[0022] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0023] The pad layer is composed of at least two sub-pads stacked in sequence, and the orthographic projection of the sub-pad closest to the epitaxial layer on the plane where the epitaxial layer is located is used as the reference projection. Since the orthographic projections of each sub-pad on the plane where the epitaxial layer is located are all within the reference projection, it can be ensured that the pad layer formed by the stacking of the sub-pads can have good morphological consistency.

[0024] That is to say, dividing the pad layer into a plurality of stacked sub-pads can avoid the problem of inconsistent morphology between the top area and the bottom area due to excessive thickness during the overall preparation of the pad layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 It is a schematic diagram of the pad layer structure provided by the related technology;

[0027] Figure 2 is a schematic structural diagram of a light-emitting diode chip provided by an embodiment of the present disclosure;

[0028] Figure 3 is a schematic structural diagram of a pad layer provided by an embodiment of the present disclosure;

[0029] Figure 4 is a flow chart of a method for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0030] Figure 5 It is a flow chart of another method for preparing a light emitting diode chip provided in an embodiment of the present disclosure.

[0031] The symbols in the figure mean the following:

[0032] 10. Epitaxial layer;

[0033] 110, first semiconductor layer; 120, multi-quantum well layer; 130, second semiconductor layer;

[0034] 20. Pad layer;

[0035] 210, first pad layer; 220, second pad layer;

[0036] 30. Sub-pad;

[0037] 310, first sub-pad; 320, second sub-pad; 330, third sub-pad; 340, fourth sub-pad;

[0038] 410, a first electrode; 420, a second electrode;

[0039] 50. Passivation layer;

[0040] 60. Protective layer;

[0041] 70. Sapphire substrate;

[0042] 80. Bonding layer.

[0043] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0045] In order to better understand the light emitting diode chip provided by the embodiments of the present disclosure, the relevant technology is first introduced below.

[0046] In the related art, the pad layer is prepared by evaporation. During the evaporation process, a glue mask is used to control the morphology of the pad layer. However, the metal deposited by evaporation will form residues on the sidewalls of the glue mask. When the glue mask is peeled off, the residual metal will be peeled off together, thereby deteriorating the smoothness of the sidewalls of the pad layer, which in turn seriously affects the morphology consistency of the pad layer. Figure 1 It can be seen that the size of the top area of ​​the pad layer is significantly smaller than that of the bottom area, resulting in inconsistent morphology of the pad layer. In addition, in the actual preparation process, it is found that when the thickness of the pad layer exceeds 1.5μm, the above residue has a particularly significant impact on the morphology consistency of the pad layer.

[0047] In order to solve the above technical problems, the present disclosure provides a light emitting diode chip. Figure 2 is a schematic diagram of the structure of the light-emitting diode chip, combined with Figure 2 In this embodiment, the light emitting diode chip includes: an epitaxial layer 10 and a pad layer 20 .

[0048] Figure 3 is a schematic diagram of the structure of the pad layer 20, combined with Figure 3 In this embodiment, the pad layer 20 is located on one side of the epitaxial layer 10 and is electrically connected to the epitaxial layer 10. The pad layer 20 includes at least two layers of sub-pads 30. The sub-pads 30 are stacked in sequence along the growth direction of the epitaxial layer 10. The orthographic projection of a sub-pad 30 closest to the epitaxial layer 10 on the plane where the epitaxial layer 10 is located is the reference projection. The orthographic projections of each sub-pad 30 on the plane where the epitaxial layer 10 is located are all located within the reference projection.

[0049] The pad layer 20 is composed of at least two sub-pads 30 stacked in sequence. The orthographic projection of a sub-pad 30 closest to the epitaxial layer 10 on the plane where the epitaxial layer 10 is located is used as the reference projection. Since the orthographic projections of each sub-pad 30 on the plane where the epitaxial layer 10 is located are all within the reference projection, it can be ensured that the pad layer 20 formed by the stacking of each sub-pad 30 can have good morphological consistency.

[0050] That is to say, dividing the pad layer 20 into a plurality of stacked sub-pads 30 can avoid the problem of inconsistent morphology between the top area and the bottom area due to excessive thickness during the overall preparation of the pad layer 20 .

[0051] It is worth noting that, in the light-emitting diode chip provided in the embodiment of the present disclosure, when the thickness of the pad layer 20 exceeds 1.5 μm, the chip can still have good morphological consistency.

[0052] In this embodiment, the thickness of each sub-pad 30 is no greater than 0.5 μm.

[0053] In the above implementation, when the total thickness of the pad layer 20 is constant, the thickness of the sub-pad 30 determines the number of the sub-pads 30. For example, the smaller the thickness of the sub-pad 30, the more sub-pads 30 are required to form the pad layer 20. The smaller the thickness of the sub-pad 30, the less residue it leaves on the glue mask, and the better the morphology consistency of each sub-pad 30.

[0054] Of course, if the thickness of the sub-pad 30 is too small, the number of times the glue mask is peeled off will be too many, and the manufacturing efficiency will be too low. Therefore, it is more appropriate to set the number of sub-pads 30 to 4 to 6. This can ensure the consistency of the morphology of the pad layer 20 and the manufacturing efficiency of the pad layer 20.

[0055] In this embodiment, the number of the sub-pads 30 is 4. Of course, in other embodiments, the number of the sub-pads 30 can also be designed to be other values ​​according to actual needs, and the present disclosure does not limit this.

[0056] In this embodiment, the four sub-pads 30 are respectively called the first sub-pad 310, the second sub-pad 320, the third sub-pad 330 and the fourth sub-pad 340. The first sub-pad 310, the second sub-pad 320, the third sub-pad 330 and the fourth sub-pad 340 are stacked in sequence along the growth direction of the epitaxial layer 10.

[0057] In the present embodiment, a sub-pad 30 closest to the epitaxial layer 10 includes: a Cr layer, an Al layer, a Ti layer, a Ni layer, and an Au layer stacked in sequence.

[0058] In the above implementation, the sub-pad 30 closest to the epitaxial layer 10 is also the first sub-pad 310, which is composed of a Cr layer, an Al layer, a Ti layer, a Ni layer, and an Au layer stacked in sequence. Among them, the Al layer is a reflective layer, which can effectively improve the light efficiency of the light-emitting diode. The Ti layer has good ductility, plasticity and mechanical properties. It is arranged in the first sub-pad 310, which can effectively enhance the adhesion of the first sub-pad 310. The toughness of the Ni layer is good. On the one hand, it can reduce the residue of the first sub-pad 310 on the glue mask, and on the other hand, it increases the welding strength of the pad layer 20. The Au layer has good electrical conductivity, thereby effectively enhancing the electrical conductivity of the first sub-pad 310.

[0059] In the present embodiment, a sub-pad 30 farthest from the epitaxial layer 10 includes a Ti layer and an Au layer stacked in sequence.

[0060] In the above implementation, the sub-pad 30 farthest from the epitaxial layer 10 is the fourth sub-pad 340, which is composed of a Ti layer and an Au layer stacked in sequence. The Ti layer has good ductility, plasticity and mechanical properties, and is arranged in the fourth sub-pad 340, which can effectively enhance the adhesion of the fourth sub-pad 340. The Au layer has good electrical conductivity, thereby effectively enhancing the electrical conductivity of the fourth sub-pad 340.

[0061] It is worth noting that, since the fourth sub-pad 340 is the last sub-pad 30 , it does not involve stripping of the adhesive mask, and therefore does not require the provision of a Ni layer, thereby effectively improving the preparation efficiency of the fourth sub-pad 340 .

[0062] In this embodiment, each sub-pad 30 located between a sub-pad 30 closest to the epitaxial layer 10 and a sub-pad 30 farthest from the epitaxial layer 10 includes: a Ti layer, a Ni layer, and an Au layer stacked in sequence.

[0063] In the above implementation, each sub-pad 30 located between a sub-pad 30 closest to the epitaxial layer 10 and a sub-pad 30 farthest from the epitaxial layer 10 is also the second sub-pad 320 and the third sub-pad 330. The second sub-pad 320 and the third sub-pad 330 have the same structure, and are composed of a Ti layer, a Ni layer, and an Au layer stacked in sequence. Among them, the Ti layer has good ductility, plasticity and mechanical properties. It is arranged in the second sub-pad 320 and the third sub-pad 330, which can effectively enhance the adhesion of the second sub-pad 320 and the third sub-pad 330. The toughness of the Ni layer is good, on the one hand, it can reduce the residue of the second sub-pad 320 and the third sub-pad 330 on the glue mask, and on the other hand, it increases the welding strength of the pad layer 20. The Au layer has good electrical conductivity, thereby effectively enhancing the electrical conductivity of the second sub-pad 320 and the third sub-pad 330.

[0064] See again Figure 2 In the present embodiment, the epitaxial layer 10 includes a first semiconductor layer 110 , a multi-quantum well layer 120 , and a second semiconductor layer 130 which are stacked in sequence.

[0065] One of the first semiconductor layer 110 and the second semiconductor layer 130 is a p-type layer, and the other of the first semiconductor layer 110 and the second semiconductor layer 130 is an n-type layer.

[0066] In this embodiment, the first semiconductor layer 110 is a p-type layer, and the second semiconductor layer 130 is an n-type layer.

[0067] Exemplarily, the first semiconductor layer 110 is a magnesium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0068] Exemplarily, the second semiconductor layer 130 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0069] In this embodiment, the multi-quantum well layer 120 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately, and the AlGaInP quantum well layer and the AlGaInP quantum barrier layer have different Al contents. The multi-quantum well layer 120 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers stacked alternately.

[0070] Exemplarily, the multi-quantum well layer 120 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0071] By way of example, the thickness of the multi-quantum well layer 120 may be 150 nm to 200 nm.

[0072] In this embodiment, the light emitting diode chip further includes an etching stop layer, and the etching stop layer is located on a side of the second semiconductor layer 130 facing away from the multi-quantum well layer 120 .

[0073] In this embodiment, the light emitting diode chip further includes an AlInP carrier confinement layer, and the AlInP carrier confinement layer is located on a side of the multi-quantum well layer 120 facing away from the first semiconductor layer 110 .

[0074] In this embodiment, the light emitting diode chip further includes a GaP window layer, and the GaP window layer is located on a side of the first semiconductor layer 110 facing away from the multi-quantum well layer 120 .

[0075] Exemplarily, the thickness of the GaP window layer is 3 μm.

[0076] Continue to see Figure 2 In this embodiment, the light-emitting diode chip also includes a first electrode 410, a second electrode 420 and a passivation layer 50. The surface of the second semiconductor layer 130 has a groove exposing the first semiconductor layer 110. The first electrode 410 is located in the groove. The second electrode 420 is located on the surface of the second semiconductor layer 130 away from the multi-quantum well layer 120. The passivation layer 50 is at least located on the surface of the second semiconductor layer 130, the bottom surface of the groove, the surface of the first electrode 410 and the surface of the second electrode 420.

[0077] In this embodiment, the first electrode 410 is a p-type electrode, and the second electrode 420 is an n-type electrode.

[0078] For example, the passivation layer 50 may be a distributed Bragg reflector (DBR), which includes a plurality of SiO2 layers and TiO2 layers that are periodically and alternately stacked. The number of periods of the distributed Bragg reflector may be between 20 and 50.

[0079] In this embodiment, the number of periods of the distributed Bragg reflector is 32.

[0080] In addition to the passivation function, the distributed Bragg reflector is also used to reflect the light emitted from the multi-quantum well layer 120 to the distributed Bragg reflector back to the direction of the epitaxial layer 10, thereby improving the light extraction effect.

[0081] In this embodiment, there are two types of pad layers 20, namely a first pad layer 210 and a second pad layer 220. The first pad layer 210 and the second pad layer 220 are located on the passivation layer 50. The first pad layer 210 is connected to the first electrode 410 through a through hole, and the second pad layer 220 is connected to the second electrode 420 through another through hole.

[0082] In this embodiment, the light-emitting diode chip also includes a protective layer 60, which covers the surface of the passivation layer 50, and the protective layer 60 extends from the surface of the passivation layer 50 to the side of the epitaxial layer 10, and the protective layer 60 has a through hole exposing the first pad layer 210 and the second pad layer 220 to facilitate electrical connection.

[0083] Exemplarily, the protection layer 60 is a SiO 2 layer.

[0084] Figure 4 A flowchart of a method for preparing a light emitting diode chip provided in an embodiment of the present disclosure, combined with Figure 4 In this embodiment, the preparation method comprises:

[0085] Step 401 : preparing an epitaxial layer 10 .

[0086] Step 402: along the growth direction of the epitaxial layer 10, at least two layers of sub-pads 30 are sequentially prepared on one side of the epitaxial layer 10, so that the orthographic projection of each sub-pad 30 on the plane where the epitaxial layer 10 is located is located within the reference projection, and each sub-pad 30 forms a pad layer 20.

[0087] It is worth noting that the reference projection is the orthographic projection of a sub-pad 30 closest to the epitaxial layer 10 on the plane where the epitaxial layer 10 is located.

[0088] The light-emitting diode chip prepared by the preparation method provided by the embodiment of the present disclosure has a pad layer 20 composed of at least two sub-pads 30 stacked in sequence, and the orthographic projection of a sub-pad 30 closest to the epitaxial layer 10 on the plane where the epitaxial layer 10 is located is used as the reference projection. Since the orthographic projections of each sub-pad 30 on the plane where the epitaxial layer 10 is located are all located within the reference projection, it can be ensured that the pad layer 20 formed by the stacking of each sub-pad 30 can have good morphological consistency.

[0089] That is to say, dividing the pad layer 20 into a plurality of stacked sub-pads 30 can avoid the problem of inconsistent morphology between the top area and the bottom area due to excessive thickness during the overall preparation of the pad layer 20 .

[0090] Figure 5 A flowchart of another method for preparing a light emitting diode chip provided in an embodiment of the present disclosure, combined with Figure 5 In this embodiment, the preparation method comprises:

[0091] Step 501: Provide a GaAs substrate.

[0092] Step 502: Prepare an epitaxial layer 10 on one side of a GaAs substrate.

[0093] In the present embodiment, the epitaxial layer 10 includes a first semiconductor layer 110 , a multi-quantum well layer 120 , and a second semiconductor layer 130 which are sequentially stacked.

[0094] One of the first semiconductor layer 110 and the second semiconductor layer 130 is a p-type layer, and the other of the first semiconductor layer 110 and the second semiconductor layer 130 is an n-type layer.

[0095] In this embodiment, the first semiconductor layer 110 is a p-type layer, and the second semiconductor layer 130 is an n-type layer.

[0096] Exemplarily, the first semiconductor layer 110 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0097] Exemplarily, the second semiconductor layer 130 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0098] In this embodiment, the multi-quantum well layer 120 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately, and the AlGaInP quantum well layer and the AlGaInP quantum barrier layer have different Al contents. The multi-quantum well layer 120 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers stacked alternately.

[0099] Exemplarily, the multi-quantum well layer 120 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0100] By way of example, the thickness of the multi-quantum well layer 120 may be 150 nm to 200 nm.

[0101] In this embodiment, an etching stop layer may be grown before growing the second semiconductor layer 130 , and an AlInP carrier confinement layer may be grown before growing the multi-quantum well layer 120 .

[0102] In this embodiment, a GaP window layer may be further grown after the first semiconductor layer 110 is grown.

[0103] Exemplarily, the thickness of the GaP window layer is 3 μm.

[0104] Step 503: Provide a sapphire substrate 70.

[0105] In the above implementation, since the sapphire substrate 70 has a relatively high light transmittance, and the sapphire material is relatively hard and has relatively stable chemical properties, the use of the sapphire substrate 70 can enable the light-emitting diode to have good light-emitting effect and stability.

[0106] Step 504: forming a bonding layer 80 between the sapphire substrate 70 and the first semiconductor layer 110, bonding the epitaxial layer 10 to the sapphire substrate 70, and removing the GaAs wafer to obtain an epitaxial wafer.

[0107] Exemplarily, in step 504, silicon oxide liquid is coated on the surface of the first semiconductor layer 110, and the sapphire substrate 70 is placed on the surface of the first semiconductor layer 110. The silicon oxide liquid is heated and cured to form a bonding layer 80 between the first semiconductor layer 110 and the sapphire substrate 70.

[0108] Exemplarily, the temperature of the heating and curing is 250° C. to 350° C. In this embodiment, the heating temperature may be 300° C.

[0109] Step 505: Etch the epitaxial wafer by dry etching to form steps of three heights on the epitaxial wafer, so that the groove of the first semiconductor and the sapphire substrate 70 are exposed.

[0110] Step 506: fabricating a first electrode 410 and a second electrode 420 on the epitaxial wafer.

[0111] The first electrode 410 is located in the groove of the first semiconductor, and the second electrode 420 is located on a side of the second semiconductor layer 130 away from the substrate.

[0112] Exemplarily, the first electrode 410 has AuBe as a main component, and the second electrode 420 has AuGe as a main component.

[0113] Step 507: forming a passivation layer 50 on the epitaxial wafer.

[0114] In step 507, the passivation layer 50 is at least located on the second semiconductor layer 130, the first electrode 410, the groove and the second electrode 420. In addition, the passivation layer 50 has two through holes that expose the first electrode 410 and the second electrode 420 respectively.

[0115] Step 508 : preparing a pad layer 20 on the surface of the passivation layer 50 .

[0116] The pad layer 20 is connected to the first electrode 410 and the second electrode 420 through the through holes. The pad layer 20 connected to the first electrode 410 is the first pad layer 210 , and the pad layer 20 connected to the second electrode 420 is the second pad layer 220 .

[0117] Exemplarily, step 508 is performed in the following manner:

[0118] Along the growth direction of the epitaxial layer 10, at least two layers of sub-pads 30 are prepared in sequence on one side of the epitaxial layer 10, so that the orthographic projections of each sub-pad 30 on the plane where the epitaxial layer 10 is located are all located within the reference projection. The reference projection is the orthographic projection of a sub-pad 30 closest to the epitaxial layer 10 on the plane where the epitaxial layer 10 is located, and each sub-pad 30 forms a pad layer 20.

[0119] Exemplarily, the thickness of each sub-pad 30 is set to be no greater than 0.5 μm.

[0120] When preparing each sub-pad 30, the steps include:

[0121] The preparation of a sub-pad 30 closest to the epitaxial layer 10 includes: sequentially preparing a Cr layer, an Al layer, a Ti layer, a Ni layer, and an Au layer.

[0122] In the above implementation, the sub-pad 30 closest to the epitaxial layer 10 is also the first sub-pad 310, which is composed of a Cr layer, an Al layer, a Ti layer, a Ni layer, and an Au layer stacked in sequence. Among them, the Al layer is a reflective layer, which can effectively improve the light efficiency of the light-emitting diode. The Ti layer has good ductility, plasticity and mechanical properties. It is arranged in the first sub-pad 310, which can effectively enhance the adhesion of the first sub-pad 310. The toughness of the Ni layer is good. On the one hand, it can reduce the residue of the first sub-pad 310 on the glue mask, and on the other hand, it increases the welding strength of the pad layer 20. The Au layer has good electrical conductivity, thereby effectively enhancing the electrical conductivity of the first sub-pad 310.

[0123] The preparation of a sub-pad 30 farthest from the epitaxial layer 10 includes: sequentially preparing a Ti layer and an Au layer.

[0124] In the above implementation, the sub-pad 30 farthest from the epitaxial layer 10 is the fourth sub-pad 340, which is composed of a Ti layer and an Au layer stacked in sequence. The Ti layer has good ductility, plasticity and mechanical properties, and is arranged in the fourth sub-pad 340, which can effectively enhance the adhesion of the fourth sub-pad 340. The Au layer has good electrical conductivity, thereby effectively enhancing the electrical conductivity of the fourth sub-pad 340.

[0125] The sub-pads 30 located between a sub-pad 30 closest to the epitaxial layer 10 and a sub-pad 30 farthest from the epitaxial layer 10 are prepared, including: sequentially preparing a Ti layer, a Ni layer, and an Au layer.

[0126] In the above implementation, each sub-pad 30 located between a sub-pad 30 closest to the epitaxial layer 10 and a sub-pad 30 farthest from the epitaxial layer 10 is also the second sub-pad 320 and the third sub-pad 330. The second sub-pad 320 and the third sub-pad 330 have the same structure, and are composed of a Ti layer, a Ni layer, and an Au layer stacked in sequence. Among them, the Ti layer has good ductility, plasticity and mechanical properties. It is arranged in the second sub-pad 320 and the third sub-pad 330, which can effectively enhance the adhesion of the second sub-pad 320 and the third sub-pad 330. The toughness of the Ni layer is good, on the one hand, it can reduce the residue of the second sub-pad 320 and the third sub-pad 330 on the glue mask, and on the other hand, it increases the welding strength of the pad layer 20. The Au layer has good electrical conductivity, thereby effectively enhancing the electrical conductivity of the second sub-pad 320 and the third sub-pad 330.

[0127] Step 509 : preparing a protection layer 60 on the surface of the passivation layer 50 .

[0128] Exemplarily, the protection layer 60 may be a SiO 2 layer.

[0129] After the protective layer 60 is grown on the surface of the passivation layer 50 , a through hole exposing the pad layer 20 may be etched on the surface of the protective layer 60 using a photolithography technique to facilitate electrical connection.

[0130] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0131] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode chip, characterized in that: include: An epitaxial layer (10) and a pad layer (20); The pad layer (20) is located on one side of the epitaxial layer (10) and is electrically connected to the epitaxial layer (10). The pad layer (20) comprises at least two layers of sub-pads (30). The sub-pads (30) are stacked in sequence along the growth direction of the epitaxial layer (10). The orthographic projection of a sub-pad (30) closest to the epitaxial layer (10) on the plane where the epitaxial layer (10) is located is a reference projection. The orthographic projections of the sub-pads (30) on the plane where the epitaxial layer (10) is located are all located within the reference projection.

2. The light emitting diode chip according to claim 1, characterized in that: The thickness of each sub-pad (30) is no greater than 0.5 μm.

3. The light emitting diode chip according to claim 1, characterized in that: The sub-pad (30) closest to the epitaxial layer (10) comprises: a Cr layer, an Al layer, a Ti layer, a Ni layer, and an Au layer stacked in sequence.

4. The light emitting diode chip according to claim 1, characterized in that: The sub-pad (30) farthest from the epitaxial layer (10) comprises a Ti layer and an Au layer stacked in sequence.

5. The light emitting diode chip according to claim 1, characterized in that: Each of the sub-pads (30) located between a sub-pad (30) closest to the epitaxial layer (10) and a sub-pad (30) farthest from the epitaxial layer (10) comprises: a Ti layer, a Ni layer, and an Au layer stacked in sequence.

6. A method for preparing a light emitting diode chip, characterized in that: For preparing the light emitting diode chip according to claim 1, the preparation method comprises: preparing an epitaxial layer (10); At least two layers of sub-pads (30) are sequentially prepared on one side of the epitaxial layer (10) along the growth direction of the epitaxial layer (10), so that the orthographic projections of each of the sub-pads (30) on the plane where the epitaxial layer (10) is located are all located within a reference projection, the reference projection being the orthographic projection of a sub-pad (30) closest to the epitaxial layer (10) on the plane where the epitaxial layer (10) is located, and each of the sub-pads (30) forms a pad layer (20).

7. The preparation method according to claim 6, characterized in that: The thickness of each sub-pad (30) is set to be no greater than 0.5 μm.

8. The preparation method according to claim 6, characterized in that: Preparing a sub-pad (30) closest to the epitaxial layer (10), comprising: The Cr layer, Al layer, Ti layer, Ni layer and Au layer are prepared in sequence.

9. The preparation method according to claim 6, characterized in that: Preparing a sub-pad (30) farthest from the epitaxial layer (10), comprising: The Ti layer and the Au layer are prepared in sequence.

10. The preparation method according to claim 6, characterized in that: The sub-pads (30) are prepared between a sub-pad (30) closest to the epitaxial layer (10) and a sub-pad (30) farthest from the epitaxial layer (10), comprising: The Ti layer, the Ni layer and the Au layer are prepared in sequence.

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