Closed loop stability ramp implementation for constant on-time buck converter

Abstract

The invention relates to a closed loop stability ramp implementation for a constant on-time buck converter. An integrated circuit device includes: one or more switches of a buck converter; and a control circuit for the buck converter, comprising: a comparator configured to compare a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator configured to generate a pulse signal for controlling the buck converter in response to a rising edge of the comparator output signal; a transconductance amplifier (TA) configured to generate, at an output terminal of the TA, a current proportional to a difference between the reference voltage and the feedback voltage; a capacitor coupled between an output terminal of the TA and a reference voltage node; and a ramp signal generator configured to generate a compensated ramp voltage by adding a voltage at an output terminal of the TA to a ramp voltage having a gradient proportional to a switching frequency of the buck converter.

Description

Technical Field

[0001] The present invention relates generally to a switched mode power supply (SMPS) and, in a particular embodiment, to a constant on-time (COT) buck converter with internal slope compensation. Background Art

[0002] Power converters are widely used in many electronic applications from computers to automobiles. In some embodiments, the voltage in the power converter is generated by operating a switch loaded with an inductor or transformer to perform DC-DC, DC-AC and / or AC-DC conversion. Examples of power converters include switch mode power supplies (SMPS) and linear regulators. SMPS is generally more efficient than other types of power conversion systems because power conversion is performed by controlled charging and discharging of an inductor or transformer, and reduces the energy lost due to power dissipation across the resistive voltage drop.

[0003] An SMPS typically includes at least one switch (also called a power switch) and an inductor or transformer. Some specific topologies include buck converters, boost converters, and flyback converters, among others. A control circuit is typically used to open and close the switch to charge and discharge the inductor. In some applications, the current supplied to the load and / or the voltage supplied to the load is controlled via a feedback loop. In some types, the switches used in an SMPS are implemented using cascode switches. A linear regulator is another type of power converter in which a pass transistor is controlled (e.g., turned on and off) by a controller to provide a stable voltage to an external load.

[0004] Buck converters are a popular choice for SMPS and are often used to provide power to downstream devices such as sensors or processors. Constant on-time (COT) control for DC-DC converters allows fast transient response, but requires careful compensation design. The stability of COT buck converters is usually solved with a ripple injection strategy using external components (e.g., equivalent series resistors (ESR) or time constant matched filters (TCMF)). However, the use of ESR reduces the efficiency of the buck converter, and the large number of bulky external components used in TCMF are undesirable for customers in terms of cost, complexity, and required space. There is a need in the art for a control circuit that can be integrated with a buck converter in the same integrated circuit (IC) device and does not require or hardly requires external components. Summary of the invention

[0005] According to an embodiment, a switch mode power supply (SMPS) includes: a buck converter and a control circuit for the buck converter. The control circuit includes: a comparator configured to compare a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator coupled to an output terminal of the comparator and configured to generate a pulse signal in response to a rising edge of an output signal of the comparator, wherein a switch of the buck converter is controlled by the pulse signal; a transconductance amplifier, wherein a first input terminal of the transconductance amplifier is configured to receive the feedback voltage, and a second input terminal of the transconductance amplifier is configured to receive a reference voltage; a first capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and a ramp signal generator configured to generate a ramp voltage and add the ramp voltage to a first voltage at the output terminal of the transconductance amplifier to generate a compensation ramp voltage, wherein the ramp voltage is a linear voltage signal, and the ramp signal generator is configured to adjust the gradient of the linear voltage signal according to the switching frequency of the buck converter.

[0006] According to an embodiment, an integrated circuit (IC) device includes: one or more switches of a buck converter and a control circuit for the buck converter. The control circuit includes: a comparator configured to generate a comparator output signal by comparing a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator configured to generate a pulse signal in response to a rising edge of the comparator output signal, wherein the buck converter is configured to be controlled by a switch control signal derived from the pulse signal; a transconductance amplifier configured to generate a current proportional to a difference between a reference voltage and a feedback voltage at an output terminal of the transconductance amplifier; a first capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and a ramp signal generator configured to generate a compensation ramp voltage by adding a first voltage at the output terminal of the transconductance amplifier to a ramp voltage generated by the ramp signal generator, wherein the ramp voltage is a linear voltage signal having a gradient proportional to a switching frequency of the buck converter.

[0007] According to an embodiment, a method for operating a buck converter includes: dividing the output voltage of the buck converter to generate a feedback voltage; sending the feedback voltage to a first input terminal of a comparator; sending the feedback voltage and a reference voltage to a first input terminal of a transconductance amplifier and a second input terminal of the transconductance amplifier, respectively; using a ramp signal generator to generate a compensation ramp voltage, which is equal to the sum of a first voltage at the output terminal of the transconductance amplifier and the ramp voltage, wherein the ramp voltage is a linear voltage signal having a gradient proportional to a switching frequency of the buck converter; sending the compensation ramp voltage to a second input terminal of the comparator; using a pulse generator to generate a pulse signal, which includes a pulse corresponding to a rising edge in the output signal of the comparator; and switching the buck converter under the control of a switch control signal derived from the pulse signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 A block diagram of a switch mode power supply (SMPS) in an embodiment is illustrated;

[0010] Figure 2 A block diagram of a pulse generator in an embodiment is shown;

[0011] Figure 3 The diagram shows the embodiment used for Figure 2 Timing diagram of the pulse generator;

[0012] Figure 4 FIG. 1 illustrates a block diagram of a ramp signal generator in an embodiment;

[0013] Figure 5A and Figure 5B The embodiment is shown in the figure Figure 1 Timing diagram of a constant on-time (COT) buck converter at two different switching frequencies;

[0014] Figure 6 The figure shows the gradient of the compensation ramp voltage at different moments in the cycle of the compensation ramp voltage in the embodiment;

[0015] Figure 7 A block diagram of a ramp signal generator having a phase locked loop (PLL) in an embodiment is illustrated;

[0016] Figure 8 A block diagram of a ramp signal generator having a phase locked loop (PLL) in another embodiment is illustrated;

[0017] Fig. 9 A block diagram of a ramp signal generator having an integrator circuit with closed-loop control in an embodiment is illustrated;

[0018] Fig.10 The embodiment is shown in the figure Figure 1 the pins of an integrated circuit (IC) device; and

[0019] Fig.11 A flow chart illustrating a method of operating a buck converter in some embodiments is illustrated. DETAILED DESCRIPTION

[0020] The making and use of the currently disclosed examples are discussed in detail below. However, it should be appreciated that the present invention provides many applicable inventive concepts that can be implemented in a variety of specific contexts. The specific examples discussed merely illustrate specific ways to make and use the present invention and do not limit the scope of the present invention. Throughout the discussion herein, unless otherwise specified, the same or similar reference numerals or labels in different figures refer to the same or similar components or signals.

[0021] The present disclosure will be described with respect to an example in a specific context, namely, a COT buck converter with a control circuit for stability control. In some embodiments, most components of the control circuit and the COT buck converter are integrated into the same integrated circuit (IC) device, and a few components are implemented as external components of the IC device.

[0022] Figure 1 A block diagram of a switch mode power supply (SMPS) 100 in an embodiment is shown. Note that for simplicity, not all features of the SMPS 100 are shown.

[0023] Figure 1 The SMPS 100 in the embodiment is a buck converter having a control circuit that implements stability control of the buck converter in the steady state of the buck converter. As will be discussed in more detail below, the buck converter discussed herein is a COT buck converter, and the control circuit of the buck converter performs stability compensation through two feedback paths: a fast path that directly provides a feedback voltage V to a first input terminal of a pulse width modulation (PWM) comparator 121; and a second path that provides a feedback voltage V to a first input terminal of a pulse width modulation (PWM) comparator 121. FB ; and a slow path that achieves better accuracy by providing a new set point (e.g., voltage COMP) for the PWM comparator 121. The ramp signal generator 119 of the control circuit generates a linear ramp voltage with a gradient proportional to the switching frequency of the buck converter, adds the linear ramp voltage to the voltage COMP to generate a compensation ramp voltage 120, and sends the compensation ramp voltage 120 to the second input terminal of the PWM comparator 121. The pulse generator 123 generates a pulse signal 124 with a fixed pulse width in response to the rising edge of the output signal 122 of the PWM comparator 121. The pulse signal 124 or a switch control signal 128 derived from the pulse signal by the logic circuit 127 is used to control the switch of the buck converter.

[0024] exist Figure 1In the example of FIG. 1 , the components within the dashed box are integrated together on the same semiconductor substrate (e.g., silicon) to form an integrated circuit (IC) device 110 or a portion of the IC device 110. An example of the IC device 110 may be a power management integrated circuit (PMIC) device. The components outside the dashed box are referred to as external components connected to the IC device 110. The pins of the IC device 110 are Figure 1 is shown as a rectangular connector. Figure 1 As shown in , the number of external components required for IC device 110 is very small, which advantageously reduces the pin count for IC device 110.

[0025] exist Figure 1 In the embodiment, the buck converter includes a switch 109 (also referred to as a high-side switch), a switch 131 (also referred to as a low-side switch), a gate driver circuit 107 for the switch 109, a gate driver circuit 129 for the switch 131, and a logic circuit 127 for generating a switch control signal 128 (e.g., 128A and 128B) according to a pulse signal 124 generated by a pulse generator 123. The buck converter also includes an inductor L O and capacitor C o .exist Figure 1 In the example of , switches 109 and 131 are N-type transistors. In another embodiment, switch 109 is a P-type transistor and switch 131 is an N-type transistor. These and other variations are fully intended to be included within the scope of the present disclosure.

[0026] The switch 109 is coupled to the pin V of the IC device 110. IN and the pin SW of the IC device 110, and the switch 131 is coupled between the pin SW and the pin GND. IN The inductor L is configured to receive a supply voltage (eg, a voltage between +10V and +100V), and the pin GND is configured to be connected to a reference voltage (eg, electrical ground). O is coupled between the pin SW and the node 133, and the capacitor C O is coupled between node 133 and pin GND. During operation of the buck converter, the voltage at node 133 is the output voltage V of the buck converter. OUT .

[0027] The gate driver circuits 107 and 129 are configured to receive the switch control signals 128A and 128B, respectively, and are configured to generate control signals (e.g., gate control signals) for the switches 109 and 131, for example, by amplifying and / or voltage shifting the switch control signals 128A and 128B, or by enabling or disabling a voltage source to be applied as a gate-source voltage of the corresponding transistor 109 or 131. In the illustrated embodiment, the switches 109 and 131 are transistors. In an embodiment where the buck converter operates in a continuous conduction mode, the switches 109 and 131 are transistors of the same type (e.g., N-type), and the logic circuit 127 generates the switch control signals 128A and 128B with opposite values ​​(e.g., logic high (HIGH) or logic low (LOW)), thereby setting the switches 109 and 131 to opposite states (e.g., ON state or OFF state) during operation of the buck converter. In other words, for the above-described example of continuous conduction mode, during operation of the buck converter, when switch 131 is open, switch 109 is closed, and when switch 131 is closed, switch 109 is open.

[0028] Figure 1 The buck converter further includes a bootstrap capacitor 111, a bootstrap control circuit 103, a switch 105 (eg, a transistor 105), and a low dropout (LDO) regulator 101. The bootstrap capacitor 111 is coupled to the pin V BOOT The load path terminals (eg, drain terminal and source terminal) of transistor 105 are coupled to pin V BOOT With pin V CC Between pins V CC is configured to be coupled to another supply voltage (e.g., +5V) that is provided by Figure 1 In the example of LDO regulator 101, the voltage at pin V IN In addition to LDO regulators, other types of linear regulators can be used to generate the supply voltage at pin V CC In some embodiments, pin V CCThe supply voltage at pin SW may be provided by an external voltage source external to IC device 110 without using a regulator inside IC device 110. During operation of the buck converter, when switch 109 (e.g., an N-type transistor) needs to be closed (e.g., transistor 109 needs to be turned on), bootstrap control circuit 103 turns switch 105 off, and the voltage across bootstrap capacitor 111 (provided by the charge stored in bootstrap capacitor 111) provides a gate-source voltage (e.g., +5V) to transistor 109 to turn on transistor 109. When switch 109 is opened (e.g., transistor 109 is turned off), the voltage at pin SW is low (e.g., pin V BOOT The corresponding voltage at the pin is equal to or lower than the VC C When the voltage at the pin V CC The supply voltage at the V pin charges the bootstrap capacitor 111 (e.g., to restore the +5V voltage across the bootstrap capacitor 111). The capacitance of the bootstrap capacitor 111 can be large, so an external capacitor is used as the bootstrap capacitor 111, and the pin V BOOT is used to provide an electrical connection between the bootstrap capacitor 111 and the switch 105 .

[0029] Figure 1 The buck converter shown in is merely a non-limiting example. Variations are possible and are fully intended to be included within the scope of this disclosure. For example, Figure 1 The switch 131 in may be replaced by a diode whose cathode is connected to the pin SW and whose anode is connected to the pin GND.

[0030] The control circuit for the buck converter and the operation of the control circuit are discussed below. Figure 1 In the embodiment shown in , the components which do not belong to the buck converter belong to the control circuit.

[0031] Still reference Figure 1 , the output voltage of the buck converter V OUT is sent to a voltage divider formed by resistors 135 and 137, which are coupled between node 133 and a reference node connected to a reference voltage (e.g., electrical ground). The output of the voltage divider, referred to as feedback voltage 136, is sent to pin V FB .exist Figure 1 In the example, the feedforward capacitor C FF The node 113 is coupled to the pin V FB Between. Feedforward capacitor C FF can be used to stabilize the system at a large number of application points in terms of output voltage and frequency. In some embodiments, the feedforward capacitor C is omitted FF .

[0032] like Figure 1 As shown in FIG. 1 , the feedback voltage 136 is sent to the inverting input terminal of the PWM comparator 121 (also referred to as the comparator 121 ) and to the inverting input terminal of the transconductance amplifier 113 . REF is supplied to the non-inverting input terminal of the transconductance amplifier 113. In some embodiments, the reference voltage V REF The internal voltage of the IC device 110 may be obtained and used to set the target output voltage or feedback voltage of the buck converter.

[0033] The transconductance amplifier 113 generates a voltage at an output terminal 114 of the transconductance amplifier 113 that is equal to the reference voltage V REF The output current is proportional to the difference between the output terminal 114 and the feedback voltage 136. Capacitor 117 is coupled between the output terminal 114 and a reference voltage node (eg, electrical ground). In some embodiments, the output current of the transconductance amplifier 113 charges the capacitor 117 and generates a voltage COMP at the output terminal 114.

[0034] The voltage COMP is sent to the ramp signal generator 119. In addition, the control signal 140 for the ramp signal generator 109 generated by the edge detector 139 is also sent to the ramp signal generator 119. In an embodiment, the edge detector 139 is a rising edge detector that generates a narrow pulse (e.g., having a pulse width between a few nanoseconds and tens of nanoseconds) when a rising edge in the switch control signal 128A is detected. In other words, the edge detector 139 generates a narrow pulse in the control signal 140 in response to the rising edge in the switch control signal 128A, so that the narrow pulse occurs at the rising edge of the switch control signal 128A. The narrow pulse in the control signal 140 can be used as a reset signal for the ramp signal generator 119 and other circuits of the IC device 110.

[0035] The ramp signal generator 119 generates a linear ramp voltage and adds the linear ramp voltage to the voltage COMP to generate a compensation ramp voltage 120 at the output terminal of the ramp signal generator 119. Figure 1 In the example of FIG. 1 , the compensation ramp voltage 120 is sent to the non-inverting input terminal of the comparator 121. Details of the linear ramp voltage and different embodiments of the ramp signal generator 119 will be discussed below.

[0036] The comparator 121 compares the compensation ramp voltage 120 with the feedback voltage 136 and generates an output signal 122 (also referred to as a PWM_COMP signal). For example, if the compensation ramp voltage 120 is higher than the feedback voltage 136, the output signal 122 has a logic high (HIGH) value; and if the compensation ramp voltage 120 is lower than the feedback voltage 136, the output signal 122 has a logic low (LOW) value.

[0037] exist Figure 1 In the example of , the pulse generator 123 is configured to detect a rising edge in the output signal 122 and generate a pulse in the pulse signal 124 in response to detecting the rising edge. The pulses in the pulse signal 124 have a fixed pulse width and are used by the logic circuit 127 to generate the switch control signals 128A and 128B. For example, if the buck converter operates in a continuous conduction mode, the pulse signal 124 can pass through the logic circuit 127 and be used as the switch control signal 128A, while the complement of the pulse signal 124 (e.g., generated by an inverter in the logic circuit 127) is used as the switch control signal 128B. If the buck converter operates in a discontinuous conduction mode, the logic circuit 127 can include additional circuitry for generating a dead time when both switches 109 and 131 are off. In the illustrated embodiment, the pulse width of the pulse signal 124 (e.g., the duration that the pulse signal 124 has a logic high value) determines (e.g., is equal to) the on time of the switch 109, and since the pulse width of the pulse signal 124 is constant, the buck converter discussed herein functions as a constant on time (COT) buck converter. Note that in Figure 1 In FIG. 1 , the resistor 125 is coupled to the pin RRON of the IC device 110 and is used to determine the pulse width of the pulse signal 124. Therefore, Figure 1 The pulse generator 123 shown in the dashed box corresponds to a portion of the pulse generator integrated in the IC device 110 , and the resistor 125 is a portion of the pulse generator but is implemented as an external component.

[0038] Figure 2 FIG. 1 is a block diagram of a pulse generator 150 in an embodiment. The pulse generator 150 may be used as Figure 1 The pulse generator 123. Note that Figure 1 The resistor 125 coupled to the pin RRON of the IC device 110 is also Figure 2 Medium picture.

[0039] exist Figure 2 , the pulse generator 150 includes an operational amplifier 145. A first input terminal (eg, a non-inverting input terminal) of the operational amplifier 145 is coupled to an output terminal of a voltage divider formed by resistors 141 and 143. The resistors 141 and 143 are coupled to a pin VIN The voltage divider provides a voltage between the pin V and a reference voltage node (eg, electrical ground) to the first input terminal of the operational amplifier 145. IN A scaled version of the voltage at , denoted as K s ×V IN , where K s is a constant scaling factor.

[0040] A second input terminal (eg, inverting input terminal) of the operational amplifier 145 is coupled to the pin RRON. A voltage at the second input terminal of the operational amplifier 145 equal to the voltage at the first input terminal of the operational amplifier 145 generates a current I=K flowing through the resistor 125. s ×V IN / R RON , where R RON is the resistance of resistor 125. The mirror current I m is generated by a current mirror circuit (which includes transistors 147 and 149 ) and charges capacitor 155 which is coupled to the non-inverting input terminal of comparator 157 .

[0041] The switch 153 is coupled in parallel with the capacitor 155 and is controlled by the control signal T OFF Control. When the control signal T OFF When the control signal T is logic high, the switch 153 is closed to discharge the capacitor 155 and reset the voltage across the capacitor 155 to zero. OFF When the logic is low, the switch 153 is turned off and the mirror current I m The capacitor 155 is charged. Therefore, the voltage across the capacitor 155 (expressed as voltage V RAMPI ) increases linearly from zero over time. Comparator 157 converts the voltage V RAMPI and the reference voltage V applied to the inverting input terminal of the comparator 157 REFI Compare and generate output signal T ON_END . Reference voltage V REFI The reference voltage may be a constant reference voltage that is internally generated from other supply voltages within the IC device 110 .

[0042] Still refer to Figure 2 , the output signal T of the comparator 157 ON_END is sent to the edge detector 163. The edge detector 163 is configured to detect the output signal T ON_END The rising edge in the output signal T ON_END The output signal 164 starts at the rising edge of (eg, a short pulse for each rising edge, also referred to as END TON pulse). Figure 2Another edge detector 175 is also shown. The edge detector 175 is configured to Figure 1 The comparator 121 receives the PWM_COMP signal, detects the rising edge in the PWM_COMP signal and generates an output signal 176 starting at the rising edge of the PWM_COMP signal (e.g., a short pulse for each rising edge, also referred to as a START TON pulse). Each START TON Pulse and corresponding END TON Pulse is used to generate pulse signals, details are given below. Figure 2 and Figure 3 Have a discussion.

[0043] exist Figure 2 In the example of FIG. 1 , the output signal 176 (eg, START TON The pulse) is sent to the set (SET, S) terminal of the flip-flop 167, and the output signal 164 (e.g., END) of the edge detector 163 TON A pulse) is sent to a reset (RESET, R) terminal of flip-flop 167. Flip-flop 167 can be, for example, a set-reset (SR) latch formed by a pair of cross-coupled NOR gates. In some embodiments, when the set terminal and the reset terminal are in a logic low state (e.g., the signals at the set and reset terminals have logic low values), the output of flip-flop 167 (e.g., pulse signal 124) maintains its current value. If the set terminal is pulsed high and the reset terminal remains low, then pulse signal 124 is forced high and stays high when the set terminal returns to low; similarly, if the reset terminal is pulsed high while the set terminal remains low, then pulse signal 124 is forced low and stays low when the reset terminal returns to low. Pulse signal 124 may also be referred to as T ON signal, and T OFF The signal is obtained by using an inverter 179 to convert the signal T ON Generated by inversion.

[0044] Figure 3 The diagram shows the embodiment used for Figure 2 The timing diagram of the pulse generator. Figure 3 As shown in, signal T ON The pulse width is determined by Figure 2 The voltage across capacitor 155 increases linearly from zero to voltage V REFI In other words, the mirror current I m The speed at which capacitor 155 is charged determines T ON The pulse width of the signal. Those skilled in the art will readily recognize that given the capacitance of capacitor 155, the signal T ONThe pulse width can be adjusted by adjusting the resistance R of resistor 125 RON In some embodiments, the larger the resistance of resistor 125, the smaller the mirror current I m The smaller the signal T ON The larger the pulse width, the smaller the resistance of resistor 125, resulting in a mirror current I m The larger the T ON The smaller the pulse width of the signal.

[0045] To achieve stability of the buck converter, the control circuit for the buck converter may require information about the output voltage of the buck converter and / or the switching frequency of the buck converter. In some embodiments, the switching frequency of the buck converter is the frequency at which the switch 109 is switched on and off during operation. The switching frequency of the buck converter may be calculated as Where P TON It is signal T ON The duration of the positive pulse (see, for example, Figure 3 ), and P TOFF It is signal T OFF The duration of the positive pulse (see, for example, Figure 3 ). However, the output voltage of the buck converter and the switching frequency of the buck converter may not be easily available to the control circuit. In addition, for the design of IC device 110, it is advantageous to keep the pin count of IC device 110 low to keep the design simple and cost-effective. Therefore, it would be advantageous to design a control circuit that can receive combined information about the output voltage and switching frequency of the buck converter using fewer pins. In some embodiments, Figure 1 The resistance R of the resistor 125 RON Given by:

[0046]

[0047] Where V OUT is the target output voltage of the buck converter in volts; f SW is the target switching frequency of the buck converter in kHz; K RON is a constant; and R RON The unit is kΩ. In some embodiments, the resistor R RON The range is between several thousand ohms and several hundred kiloohms, and the constant K RON is defined as the resistor R RON Keep within this range. The resistance R in equation (1) RON T is determined based on the combined information about the output voltage and switching frequency of the buck converter. ONThe pulse width of the signal. The resistance R of the resistor 125 in equation (1) is RON The selection of reduces the pin count of the IC device 110 while achieving improved stability of the buck converter.

[0048] From the above discussion, the skilled person will readily appreciate that, among other factors, the compensation ramp voltage 120 generated by the ramp signal generator 119 largely determines the switching behavior and performance of the buck converter. In order to achieve good control of the buck converter, the compensation ramp voltage 120 should have a sufficiently large amplitude to avoid jitter due to the accuracy of the comparator 121. In addition, the gradient (also called the slope) of the compensation ramp voltage 120 should be within a specific range. In particular, the inventors of the present application have found that, given the target output voltage ripple ΔV of the buck converter, the compensation ramp voltage 120 should be within a specific range. OUT (For example, the output voltage V OUT ripple in the buck converter) and the target switching frequency f x , the gradient S of the compensation ramp voltage 120 x (also called the slope) is given by:

[0049] S x >K×f x ×ΔV OUT (2)

[0050] Where K is a multiplication factor having a value between about 1.5 and about 5. The value of K can be found, for example, by performing simulations and analysis on a buck converter. In this discussion, the inverse of the switching frequency (e.g., 1 / f x ) is called the switching cycle of the buck converter. In the embodiment shown, due to the feed-forward capacitor C FF , output voltage ripple ΔV OUT The feedback voltage ripple ΔV of the buck converter FB (e.g., the ripple in the feedback voltage 136) is the same. In other words, in the illustrated embodiment, ΔV OUT =ΔV FB .

[0051] As shown in equation (2), the slope value required for the compensation ramp voltage 120 is related to the switching frequency f x However, in Figure 1 The switching frequency f is not known in the control circuit x A solution to this challenge is to use a closed loop system to track (eg, measure) the switching frequency of the buck converter and generate the compensation ramp voltage 120 as a linear voltage with a constant slope that is proportional to the switching frequency of the buck converter.

[0052] Figure 4FIG. 2 is a block diagram of a ramp signal generator 200 in an embodiment. The ramp signal generator 200 can be used as Figure 1 The ramp signal generator 119 in FIG. Figure 4 A high-level general block diagram of the ramp signal generator 200 is shown. Figure 7-9 discuss Figure 4 Different embodiments of the ramp signal generator 200 in FIG.

[0053] exist Figure 4 In the embodiment, the ramp signal generator 200 includes a frequency tracking circuit 201 and a ramp generator 203. The frequency tracking circuit 201 receives an input signal indicating the switching frequency of the buck converter, such as a control signal 140 (also referred to as an Edge_Dect_Out signal) generated by the edge detector 139. In addition to the control signal 140, other signals may be used, such as the output signal 122 (also referred to as the PWM_COMP signal) of the PWM comparator 121 or the pulse signal 124 (also referred to as the T ON Based on the input signal (eg, the control signal 140), the frequency tracking circuit 201 tracks (eg, measures or estimates) the switching frequency of the buck converter and converts the estimated switching frequency f SW is sent to the ramp generator 203. Then, the ramp generator 203 generates a switching frequency having the same value as the estimated switching frequency f SW A linear ramp voltage with a gradient proportional to V RAMP , and the linear ramp voltage V RAMP The voltage COMP at the output terminal 114 of the transconductance amplifier 113 is added to generate the compensation ramp voltage 120 (also referred to as V COMP_RAMP Signal).

[0054] Figure 5A and Figure 5B The embodiment is shown in the figure Figure 1 Timing diagram of a constant on-time (COT) buck converter at two different switching frequencies. Figure 5A shows the buck converter at low switching frequency F SW1 Press the switch, and Figure 5B shows that the buck converter operates at a higher switching frequency F SW2 Press the switch.

[0055] exist Figure 5A In some embodiments, during steady-state operation of the buck converter, the voltage COMP is shown as a constant voltage. Figure 1The voltage COMP at the output terminal 114 in the buck converter is quasi-static (e.g., changes very slowly) so that the voltage COMP can be treated as if it has a constant value over tens, hundreds, or more switching cycles of the buck converter. In some embodiments, in the steady state of the buck converter, the voltage COMP has a quasi-static value of zero.

[0056] Still refer to Figure 5A , ramp voltage V RAMP The ramp signal generator 119 (see Figure 1 ) is generated and added to the voltage COMP to form a compensation ramp voltage 120. For ease of discussion, the voltage COMP can be considered to be zero, so the ramp voltage V RAMP is considered to be the same as the compensation ramp voltage 120 . Figure 5A The sinusoidal waveform curve in the figure shows the feedback voltage V FB , which revolves around a constant reference voltage V REF oscillation. Note that the feedback voltage V FB The feedback voltage V is shown as a sinusoidal waveform for illustration purposes only. FB The actual shape of may not be a sine wave. Figure 5A and Figure 1 , when the rising ramp voltage V RAMP Reaching the feedback voltage V FB When the PWM_COMP signal at the output terminal of the comparator 121 is the same value, the PWM_COMP signal at the output terminal of the comparator 121 becomes logic high. In response to the rising edge of the PWM_COMP signal, the pulse generator 123 ON A pulse is generated in the signal (eg, pulse signal 124). ON The signal is used by logic circuit 127 to generate switch control signals 128A and 128B for switching switches 109 and 131 of the buck converter. The rising edge of switch control signal 128A is detected by edge detector 139 to generate a narrow pulse in control signal 140. As will be discussed in more detail, the narrow pulse in control signal 140 increases the ramp voltage V RAMP Therefore, the PWM_COMP signal becomes logic low soon after it becomes logic high, and the ramp voltage V RAMP The increment starts again from zero and the process discussed above repeats again.

[0057] Figure 5B and Figure 5A Similar, but the buck converter switches at a higher switching frequency. Figure 5B As shown in FIG. 1 , due to the higher switching frequency, the ramp voltage V generated by the ramp signal generator 119 RAMP has a higher gradient. It is worth noting that Figure 5A and Figure 5BIn each switching cycle (equal to the ramp voltage V RAMP The ramp voltage V RAMP In other words, the ramp voltage V at the end of each switching cycle is always the same regardless of the buck converter’s switching frequency. RAMP The final values ​​of all have the same fixed value.

[0058] Figure 6 The figure shows the gradient of the compensation ramp voltage of the buck converter at different switching frequencies in the embodiment. In the discussion of this article, the gradient of the compensation ramp voltage 120 is related to the ramp voltage V RAMP The gradients of are considered to be the same. The first column shows the switching frequency, and the second column shows the corresponding switching period. The third column shows the slope S of the compensation ramp voltage at the corresponding switching frequency. x The fourth column shows the equivalent ramp amplitude for each switching frequency, where the equivalent ramp amplitude is the final value of the compensation ramp voltage 120 at the end of each switching cycle. It is worth noting that in the example of FIG. 5 , the equivalent ramp amplitudes for all switching frequencies have the same value.

[0059] Figure 7 The block diagram of a ramp signal generator 200A having a phase-locked loop (PLL) in an embodiment is shown. The ramp signal generator 200A includes a PLL circuit 211 that tracks (eg, measures, estimates) the switching frequency of the buck converter based on an input signal indicating the switching frequency of the buck converter. Figure 7-9 In the embodiment of the present invention, as a non-limiting example, a control signal 140 generated by an edge detector 139 is used as an input signal. In addition to the control signal 140, other signals such as the output signal 122 of the PWM comparator 121 or the pulse signal 124 generated by the pulse generator 123 may also be used. PLL circuits for tracking frequency are known and used in the art, so the details thereof are not discussed here. Figure 7 In the example of FIG. 1 , the PLL circuit 211 is configured to generate an output current I PLL , where the output current I PLL The value of is proportional to the estimated buck converter frequency.

[0060] The ramp signal generator 200A further includes an operational amplifier 213. The non-inverting input terminal of the operational amplifier 213 is configured to be coupled to the output terminal 114 of the transconductance amplifier 113, so as to be supplied with the voltage COMP. The inverting input terminal of the operational amplifier 213 is coupled to the output terminal of the PLL circuit 211. The capacitor 215 is coupled between the inverting input terminal of the operational amplifier 213 and the output terminal of the operational amplifier 213. A switch 217 (e.g., a transistor, etc.) controlled by, for example, the control signal 140 (Edge_Dect_Out signal) is coupled in parallel with the capacitor 215.

[0061] At the beginning of the buck converter's switching cycle, a short pulse in the Edge_Dect_Out signal closes switch 217 for a short period of time to discharge capacitor 215 and reset the voltage across capacitor 215 to zero. Switch 217 then opens, allowing output current I PLL The capacitor 215 is charged. The voltage across the capacitor 215, i.e., the ramp voltage V RAMP , increases linearly with time. The ramp voltage V RAMP The gradient of the output current I PLL The output current I PLL The direction of Figure 7 As shown in FIG. 1 , therefore, the voltage 120 at the output terminal of the operational amplifier 213 is the ramp voltage V RAMP Superimposed on the voltage COMP, the voltage 120 is the compensation ramp voltage 120 .

[0062] Figure 8 FIG. 2 is a block diagram of a ramp signal generator 200B having a phase-locked loop (PLL) in another embodiment. The ramp signal generator 200B is similar to the ramp signal generator 200A, but has a ramp current generator 219 coupled between the PLL circuit 211 and the inverting input terminal of the operational amplifier 213, and has a resistor 221 instead of Figure 7 Capacitor 215 in.

[0063] exist Figure 8 The output current I generated by the PLL circuit 211 is proportional to the switching frequency of the buck converter. PLL is sent to the ramp current generator 219. The ramp current generator 219 is configured to generate a ramp current I which increases linearly from zero to a final value during the switching cycle of the buck converter. RAMP The ramp current I RAMP The gradient of the ramp current I RAMP flows through resistor 221 to generate a ramp voltage V RAMP Other details and Figure 7Those are the same or similar and therefore will not be repeated here.

[0064] Fig. 9 A block diagram of a ramp signal generator 200C with an integrator circuit for closed-loop control in an embodiment is illustrated. The ramp signal generator 200C includes two circuits disposed on opposite sides of a dashed line 250: a current generating circuit 220 and a voltage generating circuit 260. The current generating circuit 220 is configured to generate a current I2 proportional to the switching frequency of the buck converter in the steady state of the buck converter. The voltage generating circuit 260 is configured to generate a compensation ramp voltage 120 based on the current I2. Details are discussed below.

[0065] The current generating circuit 220 includes a current source 231, which is an adjustable current source for generating a current I1 based on an adjustment signal 244. In some embodiments, the generated current I1 is proportional to the adjustment signal 244. A capacitor 235 is coupled between the current source 231 and a reference node (e.g., electrical ground). A switch 233 is coupled in parallel with the capacitor 235 and is controlled by a control signal 140 generated, for example, by an edge detector 139. When the control signal 140 is logic high, the switch 233 is closed, and when the control signal 140 is logic low, the switch 233 is open.

[0066] Still see Fig. 9 , the resistor 237 is coupled between the inverting input terminal of the operational amplifier 239 and the node 234 between the current source 231 and the capacitor 235. The non-inverting input terminal of the operational amplifier 239 is supplied with a reference voltage V REF The capacitor 241 is coupled between the inverting input terminal of the operational amplifier 239 and the output terminal of the operational amplifier 239.

[0067] The current generating circuit 220 also includes a gain circuit 243 that generates an adjustment signal 244 based on a voltage 240 at an output terminal of the operational amplifier 239. The gain factor of the gain circuit 243 is represented as gm and may also be referred to as a transconductance gain. For example, the adjustment signal 244 may be obtained by multiplying the value of the voltage signal 240 by the gain factor gm. The current I1 generated by the current source 231 is actually controlled by the voltage 240, and therefore, the current source 231 may be considered as a voltage-controlled current source (VCCS). In some embodiments, the current source 231 and the gain circuit 220 may be implemented together as a voltage-controlled current source, such as a transconductance amplifier whose transconductance gain is gm.

[0068] The current generating circuit 220 further includes a current source 247, which is an adjustable current source that generates a current I2 based on an adjustment signal 246 generated by the gain circuit 245. In some embodiments, the current I2 generated by the current source 247 is proportional to the adjustment signal 246. In some embodiments, if the adjustment signals of the current source 247 and the current source 231 are the same, then the current source 247 and the current source 231 generate the same output current value. The gain circuit 245 has a gain factor Note that for ease of discussion, V RAMP In this article, it is also used to represent the ramp voltage V RAMP The final value (e.g., maximum value) during the switching cycle, and V REF In this article, it is also used to represent the reference voltage V REF In some embodiments, the adjustment signal 246 can be obtained by multiplying the value of the voltage signal 240 by the gain factor gm×V RAMP / V REF The current I2 generated by the current source 247 is actually controlled by the voltage 240, so the current source 247 can be considered as a voltage controlled current source (VCCS). In some embodiments, the current source 247 and the gain circuit 245 can be implemented together as a voltage controlled current source, such as a transconductance gain of gm×V RAMP / V REF transconductance amplifier.

[0069] Gain circuit 243 is used as a feedback path to form a closed-loop control system so that during the steady state of the buck converter, voltage 240 is at a target value (eg, V REF / 2), or equivalently, at the end of each switching cycle, the voltage across capacitor 235 is equal to the target value V REF As discussed in detail below, in order to achieve the target value V REF , the value of current I1 is adjusted according to the switching frequency of the buck converter.

[0070] At the beginning of each switching cycle, switch 233 is closed for a short period of time to reset the voltage across capacitor 235 to zero. Then, switch 233 is opened, and current I1 charges capacitor 235, so the voltage across capacitor 235 increases linearly during the switching cycle. The voltage difference across resistor 237, i.e., voltage V REF The difference between 1 / 2 and the voltage across capacitor 235 generates a current through resistor 237 and capacitor 241. In the illustrated embodiment, capacitor 241 forms a low bandwidth filter such that voltage 240 at the output terminal of operational amplifier 239 has a substantially constant value.

[0071] Those skilled in the art will readily recognize that, given the switching frequency of the buck converter and the capacitance of capacitor 235, the value of current I1 determines the final value reached by linearly increasing the voltage across capacitor 235 at the end of the switching cycle. If the final value of the voltage across capacitor 235 is lower or higher than the target value V REF , then the voltage 240 deviates from its target value (e.g., V REF / 2). The feedback control loop will adjust (e.g., increase or decrease) current I1 so that the final value of the voltage across capacitor 235 is at the target value. In other words, the feedback control loop ensures that current I1 is proportional to the switching frequency of the buck converter and that charging capacitor 235 with current I1 results in a final value V at the end of the buck converter's switching cycle. REF The linear voltage.

[0072] Still refer to Fig. 9 The voltage generating circuit 260 includes an operational amplifier 249. The inverting input terminal of the operational amplifier 249 is coupled to the current source 247, and the non-inverting input terminal of the operational amplifier 249 is coupled to the output terminal 114 of the transconductance amplifier 113 (see Figure 1 ), thereby being configured to be supplied with voltage COMP. Capacitor 251 is coupled between the non-inverting input terminal of operational amplifier 249 and the output terminal of operational amplifier 249. Switch 253 is coupled in parallel with capacitor 251 and is controlled in the same or similar manner as switch 233, for example, by control signal 140. It is worth noting that capacitor 251 has the same capacitance C as capacitor 235. The capacitance matching between capacitor 251 and capacitor 235 ensures that the ramp voltage V across capacitor 251 is RAMP At the end of the switching cycle, it is at the target value V RAMP , as discussed below.

[0073] Since the ratio of the gain factor of gain circuit 245 to the gain factor of gain circuit 243 is V RAMP / V REF , so the current I2 generated by the current source 247 is a factor of V compared to the current I1 RAMP / V REF Therefore, when the capacitor 251 (which has the same capacitance C as the capacitor 235) is charged using the current I2, the final value of the ramp voltage across the capacitor 251 is In other words, the final value of the ramp voltage achieved at the end of the switching cycle is V RAMP The voltage 120 at the output terminal of the operational amplifier 249 is the compensation ramp voltage 120, which is equal to the ramp voltage V added to the voltage COMP. RAMP .

[0074] Fig.10 The embodiment of the invention is shown in FIG. Figure 1 The pins of the integrated circuit (IC) device 110 are as follows. Fig.10 As shown in , the number of pins used for IC device 110 is very small, for example, only 8 pins, which reduces the manufacturing cost and the cost of deploying IC device 110 in the field. Fig.10 The pins in Figure 1 The pins shown in the figure match the pin names. Note that Fig.10 The diagram shows Figure 1 Compared to an additional pin (eg, an enable pin EN / UVLO), the enable pin EN / UVLO is used to enable or disable the IC device 110. The number of external components required for the IC device 110 is also very limited, such as Fig.10 The two capacitors CVIN and CVCC are used to filter out the in and V cc The high frequency components of the supply voltage at Figure 1 , so it will not be discussed here.

[0075] Fig.11 1 is a flow chart illustrating a method 1000 of operating a buck converter in some embodiments. It should be understood that Fig.11 The example methods shown in are merely examples of many possible example methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, or repeated: Fig.11 The various steps shown in .

[0076] refer to Fig.11 At block 1010, the output voltage of the buck converter is divided to generate a feedback voltage. At block 1020, the feedback voltage is sent to a first input terminal of a comparator. At block 1030, the feedback voltage and the reference voltage are sent to a first input terminal of a transconductance amplifier and a second input terminal of the transconductance amplifier, respectively. At block 1040, a ramp signal generator generates a compensation ramp voltage, which is equal to the sum of a first voltage at the output terminal of the transconductance amplifier and the ramp voltage, wherein the ramp voltage is a linear voltage signal having a gradient proportional to the switching frequency of the buck converter. At block 1050, the compensation ramp voltage is sent to a second input terminal of the comparator. At block 1060, a pulse generator generates a pulse signal, which includes a pulse corresponding to a rising edge in the output signal of the comparator. At block 1070, the buck converter is switched under the control of a switch control signal derived from the pulse signal.

[0077] Embodiments can achieve the advantages described below. For example, the disclosed control circuit for a COT buck converter does not require direct information of the output voltage and the switching frequency to be input from the pins of the IC device 110, thereby reducing the number of pins required for the IC device 110. The combination of the output voltage and the switching frequency is provided to the pin RRON of the IC device 110 to determine the signal T ON In the feedback path, in addition to the voltage divider, only non-dissipative capacitor C is used. FF (which is optional), which reduces power consumption and improves the power efficiency of the buck converter. In addition, the control circuit of the buck converter performs stability control by using a PLL circuit to generate an output signal (e.g., a current signal) proportional to the switching frequency of the buck converter, and then generates a compensation ramp voltage with a gradient proportional to the output signal. The compensation ramp voltage generated by the disclosed ramp signal generator achieves stability of the buck converter over a wide range of output voltage ripple and switching frequency.

[0078] Examples of the invention are summarized here. Other examples can also be understood from the overall description and claims submitted herein.

[0079] Example 1. According to an embodiment, a switch mode power supply (SMPS) includes: a buck converter; and a control circuit for the buck converter, including: a comparator configured to compare a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator coupled to an output terminal of the comparator and configured to generate a pulse signal in response to a rising edge of an output signal of the comparator, wherein a switch of the buck converter is controlled by the pulse signal; a transconductance amplifier, wherein a first input terminal of the transconductance amplifier is configured to receive the feedback voltage, and a second input terminal of the transconductance amplifier is configured to receive a reference voltage; a first capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and a ramp signal generator configured to generate a ramp voltage and add the ramp voltage to a first voltage at the output terminal of the transconductance amplifier to generate a compensation ramp voltage, wherein the ramp voltage is a linear voltage signal, and the ramp signal generator is configured to adjust the gradient of the linear voltage signal according to the switching frequency of the buck converter.

[0080] Example 2. The SMPS of Example 1, wherein the ramp signal generator is configured to adjust the gradient of the linear voltage signal to be proportional to the switching frequency of the buck converter.

[0081] Example 3. The SMPS of Example 2, wherein in a steady state of the buck converter, the value of the ramp voltage at the end of a switching cycle of the buck converter has a fixed value, wherein the fixed value is independent of the switching frequency of the buck converter.

[0082] Example 4. The SMPS of Example 3 further includes: a logic circuit configured to derive a switch control signal for a buck converter from the pulse signal, wherein the switch control signal controls switching of one or more switches of the buck converter; and an edge detector configured to generate a control signal for a ramp signal generator by detecting a rising edge in the switch control signal.

[0083] Example 5. The SMPS of Example 3, wherein the pulse signal has a fixed pulse width.

[0084] Example 6. The SMPS of Example 3, wherein the gradient of the linear voltage signal is equal to or greater than S x , where S x =K×f swx ×ΔV out , ΔV out is the output voltage ripple of the buck converter, f swx is the switching frequency of the buck converter, and K is a constant value.

[0085] Example 7. The SMPS of Example 1, further comprising: a voltage divider coupled between the output terminal of the buck converter and a reference voltage node, wherein the voltage divider comprises a first resistor and a second resistor coupled in series; and a feed-forward capacitor coupled between the output terminal of the buck converter and a node between the first resistor and the second resistor.

[0086] Example 8. The SMPS of Example 1, wherein the ramp signal generator comprises: a phase-locked loop (PLL) configured to track the switching frequency of the buck converter and generate an output current signal proportional to the switching frequency of the buck converter; an operational amplifier, wherein a non-inverting input terminal of the operational amplifier is coupled to the output terminal of the transconductance amplifier, and an inverting input terminal of the operational amplifier is coupled to the output terminal of the PLL; a second capacitor coupled between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier; and a switch coupled in parallel with the second capacitor, wherein the switch is configured to be closed for a period of time at the beginning of a switching cycle of the buck converter.

[0087] Example 9. The SMPS of Example 1, wherein the ramp signal generator comprises: a phase-locked loop (PLL) configured to track the switching frequency of the buck converter and generate a first current signal proportional to the switching frequency of the buck converter; a ramp current generator configured to generate a second current signal that increases linearly within the switching cycle of the buck converter, wherein the gradient of the second current signal is proportional to the value of the first current signal; an operational amplifier, wherein a non-inverting input terminal of the operational amplifier is coupled to the output terminal of the transconductance amplifier, and an inverting input terminal of the operational amplifier is coupled to the output terminal of the ramp current generator; a resistor coupled between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier; and a switch coupled in parallel with the resistor, wherein the switch is configured to be closed for a period of time at the beginning of the switching cycle of the buck converter.

[0088] Example 10. The SMPS of Example 1, wherein the ramp signal generator comprises: a first adjustable current source, wherein the first adjustable current source is configured to be controlled by a first adjustment signal and to generate a first supply current proportional to a switching frequency of the buck converter; a first operational amplifier, wherein a non-inverting input terminal of the first operational amplifier is coupled to an output terminal of the transconductance amplifier, and an inverting input terminal of the first operational amplifier is coupled to the first adjustable current source; a second capacitor coupled between an inverting input terminal of the first operational amplifier and an output terminal of the first operational amplifier; and a first switch coupled in parallel with the second capacitor, wherein the first switch is configured to be closed for a period of time at the beginning of a switching cycle of the buck converter.

[0089] Example 11. The SMPS of Example 10, wherein the ramp signal generator further comprises: a second adjustable current source, wherein the second adjustable current source is configured to be controlled by a second adjustment signal and to generate a second supply current; a third capacitor coupled between the second adjustable current source and a reference voltage node; a second switch coupled in parallel with the third capacitor, wherein the second switch and the first switch are controlled by the same control signal; a second operational amplifier, wherein a non-inverting input terminal of the second operational amplifier is configured to receive a voltage equal to half the reference voltage; a resistor coupled between an inverting input terminal of the second operational amplifier and a node between the second adjustable current source and the third capacitor; a fourth capacitor coupled between an inverting input terminal of the second operational amplifier and an output terminal of the second operational amplifier; a first gain circuit coupled to the output terminal of the second operational amplifier and configured to generate a first adjustment signal; and a second gain circuit coupled to the output terminal of the second operational amplifier and configured to generate a second adjustment signal.

[0090] Example 12. The SMPS of Example 11, wherein the second capacitor and the third capacitor have the same capacitance, and wherein the second gain circuit has a transconductance gain G m, and the first gain circuit has a transconductance gain G m ×V RAMP ×V REF , where V RAMP is the value of the ramp voltage at the end of the buck converter switching cycle, and V REF is the reference voltage.

[0091] Example 13. According to an embodiment, an integrated circuit (IC) device includes: one or more switches of a buck converter; and a control circuit for the buck converter, including: a comparator configured to generate a comparator output signal by comparing a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator configured to generate a pulse signal in response to a rising edge of the comparator output signal, wherein the buck converter is configured to be controlled by a switch control signal derived from the pulse signal; a transconductance amplifier configured to generate a current proportional to a difference between a reference voltage and a feedback voltage at an output terminal of the transconductance amplifier; a first capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and a ramp signal generator configured to generate a compensation ramp voltage by adding a first voltage at the output terminal of the transconductance amplifier to a ramp voltage generated by the ramp signal generator, wherein the ramp voltage is a linear voltage signal having a gradient proportional to a switching frequency of the buck converter.

[0092] Example 14. The IC device of Example 13, wherein the pulse signal has a fixed pulse width.

[0093] Example 15. The IC device of Example 13, wherein in a steady state of the buck converter, a value of the ramp voltage at the end of a switching cycle of the buck converter has a fixed value, wherein the fixed value is independent of a switching frequency of the buck converter.

[0094] Example 16. The IC device of Example 13, wherein the gradient of the linear voltage signal is equal to or greater than S x , where S x =K×f swx ×ΔV out , ΔV out is the output voltage ripple of the buck converter, f swx is the switching frequency of the buck converter, and K is a constant value.

[0095] Example 17. An IC device of Example 13, wherein the ramp signal generator includes: a phase tracking circuit configured to track the switching frequency of the buck converter and generate an output signal proportional to the switching frequency of the buck converter; and a ramp generating circuit configured to: generate a ramp voltage having a gradient proportional to the switching frequency of the buck converter based on the output signal of the phase tracking circuit; and add the ramp voltage to the first voltage at the output terminal of the transconductance amplifier to generate a compensation ramp voltage.

[0096] Example 18. According to an embodiment, a method for operating a buck converter includes: dividing the output voltage of the buck converter to generate a feedback voltage; sending the feedback voltage to a first input terminal of a comparator; sending the feedback voltage and a reference voltage to a first input terminal of a transconductance amplifier and a second input terminal of the transconductance amplifier, respectively; using a ramp signal generator to generate a compensation ramp voltage, which is equal to the sum of a first voltage at the output terminal of the transconductance amplifier and the ramp voltage, wherein the ramp voltage is a linear voltage signal having a gradient proportional to a switching frequency of the buck converter; sending the compensation ramp voltage to a second input terminal of the comparator; using a pulse generator to generate a pulse signal, which includes a pulse corresponding to a rising edge in the output signal of the comparator; and switching the buck converter under the control of a switch control signal derived from the pulse signal.

[0097] Example 19. The method of Example 18, wherein the pulses of the pulse signal are generated to have a fixed pulse width.

[0098] Example 20. The method of Example 19, further comprising charging a capacitor using an output current generated by the transconductance amplifier, wherein the capacitor is coupled between an output terminal of the transconductance amplifier and a reference voltage node.

[0099] Although the present invention has been described with reference to illustrative examples, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative examples and other examples of the present invention will be apparent to those skilled in the art after reference to this description. Therefore, the appended claims are intended to cover any such modifications or examples.

Claims

1. A switch mode power supply (SMPS), comprising: Buck converter; as well as A control circuit for a buck converter comprising: a comparator configured to compare a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator coupled to the output terminal of the comparator and configured to generate a pulse signal in response to a rising edge of an output signal of the comparator, wherein a switch of the buck converter is controlled by the pulse signal; a transconductance amplifier, wherein a first input terminal of the transconductance amplifier is configured to receive a feedback voltage and a second input terminal of the transconductance amplifier is configured to receive a reference voltage; a first capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and A ramp signal generator is configured to generate a ramp voltage and add the ramp voltage to the first voltage at the output terminal of the transconductance amplifier to generate a compensation ramp voltage, wherein the ramp voltage is a linear voltage signal, and the ramp signal generator is configured to adjust the gradient of the linear voltage signal according to the switching frequency of the buck converter. 2 . The SMPS of claim 1 , wherein the ramp signal generator is configured to adjust a gradient of the linear voltage signal to be proportional to a switching frequency of the buck converter.

3. The SMPS of claim 2, wherein in a steady state of the buck converter, the value of the ramp voltage at the end of a switching cycle of the buck converter has a fixed value, wherein the fixed value is independent of the switching frequency of the buck converter.

4. The SMPS of claim 3, further comprising: a logic circuit configured to derive a switch control signal for the buck converter from the pulse signal, wherein the switch control signal controls switching of one or more switches of the buck converter; as well as The edge detector is configured to generate a control signal for the ramp signal generator by detecting a rising edge in the switch control signal. The SMPS of claim 3 , wherein the pulse signal has a fixed pulse width.

6. The SMPS of claim 3, wherein the gradient of the linear voltage signal is equal to or greater than S x , where S x =K×f swx ×ΔV out , ΔV out is the output voltage ripple of the buck converter, f swx is the switching frequency of the buck converter, and K is a constant value.

7. The SMPS of claim 1, further comprising: a voltage divider coupled between an output terminal of the buck converter and a reference voltage node, wherein the voltage divider includes a first resistor and a second resistor coupled in series; as well as A feed-forward capacitor is coupled between an output terminal of the buck converter and a node between the first resistor and the second resistor.

8. The SMPS of claim 1 , wherein the ramp signal generator comprises: a phase-locked loop (PLL) configured to track a switching frequency of the buck converter and generate an output current signal proportional to the switching frequency of the buck converter; an operational amplifier, wherein a non-inverting input terminal of the operational amplifier is coupled to the output terminal of the transconductance amplifier, and an inverting input terminal of the operational amplifier is coupled to the output terminal of the PLL; a second capacitor coupled between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier; as well as A switch is coupled in parallel with the second capacitor, wherein the switch is configured to be closed for a period of time at the beginning of a switching cycle of the buck converter.

9. The SMPS of claim 1 , wherein the ramp signal generator comprises: a phase-locked loop (PLL) configured to track a switching frequency of the buck converter and generate a first current signal proportional to the switching frequency of the buck converter; a ramp current generator configured to generate a second current signal that increases linearly during a switching period of the buck converter, wherein a gradient of the second current signal is proportional to a value of the first current signal; an operational amplifier, wherein a non-inverting input terminal of the operational amplifier is coupled to the output terminal of the transconductance amplifier, and an inverting input terminal of the operational amplifier is coupled to the output terminal of the ramp current generator; a resistor coupled between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier; as well as A switch is coupled in parallel with the resistor, wherein the switch is configured to be closed for a period of time at the beginning of a switching cycle of the buck converter.

10. The SMPS of claim 1, wherein the ramp signal generator comprises: a first adjustable current source, wherein the first adjustable current source is configured to be controlled by a first adjustment signal and to generate a first supply current proportional to a switching frequency of the buck converter; a first operational amplifier, wherein a non-inverting input terminal of the first operational amplifier is coupled to the output terminal of the transconductance amplifier and an inverting input terminal of the first operational amplifier is coupled to a first adjustable current source; a second capacitor coupled between the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier; as well as A first switch is coupled in parallel with the second capacitor, wherein the first switch is configured to be closed for a period of time at the beginning of a switching cycle of the buck converter.

11. The SMPS of claim 10, wherein the ramp signal generator further comprises: a second adjustable current source, wherein the second adjustable current source is configured to be controlled by a second adjustment signal and to generate a second supply current; a third capacitor coupled between the second adjustable current source and the reference voltage node; a second switch coupled in parallel with the third capacitor, wherein the second switch and the first switch are controlled by the same control signal; a second operational amplifier, wherein a non-inverting input terminal of the second operational amplifier is configured to receive a voltage equal to half the reference voltage; a resistor coupled between the inverting input terminal of the second operational amplifier and a node between the second adjustable current source and the third capacitor; a fourth capacitor coupled between the inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier; a first gain circuit coupled to the output terminal of the second operational amplifier and configured to generate a first adjustment signal; as well as The second gain circuit is coupled to the output terminal of the second operational amplifier and is configured to generate a second adjustment signal.

12. The SMPS of claim 11, wherein the second capacitor and the third capacitor have the same capacitance, and wherein the second gain circuit has a transconductance gain G m , and the first gain circuit has a transconductance gain G m ×V RAMP ×V EED , where V RAMP is the value of the ramp voltage at the end of the buck converter switching cycle, and V REF is the reference voltage.

13. An integrated circuit IC device, comprising: one or more switches of a buck converter; as well as A control circuit for a buck converter comprising: a comparator configured to generate a comparator output signal by comparing a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator configured to generate a pulse signal in response to a rising edge of the comparator output signal, wherein the buck converter is configured to be controlled by a switch control signal derived from the pulse signal; a transconductance amplifier configured to generate a current proportional to a difference between a reference voltage and a feedback voltage at an output terminal of the transconductance amplifier; a first capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and The ramp signal generator is configured to generate a compensation ramp voltage by adding a first voltage at an output terminal of the transconductance amplifier to a ramp voltage generated by the ramp signal generator, wherein the ramp voltage is a linear voltage signal having a gradient proportional to a switching frequency of the buck converter.

14. The IC device as claimed in claim 13, wherein the pulse signal has a fixed pulse width.

15. The IC device of claim 13, wherein in a steady state of the buck converter, a value of the ramp voltage at the end of a switching cycle of the buck converter has a fixed value, wherein the fixed value is independent of a switching frequency of the buck converter.

16. The IC device of claim 13, wherein the gradient of the linear voltage signal is equal to or greater than S x , where S x =K×f swx ×ΔV out , ΔV out is the output voltage ripple of the buck converter, f swx is the switching frequency of the buck converter, and K is a constant value.

17. The IC device of claim 13, wherein the ramp signal generator comprises: a phase tracking circuit configured to track a switching frequency of the buck converter and generate an output signal proportional to the switching frequency of the buck converter; as well as The ramp generation circuit is configured to be based on the output signal of the phase tracking circuit: generating a ramp voltage having a gradient proportional to a switching frequency of the buck converter; as well as The ramp voltage is added to the first voltage at the output terminal of the transconductance amplifier to generate a compensation ramp voltage.

18. A method of operating a buck converter, the method comprising: dividing the output voltage of the buck converter to generate a feedback voltage; sending a feedback voltage to a first input terminal of a comparator; sending a feedback voltage and a reference voltage to a first input terminal of a transconductance amplifier and a second input terminal of the transconductance amplifier, respectively; generating a compensating ramp voltage using a ramp signal generator, the compensating ramp voltage being equal to the sum of the first voltage at the output terminal of the transconductance amplifier and the ramp voltage, wherein the ramp voltage is a linear voltage signal having a gradient proportional to the switching frequency of the buck converter; sending the compensation ramp voltage to a second input terminal of the comparator; generating a pulse signal using a pulse generator, the pulse signal including a pulse corresponding to a rising edge in an output signal of the comparator; as well as The buck converter is switched under control of a switching control signal derived from the pulse signal. The method of claim 18 , wherein the pulses of the pulse signal are generated to have a fixed pulse width.

20. The method of claim 19, further comprising charging a capacitor using an output current generated by the transconductance amplifier, wherein the capacitor is coupled between an output terminal of the transconductance amplifier and a reference voltage node.

Images